mpt3sas/mpi/mpi2_ioc.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright 2000-2020 Broadcom Inc. All rights reserved.
0004  *
0005  *
0006  *          Name:  mpi2_ioc.h
0007  *         Title:  MPI IOC, Port, Event, FW Download, and FW Upload messages
0008  * Creation Date:  October 11, 2006
0009  *
0010  * mpi2_ioc.h Version:  02.00.37
0011  *
0012  * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
0013  *       prefix are for use only on MPI v2.5 products, and must not be used
0014  *       with MPI v2.0 products. Unless otherwise noted, names beginning with
0015  *       MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
0016  *
0017  * Version History
0018  * ---------------
0019  *
0020  * Date      Version   Description
0021  * --------  --------  ------------------------------------------------------
0022  * 04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
0023  * 06-04-07  02.00.01  In IOCFacts Reply structure, renamed MaxDevices to
0024  *                     MaxTargets.
0025  *                     Added TotalImageSize field to FWDownload Request.
0026  *                     Added reserved words to FWUpload Request.
0027  * 06-26-07  02.00.02  Added IR Configuration Change List Event.
0028  * 08-31-07  02.00.03  Removed SystemReplyQueueDepth field from the IOCInit
0029  *                     request and replaced it with
0030  *                     ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
0031  *                     Replaced the MinReplyQueueDepth field of the IOCFacts
0032  *                     reply with MaxReplyDescriptorPostQueueDepth.
0033  *                     Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
0034  *                     depth for the Reply Descriptor Post Queue.
0035  *                     Added SASAddress field to Initiator Device Table
0036  *                     Overflow Event data.
0037  * 10-31-07  02.00.04  Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
0038  *                     for SAS Initiator Device Status Change Event data.
0039  *                     Modified Reason Code defines for SAS Topology Change
0040  *                     List Event data, including adding a bit for PHY Vacant
0041  *                     status, and adding a mask for the Reason Code.
0042  *                     Added define for
0043  *                     MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
0044  *                     Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
0045  * 12-18-07  02.00.05  Added Boot Status defines for the IOCExceptions field of
0046  *                     the IOCFacts Reply.
0047  *                     Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
0048  *                     Moved MPI2_VERSION_UNION to mpi2.h.
0049  *                     Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
0050  *                     instead of enables, and added SASBroadcastPrimitiveMasks
0051  *                     field.
0052  *                     Added Log Entry Added Event and related structure.
0053  * 02-29-08  02.00.06  Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
0054  *                     Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
0055  *                     Added MaxVolumes and MaxPersistentEntries fields to
0056  *                     IOCFacts reply.
0057  *                     Added ProtocalFlags and IOCCapabilities fields to
0058  *                     MPI2_FW_IMAGE_HEADER.
0059  *                     Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
0060  * 03-03-08  02.00.07  Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
0061  *                     a U16 (from a U32).
0062  *                     Removed extra 's' from EventMasks name.
0063  * 06-27-08  02.00.08  Fixed an offset in a comment.
0064  * 10-02-08  02.00.09  Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
0065  *                     Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
0066  *                     renamed MinReplyFrameSize to ReplyFrameSize.
0067  *                     Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
0068  *                     Added two new RAIDOperation values for Integrated RAID
0069  *                     Operations Status Event data.
0070  *                     Added four new IR Configuration Change List Event data
0071  *                     ReasonCode values.
0072  *                     Added two new ReasonCode defines for SAS Device Status
0073  *                     Change Event data.
0074  *                     Added three new DiscoveryStatus bits for the SAS
0075  *                     Discovery event data.
0076  *                     Added Multiplexing Status Change bit to the PhyStatus
0077  *                     field of the SAS Topology Change List event data.
0078  *                     Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
0079  *                     BootFlags are now product-specific.
0080  *                     Added defines for the indivdual signature bytes
0081  *                     for MPI2_INIT_IMAGE_FOOTER.
0082  * 01-19-09  02.00.10  Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
0083  *                     Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
0084  *                     define.
0085  *                     Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
0086  *                     define.
0087  *                     Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
0088  * 05-06-09  02.00.11  Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
0089  *                     Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
0090  *                     Added two new reason codes for SAS Device Status Change
0091  *                     Event.
0092  *                     Added new event: SAS PHY Counter.
0093  * 07-30-09  02.00.12  Added GPIO Interrupt event define and structure.
0094  *                     Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
0095  *                     Added new product id family for 2208.
0096  * 10-28-09  02.00.13  Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
0097  *                     Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
0098  *                     Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
0099  *                     Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
0100  *                     Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
0101  *                     Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
0102  *                     Added Host Based Discovery Phy Event data.
0103  *                     Added defines for ProductID Product field
0104  *                     (MPI2_FW_HEADER_PID_).
0105  *                     Modified values for SAS ProductID Family
0106  *                     (MPI2_FW_HEADER_PID_FAMILY_).
0107  * 02-10-10  02.00.14  Added SAS Quiesce Event structure and defines.
0108  *                     Added PowerManagementControl Request structures and
0109  *                     defines.
0110  * 05-12-10  02.00.15  Marked Task Set Full Event as obsolete.
0111  *                     Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
0112  * 11-10-10  02.00.16  Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
0113  * 02-23-11  02.00.17  Added SAS NOTIFY Primitive event, and added
0114  *                     SASNotifyPrimitiveMasks field to
0115  *                     MPI2_EVENT_NOTIFICATION_REQUEST.
0116  *                     Added Temperature Threshold Event.
0117  *                     Added Host Message Event.
0118  *                     Added Send Host Message request and reply.
0119  * 05-25-11  02.00.18  For Extended Image Header, added
0120  *                     MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and
0121  *                     MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines.
0122  *                     Deprecated MPI2_EXT_IMAGE_TYPE_MAX define.
0123  * 08-24-11  02.00.19  Added PhysicalPort field to
0124  *                     MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure.
0125  *                     Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete.
0126  * 11-18-11  02.00.20  Incorporating additions for MPI v2.5.
0127  * 03-29-12  02.00.21  Added a product specific range to event values.
0128  * 07-26-12  02.00.22  Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE.
0129  *                     Added ElapsedSeconds field to
0130  *                     MPI2_EVENT_DATA_IR_OPERATION_STATUS.
0131  * 08-19-13  02.00.23  For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE
0132  *          and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY.
0133  *          Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE.
0134  *          Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY.
0135  *          Added Encrypted Hash Extended Image.
0136  * 12-05-13  02.00.24  Added MPI25_HASH_IMAGE_TYPE_BIOS.
0137  * 11-18-14  02.00.25  Updated copyright information.
0138  * 03-16-15  02.00.26  Updated for MPI v2.6.
0139  *             Added MPI2_EVENT_ACTIVE_CABLE_EXCEPTION and
0140  *             MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT.
0141  *                     Added MPI26_FW_HEADER_PID_FAMILY_3324_SAS and
0142  *                     MPI26_FW_HEADER_PID_FAMILY_3516_SAS.
0143  *                     Added MPI26_CTRL_OP_SHUTDOWN.
0144  * 08-25-15  02.00.27  Added IC ARCH Class based signature defines.
0145  *                     Added MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED event.
0146  *                     Added ConigurationFlags field to IOCInit message to
0147  *                     support NVMe SGL format control.
0148  *                     Added PCIe SRIOV support.
0149  * 02-17-16   02.00.28 Added SAS 4 22.5 gbs speed support.
0150  *                     Added PCIe 4 16.0 GT/sec speec support.
0151  *                     Removed AHCI support.
0152  *                     Removed SOP support.
0153  * 07-01-16   02.00.29 Added Archclass for 4008 product.
0154  *                     Added IOCException MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED
0155  * 08-23-16   02.00.30 Added new defines for the ImageType field of FWDownload
0156  *                     Request Message.
0157  *                     Added new defines for the ImageType field of FWUpload
0158  *                     Request Message.
0159  *                     Added new values for the RegionType field in the Layout
0160  *                     Data sections of the FLASH Layout Extended Image Data.
0161  *                     Added new defines for the ReasonCode field of
0162  *                     Active Cable Exception Event.
0163  *                     Added MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE and
0164  *                     MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE.
0165  * 11-23-16   02.00.31 Added MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR and
0166  *                     MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR.
0167  * 02-02-17   02.00.32 Added MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP.
0168  *                     Added MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT and related
0169  *                     defines for the ReasonCode field.
0170  * 06-13-17   02.00.33 Added MPI2_FW_DOWNLOAD_ITYPE_CPLD.
0171  * 09-29-17   02.00.34 Added MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED
0172  *                     to the ReasonCode field in PCIe Device Status Change
0173  *                     Event Data.
0174  * 07-22-18   02.00.35 Added FW_DOWNLOAD_ITYPE_CPLD and _PSOC.
0175  *                     Moved FW image definitions ionto new mpi2_image,h
0176  * 08-14-18   02.00.36 Fixed definition of MPI2_FW_DOWNLOAD_ITYPE_PSOC (0x16)
0177  * 09-07-18   02.00.37 Added MPI26_EVENT_PCIE_TOPO_PI_16_LANES
0178  * 10-02-19   02.00.38 Added MPI26_IOCINIT_CFGFLAGS_COREDUMP_ENABLE
0179  *                     Added MPI26_IOCFACTS_CAPABILITY_COREDUMP_ENABLED
0180  *                     Added MPI2_FW_DOWNLOAD_ITYPE_COREDUMP
0181  *                     Added MPI2_FW_UPLOAD_ITYPE_COREDUMP
0182  * --------------------------------------------------------------------------
0183  */
0184
0185 #ifndef MPI2_IOC_H
0186 #define MPI2_IOC_H
0187
0188 /*****************************************************************************
0189 *
0190 *              IOC Messages
0191 *
0192 *****************************************************************************/
0193
0194 /****************************************************************************
0195 * IOCInit message
0196 ****************************************************************************/
0197
0198 /*IOCInit Request message */
0199 typedef struct _MPI2_IOC_INIT_REQUEST {
0200     U8 WhoInit;     /*0x00 */
0201     U8 Reserved1;       /*0x01 */
0202     U8 ChainOffset;     /*0x02 */
0203     U8 Function;        /*0x03 */
0204     U16 Reserved2;      /*0x04 */
0205     U8 Reserved3;       /*0x06 */
0206     U8 MsgFlags;        /*0x07 */
0207     U8 VP_ID;       /*0x08 */
0208     U8 VF_ID;       /*0x09 */
0209     U16 Reserved4;      /*0x0A */
0210     U16 MsgVersion;     /*0x0C */
0211     U16 HeaderVersion;  /*0x0E */
0212     U32 Reserved5;      /*0x10 */
0213     U16 ConfigurationFlags; /* 0x14 */
0214     U8 HostPageSize;    /*0x16 */
0215     U8 HostMSIxVectors; /*0x17 */
0216     U16 Reserved8;      /*0x18 */
0217     U16 SystemRequestFrameSize; /*0x1A */
0218     U16 ReplyDescriptorPostQueueDepth;  /*0x1C */
0219     U16 ReplyFreeQueueDepth;    /*0x1E */
0220     U32 SenseBufferAddressHigh; /*0x20 */
0221     U32 SystemReplyAddressHigh; /*0x24 */
0222     U64 SystemRequestFrameBaseAddress;  /*0x28 */
0223     U64 ReplyDescriptorPostQueueAddress;    /*0x30 */
0224     U64 ReplyFreeQueueAddress;  /*0x38 */
0225     U64 TimeStamp;      /*0x40 */
0226 } MPI2_IOC_INIT_REQUEST, *PTR_MPI2_IOC_INIT_REQUEST,
0227     Mpi2IOCInitRequest_t, *pMpi2IOCInitRequest_t;
0228
0229 /*WhoInit values */
0230 #define MPI2_WHOINIT_NOT_INITIALIZED            (0x00)
0231 #define MPI2_WHOINIT_SYSTEM_BIOS                (0x01)
0232 #define MPI2_WHOINIT_ROM_BIOS                   (0x02)
0233 #define MPI2_WHOINIT_PCI_PEER                   (0x03)
0234 #define MPI2_WHOINIT_HOST_DRIVER                (0x04)
0235 #define MPI2_WHOINIT_MANUFACTURER               (0x05)
0236
0237 /* MsgFlags */
0238 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE    (0x01)
0239
0240
0241 /*MsgVersion */
0242 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK      (0xFF00)
0243 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT     (8)
0244 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK      (0x00FF)
0245 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT     (0)
0246
0247 /*HeaderVersion */
0248 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK       (0xFF00)
0249 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT      (8)
0250 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK        (0x00FF)
0251 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT       (0)
0252
0253 /*ConfigurationFlags */
0254 #define MPI26_IOCINIT_CFGFLAGS_NVME_SGL_FORMAT  (0x0001)
0255 #define MPI26_IOCINIT_CFGFLAGS_COREDUMP_ENABLE  (0x0002)
0256
0257 /*minimum depth for a Reply Descriptor Post Queue */
0258 #define MPI2_RDPQ_DEPTH_MIN                     (16)
0259
0260 /* Reply Descriptor Post Queue Array Entry */
0261 typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
0262     U64                 RDPQBaseAddress;                    /* 0x00 */
0263     U32                 Reserved1;                          /* 0x08 */
0264     U32                 Reserved2;                          /* 0x0C */
0265 } MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
0266 *PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
0267 Mpi2IOCInitRDPQArrayEntry, *pMpi2IOCInitRDPQArrayEntry;
0268
0269
0270 /*IOCInit Reply message */
0271 typedef struct _MPI2_IOC_INIT_REPLY {
0272     U8 WhoInit;     /*0x00 */
0273     U8 Reserved1;       /*0x01 */
0274     U8 MsgLength;       /*0x02 */
0275     U8 Function;        /*0x03 */
0276     U16 Reserved2;      /*0x04 */
0277     U8 Reserved3;       /*0x06 */
0278     U8 MsgFlags;        /*0x07 */
0279     U8 VP_ID;       /*0x08 */
0280     U8 VF_ID;       /*0x09 */
0281     U16 Reserved4;      /*0x0A */
0282     U16 Reserved5;      /*0x0C */
0283     U16 IOCStatus;      /*0x0E */
0284     U32 IOCLogInfo;     /*0x10 */
0285 } MPI2_IOC_INIT_REPLY, *PTR_MPI2_IOC_INIT_REPLY,
0286     Mpi2IOCInitReply_t, *pMpi2IOCInitReply_t;
0287
0288 /****************************************************************************
0289 * IOCFacts message
0290 ****************************************************************************/
0291
0292 /*IOCFacts Request message */
0293 typedef struct _MPI2_IOC_FACTS_REQUEST {
0294     U16 Reserved1;      /*0x00 */
0295     U8 ChainOffset;     /*0x02 */
0296     U8 Function;        /*0x03 */
0297     U16 Reserved2;      /*0x04 */
0298     U8 Reserved3;       /*0x06 */
0299     U8 MsgFlags;        /*0x07 */
0300     U8 VP_ID;       /*0x08 */
0301     U8 VF_ID;       /*0x09 */
0302     U16 Reserved4;      /*0x0A */
0303 } MPI2_IOC_FACTS_REQUEST, *PTR_MPI2_IOC_FACTS_REQUEST,
0304     Mpi2IOCFactsRequest_t, *pMpi2IOCFactsRequest_t;
0305
0306 /*IOCFacts Reply message */
0307 typedef struct _MPI2_IOC_FACTS_REPLY {
0308     U16 MsgVersion;     /*0x00 */
0309     U8 MsgLength;       /*0x02 */
0310     U8 Function;        /*0x03 */
0311     U16 HeaderVersion;  /*0x04 */
0312     U8 IOCNumber;       /*0x06 */
0313     U8 MsgFlags;        /*0x07 */
0314     U8 VP_ID;       /*0x08 */
0315     U8 VF_ID;       /*0x09 */
0316     U16 Reserved1;      /*0x0A */
0317     U16 IOCExceptions;  /*0x0C */
0318     U16 IOCStatus;      /*0x0E */
0319     U32 IOCLogInfo;     /*0x10 */
0320     U8 MaxChainDepth;   /*0x14 */
0321     U8 WhoInit;     /*0x15 */
0322     U8 NumberOfPorts;   /*0x16 */
0323     U8 MaxMSIxVectors;  /*0x17 */
0324     U16 RequestCredit;  /*0x18 */
0325     U16 ProductID;      /*0x1A */
0326     U32 IOCCapabilities;    /*0x1C */
0327     MPI2_VERSION_UNION FWVersion;   /*0x20 */
0328     U16 IOCRequestFrameSize;    /*0x24 */
0329     U16 IOCMaxChainSegmentSize; /*0x26 */
0330     U16 MaxInitiators;  /*0x28 */
0331     U16 MaxTargets;     /*0x2A */
0332     U16 MaxSasExpanders;    /*0x2C */
0333     U16 MaxEnclosures;  /*0x2E */
0334     U16 ProtocolFlags;  /*0x30 */
0335     U16 HighPriorityCredit; /*0x32 */
0336     U16 MaxReplyDescriptorPostQueueDepth;   /*0x34 */
0337     U8 ReplyFrameSize;  /*0x36 */
0338     U8 MaxVolumes;      /*0x37 */
0339     U16 MaxDevHandle;   /*0x38 */
0340     U16 MaxPersistentEntries;   /*0x3A */
0341     U16 MinDevHandle;   /*0x3C */
0342     U8 CurrentHostPageSize; /* 0x3E */
0343     U8 Reserved4;       /* 0x3F */
0344     U8 SGEModifierMask; /*0x40 */
0345     U8 SGEModifierValue;    /*0x41 */
0346     U8 SGEModifierShift;    /*0x42 */
0347     U8 Reserved5;       /*0x43 */
0348 } MPI2_IOC_FACTS_REPLY, *PTR_MPI2_IOC_FACTS_REPLY,
0349     Mpi2IOCFactsReply_t, *pMpi2IOCFactsReply_t;
0350
0351 /*MsgVersion */
0352 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK             (0xFF00)
0353 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT            (8)
0354 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK             (0x00FF)
0355 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT            (0)
0356
0357 /*HeaderVersion */
0358 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK              (0xFF00)
0359 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT             (8)
0360 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK               (0x00FF)
0361 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT              (0)
0362
0363 /*IOCExceptions */
0364 #define MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED              (0x0400)
0365 #define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE     (0x0200)
0366 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX      (0x0100)
0367
0368 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK              (0x00E0)
0369 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD              (0x0000)
0370 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP            (0x0020)
0371 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED          (0x0040)
0372 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP    (0x0060)
0373
0374 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED       (0x0010)
0375 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL     (0x0008)
0376 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL           (0x0004)
0377 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID        (0x0002)
0378 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL       (0x0001)
0379
0380 /*defines for WhoInit field are after the IOCInit Request */
0381
0382 /*ProductID field uses MPI2_FW_HEADER_PID_ */
0383
0384 /*IOCCapabilities */
0385 #define MPI26_IOCFACTS_CAPABILITY_COREDUMP_ENABLED      (0x00200000)
0386 #define MPI26_IOCFACTS_CAPABILITY_PCIE_SRIOV            (0x00100000)
0387 #define MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ            (0x00080000)
0388 #define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE     (0x00040000)
0389 #define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE     (0x00020000)
0390 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY   (0x00010000)
0391 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX            (0x00008000)
0392 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR       (0x00004000)
0393 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY           (0x00002000)
0394 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID        (0x00001000)
0395 #define MPI2_IOCFACTS_CAPABILITY_TLR                    (0x00000800)
0396 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST              (0x00000100)
0397 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET   (0x00000080)
0398 #define MPI2_IOCFACTS_CAPABILITY_EEDP                   (0x00000040)
0399 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER        (0x00000020)
0400 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER        (0x00000010)
0401 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER      (0x00000008)
0402 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
0403
0404 /*ProtocolFlags */
0405 #define MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES             (0x0008)
0406 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR           (0x0002)
0407 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET              (0x0001)
0408
0409 /****************************************************************************
0410 * PortFacts message
0411 ****************************************************************************/
0412
0413 /*PortFacts Request message */
0414 typedef struct _MPI2_PORT_FACTS_REQUEST {
0415     U16 Reserved1;      /*0x00 */
0416     U8 ChainOffset;     /*0x02 */
0417     U8 Function;        /*0x03 */
0418     U16 Reserved2;      /*0x04 */
0419     U8 PortNumber;      /*0x06 */
0420     U8 MsgFlags;        /*0x07 */
0421     U8 VP_ID;       /*0x08 */
0422     U8 VF_ID;       /*0x09 */
0423     U16 Reserved3;      /*0x0A */
0424 } MPI2_PORT_FACTS_REQUEST, *PTR_MPI2_PORT_FACTS_REQUEST,
0425     Mpi2PortFactsRequest_t, *pMpi2PortFactsRequest_t;
0426
0427 /*PortFacts Reply message */
0428 typedef struct _MPI2_PORT_FACTS_REPLY {
0429     U16 Reserved1;      /*0x00 */
0430     U8 MsgLength;       /*0x02 */
0431     U8 Function;        /*0x03 */
0432     U16 Reserved2;      /*0x04 */
0433     U8 PortNumber;      /*0x06 */
0434     U8 MsgFlags;        /*0x07 */
0435     U8 VP_ID;       /*0x08 */
0436     U8 VF_ID;       /*0x09 */
0437     U16 Reserved3;      /*0x0A */
0438     U16 Reserved4;      /*0x0C */
0439     U16 IOCStatus;      /*0x0E */
0440     U32 IOCLogInfo;     /*0x10 */
0441     U8 Reserved5;       /*0x14 */
0442     U8 PortType;        /*0x15 */
0443     U16 Reserved6;      /*0x16 */
0444     U16 MaxPostedCmdBuffers;    /*0x18 */
0445     U16 Reserved7;      /*0x1A */
0446 } MPI2_PORT_FACTS_REPLY, *PTR_MPI2_PORT_FACTS_REPLY,
0447     Mpi2PortFactsReply_t, *pMpi2PortFactsReply_t;
0448
0449 /*PortType values */
0450 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE            (0x00)
0451 #define MPI2_PORTFACTS_PORTTYPE_FC                  (0x10)
0452 #define MPI2_PORTFACTS_PORTTYPE_ISCSI               (0x20)
0453 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL        (0x30)
0454 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL         (0x31)
0455 #define MPI2_PORTFACTS_PORTTYPE_TRI_MODE            (0x40)
0456
0457
0458 /****************************************************************************
0459 * PortEnable message
0460 ****************************************************************************/
0461
0462 /*PortEnable Request message */
0463 typedef struct _MPI2_PORT_ENABLE_REQUEST {
0464     U16 Reserved1;      /*0x00 */
0465     U8 ChainOffset;     /*0x02 */
0466     U8 Function;        /*0x03 */
0467     U8 Reserved2;       /*0x04 */
0468     U8 PortFlags;       /*0x05 */
0469     U8 Reserved3;       /*0x06 */
0470     U8 MsgFlags;        /*0x07 */
0471     U8 VP_ID;       /*0x08 */
0472     U8 VF_ID;       /*0x09 */
0473     U16 Reserved4;      /*0x0A */
0474 } MPI2_PORT_ENABLE_REQUEST, *PTR_MPI2_PORT_ENABLE_REQUEST,
0475     Mpi2PortEnableRequest_t, *pMpi2PortEnableRequest_t;
0476
0477 /*PortEnable Reply message */
0478 typedef struct _MPI2_PORT_ENABLE_REPLY {
0479     U16 Reserved1;      /*0x00 */
0480     U8 MsgLength;       /*0x02 */
0481     U8 Function;        /*0x03 */
0482     U8 Reserved2;       /*0x04 */
0483     U8 PortFlags;       /*0x05 */
0484     U8 Reserved3;       /*0x06 */
0485     U8 MsgFlags;        /*0x07 */
0486     U8 VP_ID;       /*0x08 */
0487     U8 VF_ID;       /*0x09 */
0488     U16 Reserved4;      /*0x0A */
0489     U16 Reserved5;      /*0x0C */
0490     U16 IOCStatus;      /*0x0E */
0491     U32 IOCLogInfo;     /*0x10 */
0492 } MPI2_PORT_ENABLE_REPLY, *PTR_MPI2_PORT_ENABLE_REPLY,
0493     Mpi2PortEnableReply_t, *pMpi2PortEnableReply_t;
0494
0495 /****************************************************************************
0496 * EventNotification message
0497 ****************************************************************************/
0498
0499 /*EventNotification Request message */
0500 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS           (4)
0501
0502 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST {
0503     U16 Reserved1;      /*0x00 */
0504     U8 ChainOffset;     /*0x02 */
0505     U8 Function;        /*0x03 */
0506     U16 Reserved2;      /*0x04 */
0507     U8 Reserved3;       /*0x06 */
0508     U8 MsgFlags;        /*0x07 */
0509     U8 VP_ID;       /*0x08 */
0510     U8 VF_ID;       /*0x09 */
0511     U16 Reserved4;      /*0x0A */
0512     U32 Reserved5;      /*0x0C */
0513     U32 Reserved6;      /*0x10 */
0514     U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];  /*0x14 */
0515     U16 SASBroadcastPrimitiveMasks; /*0x24 */
0516     U16 SASNotifyPrimitiveMasks;    /*0x26 */
0517     U32 Reserved8;      /*0x28 */
0518 } MPI2_EVENT_NOTIFICATION_REQUEST,
0519     *PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
0520     Mpi2EventNotificationRequest_t,
0521     *pMpi2EventNotificationRequest_t;
0522
0523 /*EventNotification Reply message */
0524 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY {
0525     U16 EventDataLength;    /*0x00 */
0526     U8 MsgLength;       /*0x02 */
0527     U8 Function;        /*0x03 */
0528     U16 Reserved1;      /*0x04 */
0529     U8 AckRequired;     /*0x06 */
0530     U8 MsgFlags;        /*0x07 */
0531     U8 VP_ID;       /*0x08 */
0532     U8 VF_ID;       /*0x09 */
0533     U16 Reserved2;      /*0x0A */
0534     U16 Reserved3;      /*0x0C */
0535     U16 IOCStatus;      /*0x0E */
0536     U32 IOCLogInfo;     /*0x10 */
0537     U16 Event;      /*0x14 */
0538     U16 Reserved4;      /*0x16 */
0539     U32 EventContext;   /*0x18 */
0540     U32 EventData[];    /*0x1C */
0541 } MPI2_EVENT_NOTIFICATION_REPLY, *PTR_MPI2_EVENT_NOTIFICATION_REPLY,
0542     Mpi2EventNotificationReply_t,
0543     *pMpi2EventNotificationReply_t;
0544
0545 /*AckRequired */
0546 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED    (0x00)
0547 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED        (0x01)
0548
0549 /*Event */
0550 #define MPI2_EVENT_LOG_DATA                         (0x0001)
0551 #define MPI2_EVENT_STATE_CHANGE                     (0x0002)
0552 #define MPI2_EVENT_HARD_RESET_RECEIVED              (0x0005)
0553 #define MPI2_EVENT_EVENT_CHANGE                     (0x000A)
0554 #define MPI2_EVENT_TASK_SET_FULL                    (0x000E)    /*obsolete */
0555 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE         (0x000F)
0556 #define MPI2_EVENT_IR_OPERATION_STATUS              (0x0014)
0557 #define MPI2_EVENT_SAS_DISCOVERY                    (0x0016)
0558 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE          (0x0017)
0559 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE    (0x0018)
0560 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW          (0x0019)
0561 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST         (0x001C)
0562 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE    (0x001D)
0563 #define MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE        (0x001D)
0564 #define MPI2_EVENT_IR_VOLUME                        (0x001E)
0565 #define MPI2_EVENT_IR_PHYSICAL_DISK                 (0x001F)
0566 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST     (0x0020)
0567 #define MPI2_EVENT_LOG_ENTRY_ADDED                  (0x0021)
0568 #define MPI2_EVENT_SAS_PHY_COUNTER                  (0x0022)
0569 #define MPI2_EVENT_GPIO_INTERRUPT                   (0x0023)
0570 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY         (0x0024)
0571 #define MPI2_EVENT_SAS_QUIESCE                      (0x0025)
0572 #define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE             (0x0026)
0573 #define MPI2_EVENT_TEMP_THRESHOLD                   (0x0027)
0574 #define MPI2_EVENT_HOST_MESSAGE                     (0x0028)
0575 #define MPI2_EVENT_POWER_PERFORMANCE_CHANGE         (0x0029)
0576 #define MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE        (0x0030)
0577 #define MPI2_EVENT_PCIE_ENUMERATION                 (0x0031)
0578 #define MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST        (0x0032)
0579 #define MPI2_EVENT_PCIE_LINK_COUNTER                (0x0033)
0580 #define MPI2_EVENT_ACTIVE_CABLE_EXCEPTION           (0x0034)
0581 #define MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR       (0x0035)
0582 #define MPI2_EVENT_MIN_PRODUCT_SPECIFIC             (0x006E)
0583 #define MPI2_EVENT_MAX_PRODUCT_SPECIFIC             (0x007F)
0584
0585 /*Log Entry Added Event data */
0586
0587 /*the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
0588 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH             (0x1C)
0589
0590 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED {
0591     U64 TimeStamp;      /*0x00 */
0592     U32 Reserved1;      /*0x08 */
0593     U16 LogSequence;    /*0x0C */
0594     U16 LogEntryQualifier;  /*0x0E */
0595     U8 VP_ID;       /*0x10 */
0596     U8 VF_ID;       /*0x11 */
0597     U16 Reserved2;      /*0x12 */
0598     U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];    /*0x14 */
0599 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
0600     *PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
0601     Mpi2EventDataLogEntryAdded_t,
0602     *pMpi2EventDataLogEntryAdded_t;
0603
0604 /*GPIO Interrupt Event data */
0605
0606 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT {
0607     U8 GPIONum;     /*0x00 */
0608     U8 Reserved1;       /*0x01 */
0609     U16 Reserved2;      /*0x02 */
0610 } MPI2_EVENT_DATA_GPIO_INTERRUPT,
0611     *PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
0612     Mpi2EventDataGpioInterrupt_t,
0613     *pMpi2EventDataGpioInterrupt_t;
0614
0615 /*Temperature Threshold Event data */
0616
0617 typedef struct _MPI2_EVENT_DATA_TEMPERATURE {
0618     U16 Status;     /*0x00 */
0619     U8 SensorNum;       /*0x02 */
0620     U8 Reserved1;       /*0x03 */
0621     U16 CurrentTemperature; /*0x04 */
0622     U16 Reserved2;      /*0x06 */
0623     U32 Reserved3;      /*0x08 */
0624     U32 Reserved4;      /*0x0C */
0625 } MPI2_EVENT_DATA_TEMPERATURE,
0626     *PTR_MPI2_EVENT_DATA_TEMPERATURE,
0627     Mpi2EventDataTemperature_t, *pMpi2EventDataTemperature_t;
0628
0629 /*Temperature Threshold Event data Status bits */
0630 #define MPI2_EVENT_TEMPERATURE3_EXCEEDED            (0x0008)
0631 #define MPI2_EVENT_TEMPERATURE2_EXCEEDED            (0x0004)
0632 #define MPI2_EVENT_TEMPERATURE1_EXCEEDED            (0x0002)
0633 #define MPI2_EVENT_TEMPERATURE0_EXCEEDED            (0x0001)
0634
0635 /*Host Message Event data */
0636
0637 typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE {
0638     U8 SourceVF_ID;     /*0x00 */
0639     U8 Reserved1;       /*0x01 */
0640     U16 Reserved2;      /*0x02 */
0641     U32 Reserved3;      /*0x04 */
0642     U32 HostData[];     /*0x08 */
0643 } MPI2_EVENT_DATA_HOST_MESSAGE, *PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
0644     Mpi2EventDataHostMessage_t, *pMpi2EventDataHostMessage_t;
0645
0646 /*Power Performance Change Event data */
0647
0648 typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE {
0649     U8 CurrentPowerMode;    /*0x00 */
0650     U8 PreviousPowerMode;   /*0x01 */
0651     U16 Reserved1;      /*0x02 */
0652 } MPI2_EVENT_DATA_POWER_PERF_CHANGE,
0653     *PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE,
0654     Mpi2EventDataPowerPerfChange_t,
0655     *pMpi2EventDataPowerPerfChange_t;
0656
0657 /*defines for CurrentPowerMode and PreviousPowerMode fields */
0658 #define MPI2_EVENT_PM_INIT_MASK              (0xC0)
0659 #define MPI2_EVENT_PM_INIT_UNAVAILABLE       (0x00)
0660 #define MPI2_EVENT_PM_INIT_HOST              (0x40)
0661 #define MPI2_EVENT_PM_INIT_IO_UNIT           (0x80)
0662 #define MPI2_EVENT_PM_INIT_PCIE_DPA          (0xC0)
0663
0664 #define MPI2_EVENT_PM_MODE_MASK              (0x07)
0665 #define MPI2_EVENT_PM_MODE_UNAVAILABLE       (0x00)
0666 #define MPI2_EVENT_PM_MODE_UNKNOWN           (0x01)
0667 #define MPI2_EVENT_PM_MODE_FULL_POWER        (0x04)
0668 #define MPI2_EVENT_PM_MODE_REDUCED_POWER     (0x05)
0669 #define MPI2_EVENT_PM_MODE_STANDBY           (0x06)
0670
0671 /* Active Cable Exception Event data */
0672
0673 typedef struct _MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT {
0674     U32         ActiveCablePowerRequirement;        /* 0x00 */
0675     U8          ReasonCode;                         /* 0x04 */
0676     U8          ReceptacleID;                       /* 0x05 */
0677     U16         Reserved1;                          /* 0x06 */
0678 } MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
0679     *PTR_MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
0680     Mpi25EventDataActiveCableExcept_t,
0681     *pMpi25EventDataActiveCableExcept_t,
0682     MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
0683     *PTR_MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
0684     Mpi26EventDataActiveCableExcept_t,
0685     *pMpi26EventDataActiveCableExcept_t;
0686
0687 /*MPI2.5 defines for the ReasonCode field */
0688 #define MPI25_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER     (0x00)
0689 #define MPI25_EVENT_ACTIVE_CABLE_PRESENT                (0x01)
0690 #define MPI25_EVENT_ACTIVE_CABLE_DEGRADED               (0x02)
0691
0692 /* defines for ReasonCode field */
0693 #define MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER     (0x00)
0694 #define MPI26_EVENT_ACTIVE_CABLE_PRESENT                (0x01)
0695 #define MPI26_EVENT_ACTIVE_CABLE_DEGRADED               (0x02)
0696
0697 /*Hard Reset Received Event data */
0698
0699 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED {
0700     U8 Reserved1;       /*0x00 */
0701     U8 Port;        /*0x01 */
0702     U16 Reserved2;      /*0x02 */
0703 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
0704     *PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
0705     Mpi2EventDataHardResetReceived_t,
0706     *pMpi2EventDataHardResetReceived_t;
0707
0708 /*Task Set Full Event data */
0709 /*  this event is obsolete */
0710
0711 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL {
0712     U16 DevHandle;      /*0x00 */
0713     U16 CurrentDepth;   /*0x02 */
0714 } MPI2_EVENT_DATA_TASK_SET_FULL, *PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
0715     Mpi2EventDataTaskSetFull_t, *pMpi2EventDataTaskSetFull_t;
0716
0717 /*SAS Device Status Change Event data */
0718
0719 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE {
0720     U16 TaskTag;        /*0x00 */
0721     U8 ReasonCode;      /*0x02 */
0722     U8 PhysicalPort;    /*0x03 */
0723     U8 ASC;         /*0x04 */
0724     U8 ASCQ;        /*0x05 */
0725     U16 DevHandle;      /*0x06 */
0726     U32 Reserved2;      /*0x08 */
0727     U64 SASAddress;     /*0x0C */
0728     U8 LUN[8];      /*0x14 */
0729 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
0730     *PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
0731     Mpi2EventDataSasDeviceStatusChange_t,
0732     *pMpi2EventDataSasDeviceStatusChange_t;
0733
0734 /*SAS Device Status Change Event data ReasonCode values */
0735 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA                           (0x05)
0736 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED                          (0x07)
0737 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET                (0x08)
0738 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL                  (0x09)
0739 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL              (0x0A)
0740 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL              (0x0B)
0741 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL                  (0x0C)
0742 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION                   (0x0D)
0743 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET               (0x0E)
0744 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL              (0x0F)
0745 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE                    (0x10)
0746 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY       (0x11)
0747 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY   (0x12)
0748
0749 /*Integrated RAID Operation Status Event data */
0750
0751 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS {
0752     U16 VolDevHandle;   /*0x00 */
0753     U16 Reserved1;      /*0x02 */
0754     U8 RAIDOperation;   /*0x04 */
0755     U8 PercentComplete; /*0x05 */
0756     U16 Reserved2;      /*0x06 */
0757     U32 ElapsedSeconds; /*0x08 */
0758 } MPI2_EVENT_DATA_IR_OPERATION_STATUS,
0759     *PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
0760     Mpi2EventDataIrOperationStatus_t,
0761     *pMpi2EventDataIrOperationStatus_t;
0762
0763 /*Integrated RAID Operation Status Event data RAIDOperation values */
0764 #define MPI2_EVENT_IR_RAIDOP_RESYNC                     (0x00)
0765 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION       (0x01)
0766 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK          (0x02)
0767 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT            (0x03)
0768 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT       (0x04)
0769
0770 /*Integrated RAID Volume Event data */
0771
0772 typedef struct _MPI2_EVENT_DATA_IR_VOLUME {
0773     U16 VolDevHandle;   /*0x00 */
0774     U8 ReasonCode;      /*0x02 */
0775     U8 Reserved1;       /*0x03 */
0776     U32 NewValue;       /*0x04 */
0777     U32 PreviousValue;  /*0x08 */
0778 } MPI2_EVENT_DATA_IR_VOLUME, *PTR_MPI2_EVENT_DATA_IR_VOLUME,
0779     Mpi2EventDataIrVolume_t, *pMpi2EventDataIrVolume_t;
0780
0781 /*Integrated RAID Volume Event data ReasonCode values */
0782 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED        (0x01)
0783 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED    (0x02)
0784 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED           (0x03)
0785
0786 /*Integrated RAID Physical Disk Event data */
0787
0788 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK {
0789     U16 Reserved1;      /*0x00 */
0790     U8 ReasonCode;      /*0x02 */
0791     U8 PhysDiskNum;     /*0x03 */
0792     U16 PhysDiskDevHandle;  /*0x04 */
0793     U16 Reserved2;      /*0x06 */
0794     U16 Slot;       /*0x08 */
0795     U16 EnclosureHandle;    /*0x0A */
0796     U32 NewValue;       /*0x0C */
0797     U32 PreviousValue;  /*0x10 */
0798 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
0799     *PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
0800     Mpi2EventDataIrPhysicalDisk_t,
0801     *pMpi2EventDataIrPhysicalDisk_t;
0802
0803 /*Integrated RAID Physical Disk Event data ReasonCode values */
0804 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED      (0x01)
0805 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED  (0x02)
0806 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED         (0x03)
0807
0808 /*Integrated RAID Configuration Change List Event data */
0809
0810 /*
0811  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
0812  *one and check NumElements at runtime.
0813  */
0814 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
0815 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT          (1)
0816 #endif
0817
0818 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT {
0819     U16 ElementFlags;   /*0x00 */
0820     U16 VolDevHandle;   /*0x02 */
0821     U8 ReasonCode;      /*0x04 */
0822     U8 PhysDiskNum;     /*0x05 */
0823     U16 PhysDiskDevHandle;  /*0x06 */
0824 } MPI2_EVENT_IR_CONFIG_ELEMENT, *PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
0825     Mpi2EventIrConfigElement_t, *pMpi2EventIrConfigElement_t;
0826
0827 /*IR Configuration Change List Event data ElementFlags values */
0828 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK   (0x000F)
0829 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT      (0x0000)
0830 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
0831 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT    (0x0002)
0832
0833 /*IR Configuration Change List Event data ReasonCode values */
0834 #define MPI2_EVENT_IR_CHANGE_RC_ADDED                   (0x01)
0835 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED                 (0x02)
0836 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE               (0x03)
0837 #define MPI2_EVENT_IR_CHANGE_RC_HIDE                    (0x04)
0838 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE                  (0x05)
0839 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED          (0x06)
0840 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED          (0x07)
0841 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED              (0x08)
0842 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED              (0x09)
0843
0844 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST {
0845     U8 NumElements;     /*0x00 */
0846     U8 Reserved1;       /*0x01 */
0847     U8 Reserved2;       /*0x02 */
0848     U8 ConfigNum;       /*0x03 */
0849     U32 Flags;      /*0x04 */
0850     MPI2_EVENT_IR_CONFIG_ELEMENT
0851         ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT];/*0x08 */
0852 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
0853     *PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
0854     Mpi2EventDataIrConfigChangeList_t,
0855     *pMpi2EventDataIrConfigChangeList_t;
0856
0857 /*IR Configuration Change List Event data Flags values */
0858 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG   (0x00000001)
0859
0860 /*SAS Discovery Event data */
0861
0862 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY {
0863     U8 Flags;       /*0x00 */
0864     U8 ReasonCode;      /*0x01 */
0865     U8 PhysicalPort;    /*0x02 */
0866     U8 Reserved1;       /*0x03 */
0867     U32 DiscoveryStatus;    /*0x04 */
0868 } MPI2_EVENT_DATA_SAS_DISCOVERY,
0869     *PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
0870     Mpi2EventDataSasDiscovery_t, *pMpi2EventDataSasDiscovery_t;
0871
0872 /*SAS Discovery Event data Flags values */
0873 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE                   (0x02)
0874 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS                     (0x01)
0875
0876 /*SAS Discovery Event data ReasonCode values */
0877 #define MPI2_EVENT_SAS_DISC_RC_STARTED                      (0x01)
0878 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED                    (0x02)
0879
0880 /*SAS Discovery Event data DiscoveryStatus values */
0881 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED            (0x80000000)
0882 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED             (0x40000000)
0883 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED               (0x20000000)
0884 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
0885 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR             (0x08000000)
0886 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE    (0x00008000)
0887 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE            (0x00004000)
0888 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN                (0x00002000)
0889 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK        (0x00001000)
0890 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE               (0x00000800)
0891 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK                       (0x00000400)
0892 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK                 (0x00000200)
0893 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR                    (0x00000100)
0894 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED              (0x00000080)
0895 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST                  (0x00000040)
0896 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES                (0x00000020)
0897 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT                      (0x00000010)
0898 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS                   (0x00000004)
0899 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE             (0x00000002)
0900 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED                    (0x00000001)
0901
0902 /*SAS Broadcast Primitive Event data */
0903
0904 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE {
0905     U8 PhyNum;      /*0x00 */
0906     U8 Port;        /*0x01 */
0907     U8 PortWidth;       /*0x02 */
0908     U8 Primitive;       /*0x03 */
0909 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
0910     *PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
0911     Mpi2EventDataSasBroadcastPrimitive_t,
0912     *pMpi2EventDataSasBroadcastPrimitive_t;
0913
0914 /*defines for the Primitive field */
0915 #define MPI2_EVENT_PRIMITIVE_CHANGE                         (0x01)
0916 #define MPI2_EVENT_PRIMITIVE_SES                            (0x02)
0917 #define MPI2_EVENT_PRIMITIVE_EXPANDER                       (0x03)
0918 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT             (0x04)
0919 #define MPI2_EVENT_PRIMITIVE_RESERVED3                      (0x05)
0920 #define MPI2_EVENT_PRIMITIVE_RESERVED4                      (0x06)
0921 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED               (0x07)
0922 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED               (0x08)
0923
0924 /*SAS Notify Primitive Event data */
0925
0926 typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE {
0927     U8 PhyNum;      /*0x00 */
0928     U8 Port;        /*0x01 */
0929     U8 Reserved1;       /*0x02 */
0930     U8 Primitive;       /*0x03 */
0931 } MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
0932     *PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
0933     Mpi2EventDataSasNotifyPrimitive_t,
0934     *pMpi2EventDataSasNotifyPrimitive_t;
0935
0936 /*defines for the Primitive field */
0937 #define MPI2_EVENT_NOTIFY_ENABLE_SPINUP                     (0x01)
0938 #define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED               (0x02)
0939 #define MPI2_EVENT_NOTIFY_RESERVED1                         (0x03)
0940 #define MPI2_EVENT_NOTIFY_RESERVED2                         (0x04)
0941
0942 /*SAS Initiator Device Status Change Event data */
0943
0944 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE {
0945     U8 ReasonCode;      /*0x00 */
0946     U8 PhysicalPort;    /*0x01 */
0947     U16 DevHandle;      /*0x02 */
0948     U64 SASAddress;     /*0x04 */
0949 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
0950     *PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
0951     Mpi2EventDataSasInitDevStatusChange_t,
0952     *pMpi2EventDataSasInitDevStatusChange_t;
0953
0954 /*SAS Initiator Device Status Change event ReasonCode values */
0955 #define MPI2_EVENT_SAS_INIT_RC_ADDED                (0x01)
0956 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING       (0x02)
0957
0958 /*SAS Initiator Device Table Overflow Event data */
0959
0960 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW {
0961     U16 MaxInit;        /*0x00 */
0962     U16 CurrentInit;    /*0x02 */
0963     U64 SASAddress;     /*0x04 */
0964 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
0965     *PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
0966     Mpi2EventDataSasInitTableOverflow_t,
0967     *pMpi2EventDataSasInitTableOverflow_t;
0968
0969 /*SAS Topology Change List Event data */
0970
0971 /*
0972  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
0973  *one and check NumEntries at runtime.
0974  */
0975 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
0976 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT           (1)
0977 #endif
0978
0979 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY {
0980     U16 AttachedDevHandle;  /*0x00 */
0981     U8 LinkRate;        /*0x02 */
0982     U8 PhyStatus;       /*0x03 */
0983 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, *PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
0984     Mpi2EventSasTopoPhyEntry_t, *pMpi2EventSasTopoPhyEntry_t;
0985
0986 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST {
0987     U16 EnclosureHandle;    /*0x00 */
0988     U16 ExpanderDevHandle;  /*0x02 */
0989     U8 NumPhys;     /*0x04 */
0990     U8 Reserved1;       /*0x05 */
0991     U16 Reserved2;      /*0x06 */
0992     U8 NumEntries;      /*0x08 */
0993     U8 StartPhyNum;     /*0x09 */
0994     U8 ExpStatus;       /*0x0A */
0995     U8 PhysicalPort;    /*0x0B */
0996     MPI2_EVENT_SAS_TOPO_PHY_ENTRY
0997     PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /*0x0C */
0998 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
0999     *PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
1000     Mpi2EventDataSasTopologyChangeList_t,
1001     *pMpi2EventDataSasTopologyChangeList_t;
1002
1003 /*values for the ExpStatus field */
1004 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER                  (0x00)
1005 #define MPI2_EVENT_SAS_TOPO_ES_ADDED                        (0x01)
1006 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING               (0x02)
1007 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING                   (0x03)
1008 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING         (0x04)
1009
1010 /*defines for the LinkRate field */
1011 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK                 (0xF0)
1012 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT                (4)
1013 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK                    (0x0F)
1014 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT                   (0)
1015
1016 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE            (0x00)
1017 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED                 (0x01)
1018 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED           (0x02)
1019 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE            (0x03)
1020 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR                (0x04)
1021 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS        (0x05)
1022 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY              (0x06)
1023 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5                     (0x08)
1024 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0                     (0x09)
1025 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0                     (0x0A)
1026 #define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0                   (0x0B)
1027 #define MPI26_EVENT_SAS_TOPO_LR_RATE_22_5                   (0x0C)
1028
1029 /*values for the PhyStatus field */
1030 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT                (0x80)
1031 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE             (0x10)
1032 /*values for the PhyStatus ReasonCode sub-field */
1033 #define MPI2_EVENT_SAS_TOPO_RC_MASK                         (0x0F)
1034 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED                   (0x01)
1035 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING          (0x02)
1036 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED                  (0x03)
1037 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE                    (0x04)
1038 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING         (0x05)
1039
1040 /*SAS Enclosure Device Status Change Event data */
1041
1042 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE {
1043     U16 EnclosureHandle;    /*0x00 */
1044     U8 ReasonCode;      /*0x02 */
1045     U8 PhysicalPort;    /*0x03 */
1046     U64 EnclosureLogicalID; /*0x04 */
1047     U16 NumSlots;       /*0x0C */
1048     U16 StartSlot;      /*0x0E */
1049     U32 PhyBits;        /*0x10 */
1050 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
1051     *PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
1052     Mpi2EventDataSasEnclDevStatusChange_t,
1053     *pMpi2EventDataSasEnclDevStatusChange_t,
1054     MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE,
1055     *PTR_MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE,
1056     Mpi26EventDataEnclDevStatusChange_t,
1057     *pMpi26EventDataEnclDevStatusChange_t;
1058
1059 /*SAS Enclosure Device Status Change event ReasonCode values */
1060 #define MPI2_EVENT_SAS_ENCL_RC_ADDED                (0x01)
1061 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING       (0x02)
1062
1063 /*Enclosure Device Status Change event ReasonCode values */
1064 #define MPI26_EVENT_ENCL_RC_ADDED                   (0x01)
1065 #define MPI26_EVENT_ENCL_RC_NOT_RESPONDING          (0x02)
1066
1067
1068 typedef struct _MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR {
1069     U16 DevHandle;                  /*0x00 */
1070     U8  ReasonCode;                 /*0x02 */
1071     U8  PhysicalPort;               /*0x03 */
1072     U32 Reserved1[2];               /*0x04 */
1073     U64 SASAddress;                 /*0x0C */
1074     U32 Reserved2[2];               /*0x14 */
1075 } MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR,
1076     *PTR_MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR,
1077     Mpi25EventDataSasDeviceDiscoveryError_t,
1078     *pMpi25EventDataSasDeviceDiscoveryError_t;
1079
1080 /*SAS Device Discovery Error Event data ReasonCode values */
1081 #define MPI25_EVENT_SAS_DISC_ERR_SMP_FAILED         (0x01)
1082 #define MPI25_EVENT_SAS_DISC_ERR_SMP_TIMEOUT        (0x02)
1083
1084 /*SAS PHY Counter Event data */
1085
1086 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {
1087     U64 TimeStamp;      /*0x00 */
1088     U32 Reserved1;      /*0x08 */
1089     U8 PhyEventCode;    /*0x0C */
1090     U8 PhyNum;      /*0x0D */
1091     U16 Reserved2;      /*0x0E */
1092     U32 PhyEventInfo;   /*0x10 */
1093     U8 CounterType;     /*0x14 */
1094     U8 ThresholdWindow; /*0x15 */
1095     U8 TimeUnits;       /*0x16 */
1096     U8 Reserved3;       /*0x17 */
1097     U32 EventThreshold; /*0x18 */
1098     U16 ThresholdFlags; /*0x1C */
1099     U16 Reserved4;      /*0x1E */
1100 } MPI2_EVENT_DATA_SAS_PHY_COUNTER,
1101     *PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
1102     Mpi2EventDataSasPhyCounter_t,
1103     *pMpi2EventDataSasPhyCounter_t;
1104
1105 /*use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h
1106  *for the PhyEventCode field */
1107
1108 /*use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h
1109  *for the CounterType field */
1110
1111 /*use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h
1112  *for the TimeUnits field */
1113
1114 /*use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h
1115  *for the ThresholdFlags field */
1116
1117 /*SAS Quiesce Event data */
1118
1119 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE {
1120     U8 ReasonCode;      /*0x00 */
1121     U8 Reserved1;       /*0x01 */
1122     U16 Reserved2;      /*0x02 */
1123     U32 Reserved3;      /*0x04 */
1124 } MPI2_EVENT_DATA_SAS_QUIESCE,
1125     *PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
1126     Mpi2EventDataSasQuiesce_t, *pMpi2EventDataSasQuiesce_t;
1127
1128 /*SAS Quiesce Event data ReasonCode values */
1129 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED                   (0x01)
1130 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED                 (0x02)
1131
1132 /*Host Based Discovery Phy Event data */
1133
1134 typedef struct _MPI2_EVENT_HBD_PHY_SAS {
1135     U8 Flags;       /*0x00 */
1136     U8 NegotiatedLinkRate;  /*0x01 */
1137     U8 PhyNum;      /*0x02 */
1138     U8 PhysicalPort;    /*0x03 */
1139     U32 Reserved1;      /*0x04 */
1140     U8 InitialFrame[28];    /*0x08 */
1141 } MPI2_EVENT_HBD_PHY_SAS, *PTR_MPI2_EVENT_HBD_PHY_SAS,
1142     Mpi2EventHbdPhySas_t, *pMpi2EventHbdPhySas_t;
1143
1144 /*values for the Flags field */
1145 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID        (0x02)
1146 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME         (0x01)
1147
1148 /*use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h
1149  *for the NegotiatedLinkRate field */
1150
1151 typedef union _MPI2_EVENT_HBD_DESCRIPTOR {
1152     MPI2_EVENT_HBD_PHY_SAS Sas;
1153 } MPI2_EVENT_HBD_DESCRIPTOR, *PTR_MPI2_EVENT_HBD_DESCRIPTOR,
1154     Mpi2EventHbdDescriptor_t, *pMpi2EventHbdDescriptor_t;
1155
1156 typedef struct _MPI2_EVENT_DATA_HBD_PHY {
1157     U8 DescriptorType;  /*0x00 */
1158     U8 Reserved1;       /*0x01 */
1159     U16 Reserved2;      /*0x02 */
1160     U32 Reserved3;      /*0x04 */
1161     MPI2_EVENT_HBD_DESCRIPTOR Descriptor;   /*0x08 */
1162 } MPI2_EVENT_DATA_HBD_PHY, *PTR_MPI2_EVENT_DATA_HBD_PHY,
1163     Mpi2EventDataHbdPhy_t,
1164     *pMpi2EventDataMpi2EventDataHbdPhy_t;
1165
1166 /*values for the DescriptorType field */
1167 #define MPI2_EVENT_HBD_DT_SAS               (0x01)
1168
1169
1170 /*PCIe Device Status Change Event data (MPI v2.6 and later) */
1171
1172 typedef struct _MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE {
1173     U16 TaskTag;                        /*0x00 */
1174     U8  ReasonCode;                     /*0x02 */
1175     U8  PhysicalPort;                   /*0x03 */
1176     U8  ASC;                            /*0x04 */
1177     U8  ASCQ;                           /*0x05 */
1178     U16 DevHandle;                      /*0x06 */
1179     U32 Reserved2;                      /*0x08 */
1180     U64 WWID;                           /*0x0C */
1181     U8  LUN[8];                         /*0x14 */
1182 } MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE,
1183     *PTR_MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE,
1184     Mpi26EventDataPCIeDeviceStatusChange_t,
1185     *pMpi26EventDataPCIeDeviceStatusChange_t;
1186
1187 /*PCIe Device Status Change Event data ReasonCode values */
1188 #define MPI26_EVENT_PCIDEV_STAT_RC_SMART_DATA                           (0x05)
1189 #define MPI26_EVENT_PCIDEV_STAT_RC_UNSUPPORTED                          (0x07)
1190 #define MPI26_EVENT_PCIDEV_STAT_RC_INTERNAL_DEVICE_RESET                (0x08)
1191 #define MPI26_EVENT_PCIDEV_STAT_RC_TASK_ABORT_INTERNAL                  (0x09)
1192 #define MPI26_EVENT_PCIDEV_STAT_RC_ABORT_TASK_SET_INTERNAL              (0x0A)
1193 #define MPI26_EVENT_PCIDEV_STAT_RC_CLEAR_TASK_SET_INTERNAL              (0x0B)
1194 #define MPI26_EVENT_PCIDEV_STAT_RC_QUERY_TASK_INTERNAL                  (0x0C)
1195 #define MPI26_EVENT_PCIDEV_STAT_RC_ASYNC_NOTIFICATION                   (0x0D)
1196 #define MPI26_EVENT_PCIDEV_STAT_RC_CMP_INTERNAL_DEV_RESET               (0x0E)
1197 #define MPI26_EVENT_PCIDEV_STAT_RC_CMP_TASK_ABORT_INTERNAL              (0x0F)
1198 #define MPI26_EVENT_PCIDEV_STAT_RC_DEV_INIT_FAILURE                     (0x10)
1199 #define MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED                (0x11)
1200
1201
1202 /*PCIe Enumeration Event data (MPI v2.6 and later) */
1203
1204 typedef struct _MPI26_EVENT_DATA_PCIE_ENUMERATION {
1205     U8  Flags;                      /*0x00 */
1206     U8  ReasonCode;                 /*0x01 */
1207     U8  PhysicalPort;               /*0x02 */
1208     U8  Reserved1;                  /*0x03 */
1209     U32 EnumerationStatus;          /*0x04 */
1210 } MPI26_EVENT_DATA_PCIE_ENUMERATION,
1211     *PTR_MPI26_EVENT_DATA_PCIE_ENUMERATION,
1212     Mpi26EventDataPCIeEnumeration_t,
1213     *pMpi26EventDataPCIeEnumeration_t;
1214
1215 /*PCIe Enumeration Event data Flags values */
1216 #define MPI26_EVENT_PCIE_ENUM_DEVICE_CHANGE                 (0x02)
1217 #define MPI26_EVENT_PCIE_ENUM_IN_PROGRESS                   (0x01)
1218
1219 /*PCIe Enumeration Event data ReasonCode values */
1220 #define MPI26_EVENT_PCIE_ENUM_RC_STARTED                    (0x01)
1221 #define MPI26_EVENT_PCIE_ENUM_RC_COMPLETED                  (0x02)
1222
1223 /*PCIe Enumeration Event data EnumerationStatus values */
1224 #define MPI26_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED            (0x40000000)
1225 #define MPI26_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED             (0x20000000)
1226 #define MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED            (0x10000000)
1227
1228
1229 /*PCIe Topology Change List Event data (MPI v2.6 and later) */
1230
1231 /*
1232  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1233  *one and check NumEntries at runtime.
1234  */
1235 #ifndef MPI26_EVENT_PCIE_TOPO_PORT_COUNT
1236 #define MPI26_EVENT_PCIE_TOPO_PORT_COUNT        (1)
1237 #endif
1238
1239 typedef struct _MPI26_EVENT_PCIE_TOPO_PORT_ENTRY {
1240     U16 AttachedDevHandle;      /*0x00 */
1241     U8  PortStatus;             /*0x02 */
1242     U8  Reserved1;              /*0x03 */
1243     U8  CurrentPortInfo;        /*0x04 */
1244     U8  Reserved2;              /*0x05 */
1245     U8  PreviousPortInfo;       /*0x06 */
1246     U8  Reserved3;              /*0x07 */
1247 } MPI26_EVENT_PCIE_TOPO_PORT_ENTRY,
1248     *PTR_MPI26_EVENT_PCIE_TOPO_PORT_ENTRY,
1249     Mpi26EventPCIeTopoPortEntry_t,
1250     *pMpi26EventPCIeTopoPortEntry_t;
1251
1252 /*PCIe Topology Change List Event data PortStatus values */
1253 #define MPI26_EVENT_PCIE_TOPO_PS_DEV_ADDED                  (0x01)
1254 #define MPI26_EVENT_PCIE_TOPO_PS_NOT_RESPONDING             (0x02)
1255 #define MPI26_EVENT_PCIE_TOPO_PS_PORT_CHANGED               (0x03)
1256 #define MPI26_EVENT_PCIE_TOPO_PS_NO_CHANGE                  (0x04)
1257 #define MPI26_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING       (0x05)
1258
1259 /*PCIe Topology Change List Event data defines for CurrentPortInfo and
1260  *PreviousPortInfo
1261  */
1262 #define MPI26_EVENT_PCIE_TOPO_PI_LANE_MASK                  (0xF0)
1263 #define MPI26_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN              (0x00)
1264 #define MPI26_EVENT_PCIE_TOPO_PI_1_LANE                     (0x10)
1265 #define MPI26_EVENT_PCIE_TOPO_PI_2_LANES                    (0x20)
1266 #define MPI26_EVENT_PCIE_TOPO_PI_4_LANES                    (0x30)
1267 #define MPI26_EVENT_PCIE_TOPO_PI_8_LANES                    (0x40)
1268 #define MPI26_EVENT_PCIE_TOPO_PI_16_LANES                   (0x50)
1269
1270 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_MASK                  (0x0F)
1271 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN               (0x00)
1272 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_DISABLED              (0x01)
1273 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_2_5                   (0x02)
1274 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_5_0                   (0x03)
1275 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_8_0                   (0x04)
1276 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_16_0                  (0x05)
1277
1278 typedef struct _MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST {
1279     U16 EnclosureHandle;        /*0x00 */
1280     U16 SwitchDevHandle;        /*0x02 */
1281     U8  NumPorts;               /*0x04 */
1282     U8  Reserved1;              /*0x05 */
1283     U16 Reserved2;              /*0x06 */
1284     U8  NumEntries;             /*0x08 */
1285     U8  StartPortNum;           /*0x09 */
1286     U8  SwitchStatus;           /*0x0A */
1287     U8  PhysicalPort;           /*0x0B */
1288     MPI26_EVENT_PCIE_TOPO_PORT_ENTRY
1289         PortEntry[MPI26_EVENT_PCIE_TOPO_PORT_COUNT]; /*0x0C */
1290 } MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST,
1291     *PTR_MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST,
1292     Mpi26EventDataPCIeTopologyChangeList_t,
1293     *pMpi26EventDataPCIeTopologyChangeList_t;
1294
1295 /*PCIe Topology Change List Event data SwitchStatus values */
1296 #define MPI26_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH             (0x00)
1297 #define MPI26_EVENT_PCIE_TOPO_SS_ADDED                      (0x01)
1298 #define MPI26_EVENT_PCIE_TOPO_SS_NOT_RESPONDING             (0x02)
1299 #define MPI26_EVENT_PCIE_TOPO_SS_RESPONDING                 (0x03)
1300 #define MPI26_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING       (0x04)
1301
1302 /*PCIe Link Counter Event data (MPI v2.6 and later) */
1303
1304 typedef struct _MPI26_EVENT_DATA_PCIE_LINK_COUNTER {
1305     U64 TimeStamp;          /*0x00 */
1306     U32 Reserved1;          /*0x08 */
1307     U8  LinkEventCode;      /*0x0C */
1308     U8  LinkNum;            /*0x0D */
1309     U16 Reserved2;          /*0x0E */
1310     U32 LinkEventInfo;      /*0x10 */
1311     U8  CounterType;        /*0x14 */
1312     U8  ThresholdWindow;    /*0x15 */
1313     U8  TimeUnits;          /*0x16 */
1314     U8  Reserved3;          /*0x17 */
1315     U32 EventThreshold;     /*0x18 */
1316     U16 ThresholdFlags;     /*0x1C */
1317     U16 Reserved4;          /*0x1E */
1318 } MPI26_EVENT_DATA_PCIE_LINK_COUNTER,
1319     *PTR_MPI26_EVENT_DATA_PCIE_LINK_COUNTER,
1320     Mpi26EventDataPcieLinkCounter_t, *pMpi26EventDataPcieLinkCounter_t;
1321
1322
1323 /*use MPI26_PCIELINK3_EVTCODE_ values from mpi2_cnfg.h for the LinkEventCode
1324  *field
1325  */
1326
1327 /*use MPI26_PCIELINK3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType
1328  *field
1329  */
1330
1331 /*use MPI26_PCIELINK3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits
1332  *field
1333  */
1334
1335 /*use MPI26_PCIELINK3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags
1336  *field
1337  */
1338
1339 /****************************************************************************
1340 * EventAck message
1341 ****************************************************************************/
1342
1343 /*EventAck Request message */
1344 typedef struct _MPI2_EVENT_ACK_REQUEST {
1345     U16 Reserved1;      /*0x00 */
1346     U8 ChainOffset;     /*0x02 */
1347     U8 Function;        /*0x03 */
1348     U16 Reserved2;      /*0x04 */
1349     U8 Reserved3;       /*0x06 */
1350     U8 MsgFlags;        /*0x07 */
1351     U8 VP_ID;       /*0x08 */
1352     U8 VF_ID;       /*0x09 */
1353     U16 Reserved4;      /*0x0A */
1354     U16 Event;      /*0x0C */
1355     U16 Reserved5;      /*0x0E */
1356     U32 EventContext;   /*0x10 */
1357 } MPI2_EVENT_ACK_REQUEST, *PTR_MPI2_EVENT_ACK_REQUEST,
1358     Mpi2EventAckRequest_t, *pMpi2EventAckRequest_t;
1359
1360 /*EventAck Reply message */
1361 typedef struct _MPI2_EVENT_ACK_REPLY {
1362     U16 Reserved1;      /*0x00 */
1363     U8 MsgLength;       /*0x02 */
1364     U8 Function;        /*0x03 */
1365     U16 Reserved2;      /*0x04 */
1366     U8 Reserved3;       /*0x06 */
1367     U8 MsgFlags;        /*0x07 */
1368     U8 VP_ID;       /*0x08 */
1369     U8 VF_ID;       /*0x09 */
1370     U16 Reserved4;      /*0x0A */
1371     U16 Reserved5;      /*0x0C */
1372     U16 IOCStatus;      /*0x0E */
1373     U32 IOCLogInfo;     /*0x10 */
1374 } MPI2_EVENT_ACK_REPLY, *PTR_MPI2_EVENT_ACK_REPLY,
1375     Mpi2EventAckReply_t, *pMpi2EventAckReply_t;
1376
1377 /****************************************************************************
1378 * SendHostMessage message
1379 ****************************************************************************/
1380
1381 /*SendHostMessage Request message */
1382 typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST {
1383     U16 HostDataLength; /*0x00 */
1384     U8 ChainOffset;     /*0x02 */
1385     U8 Function;        /*0x03 */
1386     U16 Reserved1;      /*0x04 */
1387     U8 Reserved2;       /*0x06 */
1388     U8 MsgFlags;        /*0x07 */
1389     U8 VP_ID;       /*0x08 */
1390     U8 VF_ID;       /*0x09 */
1391     U16 Reserved3;      /*0x0A */
1392     U8 Reserved4;       /*0x0C */
1393     U8 DestVF_ID;       /*0x0D */
1394     U16 Reserved5;      /*0x0E */
1395     U32 Reserved6;      /*0x10 */
1396     U32 Reserved7;      /*0x14 */
1397     U32 Reserved8;      /*0x18 */
1398     U32 Reserved9;      /*0x1C */
1399     U32 Reserved10;     /*0x20 */
1400     U32 HostData[];     /*0x24 */
1401 } MPI2_SEND_HOST_MESSAGE_REQUEST,
1402     *PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,
1403     Mpi2SendHostMessageRequest_t,
1404     *pMpi2SendHostMessageRequest_t;
1405
1406 /*SendHostMessage Reply message */
1407 typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY {
1408     U16 HostDataLength; /*0x00 */
1409     U8 MsgLength;       /*0x02 */
1410     U8 Function;        /*0x03 */
1411     U16 Reserved1;      /*0x04 */
1412     U8 Reserved2;       /*0x06 */
1413     U8 MsgFlags;        /*0x07 */
1414     U8 VP_ID;       /*0x08 */
1415     U8 VF_ID;       /*0x09 */
1416     U16 Reserved3;      /*0x0A */
1417     U16 Reserved4;      /*0x0C */
1418     U16 IOCStatus;      /*0x0E */
1419     U32 IOCLogInfo;     /*0x10 */
1420 } MPI2_SEND_HOST_MESSAGE_REPLY, *PTR_MPI2_SEND_HOST_MESSAGE_REPLY,
1421     Mpi2SendHostMessageReply_t, *pMpi2SendHostMessageReply_t;
1422
1423 /****************************************************************************
1424 * FWDownload message
1425 ****************************************************************************/
1426
1427 /*MPI v2.0 FWDownload Request message */
1428 typedef struct _MPI2_FW_DOWNLOAD_REQUEST {
1429     U8 ImageType;       /*0x00 */
1430     U8 Reserved1;       /*0x01 */
1431     U8 ChainOffset;     /*0x02 */
1432     U8 Function;        /*0x03 */
1433     U16 Reserved2;      /*0x04 */
1434     U8 Reserved3;       /*0x06 */
1435     U8 MsgFlags;        /*0x07 */
1436     U8 VP_ID;       /*0x08 */
1437     U8 VF_ID;       /*0x09 */
1438     U16 Reserved4;      /*0x0A */
1439     U32 TotalImageSize; /*0x0C */
1440     U32 Reserved5;      /*0x10 */
1441     MPI2_MPI_SGE_UNION SGL; /*0x14 */
1442 } MPI2_FW_DOWNLOAD_REQUEST, *PTR_MPI2_FW_DOWNLOAD_REQUEST,
1443     Mpi2FWDownloadRequest, *pMpi2FWDownloadRequest;
1444
1445 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT   (0x01)
1446
1447 #define MPI2_FW_DOWNLOAD_ITYPE_FW                   (0x01)
1448 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS                 (0x02)
1449 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING        (0x06)
1450 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1             (0x07)
1451 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2             (0x08)
1452 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID             (0x09)
1453 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE             (0x0A)
1454 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK    (0x0B)
1455 #define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY           (0x0C)
1456 #define MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP           (0x0D)
1457 #define MPI2_FW_DOWNLOAD_ITYPE_SBR                  (0x0E)
1458 #define MPI2_FW_DOWNLOAD_ITYPE_SBR_BACKUP           (0x0F)
1459 #define MPI2_FW_DOWNLOAD_ITYPE_HIIM                 (0x10)
1460 #define MPI2_FW_DOWNLOAD_ITYPE_HIIA                 (0x11)
1461 #define MPI2_FW_DOWNLOAD_ITYPE_CTLR                 (0x12)
1462 #define MPI2_FW_DOWNLOAD_ITYPE_IMR_FIRMWARE         (0x13)
1463 #define MPI2_FW_DOWNLOAD_ITYPE_MR_NVDATA            (0x14)
1464 /*MPI v2.6 and newer */
1465 #define MPI2_FW_DOWNLOAD_ITYPE_CPLD                 (0x15)
1466 #define MPI2_FW_DOWNLOAD_ITYPE_PSOC                 (0x16)
1467 #define MPI2_FW_DOWNLOAD_ITYPE_COREDUMP             (0x17)
1468 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1469
1470 /*MPI v2.0 FWDownload TransactionContext Element */
1471 typedef struct _MPI2_FW_DOWNLOAD_TCSGE {
1472     U8 Reserved1;       /*0x00 */
1473     U8 ContextSize;     /*0x01 */
1474     U8 DetailsLength;   /*0x02 */
1475     U8 Flags;       /*0x03 */
1476     U32 Reserved2;      /*0x04 */
1477     U32 ImageOffset;    /*0x08 */
1478     U32 ImageSize;      /*0x0C */
1479 } MPI2_FW_DOWNLOAD_TCSGE, *PTR_MPI2_FW_DOWNLOAD_TCSGE,
1480     Mpi2FWDownloadTCSGE_t, *pMpi2FWDownloadTCSGE_t;
1481
1482 /*MPI v2.5 FWDownload Request message */
1483 typedef struct _MPI25_FW_DOWNLOAD_REQUEST {
1484     U8 ImageType;       /*0x00 */
1485     U8 Reserved1;       /*0x01 */
1486     U8 ChainOffset;     /*0x02 */
1487     U8 Function;        /*0x03 */
1488     U16 Reserved2;      /*0x04 */
1489     U8 Reserved3;       /*0x06 */
1490     U8 MsgFlags;        /*0x07 */
1491     U8 VP_ID;       /*0x08 */
1492     U8 VF_ID;       /*0x09 */
1493     U16 Reserved4;      /*0x0A */
1494     U32 TotalImageSize; /*0x0C */
1495     U32 Reserved5;      /*0x10 */
1496     U32 Reserved6;      /*0x14 */
1497     U32 ImageOffset;    /*0x18 */
1498     U32 ImageSize;      /*0x1C */
1499     MPI25_SGE_IO_UNION SGL; /*0x20 */
1500 } MPI25_FW_DOWNLOAD_REQUEST, *PTR_MPI25_FW_DOWNLOAD_REQUEST,
1501     Mpi25FWDownloadRequest, *pMpi25FWDownloadRequest;
1502
1503 /*FWDownload Reply message */
1504 typedef struct _MPI2_FW_DOWNLOAD_REPLY {
1505     U8 ImageType;       /*0x00 */
1506     U8 Reserved1;       /*0x01 */
1507     U8 MsgLength;       /*0x02 */
1508     U8 Function;        /*0x03 */
1509     U16 Reserved2;      /*0x04 */
1510     U8 Reserved3;       /*0x06 */
1511     U8 MsgFlags;        /*0x07 */
1512     U8 VP_ID;       /*0x08 */
1513     U8 VF_ID;       /*0x09 */
1514     U16 Reserved4;      /*0x0A */
1515     U16 Reserved5;      /*0x0C */
1516     U16 IOCStatus;      /*0x0E */
1517     U32 IOCLogInfo;     /*0x10 */
1518 } MPI2_FW_DOWNLOAD_REPLY, *PTR_MPI2_FW_DOWNLOAD_REPLY,
1519     Mpi2FWDownloadReply_t, *pMpi2FWDownloadReply_t;
1520
1521 /****************************************************************************
1522 * FWUpload message
1523 ****************************************************************************/
1524
1525 /*MPI v2.0 FWUpload Request message */
1526 typedef struct _MPI2_FW_UPLOAD_REQUEST {
1527     U8 ImageType;       /*0x00 */
1528     U8 Reserved1;       /*0x01 */
1529     U8 ChainOffset;     /*0x02 */
1530     U8 Function;        /*0x03 */
1531     U16 Reserved2;      /*0x04 */
1532     U8 Reserved3;       /*0x06 */
1533     U8 MsgFlags;        /*0x07 */
1534     U8 VP_ID;       /*0x08 */
1535     U8 VF_ID;       /*0x09 */
1536     U16 Reserved4;      /*0x0A */
1537     U32 Reserved5;      /*0x0C */
1538     U32 Reserved6;      /*0x10 */
1539     MPI2_MPI_SGE_UNION SGL; /*0x14 */
1540 } MPI2_FW_UPLOAD_REQUEST, *PTR_MPI2_FW_UPLOAD_REQUEST,
1541     Mpi2FWUploadRequest_t, *pMpi2FWUploadRequest_t;
1542
1543 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT         (0x00)
1544 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH           (0x01)
1545 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH         (0x02)
1546 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP          (0x05)
1547 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING      (0x06)
1548 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1           (0x07)
1549 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2           (0x08)
1550 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID           (0x09)
1551 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE           (0x0A)
1552 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK  (0x0B)
1553 #define MPI2_FW_UPLOAD_ITYPE_CBB_BACKUP         (0x0D)
1554 #define MPI2_FW_UPLOAD_ITYPE_SBR                (0x0E)
1555 #define MPI2_FW_UPLOAD_ITYPE_SBR_BACKUP         (0x0F)
1556 #define MPI2_FW_UPLOAD_ITYPE_HIIM               (0x10)
1557 #define MPI2_FW_UPLOAD_ITYPE_HIIA               (0x11)
1558 #define MPI2_FW_UPLOAD_ITYPE_CTLR               (0x12)
1559 #define MPI2_FW_UPLOAD_ITYPE_IMR_FIRMWARE       (0x13)
1560 #define MPI2_FW_UPLOAD_ITYPE_MR_NVDATA          (0x14)
1561
1562
1563 /*MPI v2.0 FWUpload TransactionContext Element */
1564 typedef struct _MPI2_FW_UPLOAD_TCSGE {
1565     U8 Reserved1;       /*0x00 */
1566     U8 ContextSize;     /*0x01 */
1567     U8 DetailsLength;   /*0x02 */
1568     U8 Flags;       /*0x03 */
1569     U32 Reserved2;      /*0x04 */
1570     U32 ImageOffset;    /*0x08 */
1571     U32 ImageSize;      /*0x0C */
1572 } MPI2_FW_UPLOAD_TCSGE, *PTR_MPI2_FW_UPLOAD_TCSGE,
1573     Mpi2FWUploadTCSGE_t, *pMpi2FWUploadTCSGE_t;
1574
1575 /*MPI v2.5 FWUpload Request message */
1576 typedef struct _MPI25_FW_UPLOAD_REQUEST {
1577     U8 ImageType;       /*0x00 */
1578     U8 Reserved1;       /*0x01 */
1579     U8 ChainOffset;     /*0x02 */
1580     U8 Function;        /*0x03 */
1581     U16 Reserved2;      /*0x04 */
1582     U8 Reserved3;       /*0x06 */
1583     U8 MsgFlags;        /*0x07 */
1584     U8 VP_ID;       /*0x08 */
1585     U8 VF_ID;       /*0x09 */
1586     U16 Reserved4;      /*0x0A */
1587     U32 Reserved5;      /*0x0C */
1588     U32 Reserved6;      /*0x10 */
1589     U32 Reserved7;      /*0x14 */
1590     U32 ImageOffset;    /*0x18 */
1591     U32 ImageSize;      /*0x1C */
1592     MPI25_SGE_IO_UNION SGL; /*0x20 */
1593 } MPI25_FW_UPLOAD_REQUEST, *PTR_MPI25_FW_UPLOAD_REQUEST,
1594     Mpi25FWUploadRequest_t, *pMpi25FWUploadRequest_t;
1595
1596 /*FWUpload Reply message */
1597 typedef struct _MPI2_FW_UPLOAD_REPLY {
1598     U8 ImageType;       /*0x00 */
1599     U8 Reserved1;       /*0x01 */
1600     U8 MsgLength;       /*0x02 */
1601     U8 Function;        /*0x03 */
1602     U16 Reserved2;      /*0x04 */
1603     U8 Reserved3;       /*0x06 */
1604     U8 MsgFlags;        /*0x07 */
1605     U8 VP_ID;       /*0x08 */
1606     U8 VF_ID;       /*0x09 */
1607     U16 Reserved4;      /*0x0A */
1608     U16 Reserved5;      /*0x0C */
1609     U16 IOCStatus;      /*0x0E */
1610     U32 IOCLogInfo;     /*0x10 */
1611     U32 ActualImageSize;    /*0x14 */
1612 } MPI2_FW_UPLOAD_REPLY, *PTR_MPI2_FW_UPLOAD_REPLY,
1613     Mpi2FWUploadReply_t, *pMPi2FWUploadReply_t;
1614
1615
1616 /****************************************************************************
1617 * PowerManagementControl message
1618 ****************************************************************************/
1619
1620 /*PowerManagementControl Request message */
1621 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST {
1622     U8 Feature;     /*0x00 */
1623     U8 Reserved1;       /*0x01 */
1624     U8 ChainOffset;     /*0x02 */
1625     U8 Function;        /*0x03 */
1626     U16 Reserved2;      /*0x04 */
1627     U8 Reserved3;       /*0x06 */
1628     U8 MsgFlags;        /*0x07 */
1629     U8 VP_ID;       /*0x08 */
1630     U8 VF_ID;       /*0x09 */
1631     U16 Reserved4;      /*0x0A */
1632     U8 Parameter1;      /*0x0C */
1633     U8 Parameter2;      /*0x0D */
1634     U8 Parameter3;      /*0x0E */
1635     U8 Parameter4;      /*0x0F */
1636     U32 Reserved5;      /*0x10 */
1637     U32 Reserved6;      /*0x14 */
1638 } MPI2_PWR_MGMT_CONTROL_REQUEST, *PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1639     Mpi2PwrMgmtControlRequest_t, *pMpi2PwrMgmtControlRequest_t;
1640
1641 /*defines for the Feature field */
1642 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND       (0x01)
1643 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION   (0x02)
1644 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK               (0x03)  /*obsolete */
1645 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED               (0x04)
1646 #define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE    (0x05)
1647 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC    (0x80)
1648 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC    (0xFF)
1649
1650 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1651 /*Parameter1 contains a PHY number */
1652 /*Parameter2 indicates power condition action using these defines */
1653 #define MPI2_PM_CONTROL_PARAM2_PARTIAL                  (0x01)
1654 #define MPI2_PM_CONTROL_PARAM2_SLUMBER                  (0x02)
1655 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT            (0x03)
1656 /*Parameter3 and Parameter4 are reserved */
1657
1658 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION
1659  * Feature */
1660 /*Parameter1 contains SAS port width modulation group number */
1661 /*Parameter2 indicates IOC action using these defines */
1662 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP        (0x01)
1663 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION        (0x02)
1664 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP     (0x03)
1665 /*Parameter3 indicates desired modulation level using these defines */
1666 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT               (0x00)
1667 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT               (0x01)
1668 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT               (0x02)
1669 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT              (0x03)
1670 /*Parameter4 is reserved */
1671
1672 /*this next set (_PCIE_LINK) is obsolete */
1673 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
1674 /*Parameter1 indicates desired PCIe link speed using these defines */
1675 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS            (0x00)  /*obsolete */
1676 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS            (0x01)  /*obsolete */
1677 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS            (0x02)  /*obsolete */
1678 /*Parameter2 indicates desired PCIe link width using these defines */
1679 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1                 (0x01)  /*obsolete */
1680 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2                 (0x02)  /*obsolete */
1681 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4                 (0x04)  /*obsolete */
1682 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8                 (0x08)  /*obsolete */
1683 /*Parameter3 and Parameter4 are reserved */
1684
1685 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
1686 /*Parameter1 indicates desired IOC hardware clock speed using these defines */
1687 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED           (0x01)
1688 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED           (0x02)
1689 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED        (0x04)
1690 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED         (0x08)
1691 /*Parameter2, Parameter3, and Parameter4 are reserved */
1692
1693 /*parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature*/
1694 /*Parameter1 indicates host action regarding global power management mode */
1695 #define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL             (0x01)
1696 #define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE       (0x02)
1697 #define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL          (0x03)
1698 /*Parameter2 indicates the requested global power management mode */
1699 #define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF            (0x01)
1700 #define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF         (0x08)
1701 #define MPI2_PM_CONTROL_PARAM2_STANDBY                  (0x40)
1702 /*Parameter3 and Parameter4 are reserved */
1703
1704 /*PowerManagementControl Reply message */
1705 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY {
1706     U8 Feature;     /*0x00 */
1707     U8 Reserved1;       /*0x01 */
1708     U8 MsgLength;       /*0x02 */
1709     U8 Function;        /*0x03 */
1710     U16 Reserved2;      /*0x04 */
1711     U8 Reserved3;       /*0x06 */
1712     U8 MsgFlags;        /*0x07 */
1713     U8 VP_ID;       /*0x08 */
1714     U8 VF_ID;       /*0x09 */
1715     U16 Reserved4;      /*0x0A */
1716     U16 Reserved5;      /*0x0C */
1717     U16 IOCStatus;      /*0x0E */
1718     U32 IOCLogInfo;     /*0x10 */
1719 } MPI2_PWR_MGMT_CONTROL_REPLY, *PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1720     Mpi2PwrMgmtControlReply_t, *pMpi2PwrMgmtControlReply_t;
1721
1722 /****************************************************************************
1723 *  IO Unit Control messages (MPI v2.6 and later only.)
1724 ****************************************************************************/
1725
1726 /* IO Unit Control Request Message */
1727 typedef struct _MPI26_IOUNIT_CONTROL_REQUEST {
1728     U8                      Operation;          /* 0x00 */
1729     U8                      Reserved1;          /* 0x01 */
1730     U8                      ChainOffset;        /* 0x02 */
1731     U8                      Function;           /* 0x03 */
1732     U16                     DevHandle;          /* 0x04 */
1733     U8                      IOCParameter;       /* 0x06 */
1734     U8                      MsgFlags;           /* 0x07 */
1735     U8                      VP_ID;              /* 0x08 */
1736     U8                      VF_ID;              /* 0x09 */
1737     U16                     Reserved3;          /* 0x0A */
1738     U16                     Reserved4;          /* 0x0C */
1739     U8                      PhyNum;             /* 0x0E */
1740     U8                      PrimFlags;          /* 0x0F */
1741     U32                     Primitive;          /* 0x10 */
1742     U8                      LookupMethod;       /* 0x14 */
1743     U8                      Reserved5;          /* 0x15 */
1744     U16                     SlotNumber;         /* 0x16 */
1745     U64                     LookupAddress;      /* 0x18 */
1746     U32                     IOCParameterValue;  /* 0x20 */
1747     U32                     Reserved7;          /* 0x24 */
1748     U32                     Reserved8;          /* 0x28 */
1749 } MPI26_IOUNIT_CONTROL_REQUEST,
1750     *PTR_MPI26_IOUNIT_CONTROL_REQUEST,
1751     Mpi26IoUnitControlRequest_t,
1752     *pMpi26IoUnitControlRequest_t;
1753
1754 /* values for the Operation field */
1755 #define MPI26_CTRL_OP_CLEAR_ALL_PERSISTENT              (0x02)
1756 #define MPI26_CTRL_OP_SAS_PHY_LINK_RESET                (0x06)
1757 #define MPI26_CTRL_OP_SAS_PHY_HARD_RESET                (0x07)
1758 #define MPI26_CTRL_OP_PHY_CLEAR_ERROR_LOG               (0x08)
1759 #define MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG              (0x09)
1760 #define MPI26_CTRL_OP_SAS_SEND_PRIMITIVE                (0x0A)
1761 #define MPI26_CTRL_OP_FORCE_FULL_DISCOVERY              (0x0B)
1762 #define MPI26_CTRL_OP_REMOVE_DEVICE                     (0x0D)
1763 #define MPI26_CTRL_OP_LOOKUP_MAPPING                    (0x0E)
1764 #define MPI26_CTRL_OP_SET_IOC_PARAMETER                 (0x0F)
1765 #define MPI26_CTRL_OP_ENABLE_FP_DEVICE                  (0x10)
1766 #define MPI26_CTRL_OP_DISABLE_FP_DEVICE                 (0x11)
1767 #define MPI26_CTRL_OP_ENABLE_FP_ALL                     (0x12)
1768 #define MPI26_CTRL_OP_DISABLE_FP_ALL                    (0x13)
1769 #define MPI26_CTRL_OP_DEV_ENABLE_NCQ                    (0x14)
1770 #define MPI26_CTRL_OP_DEV_DISABLE_NCQ                   (0x15)
1771 #define MPI26_CTRL_OP_SHUTDOWN                          (0x16)
1772 #define MPI26_CTRL_OP_DEV_ENABLE_PERSIST_CONNECTION     (0x17)
1773 #define MPI26_CTRL_OP_DEV_DISABLE_PERSIST_CONNECTION    (0x18)
1774 #define MPI26_CTRL_OP_DEV_CLOSE_PERSIST_CONNECTION      (0x19)
1775 #define MPI26_CTRL_OP_ENABLE_NVME_SGL_FORMAT            (0x1A)
1776 #define MPI26_CTRL_OP_DISABLE_NVME_SGL_FORMAT           (0x1B)
1777 #define MPI26_CTRL_OP_PRODUCT_SPECIFIC_MIN              (0x80)
1778
1779 /* values for the PrimFlags field */
1780 #define MPI26_CTRL_PRIMFLAGS_SINGLE                     (0x08)
1781 #define MPI26_CTRL_PRIMFLAGS_TRIPLE                     (0x02)
1782 #define MPI26_CTRL_PRIMFLAGS_REDUNDANT                  (0x01)
1783
1784 /* values for the LookupMethod field */
1785 #define MPI26_CTRL_LOOKUP_METHOD_WWID_ADDRESS           (0x01)
1786 #define MPI26_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT         (0x02)
1787 #define MPI26_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME        (0x03)
1788
1789
1790 /* IO Unit Control Reply Message */
1791 typedef struct _MPI26_IOUNIT_CONTROL_REPLY {
1792     U8                      Operation;          /* 0x00 */
1793     U8                      Reserved1;          /* 0x01 */
1794     U8                      MsgLength;          /* 0x02 */
1795     U8                      Function;           /* 0x03 */
1796     U16                     DevHandle;          /* 0x04 */
1797     U8                      IOCParameter;       /* 0x06 */
1798     U8                      MsgFlags;           /* 0x07 */
1799     U8                      VP_ID;              /* 0x08 */
1800     U8                      VF_ID;              /* 0x09 */
1801     U16                     Reserved3;          /* 0x0A */
1802     U16                     Reserved4;          /* 0x0C */
1803     U16                     IOCStatus;          /* 0x0E */
1804     U32                     IOCLogInfo;         /* 0x10 */
1805 } MPI26_IOUNIT_CONTROL_REPLY,
1806     *PTR_MPI26_IOUNIT_CONTROL_REPLY,
1807     Mpi26IoUnitControlReply_t,
1808     *pMpi26IoUnitControlReply_t;
1809
1810
1811 #endif