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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright 2000-2020 Broadcom Inc. All rights reserved.
0004  *
0005  *
0006  *          Name:  mpi2.h
0007  *         Title:  MPI Message independent structures and definitions
0008  *                 including System Interface Register Set and
0009  *                 scatter/gather formats.
0010  * Creation Date:  June 21, 2006
0011  *
0012  *  mpi2.h Version:  02.00.54
0013  *
0014  * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
0015  *       prefix are for use only on MPI v2.5 products, and must not be used
0016  *       with MPI v2.0 products. Unless otherwise noted, names beginning with
0017  *       MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
0018  *
0019  * Version History
0020  * ---------------
0021  *
0022  * Date      Version   Description
0023  * --------  --------  ------------------------------------------------------
0024  * 04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
0025  * 06-04-07  02.00.01  Bumped MPI2_HEADER_VERSION_UNIT.
0026  * 06-26-07  02.00.02  Bumped MPI2_HEADER_VERSION_UNIT.
0027  * 08-31-07  02.00.03  Bumped MPI2_HEADER_VERSION_UNIT.
0028  *                     Moved ReplyPostHostIndex register to offset 0x6C of the
0029  *                     MPI2_SYSTEM_INTERFACE_REGS and modified the define for
0030  *                     MPI2_REPLY_POST_HOST_INDEX_OFFSET.
0031  *                     Added union of request descriptors.
0032  *                     Added union of reply descriptors.
0033  * 10-31-07  02.00.04  Bumped MPI2_HEADER_VERSION_UNIT.
0034  *                     Added define for MPI2_VERSION_02_00.
0035  *                     Fixed the size of the FunctionDependent5 field in the
0036  *                     MPI2_DEFAULT_REPLY structure.
0037  * 12-18-07  02.00.05  Bumped MPI2_HEADER_VERSION_UNIT.
0038  *                     Removed the MPI-defined Fault Codes and extended the
0039  *                     product specific codes up to 0xEFFF.
0040  *                     Added a sixth key value for the WriteSequence register
0041  *                     and changed the flush value to 0x0.
0042  *                     Added message function codes for Diagnostic Buffer Post
0043  *                     and Diagnsotic Release.
0044  *                     New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
0045  *                     Moved MPI2_VERSION_UNION from mpi2_ioc.h.
0046  * 02-29-08  02.00.06  Bumped MPI2_HEADER_VERSION_UNIT.
0047  * 03-03-08  02.00.07  Bumped MPI2_HEADER_VERSION_UNIT.
0048  * 05-21-08  02.00.08  Bumped MPI2_HEADER_VERSION_UNIT.
0049  *                     Added #defines for marking a reply descriptor as unused.
0050  * 06-27-08  02.00.09  Bumped MPI2_HEADER_VERSION_UNIT.
0051  * 10-02-08  02.00.10  Bumped MPI2_HEADER_VERSION_UNIT.
0052  *                     Moved LUN field defines from mpi2_init.h.
0053  * 01-19-09  02.00.11  Bumped MPI2_HEADER_VERSION_UNIT.
0054  * 05-06-09  02.00.12  Bumped MPI2_HEADER_VERSION_UNIT.
0055  *                     In all request and reply descriptors, replaced VF_ID
0056  *                     field with MSIxIndex field.
0057  *                     Removed DevHandle field from
0058  *                     MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
0059  *                     bytes reserved.
0060  *                     Added RAID Accelerator functionality.
0061  * 07-30-09  02.00.13  Bumped MPI2_HEADER_VERSION_UNIT.
0062  * 10-28-09  02.00.14  Bumped MPI2_HEADER_VERSION_UNIT.
0063  *                     Added MSI-x index mask and shift for Reply Post Host
0064  *                     Index register.
0065  *                     Added function code for Host Based Discovery Action.
0066  * 02-10-10  02.00.15  Bumped MPI2_HEADER_VERSION_UNIT.
0067  *                     Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
0068  *                     Added defines for product-specific range of message
0069  *                     function codes, 0xF0 to 0xFF.
0070  * 05-12-10  02.00.16  Bumped MPI2_HEADER_VERSION_UNIT.
0071  *                     Added alternative defines for the SGE Direction bit.
0072  * 08-11-10  02.00.17  Bumped MPI2_HEADER_VERSION_UNIT.
0073  * 11-10-10  02.00.18  Bumped MPI2_HEADER_VERSION_UNIT.
0074  *                     Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
0075  * 02-23-11  02.00.19  Bumped MPI2_HEADER_VERSION_UNIT.
0076  *                     Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
0077  * 03-09-11  02.00.20  Bumped MPI2_HEADER_VERSION_UNIT.
0078  * 05-25-11  02.00.21  Bumped MPI2_HEADER_VERSION_UNIT.
0079  * 08-24-11  02.00.22  Bumped MPI2_HEADER_VERSION_UNIT.
0080  * 11-18-11  02.00.23  Bumped MPI2_HEADER_VERSION_UNIT.
0081  *                     Incorporating additions for MPI v2.5.
0082  * 02-06-12  02.00.24  Bumped MPI2_HEADER_VERSION_UNIT.
0083  * 03-29-12  02.00.25  Bumped MPI2_HEADER_VERSION_UNIT.
0084  *                     Added Hard Reset delay timings.
0085  * 07-10-12  02.00.26  Bumped MPI2_HEADER_VERSION_UNIT.
0086  * 07-26-12  02.00.27  Bumped MPI2_HEADER_VERSION_UNIT.
0087  * 11-27-12  02.00.28  Bumped MPI2_HEADER_VERSION_UNIT.
0088  * 12-20-12  02.00.29  Bumped MPI2_HEADER_VERSION_UNIT.
0089  *                     Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET.
0090  * 04-09-13  02.00.30  Bumped MPI2_HEADER_VERSION_UNIT.
0091  * 04-17-13  02.00.31  Bumped MPI2_HEADER_VERSION_UNIT.
0092  * 08-19-13  02.00.32  Bumped MPI2_HEADER_VERSION_UNIT.
0093  * 12-05-13  02.00.33  Bumped MPI2_HEADER_VERSION_UNIT.
0094  * 01-08-14  02.00.34  Bumped MPI2_HEADER_VERSION_UNIT
0095  * 06-13-14  02.00.35  Bumped MPI2_HEADER_VERSION_UNIT.
0096  * 11-18-14  02.00.36  Updated copyright information.
0097  *                     Bumped MPI2_HEADER_VERSION_UNIT.
0098  * 03-16-15  02.00.37  Bumped MPI2_HEADER_VERSION_UNIT.
0099  *                     Added Scratchpad registers to
0100  *                     MPI2_SYSTEM_INTERFACE_REGS.
0101  *                     Added MPI2_DIAG_SBR_RELOAD.
0102  * 03-19-15  02.00.38  Bumped MPI2_HEADER_VERSION_UNIT.
0103  * 05-25-15  02.00.39  Bumped MPI2_HEADER_VERSION_UNIT.
0104  * 08-25-15  02.00.40  Bumped MPI2_HEADER_VERSION_UNIT.
0105  * 12-15-15  02.00.41  Bumped MPI_HEADER_VERSION_UNIT
0106  * 01-01-16  02.00.42  Bumped MPI_HEADER_VERSION_UNIT
0107  * 04-05-16  02.00.43  Modified  MPI26_DIAG_BOOT_DEVICE_SELECT defines
0108  *                     to be unique within first 32 characters.
0109  *                     Removed AHCI support.
0110  *                     Removed SOP support.
0111  *                     Bumped MPI2_HEADER_VERSION_UNIT.
0112  * 04-10-16  02.00.44  Bumped MPI2_HEADER_VERSION_UNIT.
0113  * 07-06-16  02.00.45  Bumped MPI2_HEADER_VERSION_UNIT.
0114  * 09-02-16  02.00.46  Bumped MPI2_HEADER_VERSION_UNIT.
0115  * 11-23-16  02.00.47  Bumped MPI2_HEADER_VERSION_UNIT.
0116  * 02-03-17  02.00.48  Bumped MPI2_HEADER_VERSION_UNIT.
0117  * 06-13-17  02.00.49  Bumped MPI2_HEADER_VERSION_UNIT.
0118  * 09-29-17  02.00.50  Bumped MPI2_HEADER_VERSION_UNIT.
0119  * 07-22-18  02.00.51  Added SECURE_BOOT define.
0120  *                     Bumped MPI2_HEADER_VERSION_UNIT
0121  * 08-15-18  02.00.52  Bumped MPI2_HEADER_VERSION_UNIT.
0122  * 08-28-18  02.00.53  Bumped MPI2_HEADER_VERSION_UNIT.
0123  *                     Added MPI2_IOCSTATUS_FAILURE
0124  * 12-17-18  02.00.54  Bumped MPI2_HEADER_VERSION_UNIT
0125  * 06-24-19  02.00.55  Bumped MPI2_HEADER_VERSION_UNIT
0126  * 08-01-19  02.00.56  Bumped MPI2_HEADER_VERSION_UNIT
0127  * 10-02-19  02.00.57  Bumped MPI2_HEADER_VERSION_UNIT
0128  *  --------------------------------------------------------------------------
0129  */
0130 
0131 #ifndef MPI2_H
0132 #define MPI2_H
0133 
0134 /*****************************************************************************
0135 *
0136 *       MPI Version Definitions
0137 *
0138 *****************************************************************************/
0139 
0140 #define MPI2_VERSION_MAJOR_MASK             (0xFF00)
0141 #define MPI2_VERSION_MAJOR_SHIFT            (8)
0142 #define MPI2_VERSION_MINOR_MASK             (0x00FF)
0143 #define MPI2_VERSION_MINOR_SHIFT            (0)
0144 
0145 /*major version for all MPI v2.x */
0146 #define MPI2_VERSION_MAJOR                  (0x02)
0147 
0148 /*minor version for MPI v2.0 compatible products */
0149 #define MPI2_VERSION_MINOR                  (0x00)
0150 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
0151                     MPI2_VERSION_MINOR)
0152 #define MPI2_VERSION_02_00                  (0x0200)
0153 
0154 /*minor version for MPI v2.5 compatible products */
0155 #define MPI25_VERSION_MINOR                 (0x05)
0156 #define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
0157                     MPI25_VERSION_MINOR)
0158 #define MPI2_VERSION_02_05                  (0x0205)
0159 
0160 /*minor version for MPI v2.6 compatible products */
0161 #define MPI26_VERSION_MINOR         (0x06)
0162 #define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
0163                     MPI26_VERSION_MINOR)
0164 #define MPI2_VERSION_02_06          (0x0206)
0165 
0166 
0167 /* Unit and Dev versioning for this MPI header set */
0168 #define MPI2_HEADER_VERSION_UNIT            (0x39)
0169 #define MPI2_HEADER_VERSION_DEV             (0x00)
0170 #define MPI2_HEADER_VERSION_UNIT_MASK       (0xFF00)
0171 #define MPI2_HEADER_VERSION_UNIT_SHIFT      (8)
0172 #define MPI2_HEADER_VERSION_DEV_MASK        (0x00FF)
0173 #define MPI2_HEADER_VERSION_DEV_SHIFT       (0)
0174 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
0175                     MPI2_HEADER_VERSION_DEV)
0176 
0177 /*****************************************************************************
0178 *
0179 *       IOC State Definitions
0180 *
0181 *****************************************************************************/
0182 
0183 #define MPI2_IOC_STATE_RESET               (0x00000000)
0184 #define MPI2_IOC_STATE_READY               (0x10000000)
0185 #define MPI2_IOC_STATE_OPERATIONAL         (0x20000000)
0186 #define MPI2_IOC_STATE_FAULT               (0x40000000)
0187 #define MPI2_IOC_STATE_COREDUMP            (0x50000000)
0188 
0189 #define MPI2_IOC_STATE_MASK                (0xF0000000)
0190 #define MPI2_IOC_STATE_SHIFT               (28)
0191 
0192 /*Fault state range for prodcut specific codes */
0193 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN                 (0x0000)
0194 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX                 (0xEFFF)
0195 
0196 /*****************************************************************************
0197 *
0198 *       System Interface Register Definitions
0199 *
0200 *****************************************************************************/
0201 
0202 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS {
0203     U32 Doorbell;       /*0x00 */
0204     U32 WriteSequence;  /*0x04 */
0205     U32 HostDiagnostic; /*0x08 */
0206     U32 Reserved1;      /*0x0C */
0207     U32 DiagRWData;     /*0x10 */
0208     U32 DiagRWAddressLow;   /*0x14 */
0209     U32 DiagRWAddressHigh;  /*0x18 */
0210     U32 Reserved2[5];   /*0x1C */
0211     U32 HostInterruptStatus;    /*0x30 */
0212     U32 HostInterruptMask;  /*0x34 */
0213     U32 DCRData;        /*0x38 */
0214     U32 DCRAddress;     /*0x3C */
0215     U32 Reserved3[2];   /*0x40 */
0216     U32 ReplyFreeHostIndex; /*0x48 */
0217     U32 Reserved4[8];   /*0x4C */
0218     U32 ReplyPostHostIndex; /*0x6C */
0219     U32 Reserved5;      /*0x70 */
0220     U32 HCBSize;        /*0x74 */
0221     U32 HCBAddressLow;  /*0x78 */
0222     U32 HCBAddressHigh; /*0x7C */
0223     U32 Reserved6[12];  /*0x80 */
0224     U32 Scratchpad[4];  /*0xB0 */
0225     U32 RequestDescriptorPostLow;   /*0xC0 */
0226     U32 RequestDescriptorPostHigh;  /*0xC4 */
0227     U32 AtomicRequestDescriptorPost;/*0xC8 */
0228     U32 Reserved7[13];  /*0xCC */
0229 } MPI2_SYSTEM_INTERFACE_REGS,
0230     *PTR_MPI2_SYSTEM_INTERFACE_REGS,
0231     Mpi2SystemInterfaceRegs_t,
0232     *pMpi2SystemInterfaceRegs_t;
0233 
0234 /*
0235  *Defines for working with the Doorbell register.
0236  */
0237 #define MPI2_DOORBELL_OFFSET                    (0x00000000)
0238 
0239 /*IOC --> System values */
0240 #define MPI2_DOORBELL_USED                      (0x08000000)
0241 #define MPI2_DOORBELL_WHO_INIT_MASK             (0x07000000)
0242 #define MPI2_DOORBELL_WHO_INIT_SHIFT            (24)
0243 #define MPI2_DOORBELL_FAULT_CODE_MASK           (0x0000FFFF)
0244 #define MPI2_DOORBELL_DATA_MASK                 (0x0000FFFF)
0245 
0246 /*System --> IOC values */
0247 #define MPI2_DOORBELL_FUNCTION_MASK             (0xFF000000)
0248 #define MPI2_DOORBELL_FUNCTION_SHIFT            (24)
0249 #define MPI2_DOORBELL_ADD_DWORDS_MASK           (0x00FF0000)
0250 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT          (16)
0251 
0252 /*
0253  *Defines for the WriteSequence register
0254  */
0255 #define MPI2_WRITE_SEQUENCE_OFFSET              (0x00000004)
0256 #define MPI2_WRSEQ_KEY_VALUE_MASK               (0x0000000F)
0257 #define MPI2_WRSEQ_FLUSH_KEY_VALUE              (0x0)
0258 #define MPI2_WRSEQ_1ST_KEY_VALUE                (0xF)
0259 #define MPI2_WRSEQ_2ND_KEY_VALUE                (0x4)
0260 #define MPI2_WRSEQ_3RD_KEY_VALUE                (0xB)
0261 #define MPI2_WRSEQ_4TH_KEY_VALUE                (0x2)
0262 #define MPI2_WRSEQ_5TH_KEY_VALUE                (0x7)
0263 #define MPI2_WRSEQ_6TH_KEY_VALUE                (0xD)
0264 
0265 /*
0266  *Defines for the HostDiagnostic register
0267  */
0268 #define MPI2_HOST_DIAGNOSTIC_OFFSET             (0x00000008)
0269 
0270 #define MPI26_DIAG_SECURE_BOOT                  (0x80000000)
0271 
0272 #define MPI2_DIAG_SBR_RELOAD                    (0x00002000)
0273 
0274 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK       (0x00001800)
0275 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT    (0x00000000)
0276 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW       (0x00000800)
0277 
0278 /* Defines for V7A/V7R HostDiagnostic Register */
0279 #define MPI26_DIAG_BOOT_DEVICE_SEL_64FLASH      (0x00000000)
0280 #define MPI26_DIAG_BOOT_DEVICE_SEL_64HCDW       (0x00000800)
0281 #define MPI26_DIAG_BOOT_DEVICE_SEL_32FLASH      (0x00001000)
0282 #define MPI26_DIAG_BOOT_DEVICE_SEL_32HCDW       (0x00001800)
0283 
0284 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG           (0x00000400)
0285 #define MPI2_DIAG_FORCE_HCB_ON_RESET            (0x00000200)
0286 #define MPI2_DIAG_HCB_MODE                      (0x00000100)
0287 #define MPI2_DIAG_DIAG_WRITE_ENABLE             (0x00000080)
0288 #define MPI2_DIAG_FLASH_BAD_SIG                 (0x00000040)
0289 #define MPI2_DIAG_RESET_HISTORY                 (0x00000020)
0290 #define MPI2_DIAG_DIAG_RW_ENABLE                (0x00000010)
0291 #define MPI2_DIAG_RESET_ADAPTER                 (0x00000004)
0292 #define MPI2_DIAG_HOLD_IOC_RESET                (0x00000002)
0293 
0294 /*
0295  *Offsets for DiagRWData and address
0296  */
0297 #define MPI2_DIAG_RW_DATA_OFFSET                (0x00000010)
0298 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET         (0x00000014)
0299 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET        (0x00000018)
0300 
0301 /*
0302  *Defines for the HostInterruptStatus register
0303  */
0304 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET       (0x00000030)
0305 #define MPI2_HIS_SYS2IOC_DB_STATUS              (0x80000000)
0306 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
0307 #define MPI2_HIS_RESET_IRQ_STATUS               (0x40000000)
0308 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT     (0x00000008)
0309 #define MPI2_HIS_IOC2SYS_DB_STATUS              (0x00000001)
0310 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
0311 
0312 /*
0313  *Defines for the HostInterruptMask register
0314  */
0315 #define MPI2_HOST_INTERRUPT_MASK_OFFSET         (0x00000034)
0316 #define MPI2_HIM_RESET_IRQ_MASK                 (0x40000000)
0317 #define MPI2_HIM_REPLY_INT_MASK                 (0x00000008)
0318 #define MPI2_HIM_RIM                            MPI2_HIM_REPLY_INT_MASK
0319 #define MPI2_HIM_IOC2SYS_DB_MASK                (0x00000001)
0320 #define MPI2_HIM_DIM                            MPI2_HIM_IOC2SYS_DB_MASK
0321 
0322 /*
0323  *Offsets for DCRData and address
0324  */
0325 #define MPI2_DCR_DATA_OFFSET                    (0x00000038)
0326 #define MPI2_DCR_ADDRESS_OFFSET                 (0x0000003C)
0327 
0328 /*
0329  *Offset for the Reply Free Queue
0330  */
0331 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET       (0x00000048)
0332 
0333 /*
0334  *Defines for the Reply Descriptor Post Queue
0335  */
0336 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET       (0x0000006C)
0337 #define MPI2_REPLY_POST_HOST_INDEX_MASK         (0x00FFFFFF)
0338 #define MPI2_RPHI_MSIX_INDEX_MASK               (0xFF000000)
0339 #define MPI2_RPHI_MSIX_INDEX_SHIFT              (24)
0340 #define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET  (0x0000030C) /*MPI v2.5 only*/
0341 
0342 
0343 /*
0344  *Defines for the HCBSize and address
0345  */
0346 #define MPI2_HCB_SIZE_OFFSET                    (0x00000074)
0347 #define MPI2_HCB_SIZE_SIZE_MASK                 (0xFFFFF000)
0348 #define MPI2_HCB_SIZE_HCB_ENABLE                (0x00000001)
0349 
0350 #define MPI2_HCB_ADDRESS_LOW_OFFSET             (0x00000078)
0351 #define MPI2_HCB_ADDRESS_HIGH_OFFSET            (0x0000007C)
0352 
0353 /*
0354  *Offsets for the Scratchpad registers
0355  */
0356 #define MPI26_SCRATCHPAD0_OFFSET                (0x000000B0)
0357 #define MPI26_SCRATCHPAD1_OFFSET                (0x000000B4)
0358 #define MPI26_SCRATCHPAD2_OFFSET                (0x000000B8)
0359 #define MPI26_SCRATCHPAD3_OFFSET                (0x000000BC)
0360 
0361 /*
0362  *Offsets for the Request Descriptor Post Queue
0363  */
0364 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET     (0x000000C0)
0365 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET    (0x000000C4)
0366 #define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8)
0367 
0368 /*Hard Reset delay timings */
0369 #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC     (50000)
0370 #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC    (255000)
0371 #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC    (256000)
0372 
0373 /*****************************************************************************
0374 *
0375 *       Message Descriptors
0376 *
0377 *****************************************************************************/
0378 
0379 /*Request Descriptors */
0380 
0381 /*Default Request Descriptor */
0382 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR {
0383     U8 RequestFlags;    /*0x00 */
0384     U8 MSIxIndex;       /*0x01 */
0385     U16 SMID;       /*0x02 */
0386     U16 LMID;       /*0x04 */
0387     U16 DescriptorTypeDependent;    /*0x06 */
0388 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
0389     *PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
0390     Mpi2DefaultRequestDescriptor_t,
0391     *pMpi2DefaultRequestDescriptor_t;
0392 
0393 /*defines for the RequestFlags field */
0394 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK               (0x1E)
0395 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT             (1)
0396 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO                 (0x00)
0397 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET             (0x02)
0398 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY           (0x06)
0399 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE            (0x08)
0400 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR        (0x0A)
0401 #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO      (0x0C)
0402 #define MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED      (0x10)
0403 
0404 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER         (0x01)
0405 
0406 /*High Priority Request Descriptor */
0407 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
0408     U8 RequestFlags;    /*0x00 */
0409     U8 MSIxIndex;       /*0x01 */
0410     U16 SMID;       /*0x02 */
0411     U16 LMID;       /*0x04 */
0412     U16 Reserved1;      /*0x06 */
0413 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
0414     *PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
0415     Mpi2HighPriorityRequestDescriptor_t,
0416     *pMpi2HighPriorityRequestDescriptor_t;
0417 
0418 /*SCSI IO Request Descriptor */
0419 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
0420     U8 RequestFlags;    /*0x00 */
0421     U8 MSIxIndex;       /*0x01 */
0422     U16 SMID;       /*0x02 */
0423     U16 LMID;       /*0x04 */
0424     U16 DevHandle;      /*0x06 */
0425 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
0426     *PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
0427     Mpi2SCSIIORequestDescriptor_t,
0428     *pMpi2SCSIIORequestDescriptor_t;
0429 
0430 /*SCSI Target Request Descriptor */
0431 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
0432     U8 RequestFlags;    /*0x00 */
0433     U8 MSIxIndex;       /*0x01 */
0434     U16 SMID;       /*0x02 */
0435     U16 LMID;       /*0x04 */
0436     U16 IoIndex;        /*0x06 */
0437 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
0438     *PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
0439     Mpi2SCSITargetRequestDescriptor_t,
0440     *pMpi2SCSITargetRequestDescriptor_t;
0441 
0442 /*RAID Accelerator Request Descriptor */
0443 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
0444     U8 RequestFlags;    /*0x00 */
0445     U8 MSIxIndex;       /*0x01 */
0446     U16 SMID;       /*0x02 */
0447     U16 LMID;       /*0x04 */
0448     U16 Reserved;       /*0x06 */
0449 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
0450     *PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
0451     Mpi2RAIDAcceleratorRequestDescriptor_t,
0452     *pMpi2RAIDAcceleratorRequestDescriptor_t;
0453 
0454 /*Fast Path SCSI IO Request Descriptor */
0455 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
0456     MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
0457     *PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
0458     Mpi25FastPathSCSIIORequestDescriptor_t,
0459     *pMpi25FastPathSCSIIORequestDescriptor_t;
0460 
0461 /*PCIe Encapsulated Request Descriptor */
0462 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
0463     MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR,
0464     *PTR_MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR,
0465     Mpi26PCIeEncapsulatedRequestDescriptor_t,
0466     *pMpi26PCIeEncapsulatedRequestDescriptor_t;
0467 
0468 /*union of Request Descriptors */
0469 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION {
0470     MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
0471     MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
0472     MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
0473     MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
0474     MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
0475     MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO;
0476     MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR PCIeEncapsulated;
0477     U64 Words;
0478 } MPI2_REQUEST_DESCRIPTOR_UNION,
0479     *PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
0480     Mpi2RequestDescriptorUnion_t,
0481     *pMpi2RequestDescriptorUnion_t;
0482 
0483 /*Atomic Request Descriptors */
0484 
0485 /*
0486  * All Atomic Request Descriptors have the same format, so the following
0487  * structure is used for all Atomic Request Descriptors:
0488  *      Atomic Default Request Descriptor
0489  *      Atomic High Priority Request Descriptor
0490  *      Atomic SCSI IO Request Descriptor
0491  *      Atomic SCSI Target Request Descriptor
0492  *      Atomic RAID Accelerator Request Descriptor
0493  *      Atomic Fast Path SCSI IO Request Descriptor
0494  *      Atomic PCIe Encapsulated Request Descriptor
0495  */
0496 
0497 /*Atomic Request Descriptor */
0498 typedef struct _MPI26_ATOMIC_REQUEST_DESCRIPTOR {
0499     U8 RequestFlags;    /* 0x00 */
0500     U8 MSIxIndex;       /* 0x01 */
0501     U16 SMID;       /* 0x02 */
0502 } MPI26_ATOMIC_REQUEST_DESCRIPTOR,
0503     *PTR_MPI26_ATOMIC_REQUEST_DESCRIPTOR,
0504     Mpi26AtomicRequestDescriptor_t,
0505     *pMpi26AtomicRequestDescriptor_t;
0506 
0507 /*for the RequestFlags field, use the same
0508  *defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR
0509  */
0510 
0511 /*Reply Descriptors */
0512 
0513 /*Default Reply Descriptor */
0514 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR {
0515     U8 ReplyFlags;      /*0x00 */
0516     U8 MSIxIndex;       /*0x01 */
0517     U16 DescriptorTypeDependent1;   /*0x02 */
0518     U32 DescriptorTypeDependent2;   /*0x04 */
0519 } MPI2_DEFAULT_REPLY_DESCRIPTOR,
0520     *PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
0521     Mpi2DefaultReplyDescriptor_t,
0522     *pMpi2DefaultReplyDescriptor_t;
0523 
0524 /*defines for the ReplyFlags field */
0525 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK                   (0x0F)
0526 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS             (0x00)
0527 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY               (0x01)
0528 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS        (0x02)
0529 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER       (0x03)
0530 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS    (0x05)
0531 #define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS  (0x06)
0532 #define MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS  (0x08)
0533 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED                      (0x0F)
0534 
0535 /*values for marking a reply descriptor as unused */
0536 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK             (0xFFFFFFFF)
0537 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK             (0xFFFFFFFF)
0538 
0539 /*Address Reply Descriptor */
0540 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR {
0541     U8 ReplyFlags;      /*0x00 */
0542     U8 MSIxIndex;       /*0x01 */
0543     U16 SMID;       /*0x02 */
0544     U32 ReplyFrameAddress;  /*0x04 */
0545 } MPI2_ADDRESS_REPLY_DESCRIPTOR,
0546     *PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
0547     Mpi2AddressReplyDescriptor_t,
0548     *pMpi2AddressReplyDescriptor_t;
0549 
0550 #define MPI2_ADDRESS_REPLY_SMID_INVALID                 (0x00)
0551 
0552 /*SCSI IO Success Reply Descriptor */
0553 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
0554     U8 ReplyFlags;      /*0x00 */
0555     U8 MSIxIndex;       /*0x01 */
0556     U16 SMID;       /*0x02 */
0557     U16 TaskTag;        /*0x04 */
0558     U16 Reserved1;      /*0x06 */
0559 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
0560     *PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
0561     Mpi2SCSIIOSuccessReplyDescriptor_t,
0562     *pMpi2SCSIIOSuccessReplyDescriptor_t;
0563 
0564 /*TargetAssist Success Reply Descriptor */
0565 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
0566     U8 ReplyFlags;      /*0x00 */
0567     U8 MSIxIndex;       /*0x01 */
0568     U16 SMID;       /*0x02 */
0569     U8 SequenceNumber;  /*0x04 */
0570     U8 Reserved1;       /*0x05 */
0571     U16 IoIndex;        /*0x06 */
0572 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
0573     *PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
0574     Mpi2TargetAssistSuccessReplyDescriptor_t,
0575     *pMpi2TargetAssistSuccessReplyDescriptor_t;
0576 
0577 /*Target Command Buffer Reply Descriptor */
0578 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
0579     U8 ReplyFlags;      /*0x00 */
0580     U8 MSIxIndex;       /*0x01 */
0581     U8 VP_ID;       /*0x02 */
0582     U8 Flags;       /*0x03 */
0583     U16 InitiatorDevHandle; /*0x04 */
0584     U16 IoIndex;        /*0x06 */
0585 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
0586     *PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
0587     Mpi2TargetCommandBufferReplyDescriptor_t,
0588     *pMpi2TargetCommandBufferReplyDescriptor_t;
0589 
0590 /*defines for Flags field */
0591 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK     (0x3F)
0592 
0593 /*RAID Accelerator Success Reply Descriptor */
0594 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
0595     U8 ReplyFlags;      /*0x00 */
0596     U8 MSIxIndex;       /*0x01 */
0597     U16 SMID;       /*0x02 */
0598     U32 Reserved;       /*0x04 */
0599 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
0600     *PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
0601     Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
0602     *pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
0603 
0604 /*Fast Path SCSI IO Success Reply Descriptor */
0605 typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
0606     MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
0607     *PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
0608     Mpi25FastPathSCSIIOSuccessReplyDescriptor_t,
0609     *pMpi25FastPathSCSIIOSuccessReplyDescriptor_t;
0610 
0611 /*PCIe Encapsulated Success Reply Descriptor */
0612 typedef MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
0613     MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR,
0614     *PTR_MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR,
0615     Mpi26PCIeEncapsulatedSuccessReplyDescriptor_t,
0616     *pMpi26PCIeEncapsulatedSuccessReplyDescriptor_t;
0617 
0618 /*union of Reply Descriptors */
0619 typedef union _MPI2_REPLY_DESCRIPTORS_UNION {
0620     MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
0621     MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
0622     MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
0623     MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
0624     MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
0625     MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
0626     MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess;
0627     MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR
0628                         PCIeEncapsulatedSuccess;
0629     U64 Words;
0630 } MPI2_REPLY_DESCRIPTORS_UNION,
0631     *PTR_MPI2_REPLY_DESCRIPTORS_UNION,
0632     Mpi2ReplyDescriptorsUnion_t,
0633     *pMpi2ReplyDescriptorsUnion_t;
0634 
0635 /*****************************************************************************
0636 *
0637 *       Message Functions
0638 *
0639 *****************************************************************************/
0640 
0641 #define MPI2_FUNCTION_SCSI_IO_REQUEST           (0x00)
0642 #define MPI2_FUNCTION_SCSI_TASK_MGMT            (0x01)
0643 #define MPI2_FUNCTION_IOC_INIT                      (0x02)
0644 #define MPI2_FUNCTION_IOC_FACTS                     (0x03)
0645 #define MPI2_FUNCTION_CONFIG                        (0x04)
0646 #define MPI2_FUNCTION_PORT_FACTS                    (0x05)
0647 #define MPI2_FUNCTION_PORT_ENABLE                   (0x06)
0648 #define MPI2_FUNCTION_EVENT_NOTIFICATION            (0x07)
0649 #define MPI2_FUNCTION_EVENT_ACK                     (0x08)
0650 #define MPI2_FUNCTION_FW_DOWNLOAD                   (0x09)
0651 #define MPI2_FUNCTION_TARGET_ASSIST                 (0x0B)
0652 #define MPI2_FUNCTION_TARGET_STATUS_SEND            (0x0C)
0653 #define MPI2_FUNCTION_TARGET_MODE_ABORT             (0x0D)
0654 #define MPI2_FUNCTION_FW_UPLOAD                     (0x12)
0655 #define MPI2_FUNCTION_RAID_ACTION                   (0x15)
0656 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH      (0x16)
0657 #define MPI2_FUNCTION_TOOLBOX                       (0x17)
0658 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR      (0x18)
0659 #define MPI2_FUNCTION_SMP_PASSTHROUGH               (0x1A)
0660 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL           (0x1B)
0661 #define MPI2_FUNCTION_IO_UNIT_CONTROL               (0x1B)
0662 #define MPI2_FUNCTION_SATA_PASSTHROUGH              (0x1C)
0663 #define MPI2_FUNCTION_DIAG_BUFFER_POST              (0x1D)
0664 #define MPI2_FUNCTION_DIAG_RELEASE                  (0x1E)
0665 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST      (0x24)
0666 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST      (0x25)
0667 #define MPI2_FUNCTION_RAID_ACCELERATOR              (0x2C)
0668 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION   (0x2F)
0669 #define MPI2_FUNCTION_PWR_MGMT_CONTROL              (0x30)
0670 #define MPI2_FUNCTION_SEND_HOST_MESSAGE             (0x31)
0671 #define MPI2_FUNCTION_NVME_ENCAPSULATED             (0x33)
0672 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC          (0xF0)
0673 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC          (0xFF)
0674 
0675 /*Doorbell functions */
0676 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET        (0x40)
0677 #define MPI2_FUNCTION_HANDSHAKE                     (0x42)
0678 
0679 /*****************************************************************************
0680 *
0681 *       IOC Status Values
0682 *
0683 *****************************************************************************/
0684 
0685 /*mask for IOCStatus status value */
0686 #define MPI2_IOCSTATUS_MASK                     (0x7FFF)
0687 
0688 /****************************************************************************
0689 * Common IOCStatus values for all replies
0690 ****************************************************************************/
0691 
0692 #define MPI2_IOCSTATUS_SUCCESS                      (0x0000)
0693 #define MPI2_IOCSTATUS_INVALID_FUNCTION             (0x0001)
0694 #define MPI2_IOCSTATUS_BUSY                         (0x0002)
0695 #define MPI2_IOCSTATUS_INVALID_SGL                  (0x0003)
0696 #define MPI2_IOCSTATUS_INTERNAL_ERROR               (0x0004)
0697 #define MPI2_IOCSTATUS_INVALID_VPID                 (0x0005)
0698 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES       (0x0006)
0699 #define MPI2_IOCSTATUS_INVALID_FIELD                (0x0007)
0700 #define MPI2_IOCSTATUS_INVALID_STATE                (0x0008)
0701 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED       (0x0009)
0702 /*MPI v2.6 and later */
0703 #define MPI2_IOCSTATUS_INSUFFICIENT_POWER           (0x000A)
0704 #define MPI2_IOCSTATUS_FAILURE                      (0x000F)
0705 
0706 /****************************************************************************
0707 * Config IOCStatus values
0708 ****************************************************************************/
0709 
0710 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION        (0x0020)
0711 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE          (0x0021)
0712 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE          (0x0022)
0713 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA          (0x0023)
0714 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS           (0x0024)
0715 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT           (0x0025)
0716 
0717 /****************************************************************************
0718 * SCSI IO Reply
0719 ****************************************************************************/
0720 
0721 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR         (0x0040)
0722 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE       (0x0042)
0723 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE        (0x0043)
0724 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN            (0x0044)
0725 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN           (0x0045)
0726 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR           (0x0046)
0727 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR          (0x0047)
0728 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED         (0x0048)
0729 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH       (0x0049)
0730 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED        (0x004A)
0731 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED          (0x004B)
0732 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED          (0x004C)
0733 
0734 /****************************************************************************
0735 * For use by SCSI Initiator and SCSI Target end-to-end data protection
0736 ****************************************************************************/
0737 
0738 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR             (0x004D)
0739 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR           (0x004E)
0740 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR           (0x004F)
0741 
0742 /****************************************************************************
0743 * SCSI Target values
0744 ****************************************************************************/
0745 
0746 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX      (0x0062)
0747 #define MPI2_IOCSTATUS_TARGET_ABORTED               (0x0063)
0748 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE     (0x0064)
0749 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION         (0x0065)
0750 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH   (0x006A)
0751 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR     (0x006D)
0752 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA   (0x006E)
0753 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT          (0x006F)
0754 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT       (0x0070)
0755 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED          (0x0071)
0756 
0757 /****************************************************************************
0758 * Serial Attached SCSI values
0759 ****************************************************************************/
0760 
0761 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED       (0x0090)
0762 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN         (0x0091)
0763 
0764 /****************************************************************************
0765 * Diagnostic Buffer Post / Diagnostic Release values
0766 ****************************************************************************/
0767 
0768 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED          (0x00A0)
0769 
0770 /****************************************************************************
0771 * RAID Accelerator values
0772 ****************************************************************************/
0773 
0774 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR             (0x00B0)
0775 
0776 /****************************************************************************
0777 * IOCStatus flag to indicate that log info is available
0778 ****************************************************************************/
0779 
0780 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE      (0x8000)
0781 
0782 /****************************************************************************
0783 * IOCLogInfo Types
0784 ****************************************************************************/
0785 
0786 #define MPI2_IOCLOGINFO_TYPE_MASK               (0xF0000000)
0787 #define MPI2_IOCLOGINFO_TYPE_SHIFT              (28)
0788 #define MPI2_IOCLOGINFO_TYPE_NONE               (0x0)
0789 #define MPI2_IOCLOGINFO_TYPE_SCSI               (0x1)
0790 #define MPI2_IOCLOGINFO_TYPE_FC                 (0x2)
0791 #define MPI2_IOCLOGINFO_TYPE_SAS                (0x3)
0792 #define MPI2_IOCLOGINFO_TYPE_ISCSI              (0x4)
0793 #define MPI2_IOCLOGINFO_LOG_DATA_MASK           (0x0FFFFFFF)
0794 
0795 /*****************************************************************************
0796 *
0797 *       Standard Message Structures
0798 *
0799 *****************************************************************************/
0800 
0801 /****************************************************************************
0802 *Request Message Header for all request messages
0803 ****************************************************************************/
0804 
0805 typedef struct _MPI2_REQUEST_HEADER {
0806     U16 FunctionDependent1; /*0x00 */
0807     U8 ChainOffset;     /*0x02 */
0808     U8 Function;        /*0x03 */
0809     U16 FunctionDependent2; /*0x04 */
0810     U8 FunctionDependent3;  /*0x06 */
0811     U8 MsgFlags;        /*0x07 */
0812     U8 VP_ID;       /*0x08 */
0813     U8 VF_ID;       /*0x09 */
0814     U16 Reserved1;      /*0x0A */
0815 } MPI2_REQUEST_HEADER, *PTR_MPI2_REQUEST_HEADER,
0816     MPI2RequestHeader_t, *pMPI2RequestHeader_t;
0817 
0818 /****************************************************************************
0819 * Default Reply
0820 ****************************************************************************/
0821 
0822 typedef struct _MPI2_DEFAULT_REPLY {
0823     U16 FunctionDependent1; /*0x00 */
0824     U8 MsgLength;       /*0x02 */
0825     U8 Function;        /*0x03 */
0826     U16 FunctionDependent2; /*0x04 */
0827     U8 FunctionDependent3;  /*0x06 */
0828     U8 MsgFlags;        /*0x07 */
0829     U8 VP_ID;       /*0x08 */
0830     U8 VF_ID;       /*0x09 */
0831     U16 Reserved1;      /*0x0A */
0832     U16 FunctionDependent5; /*0x0C */
0833     U16 IOCStatus;      /*0x0E */
0834     U32 IOCLogInfo;     /*0x10 */
0835 } MPI2_DEFAULT_REPLY, *PTR_MPI2_DEFAULT_REPLY,
0836     MPI2DefaultReply_t, *pMPI2DefaultReply_t;
0837 
0838 /*common version structure/union used in messages and configuration pages */
0839 
0840 typedef struct _MPI2_VERSION_STRUCT {
0841     U8 Dev;         /*0x00 */
0842     U8 Unit;        /*0x01 */
0843     U8 Minor;       /*0x02 */
0844     U8 Major;       /*0x03 */
0845 } MPI2_VERSION_STRUCT;
0846 
0847 typedef union _MPI2_VERSION_UNION {
0848     MPI2_VERSION_STRUCT Struct;
0849     U32 Word;
0850 } MPI2_VERSION_UNION;
0851 
0852 /*LUN field defines, common to many structures */
0853 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING             (0x0000FFFF)
0854 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING            (0xFFFF0000)
0855 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING             (0x0000FFFF)
0856 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING            (0xFFFF0000)
0857 #define MPI2_LUN_LEVEL_1_WORD                       (0xFF00)
0858 #define MPI2_LUN_LEVEL_1_DWORD                      (0x0000FF00)
0859 
0860 /*****************************************************************************
0861 *
0862 *       Fusion-MPT MPI Scatter Gather Elements
0863 *
0864 *****************************************************************************/
0865 
0866 /****************************************************************************
0867 * MPI Simple Element structures
0868 ****************************************************************************/
0869 
0870 typedef struct _MPI2_SGE_SIMPLE32 {
0871     U32 FlagsLength;
0872     U32 Address;
0873 } MPI2_SGE_SIMPLE32, *PTR_MPI2_SGE_SIMPLE32,
0874     Mpi2SGESimple32_t, *pMpi2SGESimple32_t;
0875 
0876 typedef struct _MPI2_SGE_SIMPLE64 {
0877     U32 FlagsLength;
0878     U64 Address;
0879 } MPI2_SGE_SIMPLE64, *PTR_MPI2_SGE_SIMPLE64,
0880     Mpi2SGESimple64_t, *pMpi2SGESimple64_t;
0881 
0882 typedef struct _MPI2_SGE_SIMPLE_UNION {
0883     U32 FlagsLength;
0884     union {
0885         U32 Address32;
0886         U64 Address64;
0887     } u;
0888 } MPI2_SGE_SIMPLE_UNION,
0889     *PTR_MPI2_SGE_SIMPLE_UNION,
0890     Mpi2SGESimpleUnion_t,
0891     *pMpi2SGESimpleUnion_t;
0892 
0893 /****************************************************************************
0894 * MPI Chain Element structures - for MPI v2.0 products only
0895 ****************************************************************************/
0896 
0897 typedef struct _MPI2_SGE_CHAIN32 {
0898     U16 Length;
0899     U8 NextChainOffset;
0900     U8 Flags;
0901     U32 Address;
0902 } MPI2_SGE_CHAIN32, *PTR_MPI2_SGE_CHAIN32,
0903     Mpi2SGEChain32_t, *pMpi2SGEChain32_t;
0904 
0905 typedef struct _MPI2_SGE_CHAIN64 {
0906     U16 Length;
0907     U8 NextChainOffset;
0908     U8 Flags;
0909     U64 Address;
0910 } MPI2_SGE_CHAIN64, *PTR_MPI2_SGE_CHAIN64,
0911     Mpi2SGEChain64_t, *pMpi2SGEChain64_t;
0912 
0913 typedef struct _MPI2_SGE_CHAIN_UNION {
0914     U16 Length;
0915     U8 NextChainOffset;
0916     U8 Flags;
0917     union {
0918         U32 Address32;
0919         U64 Address64;
0920     } u;
0921 } MPI2_SGE_CHAIN_UNION,
0922     *PTR_MPI2_SGE_CHAIN_UNION,
0923     Mpi2SGEChainUnion_t,
0924     *pMpi2SGEChainUnion_t;
0925 
0926 /****************************************************************************
0927 * MPI Transaction Context Element structures - for MPI v2.0 products only
0928 ****************************************************************************/
0929 
0930 typedef struct _MPI2_SGE_TRANSACTION32 {
0931     U8 Reserved;
0932     U8 ContextSize;
0933     U8 DetailsLength;
0934     U8 Flags;
0935     U32 TransactionContext[1];
0936     U32 TransactionDetails[1];
0937 } MPI2_SGE_TRANSACTION32,
0938     *PTR_MPI2_SGE_TRANSACTION32,
0939     Mpi2SGETransaction32_t,
0940     *pMpi2SGETransaction32_t;
0941 
0942 typedef struct _MPI2_SGE_TRANSACTION64 {
0943     U8 Reserved;
0944     U8 ContextSize;
0945     U8 DetailsLength;
0946     U8 Flags;
0947     U32 TransactionContext[2];
0948     U32 TransactionDetails[1];
0949 } MPI2_SGE_TRANSACTION64,
0950     *PTR_MPI2_SGE_TRANSACTION64,
0951     Mpi2SGETransaction64_t,
0952     *pMpi2SGETransaction64_t;
0953 
0954 typedef struct _MPI2_SGE_TRANSACTION96 {
0955     U8 Reserved;
0956     U8 ContextSize;
0957     U8 DetailsLength;
0958     U8 Flags;
0959     U32 TransactionContext[3];
0960     U32 TransactionDetails[1];
0961 } MPI2_SGE_TRANSACTION96, *PTR_MPI2_SGE_TRANSACTION96,
0962     Mpi2SGETransaction96_t, *pMpi2SGETransaction96_t;
0963 
0964 typedef struct _MPI2_SGE_TRANSACTION128 {
0965     U8 Reserved;
0966     U8 ContextSize;
0967     U8 DetailsLength;
0968     U8 Flags;
0969     U32 TransactionContext[4];
0970     U32 TransactionDetails[1];
0971 } MPI2_SGE_TRANSACTION128, *PTR_MPI2_SGE_TRANSACTION128,
0972     Mpi2SGETransaction_t128, *pMpi2SGETransaction_t128;
0973 
0974 typedef struct _MPI2_SGE_TRANSACTION_UNION {
0975     U8 Reserved;
0976     U8 ContextSize;
0977     U8 DetailsLength;
0978     U8 Flags;
0979     union {
0980         U32 TransactionContext32[1];
0981         U32 TransactionContext64[2];
0982         U32 TransactionContext96[3];
0983         U32 TransactionContext128[4];
0984     } u;
0985     U32 TransactionDetails[1];
0986 } MPI2_SGE_TRANSACTION_UNION,
0987     *PTR_MPI2_SGE_TRANSACTION_UNION,
0988     Mpi2SGETransactionUnion_t,
0989     *pMpi2SGETransactionUnion_t;
0990 
0991 /****************************************************************************
0992 * MPI SGE union for IO SGL's - for MPI v2.0 products only
0993 ****************************************************************************/
0994 
0995 typedef struct _MPI2_MPI_SGE_IO_UNION {
0996     union {
0997         MPI2_SGE_SIMPLE_UNION Simple;
0998         MPI2_SGE_CHAIN_UNION Chain;
0999     } u;
1000 } MPI2_MPI_SGE_IO_UNION, *PTR_MPI2_MPI_SGE_IO_UNION,
1001     Mpi2MpiSGEIOUnion_t, *pMpi2MpiSGEIOUnion_t;
1002 
1003 /****************************************************************************
1004 * MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only
1005 ****************************************************************************/
1006 
1007 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION {
1008     union {
1009         MPI2_SGE_SIMPLE_UNION Simple;
1010         MPI2_SGE_TRANSACTION_UNION Transaction;
1011     } u;
1012 } MPI2_SGE_TRANS_SIMPLE_UNION,
1013     *PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
1014     Mpi2SGETransSimpleUnion_t,
1015     *pMpi2SGETransSimpleUnion_t;
1016 
1017 /****************************************************************************
1018 * All MPI SGE types union
1019 ****************************************************************************/
1020 
1021 typedef struct _MPI2_MPI_SGE_UNION {
1022     union {
1023         MPI2_SGE_SIMPLE_UNION Simple;
1024         MPI2_SGE_CHAIN_UNION Chain;
1025         MPI2_SGE_TRANSACTION_UNION Transaction;
1026     } u;
1027 } MPI2_MPI_SGE_UNION, *PTR_MPI2_MPI_SGE_UNION,
1028     Mpi2MpiSgeUnion_t, *pMpi2MpiSgeUnion_t;
1029 
1030 /****************************************************************************
1031 * MPI SGE field definition and masks
1032 ****************************************************************************/
1033 
1034 /*Flags field bit definitions */
1035 
1036 #define MPI2_SGE_FLAGS_LAST_ELEMENT             (0x80)
1037 #define MPI2_SGE_FLAGS_END_OF_BUFFER            (0x40)
1038 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK        (0x30)
1039 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS            (0x08)
1040 #define MPI2_SGE_FLAGS_DIRECTION                (0x04)
1041 #define MPI2_SGE_FLAGS_ADDRESS_SIZE             (0x02)
1042 #define MPI2_SGE_FLAGS_END_OF_LIST              (0x01)
1043 
1044 #define MPI2_SGE_FLAGS_SHIFT                    (24)
1045 
1046 #define MPI2_SGE_LENGTH_MASK                    (0x00FFFFFF)
1047 #define MPI2_SGE_CHAIN_LENGTH_MASK              (0x0000FFFF)
1048 
1049 /*Element Type */
1050 
1051 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT      (0x00)
1052 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT           (0x10)
1053 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT            (0x30)
1054 #define MPI2_SGE_FLAGS_ELEMENT_MASK             (0x30)
1055 
1056 /*Address location */
1057 
1058 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS           (0x00)
1059 
1060 /*Direction */
1061 
1062 #define MPI2_SGE_FLAGS_IOC_TO_HOST              (0x00)
1063 #define MPI2_SGE_FLAGS_HOST_TO_IOC              (0x04)
1064 
1065 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
1066 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
1067 
1068 /*Address Size */
1069 
1070 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING        (0x00)
1071 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING        (0x02)
1072 
1073 /*Context Size */
1074 
1075 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT           (0x00)
1076 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT           (0x02)
1077 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT           (0x04)
1078 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT          (0x06)
1079 
1080 #define MPI2_SGE_CHAIN_OFFSET_MASK              (0x00FF0000)
1081 #define MPI2_SGE_CHAIN_OFFSET_SHIFT             (16)
1082 
1083 /****************************************************************************
1084 * MPI SGE operation Macros
1085 ****************************************************************************/
1086 
1087 /*SIMPLE FlagsLength manipulations... */
1088 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
1089 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> \
1090                     MPI2_SGE_FLAGS_SHIFT)
1091 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
1092 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
1093 
1094 #define MPI2_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_SGE_SET_FLAGS(f) | \
1095                     MPI2_SGE_LENGTH(l))
1096 
1097 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
1098 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
1099 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
1100                     MPI2_SGE_SET_FLAGS_LENGTH(f, l))
1101 
1102 /*CAUTION - The following are READ-MODIFY-WRITE! */
1103 #define MPI2_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
1104                     MPI2_SGE_SET_FLAGS(f))
1105 #define MPI2_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
1106                     MPI2_SGE_LENGTH(l))
1107 
1108 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> \
1109                     MPI2_SGE_CHAIN_OFFSET_SHIFT)
1110 
1111 /*****************************************************************************
1112 *
1113 *       Fusion-MPT IEEE Scatter Gather Elements
1114 *
1115 *****************************************************************************/
1116 
1117 /****************************************************************************
1118 * IEEE Simple Element structures
1119 ****************************************************************************/
1120 
1121 /*MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */
1122 typedef struct _MPI2_IEEE_SGE_SIMPLE32 {
1123     U32 Address;
1124     U32 FlagsLength;
1125 } MPI2_IEEE_SGE_SIMPLE32, *PTR_MPI2_IEEE_SGE_SIMPLE32,
1126     Mpi2IeeeSgeSimple32_t, *pMpi2IeeeSgeSimple32_t;
1127 
1128 typedef struct _MPI2_IEEE_SGE_SIMPLE64 {
1129     U64 Address;
1130     U32 Length;
1131     U16 Reserved1;
1132     U8 Reserved2;
1133     U8 Flags;
1134 } MPI2_IEEE_SGE_SIMPLE64, *PTR_MPI2_IEEE_SGE_SIMPLE64,
1135     Mpi2IeeeSgeSimple64_t, *pMpi2IeeeSgeSimple64_t;
1136 
1137 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION {
1138     MPI2_IEEE_SGE_SIMPLE32 Simple32;
1139     MPI2_IEEE_SGE_SIMPLE64 Simple64;
1140 } MPI2_IEEE_SGE_SIMPLE_UNION,
1141     *PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1142     Mpi2IeeeSgeSimpleUnion_t,
1143     *pMpi2IeeeSgeSimpleUnion_t;
1144 
1145 /****************************************************************************
1146 * IEEE Chain Element structures
1147 ****************************************************************************/
1148 
1149 /*MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */
1150 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1151 
1152 /*MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */
1153 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1154 
1155 typedef union _MPI2_IEEE_SGE_CHAIN_UNION {
1156     MPI2_IEEE_SGE_CHAIN32 Chain32;
1157     MPI2_IEEE_SGE_CHAIN64 Chain64;
1158 } MPI2_IEEE_SGE_CHAIN_UNION,
1159     *PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1160     Mpi2IeeeSgeChainUnion_t,
1161     *pMpi2IeeeSgeChainUnion_t;
1162 
1163 /*MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */
1164 typedef struct _MPI25_IEEE_SGE_CHAIN64 {
1165     U64 Address;
1166     U32 Length;
1167     U16 Reserved1;
1168     U8 NextChainOffset;
1169     U8 Flags;
1170 } MPI25_IEEE_SGE_CHAIN64,
1171     *PTR_MPI25_IEEE_SGE_CHAIN64,
1172     Mpi25IeeeSgeChain64_t,
1173     *pMpi25IeeeSgeChain64_t;
1174 
1175 /****************************************************************************
1176 * All IEEE SGE types union
1177 ****************************************************************************/
1178 
1179 /*MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */
1180 typedef struct _MPI2_IEEE_SGE_UNION {
1181     union {
1182         MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1183         MPI2_IEEE_SGE_CHAIN_UNION Chain;
1184     } u;
1185 } MPI2_IEEE_SGE_UNION, *PTR_MPI2_IEEE_SGE_UNION,
1186     Mpi2IeeeSgeUnion_t, *pMpi2IeeeSgeUnion_t;
1187 
1188 /****************************************************************************
1189 * IEEE SGE union for IO SGL's
1190 ****************************************************************************/
1191 
1192 typedef union _MPI25_SGE_IO_UNION {
1193     MPI2_IEEE_SGE_SIMPLE64 IeeeSimple;
1194     MPI25_IEEE_SGE_CHAIN64 IeeeChain;
1195 } MPI25_SGE_IO_UNION, *PTR_MPI25_SGE_IO_UNION,
1196     Mpi25SGEIOUnion_t, *pMpi25SGEIOUnion_t;
1197 
1198 /****************************************************************************
1199 * IEEE SGE field definitions and masks
1200 ****************************************************************************/
1201 
1202 /*Flags field bit definitions */
1203 
1204 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK   (0x80)
1205 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST        (0x40)
1206 
1207 #define MPI2_IEEE32_SGE_FLAGS_SHIFT             (24)
1208 
1209 #define MPI2_IEEE32_SGE_LENGTH_MASK             (0x00FFFFFF)
1210 
1211 /*Element Type */
1212 
1213 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT      (0x00)
1214 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT       (0x80)
1215 
1216 /*Next Segment Format */
1217 
1218 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK           (0x1C)
1219 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE       (0x00)
1220 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP       (0x08)
1221 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL       (0x10)
1222 
1223 /*Data Location Address Space */
1224 
1225 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK           (0x03)
1226 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR         (0x00)
1227 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR         (0x01)
1228 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR         (0x02)
1229 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR      (0x03)
1230 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR   (0x03)
1231 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \
1232      (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR)
1233 #define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR        (0x02)
1234 
1235 /****************************************************************************
1236 * IEEE SGE operation Macros
1237 ****************************************************************************/
1238 
1239 /*SIMPLE FlagsLength manipulations... */
1240 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1241 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) \
1242                  >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1243 #define MPI2_IEEE32_SGE_LENGTH(f)    ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1244 
1245 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) |\
1246                          MPI2_IEEE32_SGE_LENGTH(l))
1247 
1248 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) \
1249             MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1250 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) \
1251             MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1252 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
1253                     MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l))
1254 
1255 /*CAUTION - The following are READ-MODIFY-WRITE! */
1256 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
1257                     MPI2_IEEE32_SGE_SET_FLAGS(f))
1258 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
1259                     MPI2_IEEE32_SGE_LENGTH(l))
1260 
1261 /*****************************************************************************
1262 *
1263 *       Fusion-MPT MPI/IEEE Scatter Gather Unions
1264 *
1265 *****************************************************************************/
1266 
1267 typedef union _MPI2_SIMPLE_SGE_UNION {
1268     MPI2_SGE_SIMPLE_UNION MpiSimple;
1269     MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1270 } MPI2_SIMPLE_SGE_UNION, *PTR_MPI2_SIMPLE_SGE_UNION,
1271     Mpi2SimpleSgeUntion_t, *pMpi2SimpleSgeUntion_t;
1272 
1273 typedef union _MPI2_SGE_IO_UNION {
1274     MPI2_SGE_SIMPLE_UNION MpiSimple;
1275     MPI2_SGE_CHAIN_UNION MpiChain;
1276     MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1277     MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1278 } MPI2_SGE_IO_UNION, *PTR_MPI2_SGE_IO_UNION,
1279     Mpi2SGEIOUnion_t, *pMpi2SGEIOUnion_t;
1280 
1281 /****************************************************************************
1282 *
1283 * Values for SGLFlags field, used in many request messages with an SGL
1284 *
1285 ****************************************************************************/
1286 
1287 /*values for MPI SGL Data Location Address Space subfield */
1288 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK            (0x0C)
1289 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE          (0x00)
1290 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE          (0x04)
1291 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE          (0x08)
1292 #define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE         (0x08)
1293 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE       (0x0C)
1294 /*values for SGL Type subfield */
1295 #define MPI2_SGLFLAGS_SGL_TYPE_MASK                 (0x03)
1296 #define MPI2_SGLFLAGS_SGL_TYPE_MPI                  (0x00)
1297 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32               (0x01)
1298 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64               (0x02)
1299 
1300 #endif
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