0001
0002
0003
0004
0005
0006
0007
0008
0009
0010 #include "mpi3mr.h"
0011
0012
0013 LIST_HEAD(mrioc_list);
0014 DEFINE_SPINLOCK(mrioc_list_lock);
0015 static int mrioc_ids;
0016 static int warn_non_secure_ctlr;
0017 atomic64_t event_counter;
0018
0019 MODULE_AUTHOR(MPI3MR_DRIVER_AUTHOR);
0020 MODULE_DESCRIPTION(MPI3MR_DRIVER_DESC);
0021 MODULE_LICENSE(MPI3MR_DRIVER_LICENSE);
0022 MODULE_VERSION(MPI3MR_DRIVER_VERSION);
0023
0024
0025 int prot_mask = -1;
0026 module_param(prot_mask, int, 0);
0027 MODULE_PARM_DESC(prot_mask, "Host protection capabilities mask, def=0x07");
0028
0029 static int prot_guard_mask = 3;
0030 module_param(prot_guard_mask, int, 0);
0031 MODULE_PARM_DESC(prot_guard_mask, " Host protection guard mask, def=3");
0032 static int logging_level;
0033 module_param(logging_level, int, 0);
0034 MODULE_PARM_DESC(logging_level,
0035 " bits for enabling additional logging info (default=0)");
0036
0037
0038 static void mpi3mr_send_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
0039 struct mpi3mr_drv_cmd *cmdparam, u32 event_ctx);
0040
0041 #define MPI3MR_DRIVER_EVENT_TG_QD_REDUCTION (0xFFFF)
0042
0043
0044
0045
0046
0047
0048
0049
0050
0051
0052 static u16 mpi3mr_host_tag_for_scmd(struct mpi3mr_ioc *mrioc,
0053 struct scsi_cmnd *scmd)
0054 {
0055 struct scmd_priv *priv = NULL;
0056 u32 unique_tag;
0057 u16 host_tag, hw_queue;
0058
0059 unique_tag = blk_mq_unique_tag(scsi_cmd_to_rq(scmd));
0060
0061 hw_queue = blk_mq_unique_tag_to_hwq(unique_tag);
0062 if (hw_queue >= mrioc->num_op_reply_q)
0063 return MPI3MR_HOSTTAG_INVALID;
0064 host_tag = blk_mq_unique_tag_to_tag(unique_tag);
0065
0066 if (WARN_ON(host_tag >= mrioc->max_host_ios))
0067 return MPI3MR_HOSTTAG_INVALID;
0068
0069 priv = scsi_cmd_priv(scmd);
0070
0071 priv->host_tag = host_tag + 1;
0072 priv->scmd = scmd;
0073 priv->in_lld_scope = 1;
0074 priv->req_q_idx = hw_queue;
0075 priv->meta_chain_idx = -1;
0076 priv->chain_idx = -1;
0077 priv->meta_sg_valid = 0;
0078 return priv->host_tag;
0079 }
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
0090
0091
0092 static struct scsi_cmnd *mpi3mr_scmd_from_host_tag(
0093 struct mpi3mr_ioc *mrioc, u16 host_tag, u16 qidx)
0094 {
0095 struct scsi_cmnd *scmd = NULL;
0096 struct scmd_priv *priv = NULL;
0097 u32 unique_tag = host_tag - 1;
0098
0099 if (WARN_ON(host_tag > mrioc->max_host_ios))
0100 goto out;
0101
0102 unique_tag |= (qidx << BLK_MQ_UNIQUE_TAG_BITS);
0103
0104 scmd = scsi_host_find_tag(mrioc->shost, unique_tag);
0105 if (scmd) {
0106 priv = scsi_cmd_priv(scmd);
0107 if (!priv->in_lld_scope)
0108 scmd = NULL;
0109 }
0110 out:
0111 return scmd;
0112 }
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124 static void mpi3mr_clear_scmd_priv(struct mpi3mr_ioc *mrioc,
0125 struct scsi_cmnd *scmd)
0126 {
0127 struct scmd_priv *priv = NULL;
0128
0129 priv = scsi_cmd_priv(scmd);
0130
0131 if (WARN_ON(priv->in_lld_scope == 0))
0132 return;
0133 priv->host_tag = MPI3MR_HOSTTAG_INVALID;
0134 priv->req_q_idx = 0xFFFF;
0135 priv->scmd = NULL;
0136 priv->in_lld_scope = 0;
0137 priv->meta_sg_valid = 0;
0138 if (priv->chain_idx >= 0) {
0139 clear_bit(priv->chain_idx, mrioc->chain_bitmap);
0140 priv->chain_idx = -1;
0141 }
0142 if (priv->meta_chain_idx >= 0) {
0143 clear_bit(priv->meta_chain_idx, mrioc->chain_bitmap);
0144 priv->meta_chain_idx = -1;
0145 }
0146 }
0147
0148 static void mpi3mr_dev_rmhs_send_tm(struct mpi3mr_ioc *mrioc, u16 handle,
0149 struct mpi3mr_drv_cmd *cmdparam, u8 iou_rc);
0150 static void mpi3mr_fwevt_worker(struct work_struct *work);
0151
0152
0153
0154
0155
0156
0157
0158 static void mpi3mr_fwevt_free(struct kref *r)
0159 {
0160 kfree(container_of(r, struct mpi3mr_fwevt, ref_count));
0161 }
0162
0163
0164
0165
0166
0167
0168
0169 static void mpi3mr_fwevt_get(struct mpi3mr_fwevt *fwevt)
0170 {
0171 kref_get(&fwevt->ref_count);
0172 }
0173
0174
0175
0176
0177
0178
0179
0180 static void mpi3mr_fwevt_put(struct mpi3mr_fwevt *fwevt)
0181 {
0182 kref_put(&fwevt->ref_count, mpi3mr_fwevt_free);
0183 }
0184
0185
0186
0187
0188
0189
0190
0191
0192
0193
0194 static struct mpi3mr_fwevt *mpi3mr_alloc_fwevt(int len)
0195 {
0196 struct mpi3mr_fwevt *fwevt;
0197
0198 fwevt = kzalloc(sizeof(*fwevt) + len, GFP_ATOMIC);
0199 if (!fwevt)
0200 return NULL;
0201
0202 kref_init(&fwevt->ref_count);
0203 return fwevt;
0204 }
0205
0206
0207
0208
0209
0210
0211
0212
0213
0214
0215 static void mpi3mr_fwevt_add_to_list(struct mpi3mr_ioc *mrioc,
0216 struct mpi3mr_fwevt *fwevt)
0217 {
0218 unsigned long flags;
0219
0220 if (!mrioc->fwevt_worker_thread)
0221 return;
0222
0223 spin_lock_irqsave(&mrioc->fwevt_lock, flags);
0224
0225 mpi3mr_fwevt_get(fwevt);
0226 INIT_LIST_HEAD(&fwevt->list);
0227 list_add_tail(&fwevt->list, &mrioc->fwevt_list);
0228 INIT_WORK(&fwevt->work, mpi3mr_fwevt_worker);
0229
0230 mpi3mr_fwevt_get(fwevt);
0231 queue_work(mrioc->fwevt_worker_thread, &fwevt->work);
0232 spin_unlock_irqrestore(&mrioc->fwevt_lock, flags);
0233 }
0234
0235
0236
0237
0238
0239
0240
0241
0242
0243
0244 static void mpi3mr_fwevt_del_from_list(struct mpi3mr_ioc *mrioc,
0245 struct mpi3mr_fwevt *fwevt)
0246 {
0247 unsigned long flags;
0248
0249 spin_lock_irqsave(&mrioc->fwevt_lock, flags);
0250 if (!list_empty(&fwevt->list)) {
0251 list_del_init(&fwevt->list);
0252
0253
0254
0255
0256 mpi3mr_fwevt_put(fwevt);
0257 }
0258 spin_unlock_irqrestore(&mrioc->fwevt_lock, flags);
0259 }
0260
0261
0262
0263
0264
0265
0266
0267
0268
0269 static struct mpi3mr_fwevt *mpi3mr_dequeue_fwevt(
0270 struct mpi3mr_ioc *mrioc)
0271 {
0272 unsigned long flags;
0273 struct mpi3mr_fwevt *fwevt = NULL;
0274
0275 spin_lock_irqsave(&mrioc->fwevt_lock, flags);
0276 if (!list_empty(&mrioc->fwevt_list)) {
0277 fwevt = list_first_entry(&mrioc->fwevt_list,
0278 struct mpi3mr_fwevt, list);
0279 list_del_init(&fwevt->list);
0280
0281
0282
0283
0284 mpi3mr_fwevt_put(fwevt);
0285 }
0286 spin_unlock_irqrestore(&mrioc->fwevt_lock, flags);
0287
0288 return fwevt;
0289 }
0290
0291
0292
0293
0294
0295
0296
0297 static void mpi3mr_cancel_work(struct mpi3mr_fwevt *fwevt)
0298 {
0299
0300
0301
0302
0303
0304
0305
0306 if (cancel_work_sync(&fwevt->work)) {
0307
0308
0309
0310
0311 mpi3mr_fwevt_put(fwevt);
0312
0313
0314
0315
0316 mpi3mr_fwevt_put(fwevt);
0317 }
0318 }
0319
0320
0321
0322
0323
0324
0325
0326
0327
0328
0329 void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc)
0330 {
0331 struct mpi3mr_fwevt *fwevt = NULL;
0332
0333 if ((list_empty(&mrioc->fwevt_list) && !mrioc->current_event) ||
0334 !mrioc->fwevt_worker_thread)
0335 return;
0336
0337 while ((fwevt = mpi3mr_dequeue_fwevt(mrioc)))
0338 mpi3mr_cancel_work(fwevt);
0339
0340 if (mrioc->current_event) {
0341 fwevt = mrioc->current_event;
0342
0343
0344
0345
0346
0347
0348
0349
0350 if (current_work() == &fwevt->work || fwevt->pending_at_sml) {
0351 fwevt->discard = 1;
0352 return;
0353 }
0354
0355 mpi3mr_cancel_work(fwevt);
0356 }
0357 }
0358
0359
0360
0361
0362
0363
0364
0365
0366
0367
0368
0369
0370 static void mpi3mr_queue_qd_reduction_event(struct mpi3mr_ioc *mrioc,
0371 struct mpi3mr_throttle_group_info *tg)
0372 {
0373 struct mpi3mr_fwevt *fwevt;
0374 u16 sz = sizeof(struct mpi3mr_throttle_group_info *);
0375
0376
0377
0378
0379
0380
0381 if (tg->fw_qd != tg->modified_qd)
0382 return;
0383
0384 fwevt = mpi3mr_alloc_fwevt(sz);
0385 if (!fwevt) {
0386 ioc_warn(mrioc, "failed to queue TG QD reduction event\n");
0387 return;
0388 }
0389 *(struct mpi3mr_throttle_group_info **)fwevt->event_data = tg;
0390 fwevt->mrioc = mrioc;
0391 fwevt->event_id = MPI3MR_DRIVER_EVENT_TG_QD_REDUCTION;
0392 fwevt->send_ack = 0;
0393 fwevt->process_evt = 1;
0394 fwevt->evt_ctx = 0;
0395 fwevt->event_data_size = sz;
0396 tg->modified_qd = max_t(u16, (tg->fw_qd * tg->qd_reduction) / 10, 8);
0397
0398 dprint_event_bh(mrioc, "qd reduction event queued for tg_id(%d)\n",
0399 tg->id);
0400 mpi3mr_fwevt_add_to_list(mrioc, fwevt);
0401 }
0402
0403
0404
0405
0406
0407
0408
0409
0410
0411
0412 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc)
0413 {
0414 struct mpi3mr_tgt_dev *tgtdev;
0415 struct mpi3mr_stgt_priv_data *tgt_priv;
0416
0417 list_for_each_entry(tgtdev, &mrioc->tgtdev_list, list) {
0418 tgtdev->dev_handle = MPI3MR_INVALID_DEV_HANDLE;
0419 if (tgtdev->starget && tgtdev->starget->hostdata) {
0420 tgt_priv = tgtdev->starget->hostdata;
0421 tgt_priv->dev_handle = MPI3MR_INVALID_DEV_HANDLE;
0422 tgt_priv->io_throttle_enabled = 0;
0423 tgt_priv->io_divert = 0;
0424 tgt_priv->throttle_group = NULL;
0425 }
0426 }
0427 }
0428
0429
0430
0431
0432
0433
0434
0435
0436
0437
0438 static bool mpi3mr_print_scmd(struct request *rq, void *data)
0439 {
0440 struct mpi3mr_ioc *mrioc = (struct mpi3mr_ioc *)data;
0441 struct scsi_cmnd *scmd = blk_mq_rq_to_pdu(rq);
0442 struct scmd_priv *priv = NULL;
0443
0444 if (scmd) {
0445 priv = scsi_cmd_priv(scmd);
0446 if (!priv->in_lld_scope)
0447 goto out;
0448
0449 ioc_info(mrioc, "%s :Host Tag = %d, qid = %d\n",
0450 __func__, priv->host_tag, priv->req_q_idx + 1);
0451 scsi_print_command(scmd);
0452 }
0453
0454 out:
0455 return(true);
0456 }
0457
0458
0459
0460
0461
0462
0463
0464
0465
0466
0467
0468
0469 static bool mpi3mr_flush_scmd(struct request *rq, void *data)
0470 {
0471 struct mpi3mr_ioc *mrioc = (struct mpi3mr_ioc *)data;
0472 struct scsi_cmnd *scmd = blk_mq_rq_to_pdu(rq);
0473 struct scmd_priv *priv = NULL;
0474
0475 if (scmd) {
0476 priv = scsi_cmd_priv(scmd);
0477 if (!priv->in_lld_scope)
0478 goto out;
0479
0480 if (priv->meta_sg_valid)
0481 dma_unmap_sg(&mrioc->pdev->dev, scsi_prot_sglist(scmd),
0482 scsi_prot_sg_count(scmd), scmd->sc_data_direction);
0483 mpi3mr_clear_scmd_priv(mrioc, scmd);
0484 scsi_dma_unmap(scmd);
0485 scmd->result = DID_RESET << 16;
0486 scsi_print_command(scmd);
0487 scsi_done(scmd);
0488 mrioc->flush_io_count++;
0489 }
0490
0491 out:
0492 return(true);
0493 }
0494
0495
0496
0497
0498
0499
0500
0501
0502
0503
0504
0505
0506
0507
0508 static bool mpi3mr_count_dev_pending(struct request *rq, void *data)
0509 {
0510 struct scsi_device *sdev = (struct scsi_device *)data;
0511 struct mpi3mr_sdev_priv_data *sdev_priv_data = sdev->hostdata;
0512 struct scsi_cmnd *scmd = blk_mq_rq_to_pdu(rq);
0513 struct scmd_priv *priv;
0514
0515 if (scmd) {
0516 priv = scsi_cmd_priv(scmd);
0517 if (!priv->in_lld_scope)
0518 goto out;
0519 if (scmd->device == sdev)
0520 sdev_priv_data->pend_count++;
0521 }
0522
0523 out:
0524 return true;
0525 }
0526
0527
0528
0529
0530
0531
0532
0533
0534
0535
0536
0537
0538
0539
0540 static bool mpi3mr_count_tgt_pending(struct request *rq, void *data)
0541 {
0542 struct scsi_target *starget = (struct scsi_target *)data;
0543 struct mpi3mr_stgt_priv_data *stgt_priv_data = starget->hostdata;
0544 struct scsi_cmnd *scmd = blk_mq_rq_to_pdu(rq);
0545 struct scmd_priv *priv;
0546
0547 if (scmd) {
0548 priv = scsi_cmd_priv(scmd);
0549 if (!priv->in_lld_scope)
0550 goto out;
0551 if (scmd->device && (scsi_target(scmd->device) == starget))
0552 stgt_priv_data->pend_count++;
0553 }
0554
0555 out:
0556 return true;
0557 }
0558
0559
0560
0561
0562
0563
0564
0565
0566
0567
0568
0569 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc)
0570 {
0571 struct Scsi_Host *shost = mrioc->shost;
0572
0573 mrioc->flush_io_count = 0;
0574 ioc_info(mrioc, "%s :Flushing Host I/O cmds post reset\n", __func__);
0575 blk_mq_tagset_busy_iter(&shost->tag_set,
0576 mpi3mr_flush_scmd, (void *)mrioc);
0577 ioc_info(mrioc, "%s :Flushed %d Host I/O cmds\n", __func__,
0578 mrioc->flush_io_count);
0579 }
0580
0581
0582
0583
0584
0585
0586
0587
0588
0589 static struct mpi3mr_tgt_dev *mpi3mr_alloc_tgtdev(void)
0590 {
0591 struct mpi3mr_tgt_dev *tgtdev;
0592
0593 tgtdev = kzalloc(sizeof(*tgtdev), GFP_ATOMIC);
0594 if (!tgtdev)
0595 return NULL;
0596 kref_init(&tgtdev->ref_count);
0597 return tgtdev;
0598 }
0599
0600
0601
0602
0603
0604
0605
0606
0607
0608
0609 static void mpi3mr_tgtdev_add_to_list(struct mpi3mr_ioc *mrioc,
0610 struct mpi3mr_tgt_dev *tgtdev)
0611 {
0612 unsigned long flags;
0613
0614 spin_lock_irqsave(&mrioc->tgtdev_lock, flags);
0615 mpi3mr_tgtdev_get(tgtdev);
0616 INIT_LIST_HEAD(&tgtdev->list);
0617 list_add_tail(&tgtdev->list, &mrioc->tgtdev_list);
0618 spin_unlock_irqrestore(&mrioc->tgtdev_lock, flags);
0619 }
0620
0621
0622
0623
0624
0625
0626
0627
0628
0629
0630 static void mpi3mr_tgtdev_del_from_list(struct mpi3mr_ioc *mrioc,
0631 struct mpi3mr_tgt_dev *tgtdev)
0632 {
0633 unsigned long flags;
0634
0635 spin_lock_irqsave(&mrioc->tgtdev_lock, flags);
0636 if (!list_empty(&tgtdev->list)) {
0637 list_del_init(&tgtdev->list);
0638 mpi3mr_tgtdev_put(tgtdev);
0639 }
0640 spin_unlock_irqrestore(&mrioc->tgtdev_lock, flags);
0641 }
0642
0643
0644
0645
0646
0647
0648
0649
0650
0651
0652
0653 static struct mpi3mr_tgt_dev *__mpi3mr_get_tgtdev_by_handle(
0654 struct mpi3mr_ioc *mrioc, u16 handle)
0655 {
0656 struct mpi3mr_tgt_dev *tgtdev;
0657
0658 assert_spin_locked(&mrioc->tgtdev_lock);
0659 list_for_each_entry(tgtdev, &mrioc->tgtdev_list, list)
0660 if (tgtdev->dev_handle == handle)
0661 goto found_tgtdev;
0662 return NULL;
0663
0664 found_tgtdev:
0665 mpi3mr_tgtdev_get(tgtdev);
0666 return tgtdev;
0667 }
0668
0669
0670
0671
0672
0673
0674
0675
0676
0677
0678
0679 struct mpi3mr_tgt_dev *mpi3mr_get_tgtdev_by_handle(
0680 struct mpi3mr_ioc *mrioc, u16 handle)
0681 {
0682 struct mpi3mr_tgt_dev *tgtdev;
0683 unsigned long flags;
0684
0685 spin_lock_irqsave(&mrioc->tgtdev_lock, flags);
0686 tgtdev = __mpi3mr_get_tgtdev_by_handle(mrioc, handle);
0687 spin_unlock_irqrestore(&mrioc->tgtdev_lock, flags);
0688 return tgtdev;
0689 }
0690
0691
0692
0693
0694
0695
0696
0697
0698
0699
0700
0701 static struct mpi3mr_tgt_dev *__mpi3mr_get_tgtdev_by_perst_id(
0702 struct mpi3mr_ioc *mrioc, u16 persist_id)
0703 {
0704 struct mpi3mr_tgt_dev *tgtdev;
0705
0706 assert_spin_locked(&mrioc->tgtdev_lock);
0707 list_for_each_entry(tgtdev, &mrioc->tgtdev_list, list)
0708 if (tgtdev->perst_id == persist_id)
0709 goto found_tgtdev;
0710 return NULL;
0711
0712 found_tgtdev:
0713 mpi3mr_tgtdev_get(tgtdev);
0714 return tgtdev;
0715 }
0716
0717
0718
0719
0720
0721
0722
0723
0724
0725
0726
0727 static struct mpi3mr_tgt_dev *mpi3mr_get_tgtdev_by_perst_id(
0728 struct mpi3mr_ioc *mrioc, u16 persist_id)
0729 {
0730 struct mpi3mr_tgt_dev *tgtdev;
0731 unsigned long flags;
0732
0733 spin_lock_irqsave(&mrioc->tgtdev_lock, flags);
0734 tgtdev = __mpi3mr_get_tgtdev_by_perst_id(mrioc, persist_id);
0735 spin_unlock_irqrestore(&mrioc->tgtdev_lock, flags);
0736 return tgtdev;
0737 }
0738
0739
0740
0741
0742
0743
0744
0745
0746
0747
0748
0749 static struct mpi3mr_tgt_dev *__mpi3mr_get_tgtdev_from_tgtpriv(
0750 struct mpi3mr_ioc *mrioc, struct mpi3mr_stgt_priv_data *tgt_priv)
0751 {
0752 struct mpi3mr_tgt_dev *tgtdev;
0753
0754 assert_spin_locked(&mrioc->tgtdev_lock);
0755 tgtdev = tgt_priv->tgt_dev;
0756 if (tgtdev)
0757 mpi3mr_tgtdev_get(tgtdev);
0758 return tgtdev;
0759 }
0760
0761
0762
0763
0764
0765
0766
0767
0768
0769
0770
0771
0772 static void mpi3mr_set_io_divert_for_all_vd_in_tg(struct mpi3mr_ioc *mrioc,
0773 struct mpi3mr_throttle_group_info *tg, u8 divert_value)
0774 {
0775 unsigned long flags;
0776 struct mpi3mr_tgt_dev *tgtdev;
0777 struct mpi3mr_stgt_priv_data *tgt_priv;
0778
0779 spin_lock_irqsave(&mrioc->tgtdev_lock, flags);
0780 list_for_each_entry(tgtdev, &mrioc->tgtdev_list, list) {
0781 if (tgtdev->starget && tgtdev->starget->hostdata) {
0782 tgt_priv = tgtdev->starget->hostdata;
0783 if (tgt_priv->throttle_group == tg)
0784 tgt_priv->io_divert = divert_value;
0785 }
0786 }
0787 spin_unlock_irqrestore(&mrioc->tgtdev_lock, flags);
0788 }
0789
0790
0791
0792
0793
0794
0795
0796
0797
0798
0799 static void mpi3mr_print_device_event_notice(struct mpi3mr_ioc *mrioc,
0800 bool device_add)
0801 {
0802 ioc_notice(mrioc, "Device %s was in progress before the reset and\n",
0803 (device_add ? "addition" : "removal"));
0804 ioc_notice(mrioc, "completed after reset, verify whether the exposed devices\n");
0805 ioc_notice(mrioc, "are matched with attached devices for correctness\n");
0806 }
0807
0808
0809
0810
0811
0812
0813
0814
0815
0816
0817
0818
0819 static void mpi3mr_remove_tgtdev_from_host(struct mpi3mr_ioc *mrioc,
0820 struct mpi3mr_tgt_dev *tgtdev)
0821 {
0822 struct mpi3mr_stgt_priv_data *tgt_priv;
0823
0824 ioc_info(mrioc, "%s :Removing handle(0x%04x), wwid(0x%016llx)\n",
0825 __func__, tgtdev->dev_handle, (unsigned long long)tgtdev->wwid);
0826 if (tgtdev->starget && tgtdev->starget->hostdata) {
0827 tgt_priv = tgtdev->starget->hostdata;
0828 tgt_priv->dev_handle = MPI3MR_INVALID_DEV_HANDLE;
0829 }
0830
0831 if (tgtdev->starget) {
0832 if (mrioc->current_event)
0833 mrioc->current_event->pending_at_sml = 1;
0834 scsi_remove_target(&tgtdev->starget->dev);
0835 tgtdev->host_exposed = 0;
0836 if (mrioc->current_event) {
0837 mrioc->current_event->pending_at_sml = 0;
0838 if (mrioc->current_event->discard) {
0839 mpi3mr_print_device_event_notice(mrioc, false);
0840 return;
0841 }
0842 }
0843 }
0844 ioc_info(mrioc, "%s :Removed handle(0x%04x), wwid(0x%016llx)\n",
0845 __func__, tgtdev->dev_handle, (unsigned long long)tgtdev->wwid);
0846 }
0847
0848
0849
0850
0851
0852
0853
0854
0855
0856
0857
0858
0859 static int mpi3mr_report_tgtdev_to_host(struct mpi3mr_ioc *mrioc,
0860 u16 perst_id)
0861 {
0862 int retval = 0;
0863 struct mpi3mr_tgt_dev *tgtdev;
0864
0865 tgtdev = mpi3mr_get_tgtdev_by_perst_id(mrioc, perst_id);
0866 if (!tgtdev) {
0867 retval = -1;
0868 goto out;
0869 }
0870 if (tgtdev->is_hidden) {
0871 retval = -1;
0872 goto out;
0873 }
0874 if (!tgtdev->host_exposed && !mrioc->reset_in_progress) {
0875 tgtdev->host_exposed = 1;
0876 if (mrioc->current_event)
0877 mrioc->current_event->pending_at_sml = 1;
0878 scsi_scan_target(&mrioc->shost->shost_gendev, 0,
0879 tgtdev->perst_id,
0880 SCAN_WILD_CARD, SCSI_SCAN_INITIAL);
0881 if (!tgtdev->starget)
0882 tgtdev->host_exposed = 0;
0883 if (mrioc->current_event) {
0884 mrioc->current_event->pending_at_sml = 0;
0885 if (mrioc->current_event->discard) {
0886 mpi3mr_print_device_event_notice(mrioc, true);
0887 goto out;
0888 }
0889 }
0890 }
0891 out:
0892 if (tgtdev)
0893 mpi3mr_tgtdev_put(tgtdev);
0894
0895 return retval;
0896 }
0897
0898
0899
0900
0901
0902
0903
0904
0905
0906
0907 static int mpi3mr_change_queue_depth(struct scsi_device *sdev,
0908 int q_depth)
0909 {
0910 struct scsi_target *starget = scsi_target(sdev);
0911 struct Scsi_Host *shost = dev_to_shost(&starget->dev);
0912 int retval = 0;
0913
0914 if (!sdev->tagged_supported)
0915 q_depth = 1;
0916 if (q_depth > shost->can_queue)
0917 q_depth = shost->can_queue;
0918 else if (!q_depth)
0919 q_depth = MPI3MR_DEFAULT_SDEV_QD;
0920 retval = scsi_change_queue_depth(sdev, q_depth);
0921 sdev->max_queue_depth = sdev->queue_depth;
0922
0923 return retval;
0924 }
0925
0926
0927
0928
0929
0930
0931
0932
0933
0934
0935
0936
0937 static void
0938 mpi3mr_update_sdev(struct scsi_device *sdev, void *data)
0939 {
0940 struct mpi3mr_tgt_dev *tgtdev;
0941
0942 tgtdev = (struct mpi3mr_tgt_dev *)data;
0943 if (!tgtdev)
0944 return;
0945
0946 mpi3mr_change_queue_depth(sdev, tgtdev->q_depth);
0947 switch (tgtdev->dev_type) {
0948 case MPI3_DEVICE_DEVFORM_PCIE:
0949
0950 if ((tgtdev->dev_spec.pcie_inf.dev_info &
0951 MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK) ==
0952 MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE) {
0953 blk_queue_max_hw_sectors(sdev->request_queue,
0954 tgtdev->dev_spec.pcie_inf.mdts / 512);
0955 if (tgtdev->dev_spec.pcie_inf.pgsz == 0)
0956 blk_queue_virt_boundary(sdev->request_queue,
0957 ((1 << MPI3MR_DEFAULT_PGSZEXP) - 1));
0958 else
0959 blk_queue_virt_boundary(sdev->request_queue,
0960 ((1 << tgtdev->dev_spec.pcie_inf.pgsz) - 1));
0961 }
0962 break;
0963 default:
0964 break;
0965 }
0966 }
0967
0968
0969
0970
0971
0972
0973
0974
0975
0976
0977
0978
0979 void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc)
0980 {
0981 struct mpi3mr_tgt_dev *tgtdev, *tgtdev_next;
0982
0983 list_for_each_entry_safe(tgtdev, tgtdev_next, &mrioc->tgtdev_list,
0984 list) {
0985 if (tgtdev->dev_handle == MPI3MR_INVALID_DEV_HANDLE) {
0986 dprint_reset(mrioc, "removing target device with perst_id(%d)\n",
0987 tgtdev->perst_id);
0988 if (tgtdev->host_exposed)
0989 mpi3mr_remove_tgtdev_from_host(mrioc, tgtdev);
0990 mpi3mr_tgtdev_del_from_list(mrioc, tgtdev);
0991 mpi3mr_tgtdev_put(tgtdev);
0992 }
0993 }
0994
0995 tgtdev = NULL;
0996 list_for_each_entry(tgtdev, &mrioc->tgtdev_list, list) {
0997 if ((tgtdev->dev_handle != MPI3MR_INVALID_DEV_HANDLE) &&
0998 !tgtdev->is_hidden && !tgtdev->host_exposed)
0999 mpi3mr_report_tgtdev_to_host(mrioc, tgtdev->perst_id);
1000 }
1001 }
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015 static void mpi3mr_update_tgtdev(struct mpi3mr_ioc *mrioc,
1016 struct mpi3mr_tgt_dev *tgtdev, struct mpi3_device_page0 *dev_pg0,
1017 bool is_added)
1018 {
1019 u16 flags = 0;
1020 struct mpi3mr_stgt_priv_data *scsi_tgt_priv_data = NULL;
1021 u8 prot_mask = 0;
1022
1023 tgtdev->perst_id = le16_to_cpu(dev_pg0->persistent_id);
1024 tgtdev->dev_handle = le16_to_cpu(dev_pg0->dev_handle);
1025 tgtdev->dev_type = dev_pg0->device_form;
1026 tgtdev->encl_handle = le16_to_cpu(dev_pg0->enclosure_handle);
1027 tgtdev->parent_handle = le16_to_cpu(dev_pg0->parent_dev_handle);
1028 tgtdev->slot = le16_to_cpu(dev_pg0->slot);
1029 tgtdev->q_depth = le16_to_cpu(dev_pg0->queue_depth);
1030 tgtdev->wwid = le64_to_cpu(dev_pg0->wwid);
1031
1032 flags = le16_to_cpu(dev_pg0->flags);
1033 tgtdev->is_hidden = (flags & MPI3_DEVICE0_FLAGS_HIDDEN);
1034
1035 if (is_added == true)
1036 tgtdev->io_throttle_enabled =
1037 (flags & MPI3_DEVICE0_FLAGS_IO_THROTTLING_REQUIRED) ? 1 : 0;
1038
1039
1040 if (tgtdev->starget && tgtdev->starget->hostdata) {
1041 scsi_tgt_priv_data = (struct mpi3mr_stgt_priv_data *)
1042 tgtdev->starget->hostdata;
1043 scsi_tgt_priv_data->perst_id = tgtdev->perst_id;
1044 scsi_tgt_priv_data->dev_handle = tgtdev->dev_handle;
1045 scsi_tgt_priv_data->dev_type = tgtdev->dev_type;
1046 scsi_tgt_priv_data->io_throttle_enabled =
1047 tgtdev->io_throttle_enabled;
1048 }
1049
1050 switch (dev_pg0->access_status) {
1051 case MPI3_DEVICE0_ASTATUS_NO_ERRORS:
1052 case MPI3_DEVICE0_ASTATUS_PREPARE:
1053 case MPI3_DEVICE0_ASTATUS_NEEDS_INITIALIZATION:
1054 case MPI3_DEVICE0_ASTATUS_DEVICE_MISSING_DELAY:
1055 break;
1056 default:
1057 tgtdev->is_hidden = 1;
1058 break;
1059 }
1060
1061 switch (tgtdev->dev_type) {
1062 case MPI3_DEVICE_DEVFORM_SAS_SATA:
1063 {
1064 struct mpi3_device0_sas_sata_format *sasinf =
1065 &dev_pg0->device_specific.sas_sata_format;
1066 u16 dev_info = le16_to_cpu(sasinf->device_info);
1067
1068 tgtdev->dev_spec.sas_sata_inf.dev_info = dev_info;
1069 tgtdev->dev_spec.sas_sata_inf.sas_address =
1070 le64_to_cpu(sasinf->sas_address);
1071 if ((dev_info & MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_MASK) !=
1072 MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_END_DEVICE)
1073 tgtdev->is_hidden = 1;
1074 else if (!(dev_info & (MPI3_SAS_DEVICE_INFO_STP_SATA_TARGET |
1075 MPI3_SAS_DEVICE_INFO_SSP_TARGET)))
1076 tgtdev->is_hidden = 1;
1077 break;
1078 }
1079 case MPI3_DEVICE_DEVFORM_PCIE:
1080 {
1081 struct mpi3_device0_pcie_format *pcieinf =
1082 &dev_pg0->device_specific.pcie_format;
1083 u16 dev_info = le16_to_cpu(pcieinf->device_info);
1084
1085 tgtdev->dev_spec.pcie_inf.dev_info = dev_info;
1086 tgtdev->dev_spec.pcie_inf.capb =
1087 le32_to_cpu(pcieinf->capabilities);
1088 tgtdev->dev_spec.pcie_inf.mdts = MPI3MR_DEFAULT_MDTS;
1089
1090 tgtdev->dev_spec.pcie_inf.pgsz = 12;
1091 if (dev_pg0->access_status == MPI3_DEVICE0_ASTATUS_NO_ERRORS) {
1092 tgtdev->dev_spec.pcie_inf.mdts =
1093 le32_to_cpu(pcieinf->maximum_data_transfer_size);
1094 tgtdev->dev_spec.pcie_inf.pgsz = pcieinf->page_size;
1095 tgtdev->dev_spec.pcie_inf.reset_to =
1096 max_t(u8, pcieinf->controller_reset_to,
1097 MPI3MR_INTADMCMD_TIMEOUT);
1098 tgtdev->dev_spec.pcie_inf.abort_to =
1099 max_t(u8, pcieinf->nvme_abort_to,
1100 MPI3MR_INTADMCMD_TIMEOUT);
1101 }
1102 if (tgtdev->dev_spec.pcie_inf.mdts > (1024 * 1024))
1103 tgtdev->dev_spec.pcie_inf.mdts = (1024 * 1024);
1104 if (((dev_info & MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK) !=
1105 MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE) &&
1106 ((dev_info & MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK) !=
1107 MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SCSI_DEVICE))
1108 tgtdev->is_hidden = 1;
1109 if (!mrioc->shost)
1110 break;
1111 prot_mask = scsi_host_get_prot(mrioc->shost);
1112 if (prot_mask & SHOST_DIX_TYPE0_PROTECTION) {
1113 scsi_host_set_prot(mrioc->shost, prot_mask & 0x77);
1114 ioc_info(mrioc,
1115 "%s : Disabling DIX0 prot capability\n", __func__);
1116 ioc_info(mrioc,
1117 "because HBA does not support DIX0 operation on NVME drives\n");
1118 }
1119 break;
1120 }
1121 case MPI3_DEVICE_DEVFORM_VD:
1122 {
1123 struct mpi3_device0_vd_format *vdinf =
1124 &dev_pg0->device_specific.vd_format;
1125 struct mpi3mr_throttle_group_info *tg = NULL;
1126 u16 vdinf_io_throttle_group =
1127 le16_to_cpu(vdinf->io_throttle_group);
1128
1129 tgtdev->dev_spec.vd_inf.state = vdinf->vd_state;
1130 if (vdinf->vd_state == MPI3_DEVICE0_VD_STATE_OFFLINE)
1131 tgtdev->is_hidden = 1;
1132 tgtdev->dev_spec.vd_inf.tg_id = vdinf_io_throttle_group;
1133 tgtdev->dev_spec.vd_inf.tg_high =
1134 le16_to_cpu(vdinf->io_throttle_group_high) * 2048;
1135 tgtdev->dev_spec.vd_inf.tg_low =
1136 le16_to_cpu(vdinf->io_throttle_group_low) * 2048;
1137 if (vdinf_io_throttle_group < mrioc->num_io_throttle_group) {
1138 tg = mrioc->throttle_groups + vdinf_io_throttle_group;
1139 tg->id = vdinf_io_throttle_group;
1140 tg->high = tgtdev->dev_spec.vd_inf.tg_high;
1141 tg->low = tgtdev->dev_spec.vd_inf.tg_low;
1142 tg->qd_reduction =
1143 tgtdev->dev_spec.vd_inf.tg_qd_reduction;
1144 if (is_added == true)
1145 tg->fw_qd = tgtdev->q_depth;
1146 tg->modified_qd = tgtdev->q_depth;
1147 }
1148 tgtdev->dev_spec.vd_inf.tg = tg;
1149 if (scsi_tgt_priv_data)
1150 scsi_tgt_priv_data->throttle_group = tg;
1151 break;
1152 }
1153 default:
1154 break;
1155 }
1156 }
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169 static void mpi3mr_devstatuschg_evt_bh(struct mpi3mr_ioc *mrioc,
1170 struct mpi3mr_fwevt *fwevt)
1171 {
1172 u16 dev_handle = 0;
1173 u8 uhide = 0, delete = 0, cleanup = 0;
1174 struct mpi3mr_tgt_dev *tgtdev = NULL;
1175 struct mpi3_event_data_device_status_change *evtdata =
1176 (struct mpi3_event_data_device_status_change *)fwevt->event_data;
1177
1178 dev_handle = le16_to_cpu(evtdata->dev_handle);
1179 ioc_info(mrioc,
1180 "%s :device status change: handle(0x%04x): reason code(0x%x)\n",
1181 __func__, dev_handle, evtdata->reason_code);
1182 switch (evtdata->reason_code) {
1183 case MPI3_EVENT_DEV_STAT_RC_HIDDEN:
1184 delete = 1;
1185 break;
1186 case MPI3_EVENT_DEV_STAT_RC_NOT_HIDDEN:
1187 uhide = 1;
1188 break;
1189 case MPI3_EVENT_DEV_STAT_RC_VD_NOT_RESPONDING:
1190 delete = 1;
1191 cleanup = 1;
1192 break;
1193 default:
1194 ioc_info(mrioc, "%s :Unhandled reason code(0x%x)\n", __func__,
1195 evtdata->reason_code);
1196 break;
1197 }
1198
1199 tgtdev = mpi3mr_get_tgtdev_by_handle(mrioc, dev_handle);
1200 if (!tgtdev)
1201 goto out;
1202 if (uhide) {
1203 tgtdev->is_hidden = 0;
1204 if (!tgtdev->host_exposed)
1205 mpi3mr_report_tgtdev_to_host(mrioc, tgtdev->perst_id);
1206 }
1207 if (tgtdev->starget && tgtdev->starget->hostdata) {
1208 if (delete)
1209 mpi3mr_remove_tgtdev_from_host(mrioc, tgtdev);
1210 }
1211 if (cleanup) {
1212 mpi3mr_tgtdev_del_from_list(mrioc, tgtdev);
1213 mpi3mr_tgtdev_put(tgtdev);
1214 }
1215
1216 out:
1217 if (tgtdev)
1218 mpi3mr_tgtdev_put(tgtdev);
1219 }
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233 static void mpi3mr_devinfochg_evt_bh(struct mpi3mr_ioc *mrioc,
1234 struct mpi3_device_page0 *dev_pg0)
1235 {
1236 struct mpi3mr_tgt_dev *tgtdev = NULL;
1237 u16 dev_handle = 0, perst_id = 0;
1238
1239 perst_id = le16_to_cpu(dev_pg0->persistent_id);
1240 dev_handle = le16_to_cpu(dev_pg0->dev_handle);
1241 ioc_info(mrioc,
1242 "%s :Device info change: handle(0x%04x): persist_id(0x%x)\n",
1243 __func__, dev_handle, perst_id);
1244 tgtdev = mpi3mr_get_tgtdev_by_handle(mrioc, dev_handle);
1245 if (!tgtdev)
1246 goto out;
1247 mpi3mr_update_tgtdev(mrioc, tgtdev, dev_pg0, false);
1248 if (!tgtdev->is_hidden && !tgtdev->host_exposed)
1249 mpi3mr_report_tgtdev_to_host(mrioc, perst_id);
1250 if (tgtdev->is_hidden && tgtdev->host_exposed)
1251 mpi3mr_remove_tgtdev_from_host(mrioc, tgtdev);
1252 if (!tgtdev->is_hidden && tgtdev->host_exposed && tgtdev->starget)
1253 starget_for_each_device(tgtdev->starget, (void *)tgtdev,
1254 mpi3mr_update_sdev);
1255 out:
1256 if (tgtdev)
1257 mpi3mr_tgtdev_put(tgtdev);
1258 }
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269 static void
1270 mpi3mr_sastopochg_evt_debug(struct mpi3mr_ioc *mrioc,
1271 struct mpi3_event_data_sas_topology_change_list *event_data)
1272 {
1273 int i;
1274 u16 handle;
1275 u8 reason_code, phy_number;
1276 char *status_str = NULL;
1277 u8 link_rate, prev_link_rate;
1278
1279 switch (event_data->exp_status) {
1280 case MPI3_EVENT_SAS_TOPO_ES_NOT_RESPONDING:
1281 status_str = "remove";
1282 break;
1283 case MPI3_EVENT_SAS_TOPO_ES_RESPONDING:
1284 status_str = "responding";
1285 break;
1286 case MPI3_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING:
1287 status_str = "remove delay";
1288 break;
1289 case MPI3_EVENT_SAS_TOPO_ES_NO_EXPANDER:
1290 status_str = "direct attached";
1291 break;
1292 default:
1293 status_str = "unknown status";
1294 break;
1295 }
1296 ioc_info(mrioc, "%s :sas topology change: (%s)\n",
1297 __func__, status_str);
1298 ioc_info(mrioc,
1299 "%s :\texpander_handle(0x%04x), enclosure_handle(0x%04x) start_phy(%02d), num_entries(%d)\n",
1300 __func__, le16_to_cpu(event_data->expander_dev_handle),
1301 le16_to_cpu(event_data->enclosure_handle),
1302 event_data->start_phy_num, event_data->num_entries);
1303 for (i = 0; i < event_data->num_entries; i++) {
1304 handle = le16_to_cpu(event_data->phy_entry[i].attached_dev_handle);
1305 if (!handle)
1306 continue;
1307 phy_number = event_data->start_phy_num + i;
1308 reason_code = event_data->phy_entry[i].status &
1309 MPI3_EVENT_SAS_TOPO_PHY_RC_MASK;
1310 switch (reason_code) {
1311 case MPI3_EVENT_SAS_TOPO_PHY_RC_TARG_NOT_RESPONDING:
1312 status_str = "target remove";
1313 break;
1314 case MPI3_EVENT_SAS_TOPO_PHY_RC_DELAY_NOT_RESPONDING:
1315 status_str = "delay target remove";
1316 break;
1317 case MPI3_EVENT_SAS_TOPO_PHY_RC_PHY_CHANGED:
1318 status_str = "link status change";
1319 break;
1320 case MPI3_EVENT_SAS_TOPO_PHY_RC_NO_CHANGE:
1321 status_str = "link status no change";
1322 break;
1323 case MPI3_EVENT_SAS_TOPO_PHY_RC_RESPONDING:
1324 status_str = "target responding";
1325 break;
1326 default:
1327 status_str = "unknown";
1328 break;
1329 }
1330 link_rate = event_data->phy_entry[i].link_rate >> 4;
1331 prev_link_rate = event_data->phy_entry[i].link_rate & 0xF;
1332 ioc_info(mrioc,
1333 "%s :\tphy(%02d), attached_handle(0x%04x): %s: link rate: new(0x%02x), old(0x%02x)\n",
1334 __func__, phy_number, handle, status_str, link_rate,
1335 prev_link_rate);
1336 }
1337 }
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350 static void mpi3mr_sastopochg_evt_bh(struct mpi3mr_ioc *mrioc,
1351 struct mpi3mr_fwevt *fwevt)
1352 {
1353 struct mpi3_event_data_sas_topology_change_list *event_data =
1354 (struct mpi3_event_data_sas_topology_change_list *)fwevt->event_data;
1355 int i;
1356 u16 handle;
1357 u8 reason_code;
1358 struct mpi3mr_tgt_dev *tgtdev = NULL;
1359
1360 mpi3mr_sastopochg_evt_debug(mrioc, event_data);
1361
1362 for (i = 0; i < event_data->num_entries; i++) {
1363 if (fwevt->discard)
1364 return;
1365 handle = le16_to_cpu(event_data->phy_entry[i].attached_dev_handle);
1366 if (!handle)
1367 continue;
1368 tgtdev = mpi3mr_get_tgtdev_by_handle(mrioc, handle);
1369 if (!tgtdev)
1370 continue;
1371
1372 reason_code = event_data->phy_entry[i].status &
1373 MPI3_EVENT_SAS_TOPO_PHY_RC_MASK;
1374
1375 switch (reason_code) {
1376 case MPI3_EVENT_SAS_TOPO_PHY_RC_TARG_NOT_RESPONDING:
1377 if (tgtdev->host_exposed)
1378 mpi3mr_remove_tgtdev_from_host(mrioc, tgtdev);
1379 mpi3mr_tgtdev_del_from_list(mrioc, tgtdev);
1380 mpi3mr_tgtdev_put(tgtdev);
1381 break;
1382 default:
1383 break;
1384 }
1385 if (tgtdev)
1386 mpi3mr_tgtdev_put(tgtdev);
1387 }
1388 }
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399 static void
1400 mpi3mr_pcietopochg_evt_debug(struct mpi3mr_ioc *mrioc,
1401 struct mpi3_event_data_pcie_topology_change_list *event_data)
1402 {
1403 int i;
1404 u16 handle;
1405 u16 reason_code;
1406 u8 port_number;
1407 char *status_str = NULL;
1408 u8 link_rate, prev_link_rate;
1409
1410 switch (event_data->switch_status) {
1411 case MPI3_EVENT_PCIE_TOPO_SS_NOT_RESPONDING:
1412 status_str = "remove";
1413 break;
1414 case MPI3_EVENT_PCIE_TOPO_SS_RESPONDING:
1415 status_str = "responding";
1416 break;
1417 case MPI3_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING:
1418 status_str = "remove delay";
1419 break;
1420 case MPI3_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH:
1421 status_str = "direct attached";
1422 break;
1423 default:
1424 status_str = "unknown status";
1425 break;
1426 }
1427 ioc_info(mrioc, "%s :pcie topology change: (%s)\n",
1428 __func__, status_str);
1429 ioc_info(mrioc,
1430 "%s :\tswitch_handle(0x%04x), enclosure_handle(0x%04x) start_port(%02d), num_entries(%d)\n",
1431 __func__, le16_to_cpu(event_data->switch_dev_handle),
1432 le16_to_cpu(event_data->enclosure_handle),
1433 event_data->start_port_num, event_data->num_entries);
1434 for (i = 0; i < event_data->num_entries; i++) {
1435 handle =
1436 le16_to_cpu(event_data->port_entry[i].attached_dev_handle);
1437 if (!handle)
1438 continue;
1439 port_number = event_data->start_port_num + i;
1440 reason_code = event_data->port_entry[i].port_status;
1441 switch (reason_code) {
1442 case MPI3_EVENT_PCIE_TOPO_PS_NOT_RESPONDING:
1443 status_str = "target remove";
1444 break;
1445 case MPI3_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING:
1446 status_str = "delay target remove";
1447 break;
1448 case MPI3_EVENT_PCIE_TOPO_PS_PORT_CHANGED:
1449 status_str = "link status change";
1450 break;
1451 case MPI3_EVENT_PCIE_TOPO_PS_NO_CHANGE:
1452 status_str = "link status no change";
1453 break;
1454 case MPI3_EVENT_PCIE_TOPO_PS_RESPONDING:
1455 status_str = "target responding";
1456 break;
1457 default:
1458 status_str = "unknown";
1459 break;
1460 }
1461 link_rate = event_data->port_entry[i].current_port_info &
1462 MPI3_EVENT_PCIE_TOPO_PI_RATE_MASK;
1463 prev_link_rate = event_data->port_entry[i].previous_port_info &
1464 MPI3_EVENT_PCIE_TOPO_PI_RATE_MASK;
1465 ioc_info(mrioc,
1466 "%s :\tport(%02d), attached_handle(0x%04x): %s: link rate: new(0x%02x), old(0x%02x)\n",
1467 __func__, port_number, handle, status_str, link_rate,
1468 prev_link_rate);
1469 }
1470 }
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483 static void mpi3mr_pcietopochg_evt_bh(struct mpi3mr_ioc *mrioc,
1484 struct mpi3mr_fwevt *fwevt)
1485 {
1486 struct mpi3_event_data_pcie_topology_change_list *event_data =
1487 (struct mpi3_event_data_pcie_topology_change_list *)fwevt->event_data;
1488 int i;
1489 u16 handle;
1490 u8 reason_code;
1491 struct mpi3mr_tgt_dev *tgtdev = NULL;
1492
1493 mpi3mr_pcietopochg_evt_debug(mrioc, event_data);
1494
1495 for (i = 0; i < event_data->num_entries; i++) {
1496 if (fwevt->discard)
1497 return;
1498 handle =
1499 le16_to_cpu(event_data->port_entry[i].attached_dev_handle);
1500 if (!handle)
1501 continue;
1502 tgtdev = mpi3mr_get_tgtdev_by_handle(mrioc, handle);
1503 if (!tgtdev)
1504 continue;
1505
1506 reason_code = event_data->port_entry[i].port_status;
1507
1508 switch (reason_code) {
1509 case MPI3_EVENT_PCIE_TOPO_PS_NOT_RESPONDING:
1510 if (tgtdev->host_exposed)
1511 mpi3mr_remove_tgtdev_from_host(mrioc, tgtdev);
1512 mpi3mr_tgtdev_del_from_list(mrioc, tgtdev);
1513 mpi3mr_tgtdev_put(tgtdev);
1514 break;
1515 default:
1516 break;
1517 }
1518 if (tgtdev)
1519 mpi3mr_tgtdev_put(tgtdev);
1520 }
1521 }
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533 static void mpi3mr_logdata_evt_bh(struct mpi3mr_ioc *mrioc,
1534 struct mpi3mr_fwevt *fwevt)
1535 {
1536 mpi3mr_app_save_logdata(mrioc, fwevt->event_data,
1537 fwevt->event_data_size);
1538 }
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550 static void mpi3mr_update_sdev_qd(struct scsi_device *sdev, void *data)
1551 {
1552 u16 *q_depth = (u16 *)data;
1553
1554 scsi_change_queue_depth(sdev, (int)*q_depth);
1555 sdev->max_queue_depth = sdev->queue_depth;
1556 }
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568 static void mpi3mr_set_qd_for_all_vd_in_tg(struct mpi3mr_ioc *mrioc,
1569 struct mpi3mr_throttle_group_info *tg)
1570 {
1571 unsigned long flags;
1572 struct mpi3mr_tgt_dev *tgtdev;
1573 struct mpi3mr_stgt_priv_data *tgt_priv;
1574
1575
1576 spin_lock_irqsave(&mrioc->tgtdev_lock, flags);
1577 list_for_each_entry(tgtdev, &mrioc->tgtdev_list, list) {
1578 if (tgtdev->starget && tgtdev->starget->hostdata) {
1579 tgt_priv = tgtdev->starget->hostdata;
1580 if (tgt_priv->throttle_group == tg) {
1581 dprint_event_bh(mrioc,
1582 "updating qd due to throttling for persist_id(%d) original_qd(%d), reduced_qd (%d)\n",
1583 tgt_priv->perst_id, tgtdev->q_depth,
1584 tg->modified_qd);
1585 starget_for_each_device(tgtdev->starget,
1586 (void *)&tg->modified_qd,
1587 mpi3mr_update_sdev_qd);
1588 }
1589 }
1590 }
1591 spin_unlock_irqrestore(&mrioc->tgtdev_lock, flags);
1592 }
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604 static void mpi3mr_fwevt_bh(struct mpi3mr_ioc *mrioc,
1605 struct mpi3mr_fwevt *fwevt)
1606 {
1607 mpi3mr_fwevt_del_from_list(mrioc, fwevt);
1608 mrioc->current_event = fwevt;
1609
1610 if (mrioc->stop_drv_processing)
1611 goto out;
1612
1613 if (!fwevt->process_evt)
1614 goto evt_ack;
1615
1616 switch (fwevt->event_id) {
1617 case MPI3_EVENT_DEVICE_ADDED:
1618 {
1619 struct mpi3_device_page0 *dev_pg0 =
1620 (struct mpi3_device_page0 *)fwevt->event_data;
1621 mpi3mr_report_tgtdev_to_host(mrioc,
1622 le16_to_cpu(dev_pg0->persistent_id));
1623 break;
1624 }
1625 case MPI3_EVENT_DEVICE_INFO_CHANGED:
1626 {
1627 mpi3mr_devinfochg_evt_bh(mrioc,
1628 (struct mpi3_device_page0 *)fwevt->event_data);
1629 break;
1630 }
1631 case MPI3_EVENT_DEVICE_STATUS_CHANGE:
1632 {
1633 mpi3mr_devstatuschg_evt_bh(mrioc, fwevt);
1634 break;
1635 }
1636 case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
1637 {
1638 mpi3mr_sastopochg_evt_bh(mrioc, fwevt);
1639 break;
1640 }
1641 case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
1642 {
1643 mpi3mr_pcietopochg_evt_bh(mrioc, fwevt);
1644 break;
1645 }
1646 case MPI3_EVENT_LOG_DATA:
1647 {
1648 mpi3mr_logdata_evt_bh(mrioc, fwevt);
1649 break;
1650 }
1651 case MPI3MR_DRIVER_EVENT_TG_QD_REDUCTION:
1652 {
1653 struct mpi3mr_throttle_group_info *tg;
1654
1655 tg = *(struct mpi3mr_throttle_group_info **)fwevt->event_data;
1656 dprint_event_bh(mrioc,
1657 "qd reduction event processed for tg_id(%d) reduction_needed(%d)\n",
1658 tg->id, tg->need_qd_reduction);
1659 if (tg->need_qd_reduction) {
1660 mpi3mr_set_qd_for_all_vd_in_tg(mrioc, tg);
1661 tg->need_qd_reduction = 0;
1662 }
1663 break;
1664 }
1665 default:
1666 break;
1667 }
1668
1669 evt_ack:
1670 if (fwevt->send_ack)
1671 mpi3mr_process_event_ack(mrioc, fwevt->event_id,
1672 fwevt->evt_ctx);
1673 out:
1674
1675 mpi3mr_fwevt_put(fwevt);
1676 mrioc->current_event = NULL;
1677 }
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687 static void mpi3mr_fwevt_worker(struct work_struct *work)
1688 {
1689 struct mpi3mr_fwevt *fwevt = container_of(work, struct mpi3mr_fwevt,
1690 work);
1691 mpi3mr_fwevt_bh(fwevt->mrioc, fwevt);
1692
1693
1694
1695
1696 mpi3mr_fwevt_put(fwevt);
1697 }
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711 static int mpi3mr_create_tgtdev(struct mpi3mr_ioc *mrioc,
1712 struct mpi3_device_page0 *dev_pg0)
1713 {
1714 int retval = 0;
1715 struct mpi3mr_tgt_dev *tgtdev = NULL;
1716 u16 perst_id = 0;
1717
1718 perst_id = le16_to_cpu(dev_pg0->persistent_id);
1719 tgtdev = mpi3mr_get_tgtdev_by_perst_id(mrioc, perst_id);
1720 if (tgtdev) {
1721 mpi3mr_update_tgtdev(mrioc, tgtdev, dev_pg0, true);
1722 mpi3mr_tgtdev_put(tgtdev);
1723 } else {
1724 tgtdev = mpi3mr_alloc_tgtdev();
1725 if (!tgtdev)
1726 return -ENOMEM;
1727 mpi3mr_update_tgtdev(mrioc, tgtdev, dev_pg0, true);
1728 mpi3mr_tgtdev_add_to_list(mrioc, tgtdev);
1729 }
1730
1731 return retval;
1732 }
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743 void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc)
1744 {
1745 struct delayed_dev_rmhs_node *_rmhs_node;
1746 struct delayed_evt_ack_node *_evtack_node;
1747
1748 dprint_reset(mrioc, "flushing delayed dev_remove_hs commands\n");
1749 while (!list_empty(&mrioc->delayed_rmhs_list)) {
1750 _rmhs_node = list_entry(mrioc->delayed_rmhs_list.next,
1751 struct delayed_dev_rmhs_node, list);
1752 list_del(&_rmhs_node->list);
1753 kfree(_rmhs_node);
1754 }
1755 dprint_reset(mrioc, "flushing delayed event ack commands\n");
1756 while (!list_empty(&mrioc->delayed_evtack_cmds_list)) {
1757 _evtack_node = list_entry(mrioc->delayed_evtack_cmds_list.next,
1758 struct delayed_evt_ack_node, list);
1759 list_del(&_evtack_node->list);
1760 kfree(_evtack_node);
1761 }
1762 }
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775 static void mpi3mr_dev_rmhs_complete_iou(struct mpi3mr_ioc *mrioc,
1776 struct mpi3mr_drv_cmd *drv_cmd)
1777 {
1778 u16 cmd_idx = drv_cmd->host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN;
1779 struct delayed_dev_rmhs_node *delayed_dev_rmhs = NULL;
1780
1781 if (drv_cmd->state & MPI3MR_CMD_RESET)
1782 goto clear_drv_cmd;
1783
1784 ioc_info(mrioc,
1785 "%s :dev_rmhs_iouctrl_complete:handle(0x%04x), ioc_status(0x%04x), loginfo(0x%08x)\n",
1786 __func__, drv_cmd->dev_handle, drv_cmd->ioc_status,
1787 drv_cmd->ioc_loginfo);
1788 if (drv_cmd->ioc_status != MPI3_IOCSTATUS_SUCCESS) {
1789 if (drv_cmd->retry_count < MPI3MR_DEV_RMHS_RETRY_COUNT) {
1790 drv_cmd->retry_count++;
1791 ioc_info(mrioc,
1792 "%s :dev_rmhs_iouctrl_complete: handle(0x%04x)retrying handshake retry=%d\n",
1793 __func__, drv_cmd->dev_handle,
1794 drv_cmd->retry_count);
1795 mpi3mr_dev_rmhs_send_tm(mrioc, drv_cmd->dev_handle,
1796 drv_cmd, drv_cmd->iou_rc);
1797 return;
1798 }
1799 ioc_err(mrioc,
1800 "%s :dev removal handshake failed after all retries: handle(0x%04x)\n",
1801 __func__, drv_cmd->dev_handle);
1802 } else {
1803 ioc_info(mrioc,
1804 "%s :dev removal handshake completed successfully: handle(0x%04x)\n",
1805 __func__, drv_cmd->dev_handle);
1806 clear_bit(drv_cmd->dev_handle, mrioc->removepend_bitmap);
1807 }
1808
1809 if (!list_empty(&mrioc->delayed_rmhs_list)) {
1810 delayed_dev_rmhs = list_entry(mrioc->delayed_rmhs_list.next,
1811 struct delayed_dev_rmhs_node, list);
1812 drv_cmd->dev_handle = delayed_dev_rmhs->handle;
1813 drv_cmd->retry_count = 0;
1814 drv_cmd->iou_rc = delayed_dev_rmhs->iou_rc;
1815 ioc_info(mrioc,
1816 "%s :dev_rmhs_iouctrl_complete: processing delayed TM: handle(0x%04x)\n",
1817 __func__, drv_cmd->dev_handle);
1818 mpi3mr_dev_rmhs_send_tm(mrioc, drv_cmd->dev_handle, drv_cmd,
1819 drv_cmd->iou_rc);
1820 list_del(&delayed_dev_rmhs->list);
1821 kfree(delayed_dev_rmhs);
1822 return;
1823 }
1824
1825 clear_drv_cmd:
1826 drv_cmd->state = MPI3MR_CMD_NOTUSED;
1827 drv_cmd->callback = NULL;
1828 drv_cmd->retry_count = 0;
1829 drv_cmd->dev_handle = MPI3MR_INVALID_DEV_HANDLE;
1830 clear_bit(cmd_idx, mrioc->devrem_bitmap);
1831 }
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844 static void mpi3mr_dev_rmhs_complete_tm(struct mpi3mr_ioc *mrioc,
1845 struct mpi3mr_drv_cmd *drv_cmd)
1846 {
1847 struct mpi3_iounit_control_request iou_ctrl;
1848 u16 cmd_idx = drv_cmd->host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN;
1849 struct mpi3_scsi_task_mgmt_reply *tm_reply = NULL;
1850 int retval;
1851
1852 if (drv_cmd->state & MPI3MR_CMD_RESET)
1853 goto clear_drv_cmd;
1854
1855 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
1856 tm_reply = (struct mpi3_scsi_task_mgmt_reply *)drv_cmd->reply;
1857
1858 if (tm_reply)
1859 pr_info(IOCNAME
1860 "dev_rmhs_tr_complete:handle(0x%04x), ioc_status(0x%04x), loginfo(0x%08x), term_count(%d)\n",
1861 mrioc->name, drv_cmd->dev_handle, drv_cmd->ioc_status,
1862 drv_cmd->ioc_loginfo,
1863 le32_to_cpu(tm_reply->termination_count));
1864
1865 pr_info(IOCNAME "Issuing IOU CTL: handle(0x%04x) dev_rmhs idx(%d)\n",
1866 mrioc->name, drv_cmd->dev_handle, cmd_idx);
1867
1868 memset(&iou_ctrl, 0, sizeof(iou_ctrl));
1869
1870 drv_cmd->state = MPI3MR_CMD_PENDING;
1871 drv_cmd->is_waiting = 0;
1872 drv_cmd->callback = mpi3mr_dev_rmhs_complete_iou;
1873 iou_ctrl.operation = drv_cmd->iou_rc;
1874 iou_ctrl.param16[0] = cpu_to_le16(drv_cmd->dev_handle);
1875 iou_ctrl.host_tag = cpu_to_le16(drv_cmd->host_tag);
1876 iou_ctrl.function = MPI3_FUNCTION_IO_UNIT_CONTROL;
1877
1878 retval = mpi3mr_admin_request_post(mrioc, &iou_ctrl, sizeof(iou_ctrl),
1879 1);
1880 if (retval) {
1881 pr_err(IOCNAME "Issue DevRmHsTMIOUCTL: Admin post failed\n",
1882 mrioc->name);
1883 goto clear_drv_cmd;
1884 }
1885
1886 return;
1887 clear_drv_cmd:
1888 drv_cmd->state = MPI3MR_CMD_NOTUSED;
1889 drv_cmd->callback = NULL;
1890 drv_cmd->dev_handle = MPI3MR_INVALID_DEV_HANDLE;
1891 drv_cmd->retry_count = 0;
1892 clear_bit(cmd_idx, mrioc->devrem_bitmap);
1893 }
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908 static void mpi3mr_dev_rmhs_send_tm(struct mpi3mr_ioc *mrioc, u16 handle,
1909 struct mpi3mr_drv_cmd *cmdparam, u8 iou_rc)
1910 {
1911 struct mpi3_scsi_task_mgmt_request tm_req;
1912 int retval = 0;
1913 u16 cmd_idx = MPI3MR_NUM_DEVRMCMD;
1914 u8 retrycount = 5;
1915 struct mpi3mr_drv_cmd *drv_cmd = cmdparam;
1916 struct delayed_dev_rmhs_node *delayed_dev_rmhs = NULL;
1917
1918 if (drv_cmd)
1919 goto issue_cmd;
1920 do {
1921 cmd_idx = find_first_zero_bit(mrioc->devrem_bitmap,
1922 MPI3MR_NUM_DEVRMCMD);
1923 if (cmd_idx < MPI3MR_NUM_DEVRMCMD) {
1924 if (!test_and_set_bit(cmd_idx, mrioc->devrem_bitmap))
1925 break;
1926 cmd_idx = MPI3MR_NUM_DEVRMCMD;
1927 }
1928 } while (retrycount--);
1929
1930 if (cmd_idx >= MPI3MR_NUM_DEVRMCMD) {
1931 delayed_dev_rmhs = kzalloc(sizeof(*delayed_dev_rmhs),
1932 GFP_ATOMIC);
1933 if (!delayed_dev_rmhs)
1934 return;
1935 INIT_LIST_HEAD(&delayed_dev_rmhs->list);
1936 delayed_dev_rmhs->handle = handle;
1937 delayed_dev_rmhs->iou_rc = iou_rc;
1938 list_add_tail(&delayed_dev_rmhs->list,
1939 &mrioc->delayed_rmhs_list);
1940 ioc_info(mrioc, "%s :DevRmHs: tr:handle(0x%04x) is postponed\n",
1941 __func__, handle);
1942 return;
1943 }
1944 drv_cmd = &mrioc->dev_rmhs_cmds[cmd_idx];
1945
1946 issue_cmd:
1947 cmd_idx = drv_cmd->host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN;
1948 ioc_info(mrioc,
1949 "%s :Issuing TR TM: for devhandle 0x%04x with dev_rmhs %d\n",
1950 __func__, handle, cmd_idx);
1951
1952 memset(&tm_req, 0, sizeof(tm_req));
1953 if (drv_cmd->state & MPI3MR_CMD_PENDING) {
1954 ioc_err(mrioc, "%s :Issue TM: Command is in use\n", __func__);
1955 goto out;
1956 }
1957 drv_cmd->state = MPI3MR_CMD_PENDING;
1958 drv_cmd->is_waiting = 0;
1959 drv_cmd->callback = mpi3mr_dev_rmhs_complete_tm;
1960 drv_cmd->dev_handle = handle;
1961 drv_cmd->iou_rc = iou_rc;
1962 tm_req.dev_handle = cpu_to_le16(handle);
1963 tm_req.task_type = MPI3_SCSITASKMGMT_TASKTYPE_TARGET_RESET;
1964 tm_req.host_tag = cpu_to_le16(drv_cmd->host_tag);
1965 tm_req.task_host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INVALID);
1966 tm_req.function = MPI3_FUNCTION_SCSI_TASK_MGMT;
1967
1968 set_bit(handle, mrioc->removepend_bitmap);
1969 retval = mpi3mr_admin_request_post(mrioc, &tm_req, sizeof(tm_req), 1);
1970 if (retval) {
1971 ioc_err(mrioc, "%s :Issue DevRmHsTM: Admin Post failed\n",
1972 __func__);
1973 goto out_failed;
1974 }
1975 out:
1976 return;
1977 out_failed:
1978 drv_cmd->state = MPI3MR_CMD_NOTUSED;
1979 drv_cmd->callback = NULL;
1980 drv_cmd->dev_handle = MPI3MR_INVALID_DEV_HANDLE;
1981 drv_cmd->retry_count = 0;
1982 clear_bit(cmd_idx, mrioc->devrem_bitmap);
1983 }
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996 static void mpi3mr_complete_evt_ack(struct mpi3mr_ioc *mrioc,
1997 struct mpi3mr_drv_cmd *drv_cmd)
1998 {
1999 u16 cmd_idx = drv_cmd->host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN;
2000 struct delayed_evt_ack_node *delayed_evtack = NULL;
2001
2002 if (drv_cmd->state & MPI3MR_CMD_RESET)
2003 goto clear_drv_cmd;
2004
2005 if (drv_cmd->ioc_status != MPI3_IOCSTATUS_SUCCESS) {
2006 dprint_event_th(mrioc,
2007 "immediate event ack failed with ioc_status(0x%04x) log_info(0x%08x)\n",
2008 (drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2009 drv_cmd->ioc_loginfo);
2010 }
2011
2012 if (!list_empty(&mrioc->delayed_evtack_cmds_list)) {
2013 delayed_evtack =
2014 list_entry(mrioc->delayed_evtack_cmds_list.next,
2015 struct delayed_evt_ack_node, list);
2016 mpi3mr_send_event_ack(mrioc, delayed_evtack->event, drv_cmd,
2017 delayed_evtack->event_ctx);
2018 list_del(&delayed_evtack->list);
2019 kfree(delayed_evtack);
2020 return;
2021 }
2022 clear_drv_cmd:
2023 drv_cmd->state = MPI3MR_CMD_NOTUSED;
2024 drv_cmd->callback = NULL;
2025 clear_bit(cmd_idx, mrioc->evtack_cmds_bitmap);
2026 }
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042 static void mpi3mr_send_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
2043 struct mpi3mr_drv_cmd *cmdparam, u32 event_ctx)
2044 {
2045 struct mpi3_event_ack_request evtack_req;
2046 int retval = 0;
2047 u8 retrycount = 5;
2048 u16 cmd_idx = MPI3MR_NUM_EVTACKCMD;
2049 struct mpi3mr_drv_cmd *drv_cmd = cmdparam;
2050 struct delayed_evt_ack_node *delayed_evtack = NULL;
2051
2052 if (drv_cmd) {
2053 dprint_event_th(mrioc,
2054 "sending delayed event ack in the top half for event(0x%02x), event_ctx(0x%08x)\n",
2055 event, event_ctx);
2056 goto issue_cmd;
2057 }
2058 dprint_event_th(mrioc,
2059 "sending event ack in the top half for event(0x%02x), event_ctx(0x%08x)\n",
2060 event, event_ctx);
2061 do {
2062 cmd_idx = find_first_zero_bit(mrioc->evtack_cmds_bitmap,
2063 MPI3MR_NUM_EVTACKCMD);
2064 if (cmd_idx < MPI3MR_NUM_EVTACKCMD) {
2065 if (!test_and_set_bit(cmd_idx,
2066 mrioc->evtack_cmds_bitmap))
2067 break;
2068 cmd_idx = MPI3MR_NUM_EVTACKCMD;
2069 }
2070 } while (retrycount--);
2071
2072 if (cmd_idx >= MPI3MR_NUM_EVTACKCMD) {
2073 delayed_evtack = kzalloc(sizeof(*delayed_evtack),
2074 GFP_ATOMIC);
2075 if (!delayed_evtack)
2076 return;
2077 INIT_LIST_HEAD(&delayed_evtack->list);
2078 delayed_evtack->event = event;
2079 delayed_evtack->event_ctx = event_ctx;
2080 list_add_tail(&delayed_evtack->list,
2081 &mrioc->delayed_evtack_cmds_list);
2082 dprint_event_th(mrioc,
2083 "event ack in the top half for event(0x%02x), event_ctx(0x%08x) is postponed\n",
2084 event, event_ctx);
2085 return;
2086 }
2087 drv_cmd = &mrioc->evtack_cmds[cmd_idx];
2088
2089 issue_cmd:
2090 cmd_idx = drv_cmd->host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN;
2091
2092 memset(&evtack_req, 0, sizeof(evtack_req));
2093 if (drv_cmd->state & MPI3MR_CMD_PENDING) {
2094 dprint_event_th(mrioc,
2095 "sending event ack failed due to command in use\n");
2096 goto out;
2097 }
2098 drv_cmd->state = MPI3MR_CMD_PENDING;
2099 drv_cmd->is_waiting = 0;
2100 drv_cmd->callback = mpi3mr_complete_evt_ack;
2101 evtack_req.host_tag = cpu_to_le16(drv_cmd->host_tag);
2102 evtack_req.function = MPI3_FUNCTION_EVENT_ACK;
2103 evtack_req.event = event;
2104 evtack_req.event_context = cpu_to_le32(event_ctx);
2105 retval = mpi3mr_admin_request_post(mrioc, &evtack_req,
2106 sizeof(evtack_req), 1);
2107 if (retval) {
2108 dprint_event_th(mrioc,
2109 "posting event ack request is failed\n");
2110 goto out_failed;
2111 }
2112
2113 dprint_event_th(mrioc,
2114 "event ack in the top half for event(0x%02x), event_ctx(0x%08x) is posted\n",
2115 event, event_ctx);
2116 out:
2117 return;
2118 out_failed:
2119 drv_cmd->state = MPI3MR_CMD_NOTUSED;
2120 drv_cmd->callback = NULL;
2121 clear_bit(cmd_idx, mrioc->evtack_cmds_bitmap);
2122 }
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136 static void mpi3mr_pcietopochg_evt_th(struct mpi3mr_ioc *mrioc,
2137 struct mpi3_event_notification_reply *event_reply)
2138 {
2139 struct mpi3_event_data_pcie_topology_change_list *topo_evt =
2140 (struct mpi3_event_data_pcie_topology_change_list *)event_reply->event_data;
2141 int i;
2142 u16 handle;
2143 u8 reason_code;
2144 struct mpi3mr_tgt_dev *tgtdev = NULL;
2145 struct mpi3mr_stgt_priv_data *scsi_tgt_priv_data = NULL;
2146
2147 for (i = 0; i < topo_evt->num_entries; i++) {
2148 handle = le16_to_cpu(topo_evt->port_entry[i].attached_dev_handle);
2149 if (!handle)
2150 continue;
2151 reason_code = topo_evt->port_entry[i].port_status;
2152 scsi_tgt_priv_data = NULL;
2153 tgtdev = mpi3mr_get_tgtdev_by_handle(mrioc, handle);
2154 if (tgtdev && tgtdev->starget && tgtdev->starget->hostdata)
2155 scsi_tgt_priv_data = (struct mpi3mr_stgt_priv_data *)
2156 tgtdev->starget->hostdata;
2157 switch (reason_code) {
2158 case MPI3_EVENT_PCIE_TOPO_PS_NOT_RESPONDING:
2159 if (scsi_tgt_priv_data) {
2160 scsi_tgt_priv_data->dev_removed = 1;
2161 scsi_tgt_priv_data->dev_removedelay = 0;
2162 atomic_set(&scsi_tgt_priv_data->block_io, 0);
2163 }
2164 mpi3mr_dev_rmhs_send_tm(mrioc, handle, NULL,
2165 MPI3_CTRL_OP_REMOVE_DEVICE);
2166 break;
2167 case MPI3_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING:
2168 if (scsi_tgt_priv_data) {
2169 scsi_tgt_priv_data->dev_removedelay = 1;
2170 atomic_inc(&scsi_tgt_priv_data->block_io);
2171 }
2172 break;
2173 case MPI3_EVENT_PCIE_TOPO_PS_RESPONDING:
2174 if (scsi_tgt_priv_data &&
2175 scsi_tgt_priv_data->dev_removedelay) {
2176 scsi_tgt_priv_data->dev_removedelay = 0;
2177 atomic_dec_if_positive
2178 (&scsi_tgt_priv_data->block_io);
2179 }
2180 break;
2181 case MPI3_EVENT_PCIE_TOPO_PS_PORT_CHANGED:
2182 default:
2183 break;
2184 }
2185 if (tgtdev)
2186 mpi3mr_tgtdev_put(tgtdev);
2187 }
2188 }
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202 static void mpi3mr_sastopochg_evt_th(struct mpi3mr_ioc *mrioc,
2203 struct mpi3_event_notification_reply *event_reply)
2204 {
2205 struct mpi3_event_data_sas_topology_change_list *topo_evt =
2206 (struct mpi3_event_data_sas_topology_change_list *)event_reply->event_data;
2207 int i;
2208 u16 handle;
2209 u8 reason_code;
2210 struct mpi3mr_tgt_dev *tgtdev = NULL;
2211 struct mpi3mr_stgt_priv_data *scsi_tgt_priv_data = NULL;
2212
2213 for (i = 0; i < topo_evt->num_entries; i++) {
2214 handle = le16_to_cpu(topo_evt->phy_entry[i].attached_dev_handle);
2215 if (!handle)
2216 continue;
2217 reason_code = topo_evt->phy_entry[i].status &
2218 MPI3_EVENT_SAS_TOPO_PHY_RC_MASK;
2219 scsi_tgt_priv_data = NULL;
2220 tgtdev = mpi3mr_get_tgtdev_by_handle(mrioc, handle);
2221 if (tgtdev && tgtdev->starget && tgtdev->starget->hostdata)
2222 scsi_tgt_priv_data = (struct mpi3mr_stgt_priv_data *)
2223 tgtdev->starget->hostdata;
2224 switch (reason_code) {
2225 case MPI3_EVENT_SAS_TOPO_PHY_RC_TARG_NOT_RESPONDING:
2226 if (scsi_tgt_priv_data) {
2227 scsi_tgt_priv_data->dev_removed = 1;
2228 scsi_tgt_priv_data->dev_removedelay = 0;
2229 atomic_set(&scsi_tgt_priv_data->block_io, 0);
2230 }
2231 mpi3mr_dev_rmhs_send_tm(mrioc, handle, NULL,
2232 MPI3_CTRL_OP_REMOVE_DEVICE);
2233 break;
2234 case MPI3_EVENT_SAS_TOPO_PHY_RC_DELAY_NOT_RESPONDING:
2235 if (scsi_tgt_priv_data) {
2236 scsi_tgt_priv_data->dev_removedelay = 1;
2237 atomic_inc(&scsi_tgt_priv_data->block_io);
2238 }
2239 break;
2240 case MPI3_EVENT_SAS_TOPO_PHY_RC_RESPONDING:
2241 if (scsi_tgt_priv_data &&
2242 scsi_tgt_priv_data->dev_removedelay) {
2243 scsi_tgt_priv_data->dev_removedelay = 0;
2244 atomic_dec_if_positive
2245 (&scsi_tgt_priv_data->block_io);
2246 }
2247 break;
2248 case MPI3_EVENT_SAS_TOPO_PHY_RC_PHY_CHANGED:
2249 default:
2250 break;
2251 }
2252 if (tgtdev)
2253 mpi3mr_tgtdev_put(tgtdev);
2254 }
2255 }
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269 static void mpi3mr_devstatuschg_evt_th(struct mpi3mr_ioc *mrioc,
2270 struct mpi3_event_notification_reply *event_reply)
2271 {
2272 u16 dev_handle = 0;
2273 u8 ublock = 0, block = 0, hide = 0, delete = 0, remove = 0;
2274 struct mpi3mr_tgt_dev *tgtdev = NULL;
2275 struct mpi3mr_stgt_priv_data *scsi_tgt_priv_data = NULL;
2276 struct mpi3_event_data_device_status_change *evtdata =
2277 (struct mpi3_event_data_device_status_change *)event_reply->event_data;
2278
2279 if (mrioc->stop_drv_processing)
2280 goto out;
2281
2282 dev_handle = le16_to_cpu(evtdata->dev_handle);
2283
2284 switch (evtdata->reason_code) {
2285 case MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_STRT:
2286 case MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_STRT:
2287 block = 1;
2288 break;
2289 case MPI3_EVENT_DEV_STAT_RC_HIDDEN:
2290 delete = 1;
2291 hide = 1;
2292 break;
2293 case MPI3_EVENT_DEV_STAT_RC_VD_NOT_RESPONDING:
2294 delete = 1;
2295 remove = 1;
2296 break;
2297 case MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_CMP:
2298 case MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_CMP:
2299 ublock = 1;
2300 break;
2301 default:
2302 break;
2303 }
2304
2305 tgtdev = mpi3mr_get_tgtdev_by_handle(mrioc, dev_handle);
2306 if (!tgtdev)
2307 goto out;
2308 if (hide)
2309 tgtdev->is_hidden = hide;
2310 if (tgtdev->starget && tgtdev->starget->hostdata) {
2311 scsi_tgt_priv_data = (struct mpi3mr_stgt_priv_data *)
2312 tgtdev->starget->hostdata;
2313 if (block)
2314 atomic_inc(&scsi_tgt_priv_data->block_io);
2315 if (delete)
2316 scsi_tgt_priv_data->dev_removed = 1;
2317 if (ublock)
2318 atomic_dec_if_positive(&scsi_tgt_priv_data->block_io);
2319 }
2320 if (remove)
2321 mpi3mr_dev_rmhs_send_tm(mrioc, dev_handle, NULL,
2322 MPI3_CTRL_OP_REMOVE_DEVICE);
2323 if (hide)
2324 mpi3mr_dev_rmhs_send_tm(mrioc, dev_handle, NULL,
2325 MPI3_CTRL_OP_HIDDEN_ACK);
2326
2327 out:
2328 if (tgtdev)
2329 mpi3mr_tgtdev_put(tgtdev);
2330 }
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341 static void mpi3mr_preparereset_evt_th(struct mpi3mr_ioc *mrioc,
2342 struct mpi3_event_notification_reply *event_reply)
2343 {
2344 struct mpi3_event_data_prepare_for_reset *evtdata =
2345 (struct mpi3_event_data_prepare_for_reset *)event_reply->event_data;
2346
2347 if (evtdata->reason_code == MPI3_EVENT_PREPARE_RESET_RC_START) {
2348 dprint_event_th(mrioc,
2349 "prepare for reset event top half with rc=start\n");
2350 if (mrioc->prepare_for_reset)
2351 return;
2352 mrioc->prepare_for_reset = 1;
2353 mrioc->prepare_for_reset_timeout_counter = 0;
2354 } else if (evtdata->reason_code == MPI3_EVENT_PREPARE_RESET_RC_ABORT) {
2355 dprint_event_th(mrioc,
2356 "prepare for reset top half with rc=abort\n");
2357 mrioc->prepare_for_reset = 0;
2358 mrioc->prepare_for_reset_timeout_counter = 0;
2359 }
2360 if ((event_reply->msg_flags & MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK)
2361 == MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_REQUIRED)
2362 mpi3mr_send_event_ack(mrioc, event_reply->event, NULL,
2363 le32_to_cpu(event_reply->event_context));
2364 }
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375 static void mpi3mr_energypackchg_evt_th(struct mpi3mr_ioc *mrioc,
2376 struct mpi3_event_notification_reply *event_reply)
2377 {
2378 struct mpi3_event_data_energy_pack_change *evtdata =
2379 (struct mpi3_event_data_energy_pack_change *)event_reply->event_data;
2380 u16 shutdown_timeout = le16_to_cpu(evtdata->shutdown_timeout);
2381
2382 if (shutdown_timeout <= 0) {
2383 ioc_warn(mrioc,
2384 "%s :Invalid Shutdown Timeout received = %d\n",
2385 __func__, shutdown_timeout);
2386 return;
2387 }
2388
2389 ioc_info(mrioc,
2390 "%s :Previous Shutdown Timeout Value = %d New Shutdown Timeout Value = %d\n",
2391 __func__, mrioc->facts.shutdown_timeout, shutdown_timeout);
2392 mrioc->facts.shutdown_timeout = shutdown_timeout;
2393 }
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404 static void mpi3mr_cablemgmt_evt_th(struct mpi3mr_ioc *mrioc,
2405 struct mpi3_event_notification_reply *event_reply)
2406 {
2407 struct mpi3_event_data_cable_management *evtdata =
2408 (struct mpi3_event_data_cable_management *)event_reply->event_data;
2409
2410 switch (evtdata->status) {
2411 case MPI3_EVENT_CABLE_MGMT_STATUS_INSUFFICIENT_POWER:
2412 {
2413 ioc_info(mrioc, "An active cable with receptacle_id %d cannot be powered.\n"
2414 "Devices connected to this cable are not detected.\n"
2415 "This cable requires %d mW of power.\n",
2416 evtdata->receptacle_id,
2417 le32_to_cpu(evtdata->active_cable_power_requirement));
2418 break;
2419 }
2420 case MPI3_EVENT_CABLE_MGMT_STATUS_DEGRADED:
2421 {
2422 ioc_info(mrioc, "A cable with receptacle_id %d is not running at optimal speed\n",
2423 evtdata->receptacle_id);
2424 break;
2425 }
2426 default:
2427 break;
2428 }
2429 }
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc,
2443 struct mpi3_event_notification_reply *event_reply)
2444 {
2445 u16 evt_type, sz;
2446 struct mpi3mr_fwevt *fwevt = NULL;
2447 bool ack_req = 0, process_evt_bh = 0;
2448
2449 if (mrioc->stop_drv_processing)
2450 return;
2451
2452 if ((event_reply->msg_flags & MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK)
2453 == MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_REQUIRED)
2454 ack_req = 1;
2455
2456 evt_type = event_reply->event;
2457
2458 switch (evt_type) {
2459 case MPI3_EVENT_DEVICE_ADDED:
2460 {
2461 struct mpi3_device_page0 *dev_pg0 =
2462 (struct mpi3_device_page0 *)event_reply->event_data;
2463 if (mpi3mr_create_tgtdev(mrioc, dev_pg0))
2464 ioc_err(mrioc,
2465 "%s :Failed to add device in the device add event\n",
2466 __func__);
2467 else
2468 process_evt_bh = 1;
2469 break;
2470 }
2471 case MPI3_EVENT_DEVICE_STATUS_CHANGE:
2472 {
2473 process_evt_bh = 1;
2474 mpi3mr_devstatuschg_evt_th(mrioc, event_reply);
2475 break;
2476 }
2477 case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
2478 {
2479 process_evt_bh = 1;
2480 mpi3mr_sastopochg_evt_th(mrioc, event_reply);
2481 break;
2482 }
2483 case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
2484 {
2485 process_evt_bh = 1;
2486 mpi3mr_pcietopochg_evt_th(mrioc, event_reply);
2487 break;
2488 }
2489 case MPI3_EVENT_PREPARE_FOR_RESET:
2490 {
2491 mpi3mr_preparereset_evt_th(mrioc, event_reply);
2492 ack_req = 0;
2493 break;
2494 }
2495 case MPI3_EVENT_DEVICE_INFO_CHANGED:
2496 case MPI3_EVENT_LOG_DATA:
2497 {
2498 process_evt_bh = 1;
2499 break;
2500 }
2501 case MPI3_EVENT_ENERGY_PACK_CHANGE:
2502 {
2503 mpi3mr_energypackchg_evt_th(mrioc, event_reply);
2504 break;
2505 }
2506 case MPI3_EVENT_CABLE_MGMT:
2507 {
2508 mpi3mr_cablemgmt_evt_th(mrioc, event_reply);
2509 break;
2510 }
2511 case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE:
2512 case MPI3_EVENT_SAS_DISCOVERY:
2513 case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR:
2514 case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE:
2515 case MPI3_EVENT_PCIE_ENUMERATION:
2516 break;
2517 default:
2518 ioc_info(mrioc, "%s :event 0x%02x is not handled\n",
2519 __func__, evt_type);
2520 break;
2521 }
2522 if (process_evt_bh || ack_req) {
2523 sz = event_reply->event_data_length * 4;
2524 fwevt = mpi3mr_alloc_fwevt(sz);
2525 if (!fwevt) {
2526 ioc_info(mrioc, "%s :failure at %s:%d/%s()!\n",
2527 __func__, __FILE__, __LINE__, __func__);
2528 return;
2529 }
2530
2531 memcpy(fwevt->event_data, event_reply->event_data, sz);
2532 fwevt->mrioc = mrioc;
2533 fwevt->event_id = evt_type;
2534 fwevt->send_ack = ack_req;
2535 fwevt->process_evt = process_evt_bh;
2536 fwevt->evt_ctx = le32_to_cpu(event_reply->event_context);
2537 mpi3mr_fwevt_add_to_list(mrioc, fwevt);
2538 }
2539 }
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553 static void mpi3mr_setup_eedp(struct mpi3mr_ioc *mrioc,
2554 struct scsi_cmnd *scmd, struct mpi3_scsi_io_request *scsiio_req)
2555 {
2556 u16 eedp_flags = 0;
2557 unsigned char prot_op = scsi_get_prot_op(scmd);
2558
2559 switch (prot_op) {
2560 case SCSI_PROT_NORMAL:
2561 return;
2562 case SCSI_PROT_READ_STRIP:
2563 eedp_flags = MPI3_EEDPFLAGS_EEDP_OP_CHECK_REMOVE;
2564 break;
2565 case SCSI_PROT_WRITE_INSERT:
2566 eedp_flags = MPI3_EEDPFLAGS_EEDP_OP_INSERT;
2567 break;
2568 case SCSI_PROT_READ_INSERT:
2569 eedp_flags = MPI3_EEDPFLAGS_EEDP_OP_INSERT;
2570 scsiio_req->msg_flags |= MPI3_SCSIIO_MSGFLAGS_METASGL_VALID;
2571 break;
2572 case SCSI_PROT_WRITE_STRIP:
2573 eedp_flags = MPI3_EEDPFLAGS_EEDP_OP_CHECK_REMOVE;
2574 scsiio_req->msg_flags |= MPI3_SCSIIO_MSGFLAGS_METASGL_VALID;
2575 break;
2576 case SCSI_PROT_READ_PASS:
2577 eedp_flags = MPI3_EEDPFLAGS_EEDP_OP_CHECK;
2578 scsiio_req->msg_flags |= MPI3_SCSIIO_MSGFLAGS_METASGL_VALID;
2579 break;
2580 case SCSI_PROT_WRITE_PASS:
2581 if (scmd->prot_flags & SCSI_PROT_IP_CHECKSUM) {
2582 eedp_flags = MPI3_EEDPFLAGS_EEDP_OP_CHECK_REGEN;
2583 scsiio_req->sgl[0].eedp.application_tag_translation_mask =
2584 0xffff;
2585 } else
2586 eedp_flags = MPI3_EEDPFLAGS_EEDP_OP_CHECK;
2587
2588 scsiio_req->msg_flags |= MPI3_SCSIIO_MSGFLAGS_METASGL_VALID;
2589 break;
2590 default:
2591 return;
2592 }
2593
2594 if (scmd->prot_flags & SCSI_PROT_GUARD_CHECK)
2595 eedp_flags |= MPI3_EEDPFLAGS_CHK_GUARD;
2596
2597 if (scmd->prot_flags & SCSI_PROT_IP_CHECKSUM)
2598 eedp_flags |= MPI3_EEDPFLAGS_HOST_GUARD_IP_CHKSUM;
2599
2600 if (scmd->prot_flags & SCSI_PROT_REF_CHECK) {
2601 eedp_flags |= MPI3_EEDPFLAGS_CHK_REF_TAG |
2602 MPI3_EEDPFLAGS_INCR_PRI_REF_TAG;
2603 scsiio_req->cdb.eedp32.primary_reference_tag =
2604 cpu_to_be32(scsi_prot_ref_tag(scmd));
2605 }
2606
2607 if (scmd->prot_flags & SCSI_PROT_REF_INCREMENT)
2608 eedp_flags |= MPI3_EEDPFLAGS_INCR_PRI_REF_TAG;
2609
2610 eedp_flags |= MPI3_EEDPFLAGS_ESC_MODE_APPTAG_DISABLE;
2611
2612 switch (scsi_prot_interval(scmd)) {
2613 case 512:
2614 scsiio_req->sgl[0].eedp.user_data_size = MPI3_EEDP_UDS_512;
2615 break;
2616 case 520:
2617 scsiio_req->sgl[0].eedp.user_data_size = MPI3_EEDP_UDS_520;
2618 break;
2619 case 4080:
2620 scsiio_req->sgl[0].eedp.user_data_size = MPI3_EEDP_UDS_4080;
2621 break;
2622 case 4088:
2623 scsiio_req->sgl[0].eedp.user_data_size = MPI3_EEDP_UDS_4088;
2624 break;
2625 case 4096:
2626 scsiio_req->sgl[0].eedp.user_data_size = MPI3_EEDP_UDS_4096;
2627 break;
2628 case 4104:
2629 scsiio_req->sgl[0].eedp.user_data_size = MPI3_EEDP_UDS_4104;
2630 break;
2631 case 4160:
2632 scsiio_req->sgl[0].eedp.user_data_size = MPI3_EEDP_UDS_4160;
2633 break;
2634 default:
2635 break;
2636 }
2637
2638 scsiio_req->sgl[0].eedp.eedp_flags = cpu_to_le16(eedp_flags);
2639 scsiio_req->sgl[0].eedp.flags = MPI3_SGE_FLAGS_ELEMENT_TYPE_EXTENDED;
2640 }
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655 static inline void mpi3mr_build_sense_buffer(int desc, u8 *buf, u8 key,
2656 u8 asc, u8 ascq)
2657 {
2658 if (desc) {
2659 buf[0] = 0x72;
2660 buf[1] = key;
2661 buf[2] = asc;
2662 buf[3] = ascq;
2663 buf[7] = 0;
2664 } else {
2665 buf[0] = 0x70;
2666 buf[2] = key;
2667 buf[7] = 0xa;
2668 buf[12] = asc;
2669 buf[13] = ascq;
2670 }
2671 }
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683 static void mpi3mr_map_eedp_error(struct scsi_cmnd *scmd,
2684 u16 ioc_status)
2685 {
2686 u8 ascq = 0;
2687
2688 switch (ioc_status) {
2689 case MPI3_IOCSTATUS_EEDP_GUARD_ERROR:
2690 ascq = 0x01;
2691 break;
2692 case MPI3_IOCSTATUS_EEDP_APP_TAG_ERROR:
2693 ascq = 0x02;
2694 break;
2695 case MPI3_IOCSTATUS_EEDP_REF_TAG_ERROR:
2696 ascq = 0x03;
2697 break;
2698 default:
2699 ascq = 0x00;
2700 break;
2701 }
2702
2703 mpi3mr_build_sense_buffer(0, scmd->sense_buffer, ILLEGAL_REQUEST,
2704 0x10, ascq);
2705 scmd->result = (DID_ABORT << 16) | SAM_STAT_CHECK_CONDITION;
2706 }
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc,
2723 struct mpi3_default_reply_descriptor *reply_desc, u64 *reply_dma, u16 qidx)
2724 {
2725 u16 reply_desc_type, host_tag = 0;
2726 u16 ioc_status = MPI3_IOCSTATUS_SUCCESS;
2727 u32 ioc_loginfo = 0;
2728 struct mpi3_status_reply_descriptor *status_desc = NULL;
2729 struct mpi3_address_reply_descriptor *addr_desc = NULL;
2730 struct mpi3_success_reply_descriptor *success_desc = NULL;
2731 struct mpi3_scsi_io_reply *scsi_reply = NULL;
2732 struct scsi_cmnd *scmd = NULL;
2733 struct scmd_priv *priv = NULL;
2734 u8 *sense_buf = NULL;
2735 u8 scsi_state = 0, scsi_status = 0, sense_state = 0;
2736 u32 xfer_count = 0, sense_count = 0, resp_data = 0;
2737 u16 dev_handle = 0xFFFF;
2738 struct scsi_sense_hdr sshdr;
2739 struct mpi3mr_stgt_priv_data *stgt_priv_data = NULL;
2740 struct mpi3mr_sdev_priv_data *sdev_priv_data = NULL;
2741 u32 ioc_pend_data_len = 0, tg_pend_data_len = 0, data_len_blks = 0;
2742 struct mpi3mr_throttle_group_info *tg = NULL;
2743 u8 throttle_enabled_dev = 0;
2744
2745 *reply_dma = 0;
2746 reply_desc_type = le16_to_cpu(reply_desc->reply_flags) &
2747 MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK;
2748 switch (reply_desc_type) {
2749 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS:
2750 status_desc = (struct mpi3_status_reply_descriptor *)reply_desc;
2751 host_tag = le16_to_cpu(status_desc->host_tag);
2752 ioc_status = le16_to_cpu(status_desc->ioc_status);
2753 if (ioc_status &
2754 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
2755 ioc_loginfo = le32_to_cpu(status_desc->ioc_log_info);
2756 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK;
2757 break;
2758 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY:
2759 addr_desc = (struct mpi3_address_reply_descriptor *)reply_desc;
2760 *reply_dma = le64_to_cpu(addr_desc->reply_frame_address);
2761 scsi_reply = mpi3mr_get_reply_virt_addr(mrioc,
2762 *reply_dma);
2763 if (!scsi_reply) {
2764 panic("%s: scsi_reply is NULL, this shouldn't happen\n",
2765 mrioc->name);
2766 goto out;
2767 }
2768 host_tag = le16_to_cpu(scsi_reply->host_tag);
2769 ioc_status = le16_to_cpu(scsi_reply->ioc_status);
2770 scsi_status = scsi_reply->scsi_status;
2771 scsi_state = scsi_reply->scsi_state;
2772 dev_handle = le16_to_cpu(scsi_reply->dev_handle);
2773 sense_state = (scsi_state & MPI3_SCSI_STATE_SENSE_MASK);
2774 xfer_count = le32_to_cpu(scsi_reply->transfer_count);
2775 sense_count = le32_to_cpu(scsi_reply->sense_count);
2776 resp_data = le32_to_cpu(scsi_reply->response_data);
2777 sense_buf = mpi3mr_get_sensebuf_virt_addr(mrioc,
2778 le64_to_cpu(scsi_reply->sense_data_buffer_address));
2779 if (ioc_status &
2780 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
2781 ioc_loginfo = le32_to_cpu(scsi_reply->ioc_log_info);
2782 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK;
2783 if (sense_state == MPI3_SCSI_STATE_SENSE_BUFF_Q_EMPTY)
2784 panic("%s: Ran out of sense buffers\n", mrioc->name);
2785 break;
2786 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS:
2787 success_desc = (struct mpi3_success_reply_descriptor *)reply_desc;
2788 host_tag = le16_to_cpu(success_desc->host_tag);
2789 break;
2790 default:
2791 break;
2792 }
2793 scmd = mpi3mr_scmd_from_host_tag(mrioc, host_tag, qidx);
2794 if (!scmd) {
2795 panic("%s: Cannot Identify scmd for host_tag 0x%x\n",
2796 mrioc->name, host_tag);
2797 goto out;
2798 }
2799 priv = scsi_cmd_priv(scmd);
2800
2801 data_len_blks = scsi_bufflen(scmd) >> 9;
2802 sdev_priv_data = scmd->device->hostdata;
2803 if (sdev_priv_data) {
2804 stgt_priv_data = sdev_priv_data->tgt_priv_data;
2805 if (stgt_priv_data) {
2806 tg = stgt_priv_data->throttle_group;
2807 throttle_enabled_dev =
2808 stgt_priv_data->io_throttle_enabled;
2809 }
2810 }
2811 if (unlikely((data_len_blks >= mrioc->io_throttle_data_length) &&
2812 throttle_enabled_dev)) {
2813 ioc_pend_data_len = atomic_sub_return(data_len_blks,
2814 &mrioc->pend_large_data_sz);
2815 if (tg) {
2816 tg_pend_data_len = atomic_sub_return(data_len_blks,
2817 &tg->pend_large_data_sz);
2818 if (tg->io_divert && ((ioc_pend_data_len <=
2819 mrioc->io_throttle_low) &&
2820 (tg_pend_data_len <= tg->low))) {
2821 tg->io_divert = 0;
2822 mpi3mr_set_io_divert_for_all_vd_in_tg(
2823 mrioc, tg, 0);
2824 }
2825 } else {
2826 if (ioc_pend_data_len <= mrioc->io_throttle_low)
2827 stgt_priv_data->io_divert = 0;
2828 }
2829 } else if (unlikely((stgt_priv_data && stgt_priv_data->io_divert))) {
2830 ioc_pend_data_len = atomic_read(&mrioc->pend_large_data_sz);
2831 if (!tg) {
2832 if (ioc_pend_data_len <= mrioc->io_throttle_low)
2833 stgt_priv_data->io_divert = 0;
2834
2835 } else if (ioc_pend_data_len <= mrioc->io_throttle_low) {
2836 tg_pend_data_len = atomic_read(&tg->pend_large_data_sz);
2837 if (tg->io_divert && (tg_pend_data_len <= tg->low)) {
2838 tg->io_divert = 0;
2839 mpi3mr_set_io_divert_for_all_vd_in_tg(
2840 mrioc, tg, 0);
2841 }
2842 }
2843 }
2844
2845 if (success_desc) {
2846 scmd->result = DID_OK << 16;
2847 goto out_success;
2848 }
2849
2850 scsi_set_resid(scmd, scsi_bufflen(scmd) - xfer_count);
2851 if (ioc_status == MPI3_IOCSTATUS_SCSI_DATA_UNDERRUN &&
2852 xfer_count == 0 && (scsi_status == MPI3_SCSI_STATUS_BUSY ||
2853 scsi_status == MPI3_SCSI_STATUS_RESERVATION_CONFLICT ||
2854 scsi_status == MPI3_SCSI_STATUS_TASK_SET_FULL))
2855 ioc_status = MPI3_IOCSTATUS_SUCCESS;
2856
2857 if ((sense_state == MPI3_SCSI_STATE_SENSE_VALID) && sense_count &&
2858 sense_buf) {
2859 u32 sz = min_t(u32, SCSI_SENSE_BUFFERSIZE, sense_count);
2860
2861 memcpy(scmd->sense_buffer, sense_buf, sz);
2862 }
2863
2864 switch (ioc_status) {
2865 case MPI3_IOCSTATUS_BUSY:
2866 case MPI3_IOCSTATUS_INSUFFICIENT_RESOURCES:
2867 scmd->result = SAM_STAT_BUSY;
2868 break;
2869 case MPI3_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
2870 scmd->result = DID_NO_CONNECT << 16;
2871 break;
2872 case MPI3_IOCSTATUS_SCSI_IOC_TERMINATED:
2873 scmd->result = DID_SOFT_ERROR << 16;
2874 break;
2875 case MPI3_IOCSTATUS_SCSI_TASK_TERMINATED:
2876 case MPI3_IOCSTATUS_SCSI_EXT_TERMINATED:
2877 scmd->result = DID_RESET << 16;
2878 break;
2879 case MPI3_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
2880 if ((xfer_count == 0) || (scmd->underflow > xfer_count))
2881 scmd->result = DID_SOFT_ERROR << 16;
2882 else
2883 scmd->result = (DID_OK << 16) | scsi_status;
2884 break;
2885 case MPI3_IOCSTATUS_SCSI_DATA_UNDERRUN:
2886 scmd->result = (DID_OK << 16) | scsi_status;
2887 if (sense_state == MPI3_SCSI_STATE_SENSE_VALID)
2888 break;
2889 if (xfer_count < scmd->underflow) {
2890 if (scsi_status == SAM_STAT_BUSY)
2891 scmd->result = SAM_STAT_BUSY;
2892 else
2893 scmd->result = DID_SOFT_ERROR << 16;
2894 } else if ((scsi_state & (MPI3_SCSI_STATE_NO_SCSI_STATUS)) ||
2895 (sense_state != MPI3_SCSI_STATE_SENSE_NOT_AVAILABLE))
2896 scmd->result = DID_SOFT_ERROR << 16;
2897 else if (scsi_state & MPI3_SCSI_STATE_TERMINATED)
2898 scmd->result = DID_RESET << 16;
2899 break;
2900 case MPI3_IOCSTATUS_SCSI_DATA_OVERRUN:
2901 scsi_set_resid(scmd, 0);
2902 fallthrough;
2903 case MPI3_IOCSTATUS_SCSI_RECOVERED_ERROR:
2904 case MPI3_IOCSTATUS_SUCCESS:
2905 scmd->result = (DID_OK << 16) | scsi_status;
2906 if ((scsi_state & (MPI3_SCSI_STATE_NO_SCSI_STATUS)) ||
2907 (sense_state == MPI3_SCSI_STATE_SENSE_FAILED) ||
2908 (sense_state == MPI3_SCSI_STATE_SENSE_BUFF_Q_EMPTY))
2909 scmd->result = DID_SOFT_ERROR << 16;
2910 else if (scsi_state & MPI3_SCSI_STATE_TERMINATED)
2911 scmd->result = DID_RESET << 16;
2912 break;
2913 case MPI3_IOCSTATUS_EEDP_GUARD_ERROR:
2914 case MPI3_IOCSTATUS_EEDP_REF_TAG_ERROR:
2915 case MPI3_IOCSTATUS_EEDP_APP_TAG_ERROR:
2916 mpi3mr_map_eedp_error(scmd, ioc_status);
2917 break;
2918 case MPI3_IOCSTATUS_SCSI_PROTOCOL_ERROR:
2919 case MPI3_IOCSTATUS_INVALID_FUNCTION:
2920 case MPI3_IOCSTATUS_INVALID_SGL:
2921 case MPI3_IOCSTATUS_INTERNAL_ERROR:
2922 case MPI3_IOCSTATUS_INVALID_FIELD:
2923 case MPI3_IOCSTATUS_INVALID_STATE:
2924 case MPI3_IOCSTATUS_SCSI_IO_DATA_ERROR:
2925 case MPI3_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
2926 case MPI3_IOCSTATUS_INSUFFICIENT_POWER:
2927 default:
2928 scmd->result = DID_SOFT_ERROR << 16;
2929 break;
2930 }
2931
2932 if (scmd->result != (DID_OK << 16) && (scmd->cmnd[0] != ATA_12) &&
2933 (scmd->cmnd[0] != ATA_16)) {
2934 ioc_info(mrioc, "%s :scmd->result 0x%x\n", __func__,
2935 scmd->result);
2936 scsi_print_command(scmd);
2937 ioc_info(mrioc,
2938 "%s :Command issued to handle 0x%02x returned with error 0x%04x loginfo 0x%08x, qid %d\n",
2939 __func__, dev_handle, ioc_status, ioc_loginfo,
2940 priv->req_q_idx + 1);
2941 ioc_info(mrioc,
2942 " host_tag %d scsi_state 0x%02x scsi_status 0x%02x, xfer_cnt %d resp_data 0x%x\n",
2943 host_tag, scsi_state, scsi_status, xfer_count, resp_data);
2944 if (sense_buf) {
2945 scsi_normalize_sense(sense_buf, sense_count, &sshdr);
2946 ioc_info(mrioc,
2947 "%s :sense_count 0x%x, sense_key 0x%x ASC 0x%x, ASCQ 0x%x\n",
2948 __func__, sense_count, sshdr.sense_key,
2949 sshdr.asc, sshdr.ascq);
2950 }
2951 }
2952 out_success:
2953 if (priv->meta_sg_valid) {
2954 dma_unmap_sg(&mrioc->pdev->dev, scsi_prot_sglist(scmd),
2955 scsi_prot_sg_count(scmd), scmd->sc_data_direction);
2956 }
2957 mpi3mr_clear_scmd_priv(mrioc, scmd);
2958 scsi_dma_unmap(scmd);
2959 scsi_done(scmd);
2960 out:
2961 if (sense_buf)
2962 mpi3mr_repost_sense_buf(mrioc,
2963 le64_to_cpu(scsi_reply->sense_data_buffer_address));
2964 }
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974 static int mpi3mr_get_chain_idx(struct mpi3mr_ioc *mrioc)
2975 {
2976 u8 retry_count = 5;
2977 int cmd_idx = -1;
2978
2979 do {
2980 spin_lock(&mrioc->chain_buf_lock);
2981 cmd_idx = find_first_zero_bit(mrioc->chain_bitmap,
2982 mrioc->chain_buf_count);
2983 if (cmd_idx < mrioc->chain_buf_count) {
2984 set_bit(cmd_idx, mrioc->chain_bitmap);
2985 spin_unlock(&mrioc->chain_buf_lock);
2986 break;
2987 }
2988 spin_unlock(&mrioc->chain_buf_lock);
2989 cmd_idx = -1;
2990 } while (retry_count--);
2991 return cmd_idx;
2992 }
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006 static int mpi3mr_prepare_sg_scmd(struct mpi3mr_ioc *mrioc,
3007 struct scsi_cmnd *scmd, struct mpi3_scsi_io_request *scsiio_req)
3008 {
3009 dma_addr_t chain_dma;
3010 struct scatterlist *sg_scmd;
3011 void *sg_local, *chain;
3012 u32 chain_length;
3013 int sges_left, chain_idx;
3014 u32 sges_in_segment;
3015 u8 simple_sgl_flags;
3016 u8 simple_sgl_flags_last;
3017 u8 last_chain_sgl_flags;
3018 struct chain_element *chain_req;
3019 struct scmd_priv *priv = NULL;
3020 u32 meta_sg = le32_to_cpu(scsiio_req->flags) &
3021 MPI3_SCSIIO_FLAGS_DMAOPERATION_HOST_PI;
3022
3023 priv = scsi_cmd_priv(scmd);
3024
3025 simple_sgl_flags = MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE |
3026 MPI3_SGE_FLAGS_DLAS_SYSTEM;
3027 simple_sgl_flags_last = simple_sgl_flags |
3028 MPI3_SGE_FLAGS_END_OF_LIST;
3029 last_chain_sgl_flags = MPI3_SGE_FLAGS_ELEMENT_TYPE_LAST_CHAIN |
3030 MPI3_SGE_FLAGS_DLAS_SYSTEM;
3031
3032 if (meta_sg)
3033 sg_local = &scsiio_req->sgl[MPI3_SCSIIO_METASGL_INDEX];
3034 else
3035 sg_local = &scsiio_req->sgl;
3036
3037 if (!scsiio_req->data_length && !meta_sg) {
3038 mpi3mr_build_zero_len_sge(sg_local);
3039 return 0;
3040 }
3041
3042 if (meta_sg) {
3043 sg_scmd = scsi_prot_sglist(scmd);
3044 sges_left = dma_map_sg(&mrioc->pdev->dev,
3045 scsi_prot_sglist(scmd),
3046 scsi_prot_sg_count(scmd),
3047 scmd->sc_data_direction);
3048 priv->meta_sg_valid = 1;
3049 } else {
3050 sg_scmd = scsi_sglist(scmd);
3051 sges_left = scsi_dma_map(scmd);
3052 }
3053
3054 if (sges_left < 0) {
3055 sdev_printk(KERN_ERR, scmd->device,
3056 "scsi_dma_map failed: request for %d bytes!\n",
3057 scsi_bufflen(scmd));
3058 return -ENOMEM;
3059 }
3060 if (sges_left > MPI3MR_SG_DEPTH) {
3061 sdev_printk(KERN_ERR, scmd->device,
3062 "scsi_dma_map returned unsupported sge count %d!\n",
3063 sges_left);
3064 return -ENOMEM;
3065 }
3066
3067 sges_in_segment = (mrioc->facts.op_req_sz -
3068 offsetof(struct mpi3_scsi_io_request, sgl)) / sizeof(struct mpi3_sge_common);
3069
3070 if (scsiio_req->sgl[0].eedp.flags ==
3071 MPI3_SGE_FLAGS_ELEMENT_TYPE_EXTENDED && !meta_sg) {
3072 sg_local += sizeof(struct mpi3_sge_common);
3073 sges_in_segment--;
3074
3075 }
3076
3077 if (scsiio_req->msg_flags ==
3078 MPI3_SCSIIO_MSGFLAGS_METASGL_VALID && !meta_sg) {
3079 sges_in_segment--;
3080
3081 }
3082
3083 if (meta_sg)
3084 sges_in_segment = 1;
3085
3086 if (sges_left <= sges_in_segment)
3087 goto fill_in_last_segment;
3088
3089
3090 while (sges_in_segment > 1) {
3091 mpi3mr_add_sg_single(sg_local, simple_sgl_flags,
3092 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
3093 sg_scmd = sg_next(sg_scmd);
3094 sg_local += sizeof(struct mpi3_sge_common);
3095 sges_left--;
3096 sges_in_segment--;
3097 }
3098
3099 chain_idx = mpi3mr_get_chain_idx(mrioc);
3100 if (chain_idx < 0)
3101 return -1;
3102 chain_req = &mrioc->chain_sgl_list[chain_idx];
3103 if (meta_sg)
3104 priv->meta_chain_idx = chain_idx;
3105 else
3106 priv->chain_idx = chain_idx;
3107
3108 chain = chain_req->addr;
3109 chain_dma = chain_req->dma_addr;
3110 sges_in_segment = sges_left;
3111 chain_length = sges_in_segment * sizeof(struct mpi3_sge_common);
3112
3113 mpi3mr_add_sg_single(sg_local, last_chain_sgl_flags,
3114 chain_length, chain_dma);
3115
3116 sg_local = chain;
3117
3118 fill_in_last_segment:
3119 while (sges_left > 0) {
3120 if (sges_left == 1)
3121 mpi3mr_add_sg_single(sg_local,
3122 simple_sgl_flags_last, sg_dma_len(sg_scmd),
3123 sg_dma_address(sg_scmd));
3124 else
3125 mpi3mr_add_sg_single(sg_local, simple_sgl_flags,
3126 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
3127 sg_scmd = sg_next(sg_scmd);
3128 sg_local += sizeof(struct mpi3_sge_common);
3129 sges_left--;
3130 }
3131
3132 return 0;
3133 }
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147 static int mpi3mr_build_sg_scmd(struct mpi3mr_ioc *mrioc,
3148 struct scsi_cmnd *scmd, struct mpi3_scsi_io_request *scsiio_req)
3149 {
3150 int ret;
3151
3152 ret = mpi3mr_prepare_sg_scmd(mrioc, scmd, scsiio_req);
3153 if (ret)
3154 return ret;
3155
3156 if (scsiio_req->msg_flags == MPI3_SCSIIO_MSGFLAGS_METASGL_VALID) {
3157
3158 scsiio_req->flags |=
3159 cpu_to_le32(MPI3_SCSIIO_FLAGS_DMAOPERATION_HOST_PI);
3160 ret = mpi3mr_prepare_sg_scmd(mrioc, scmd, scsiio_req);
3161 }
3162
3163 return ret;
3164 }
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175 static const char *mpi3mr_tm_response_name(u8 resp_code)
3176 {
3177 char *desc;
3178
3179 switch (resp_code) {
3180 case MPI3_SCSITASKMGMT_RSPCODE_TM_COMPLETE:
3181 desc = "task management request completed";
3182 break;
3183 case MPI3_SCSITASKMGMT_RSPCODE_INVALID_FRAME:
3184 desc = "invalid frame";
3185 break;
3186 case MPI3_SCSITASKMGMT_RSPCODE_TM_FUNCTION_NOT_SUPPORTED:
3187 desc = "task management request not supported";
3188 break;
3189 case MPI3_SCSITASKMGMT_RSPCODE_TM_FAILED:
3190 desc = "task management request failed";
3191 break;
3192 case MPI3_SCSITASKMGMT_RSPCODE_TM_SUCCEEDED:
3193 desc = "task management request succeeded";
3194 break;
3195 case MPI3_SCSITASKMGMT_RSPCODE_TM_INVALID_LUN:
3196 desc = "invalid LUN";
3197 break;
3198 case MPI3_SCSITASKMGMT_RSPCODE_TM_OVERLAPPED_TAG:
3199 desc = "overlapped tag attempted";
3200 break;
3201 case MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC:
3202 desc = "task queued, however not sent to target";
3203 break;
3204 case MPI3_SCSITASKMGMT_RSPCODE_TM_NVME_DENIED:
3205 desc = "task management request denied by NVMe device";
3206 break;
3207 default:
3208 desc = "unknown";
3209 break;
3210 }
3211
3212 return desc;
3213 }
3214
3215 inline void mpi3mr_poll_pend_io_completions(struct mpi3mr_ioc *mrioc)
3216 {
3217 int i;
3218 int num_of_reply_queues =
3219 mrioc->num_op_reply_q + mrioc->op_reply_q_offset;
3220
3221 for (i = mrioc->op_reply_q_offset; i < num_of_reply_queues; i++)
3222 mpi3mr_process_op_reply_q(mrioc,
3223 mrioc->intr_info[i].op_reply_q);
3224 }
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245 int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type,
3246 u16 handle, uint lun, u16 htag, ulong timeout,
3247 struct mpi3mr_drv_cmd *drv_cmd,
3248 u8 *resp_code, struct scsi_cmnd *scmd)
3249 {
3250 struct mpi3_scsi_task_mgmt_request tm_req;
3251 struct mpi3_scsi_task_mgmt_reply *tm_reply = NULL;
3252 int retval = 0;
3253 struct mpi3mr_tgt_dev *tgtdev = NULL;
3254 struct mpi3mr_stgt_priv_data *scsi_tgt_priv_data = NULL;
3255 struct scmd_priv *cmd_priv = NULL;
3256 struct scsi_device *sdev = NULL;
3257 struct mpi3mr_sdev_priv_data *sdev_priv_data = NULL;
3258
3259 ioc_info(mrioc, "%s :Issue TM: TM type (0x%x) for devhandle 0x%04x\n",
3260 __func__, tm_type, handle);
3261 if (mrioc->unrecoverable) {
3262 retval = -1;
3263 ioc_err(mrioc, "%s :Issue TM: Unrecoverable controller\n",
3264 __func__);
3265 goto out;
3266 }
3267
3268 memset(&tm_req, 0, sizeof(tm_req));
3269 mutex_lock(&drv_cmd->mutex);
3270 if (drv_cmd->state & MPI3MR_CMD_PENDING) {
3271 retval = -1;
3272 ioc_err(mrioc, "%s :Issue TM: Command is in use\n", __func__);
3273 mutex_unlock(&drv_cmd->mutex);
3274 goto out;
3275 }
3276 if (mrioc->reset_in_progress) {
3277 retval = -1;
3278 ioc_err(mrioc, "%s :Issue TM: Reset in progress\n", __func__);
3279 mutex_unlock(&drv_cmd->mutex);
3280 goto out;
3281 }
3282
3283 drv_cmd->state = MPI3MR_CMD_PENDING;
3284 drv_cmd->is_waiting = 1;
3285 drv_cmd->callback = NULL;
3286 tm_req.dev_handle = cpu_to_le16(handle);
3287 tm_req.task_type = tm_type;
3288 tm_req.host_tag = cpu_to_le16(htag);
3289
3290 int_to_scsilun(lun, (struct scsi_lun *)tm_req.lun);
3291 tm_req.function = MPI3_FUNCTION_SCSI_TASK_MGMT;
3292
3293 tgtdev = mpi3mr_get_tgtdev_by_handle(mrioc, handle);
3294
3295 if (scmd) {
3296 sdev = scmd->device;
3297 sdev_priv_data = sdev->hostdata;
3298 scsi_tgt_priv_data = ((sdev_priv_data) ?
3299 sdev_priv_data->tgt_priv_data : NULL);
3300 } else {
3301 if (tgtdev && tgtdev->starget && tgtdev->starget->hostdata)
3302 scsi_tgt_priv_data = (struct mpi3mr_stgt_priv_data *)
3303 tgtdev->starget->hostdata;
3304 }
3305
3306 if (scsi_tgt_priv_data)
3307 atomic_inc(&scsi_tgt_priv_data->block_io);
3308
3309 if (tgtdev && (tgtdev->dev_type == MPI3_DEVICE_DEVFORM_PCIE)) {
3310 if (cmd_priv && tgtdev->dev_spec.pcie_inf.abort_to)
3311 timeout = tgtdev->dev_spec.pcie_inf.abort_to;
3312 else if (!cmd_priv && tgtdev->dev_spec.pcie_inf.reset_to)
3313 timeout = tgtdev->dev_spec.pcie_inf.reset_to;
3314 }
3315
3316 init_completion(&drv_cmd->done);
3317 retval = mpi3mr_admin_request_post(mrioc, &tm_req, sizeof(tm_req), 1);
3318 if (retval) {
3319 ioc_err(mrioc, "%s :Issue TM: Admin Post failed\n", __func__);
3320 goto out_unlock;
3321 }
3322 wait_for_completion_timeout(&drv_cmd->done, (timeout * HZ));
3323
3324 if (!(drv_cmd->state & MPI3MR_CMD_COMPLETE)) {
3325 drv_cmd->is_waiting = 0;
3326 retval = -1;
3327 if (!(drv_cmd->state & MPI3MR_CMD_RESET)) {
3328 dprint_tm(mrioc,
3329 "task management request timed out after %ld seconds\n",
3330 timeout);
3331 if (mrioc->logging_level & MPI3_DEBUG_TM)
3332 dprint_dump_req(&tm_req, sizeof(tm_req)/4);
3333 mpi3mr_soft_reset_handler(mrioc,
3334 MPI3MR_RESET_FROM_TM_TIMEOUT, 1);
3335 }
3336 goto out_unlock;
3337 }
3338
3339 if (!(drv_cmd->state & MPI3MR_CMD_REPLY_VALID)) {
3340 dprint_tm(mrioc, "invalid task management reply message\n");
3341 retval = -1;
3342 goto out_unlock;
3343 }
3344
3345 tm_reply = (struct mpi3_scsi_task_mgmt_reply *)drv_cmd->reply;
3346
3347 switch (drv_cmd->ioc_status) {
3348 case MPI3_IOCSTATUS_SUCCESS:
3349 *resp_code = le32_to_cpu(tm_reply->response_data) &
3350 MPI3MR_RI_MASK_RESPCODE;
3351 break;
3352 case MPI3_IOCSTATUS_SCSI_IOC_TERMINATED:
3353 *resp_code = MPI3_SCSITASKMGMT_RSPCODE_TM_COMPLETE;
3354 break;
3355 default:
3356 dprint_tm(mrioc,
3357 "task management request to handle(0x%04x) is failed with ioc_status(0x%04x) log_info(0x%08x)\n",
3358 handle, drv_cmd->ioc_status, drv_cmd->ioc_loginfo);
3359 retval = -1;
3360 goto out_unlock;
3361 }
3362
3363 switch (*resp_code) {
3364 case MPI3_SCSITASKMGMT_RSPCODE_TM_SUCCEEDED:
3365 case MPI3_SCSITASKMGMT_RSPCODE_TM_COMPLETE:
3366 break;
3367 case MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC:
3368 if (tm_type != MPI3_SCSITASKMGMT_TASKTYPE_QUERY_TASK)
3369 retval = -1;
3370 break;
3371 default:
3372 retval = -1;
3373 break;
3374 }
3375
3376 dprint_tm(mrioc,
3377 "task management request type(%d) completed for handle(0x%04x) with ioc_status(0x%04x), log_info(0x%08x), termination_count(%d), response:%s(0x%x)\n",
3378 tm_type, handle, drv_cmd->ioc_status, drv_cmd->ioc_loginfo,
3379 le32_to_cpu(tm_reply->termination_count),
3380 mpi3mr_tm_response_name(*resp_code), *resp_code);
3381
3382 if (!retval) {
3383 mpi3mr_ioc_disable_intr(mrioc);
3384 mpi3mr_poll_pend_io_completions(mrioc);
3385 mpi3mr_ioc_enable_intr(mrioc);
3386 mpi3mr_poll_pend_io_completions(mrioc);
3387 }
3388 switch (tm_type) {
3389 case MPI3_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
3390 if (!scsi_tgt_priv_data)
3391 break;
3392 scsi_tgt_priv_data->pend_count = 0;
3393 blk_mq_tagset_busy_iter(&mrioc->shost->tag_set,
3394 mpi3mr_count_tgt_pending,
3395 (void *)scsi_tgt_priv_data->starget);
3396 break;
3397 case MPI3_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
3398 if (!sdev_priv_data)
3399 break;
3400 sdev_priv_data->pend_count = 0;
3401 blk_mq_tagset_busy_iter(&mrioc->shost->tag_set,
3402 mpi3mr_count_dev_pending, (void *)sdev);
3403 break;
3404 default:
3405 break;
3406 }
3407
3408 out_unlock:
3409 drv_cmd->state = MPI3MR_CMD_NOTUSED;
3410 mutex_unlock(&drv_cmd->mutex);
3411 if (scsi_tgt_priv_data)
3412 atomic_dec_if_positive(&scsi_tgt_priv_data->block_io);
3413 if (tgtdev)
3414 mpi3mr_tgtdev_put(tgtdev);
3415 out:
3416 return retval;
3417 }
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430 static int mpi3mr_bios_param(struct scsi_device *sdev,
3431 struct block_device *bdev, sector_t capacity, int params[])
3432 {
3433 int heads;
3434 int sectors;
3435 sector_t cylinders;
3436 ulong dummy;
3437
3438 heads = 64;
3439 sectors = 32;
3440
3441 dummy = heads * sectors;
3442 cylinders = capacity;
3443 sector_div(cylinders, dummy);
3444
3445 if ((ulong)capacity >= 0x200000) {
3446 heads = 255;
3447 sectors = 63;
3448 dummy = heads * sectors;
3449 cylinders = capacity;
3450 sector_div(cylinders, dummy);
3451 }
3452
3453 params[0] = heads;
3454 params[1] = sectors;
3455 params[2] = cylinders;
3456 return 0;
3457 }
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467 static int mpi3mr_map_queues(struct Scsi_Host *shost)
3468 {
3469 struct mpi3mr_ioc *mrioc = shost_priv(shost);
3470 int i, qoff, offset;
3471 struct blk_mq_queue_map *map = NULL;
3472
3473 offset = mrioc->op_reply_q_offset;
3474
3475 for (i = 0, qoff = 0; i < HCTX_MAX_TYPES; i++) {
3476 map = &shost->tag_set.map[i];
3477
3478 map->nr_queues = 0;
3479
3480 if (i == HCTX_TYPE_DEFAULT)
3481 map->nr_queues = mrioc->default_qcount;
3482 else if (i == HCTX_TYPE_POLL)
3483 map->nr_queues = mrioc->active_poll_qcount;
3484
3485 if (!map->nr_queues) {
3486 BUG_ON(i == HCTX_TYPE_DEFAULT);
3487 continue;
3488 }
3489
3490
3491
3492
3493
3494 map->queue_offset = qoff;
3495 if (i != HCTX_TYPE_POLL)
3496 blk_mq_pci_map_queues(map, mrioc->pdev, offset);
3497 else
3498 blk_mq_map_queues(map);
3499
3500 qoff += map->nr_queues;
3501 offset += map->nr_queues;
3502 }
3503
3504 return 0;
3505
3506 }
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516 static inline int mpi3mr_get_fw_pending_ios(struct mpi3mr_ioc *mrioc)
3517 {
3518 u16 i;
3519 uint pend_ios = 0;
3520
3521 for (i = 0; i < mrioc->num_op_reply_q; i++)
3522 pend_ios += atomic_read(&mrioc->op_reply_qinfo[i].pend_ios);
3523 return pend_ios;
3524 }
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535 static void mpi3mr_print_pending_host_io(struct mpi3mr_ioc *mrioc)
3536 {
3537 struct Scsi_Host *shost = mrioc->shost;
3538
3539 ioc_info(mrioc, "%s :Pending commands prior to reset: %d\n",
3540 __func__, mpi3mr_get_fw_pending_ios(mrioc));
3541 blk_mq_tagset_busy_iter(&shost->tag_set,
3542 mpi3mr_print_scmd, (void *)mrioc);
3543 }
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout)
3555 {
3556 enum mpi3mr_iocstate iocstate;
3557 int i = 0;
3558
3559 iocstate = mpi3mr_get_iocstate(mrioc);
3560 if (iocstate != MRIOC_STATE_READY)
3561 return;
3562
3563 if (!mpi3mr_get_fw_pending_ios(mrioc))
3564 return;
3565 ioc_info(mrioc,
3566 "%s :Waiting for %d seconds prior to reset for %d I/O\n",
3567 __func__, timeout, mpi3mr_get_fw_pending_ios(mrioc));
3568
3569 for (i = 0; i < timeout; i++) {
3570 if (!mpi3mr_get_fw_pending_ios(mrioc))
3571 break;
3572 iocstate = mpi3mr_get_iocstate(mrioc);
3573 if (iocstate != MRIOC_STATE_READY)
3574 break;
3575 msleep(1000);
3576 }
3577
3578 ioc_info(mrioc, "%s :Pending I/Os after wait is: %d\n", __func__,
3579 mpi3mr_get_fw_pending_ios(mrioc));
3580 }
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593 static int mpi3mr_eh_host_reset(struct scsi_cmnd *scmd)
3594 {
3595 struct mpi3mr_ioc *mrioc = shost_priv(scmd->device->host);
3596 struct mpi3mr_stgt_priv_data *stgt_priv_data;
3597 struct mpi3mr_sdev_priv_data *sdev_priv_data;
3598 u8 dev_type = MPI3_DEVICE_DEVFORM_VD;
3599 int retval = FAILED, ret;
3600
3601 sdev_priv_data = scmd->device->hostdata;
3602 if (sdev_priv_data && sdev_priv_data->tgt_priv_data) {
3603 stgt_priv_data = sdev_priv_data->tgt_priv_data;
3604 dev_type = stgt_priv_data->dev_type;
3605 }
3606
3607 if (dev_type == MPI3_DEVICE_DEVFORM_VD) {
3608 mpi3mr_wait_for_host_io(mrioc,
3609 MPI3MR_RAID_ERRREC_RESET_TIMEOUT);
3610 if (!mpi3mr_get_fw_pending_ios(mrioc)) {
3611 retval = SUCCESS;
3612 goto out;
3613 }
3614 }
3615
3616 mpi3mr_print_pending_host_io(mrioc);
3617 ret = mpi3mr_soft_reset_handler(mrioc,
3618 MPI3MR_RESET_FROM_EH_HOS, 1);
3619 if (ret)
3620 goto out;
3621
3622 retval = SUCCESS;
3623 out:
3624 sdev_printk(KERN_INFO, scmd->device,
3625 "Host reset is %s for scmd(%p)\n",
3626 ((retval == SUCCESS) ? "SUCCESS" : "FAILED"), scmd);
3627
3628 return retval;
3629 }
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641 static int mpi3mr_eh_target_reset(struct scsi_cmnd *scmd)
3642 {
3643 struct mpi3mr_ioc *mrioc = shost_priv(scmd->device->host);
3644 struct mpi3mr_stgt_priv_data *stgt_priv_data;
3645 struct mpi3mr_sdev_priv_data *sdev_priv_data;
3646 u16 dev_handle;
3647 u8 resp_code = 0;
3648 int retval = FAILED, ret = 0;
3649
3650 sdev_printk(KERN_INFO, scmd->device,
3651 "Attempting Target Reset! scmd(%p)\n", scmd);
3652 scsi_print_command(scmd);
3653
3654 sdev_priv_data = scmd->device->hostdata;
3655 if (!sdev_priv_data || !sdev_priv_data->tgt_priv_data) {
3656 sdev_printk(KERN_INFO, scmd->device,
3657 "SCSI device is not available\n");
3658 retval = SUCCESS;
3659 goto out;
3660 }
3661
3662 stgt_priv_data = sdev_priv_data->tgt_priv_data;
3663 dev_handle = stgt_priv_data->dev_handle;
3664 if (stgt_priv_data->dev_removed) {
3665 sdev_printk(KERN_INFO, scmd->device,
3666 "%s:target(handle = 0x%04x) is removed, target reset is not issued\n",
3667 mrioc->name, dev_handle);
3668 retval = FAILED;
3669 goto out;
3670 }
3671 sdev_printk(KERN_INFO, scmd->device,
3672 "Target Reset is issued to handle(0x%04x)\n",
3673 dev_handle);
3674
3675 ret = mpi3mr_issue_tm(mrioc,
3676 MPI3_SCSITASKMGMT_TASKTYPE_TARGET_RESET, dev_handle,
3677 sdev_priv_data->lun_id, MPI3MR_HOSTTAG_BLK_TMS,
3678 MPI3MR_RESETTM_TIMEOUT, &mrioc->host_tm_cmds, &resp_code, scmd);
3679
3680 if (ret)
3681 goto out;
3682
3683 if (stgt_priv_data->pend_count) {
3684 sdev_printk(KERN_INFO, scmd->device,
3685 "%s: target has %d pending commands, target reset is failed\n",
3686 mrioc->name, stgt_priv_data->pend_count);
3687 goto out;
3688 }
3689
3690 retval = SUCCESS;
3691 out:
3692 sdev_printk(KERN_INFO, scmd->device,
3693 "%s: target reset is %s for scmd(%p)\n", mrioc->name,
3694 ((retval == SUCCESS) ? "SUCCESS" : "FAILED"), scmd);
3695
3696 return retval;
3697 }
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709 static int mpi3mr_eh_dev_reset(struct scsi_cmnd *scmd)
3710 {
3711 struct mpi3mr_ioc *mrioc = shost_priv(scmd->device->host);
3712 struct mpi3mr_stgt_priv_data *stgt_priv_data;
3713 struct mpi3mr_sdev_priv_data *sdev_priv_data;
3714 u16 dev_handle;
3715 u8 resp_code = 0;
3716 int retval = FAILED, ret = 0;
3717
3718 sdev_printk(KERN_INFO, scmd->device,
3719 "Attempting Device(lun) Reset! scmd(%p)\n", scmd);
3720 scsi_print_command(scmd);
3721
3722 sdev_priv_data = scmd->device->hostdata;
3723 if (!sdev_priv_data || !sdev_priv_data->tgt_priv_data) {
3724 sdev_printk(KERN_INFO, scmd->device,
3725 "SCSI device is not available\n");
3726 retval = SUCCESS;
3727 goto out;
3728 }
3729
3730 stgt_priv_data = sdev_priv_data->tgt_priv_data;
3731 dev_handle = stgt_priv_data->dev_handle;
3732 if (stgt_priv_data->dev_removed) {
3733 sdev_printk(KERN_INFO, scmd->device,
3734 "%s: device(handle = 0x%04x) is removed, device(LUN) reset is not issued\n",
3735 mrioc->name, dev_handle);
3736 retval = FAILED;
3737 goto out;
3738 }
3739 sdev_printk(KERN_INFO, scmd->device,
3740 "Device(lun) Reset is issued to handle(0x%04x)\n", dev_handle);
3741
3742 ret = mpi3mr_issue_tm(mrioc,
3743 MPI3_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET, dev_handle,
3744 sdev_priv_data->lun_id, MPI3MR_HOSTTAG_BLK_TMS,
3745 MPI3MR_RESETTM_TIMEOUT, &mrioc->host_tm_cmds, &resp_code, scmd);
3746
3747 if (ret)
3748 goto out;
3749
3750 if (sdev_priv_data->pend_count) {
3751 sdev_printk(KERN_INFO, scmd->device,
3752 "%s: device has %d pending commands, device(LUN) reset is failed\n",
3753 mrioc->name, sdev_priv_data->pend_count);
3754 goto out;
3755 }
3756 retval = SUCCESS;
3757 out:
3758 sdev_printk(KERN_INFO, scmd->device,
3759 "%s: device(LUN) reset is %s for scmd(%p)\n", mrioc->name,
3760 ((retval == SUCCESS) ? "SUCCESS" : "FAILED"), scmd);
3761
3762 return retval;
3763 }
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773 static void mpi3mr_scan_start(struct Scsi_Host *shost)
3774 {
3775 struct mpi3mr_ioc *mrioc = shost_priv(shost);
3776
3777 mrioc->scan_started = 1;
3778 ioc_info(mrioc, "%s :Issuing Port Enable\n", __func__);
3779 if (mpi3mr_issue_port_enable(mrioc, 1)) {
3780 ioc_err(mrioc, "%s :Issuing port enable failed\n", __func__);
3781 mrioc->scan_started = 0;
3782 mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR;
3783 }
3784 }
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797 static int mpi3mr_scan_finished(struct Scsi_Host *shost,
3798 unsigned long time)
3799 {
3800 struct mpi3mr_ioc *mrioc = shost_priv(shost);
3801 u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT;
3802 u32 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
3803
3804 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
3805 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
3806 ioc_err(mrioc, "port enable failed due to fault or reset\n");
3807 mpi3mr_print_fault_info(mrioc);
3808 mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR;
3809 mrioc->scan_started = 0;
3810 mrioc->init_cmds.is_waiting = 0;
3811 mrioc->init_cmds.callback = NULL;
3812 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3813 }
3814
3815 if (time >= (pe_timeout * HZ)) {
3816 ioc_err(mrioc, "port enable failed due to time out\n");
3817 mpi3mr_check_rh_fault_ioc(mrioc,
3818 MPI3MR_RESET_FROM_PE_TIMEOUT);
3819 mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR;
3820 mrioc->scan_started = 0;
3821 mrioc->init_cmds.is_waiting = 0;
3822 mrioc->init_cmds.callback = NULL;
3823 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3824 }
3825
3826 if (mrioc->scan_started)
3827 return 0;
3828
3829 if (mrioc->scan_failed) {
3830 ioc_err(mrioc,
3831 "port enable failed with status=0x%04x\n",
3832 mrioc->scan_failed);
3833 } else
3834 ioc_info(mrioc, "port enable is successfully completed\n");
3835
3836 mpi3mr_start_watchdog(mrioc);
3837 mrioc->is_driver_loading = 0;
3838 mrioc->stop_bsgs = 0;
3839 return 1;
3840 }
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850 static void mpi3mr_slave_destroy(struct scsi_device *sdev)
3851 {
3852 struct Scsi_Host *shost;
3853 struct mpi3mr_ioc *mrioc;
3854 struct mpi3mr_stgt_priv_data *scsi_tgt_priv_data;
3855 struct mpi3mr_tgt_dev *tgt_dev;
3856 unsigned long flags;
3857 struct scsi_target *starget;
3858
3859 if (!sdev->hostdata)
3860 return;
3861
3862 starget = scsi_target(sdev);
3863 shost = dev_to_shost(&starget->dev);
3864 mrioc = shost_priv(shost);
3865 scsi_tgt_priv_data = starget->hostdata;
3866
3867 scsi_tgt_priv_data->num_luns--;
3868
3869 spin_lock_irqsave(&mrioc->tgtdev_lock, flags);
3870 tgt_dev = __mpi3mr_get_tgtdev_by_perst_id(mrioc, starget->id);
3871 if (tgt_dev && (!scsi_tgt_priv_data->num_luns))
3872 tgt_dev->starget = NULL;
3873 if (tgt_dev)
3874 mpi3mr_tgtdev_put(tgt_dev);
3875 spin_unlock_irqrestore(&mrioc->tgtdev_lock, flags);
3876
3877 kfree(sdev->hostdata);
3878 sdev->hostdata = NULL;
3879 }
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889 static void mpi3mr_target_destroy(struct scsi_target *starget)
3890 {
3891 struct Scsi_Host *shost;
3892 struct mpi3mr_ioc *mrioc;
3893 struct mpi3mr_stgt_priv_data *scsi_tgt_priv_data;
3894 struct mpi3mr_tgt_dev *tgt_dev;
3895 unsigned long flags;
3896
3897 if (!starget->hostdata)
3898 return;
3899
3900 shost = dev_to_shost(&starget->dev);
3901 mrioc = shost_priv(shost);
3902 scsi_tgt_priv_data = starget->hostdata;
3903
3904 spin_lock_irqsave(&mrioc->tgtdev_lock, flags);
3905 tgt_dev = __mpi3mr_get_tgtdev_from_tgtpriv(mrioc, scsi_tgt_priv_data);
3906 if (tgt_dev && (tgt_dev->starget == starget) &&
3907 (tgt_dev->perst_id == starget->id))
3908 tgt_dev->starget = NULL;
3909 if (tgt_dev) {
3910 scsi_tgt_priv_data->tgt_dev = NULL;
3911 scsi_tgt_priv_data->perst_id = 0;
3912 mpi3mr_tgtdev_put(tgt_dev);
3913 mpi3mr_tgtdev_put(tgt_dev);
3914 }
3915 spin_unlock_irqrestore(&mrioc->tgtdev_lock, flags);
3916
3917 kfree(starget->hostdata);
3918 starget->hostdata = NULL;
3919 }
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930 static int mpi3mr_slave_configure(struct scsi_device *sdev)
3931 {
3932 struct scsi_target *starget;
3933 struct Scsi_Host *shost;
3934 struct mpi3mr_ioc *mrioc;
3935 struct mpi3mr_tgt_dev *tgt_dev;
3936 unsigned long flags;
3937 int retval = 0;
3938
3939 starget = scsi_target(sdev);
3940 shost = dev_to_shost(&starget->dev);
3941 mrioc = shost_priv(shost);
3942
3943 spin_lock_irqsave(&mrioc->tgtdev_lock, flags);
3944 tgt_dev = __mpi3mr_get_tgtdev_by_perst_id(mrioc, starget->id);
3945 spin_unlock_irqrestore(&mrioc->tgtdev_lock, flags);
3946 if (!tgt_dev)
3947 return -ENXIO;
3948
3949 mpi3mr_change_queue_depth(sdev, tgt_dev->q_depth);
3950
3951 sdev->eh_timeout = MPI3MR_EH_SCMD_TIMEOUT;
3952 blk_queue_rq_timeout(sdev->request_queue, MPI3MR_SCMD_TIMEOUT);
3953
3954 switch (tgt_dev->dev_type) {
3955 case MPI3_DEVICE_DEVFORM_PCIE:
3956
3957 if ((tgt_dev->dev_spec.pcie_inf.dev_info &
3958 MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK) ==
3959 MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE) {
3960 blk_queue_max_hw_sectors(sdev->request_queue,
3961 tgt_dev->dev_spec.pcie_inf.mdts / 512);
3962 if (tgt_dev->dev_spec.pcie_inf.pgsz == 0)
3963 blk_queue_virt_boundary(sdev->request_queue,
3964 ((1 << MPI3MR_DEFAULT_PGSZEXP) - 1));
3965 else
3966 blk_queue_virt_boundary(sdev->request_queue,
3967 ((1 << tgt_dev->dev_spec.pcie_inf.pgsz) - 1));
3968 }
3969 break;
3970 default:
3971 break;
3972 }
3973
3974 mpi3mr_tgtdev_put(tgt_dev);
3975
3976 return retval;
3977 }
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987 static int mpi3mr_slave_alloc(struct scsi_device *sdev)
3988 {
3989 struct Scsi_Host *shost;
3990 struct mpi3mr_ioc *mrioc;
3991 struct mpi3mr_stgt_priv_data *scsi_tgt_priv_data;
3992 struct mpi3mr_tgt_dev *tgt_dev;
3993 struct mpi3mr_sdev_priv_data *scsi_dev_priv_data;
3994 unsigned long flags;
3995 struct scsi_target *starget;
3996 int retval = 0;
3997
3998 starget = scsi_target(sdev);
3999 shost = dev_to_shost(&starget->dev);
4000 mrioc = shost_priv(shost);
4001 scsi_tgt_priv_data = starget->hostdata;
4002
4003 spin_lock_irqsave(&mrioc->tgtdev_lock, flags);
4004 tgt_dev = __mpi3mr_get_tgtdev_by_perst_id(mrioc, starget->id);
4005
4006 if (tgt_dev) {
4007 if (tgt_dev->starget == NULL)
4008 tgt_dev->starget = starget;
4009 mpi3mr_tgtdev_put(tgt_dev);
4010 retval = 0;
4011 } else {
4012 spin_unlock_irqrestore(&mrioc->tgtdev_lock, flags);
4013 return -ENXIO;
4014 }
4015
4016 spin_unlock_irqrestore(&mrioc->tgtdev_lock, flags);
4017
4018 scsi_dev_priv_data = kzalloc(sizeof(*scsi_dev_priv_data), GFP_KERNEL);
4019 if (!scsi_dev_priv_data)
4020 return -ENOMEM;
4021
4022 scsi_dev_priv_data->lun_id = sdev->lun;
4023 scsi_dev_priv_data->tgt_priv_data = scsi_tgt_priv_data;
4024 sdev->hostdata = scsi_dev_priv_data;
4025
4026 scsi_tgt_priv_data->num_luns++;
4027
4028 return retval;
4029 }
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039 static int mpi3mr_target_alloc(struct scsi_target *starget)
4040 {
4041 struct Scsi_Host *shost = dev_to_shost(&starget->dev);
4042 struct mpi3mr_ioc *mrioc = shost_priv(shost);
4043 struct mpi3mr_stgt_priv_data *scsi_tgt_priv_data;
4044 struct mpi3mr_tgt_dev *tgt_dev;
4045 unsigned long flags;
4046 int retval = 0;
4047
4048 scsi_tgt_priv_data = kzalloc(sizeof(*scsi_tgt_priv_data), GFP_KERNEL);
4049 if (!scsi_tgt_priv_data)
4050 return -ENOMEM;
4051
4052 starget->hostdata = scsi_tgt_priv_data;
4053
4054 spin_lock_irqsave(&mrioc->tgtdev_lock, flags);
4055 tgt_dev = __mpi3mr_get_tgtdev_by_perst_id(mrioc, starget->id);
4056 if (tgt_dev && !tgt_dev->is_hidden) {
4057 scsi_tgt_priv_data->starget = starget;
4058 scsi_tgt_priv_data->dev_handle = tgt_dev->dev_handle;
4059 scsi_tgt_priv_data->perst_id = tgt_dev->perst_id;
4060 scsi_tgt_priv_data->dev_type = tgt_dev->dev_type;
4061 scsi_tgt_priv_data->tgt_dev = tgt_dev;
4062 tgt_dev->starget = starget;
4063 atomic_set(&scsi_tgt_priv_data->block_io, 0);
4064 retval = 0;
4065 scsi_tgt_priv_data->io_throttle_enabled =
4066 tgt_dev->io_throttle_enabled;
4067 if (tgt_dev->dev_type == MPI3_DEVICE_DEVFORM_VD)
4068 scsi_tgt_priv_data->throttle_group =
4069 tgt_dev->dev_spec.vd_inf.tg;
4070 } else
4071 retval = -ENXIO;
4072 spin_unlock_irqrestore(&mrioc->tgtdev_lock, flags);
4073
4074 return retval;
4075 }
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089 static bool mpi3mr_check_return_unmap(struct mpi3mr_ioc *mrioc,
4090 struct scsi_cmnd *scmd)
4091 {
4092 unsigned char *buf;
4093 u16 param_len, desc_len, trunc_param_len;
4094
4095 trunc_param_len = param_len = get_unaligned_be16(scmd->cmnd + 7);
4096
4097 if (mrioc->pdev->revision) {
4098 if ((param_len > 24) && ((param_len - 8) & 0xF)) {
4099 trunc_param_len -= (param_len - 8) & 0xF;
4100 dprint_scsi_command(mrioc, scmd, MPI3_DEBUG_SCSI_ERROR);
4101 dprint_scsi_err(mrioc,
4102 "truncating param_len from (%d) to (%d)\n",
4103 param_len, trunc_param_len);
4104 put_unaligned_be16(trunc_param_len, scmd->cmnd + 7);
4105 dprint_scsi_command(mrioc, scmd, MPI3_DEBUG_SCSI_ERROR);
4106 }
4107 return false;
4108 }
4109
4110 if (!param_len) {
4111 ioc_warn(mrioc,
4112 "%s: cdb received with zero parameter length\n",
4113 __func__);
4114 scsi_print_command(scmd);
4115 scmd->result = DID_OK << 16;
4116 scsi_done(scmd);
4117 return true;
4118 }
4119
4120 if (param_len < 24) {
4121 ioc_warn(mrioc,
4122 "%s: cdb received with invalid param_len: %d\n",
4123 __func__, param_len);
4124 scsi_print_command(scmd);
4125 scmd->result = SAM_STAT_CHECK_CONDITION;
4126 scsi_build_sense_buffer(0, scmd->sense_buffer, ILLEGAL_REQUEST,
4127 0x1A, 0);
4128 scsi_done(scmd);
4129 return true;
4130 }
4131 if (param_len != scsi_bufflen(scmd)) {
4132 ioc_warn(mrioc,
4133 "%s: cdb received with param_len: %d bufflen: %d\n",
4134 __func__, param_len, scsi_bufflen(scmd));
4135 scsi_print_command(scmd);
4136 scmd->result = SAM_STAT_CHECK_CONDITION;
4137 scsi_build_sense_buffer(0, scmd->sense_buffer, ILLEGAL_REQUEST,
4138 0x1A, 0);
4139 scsi_done(scmd);
4140 return true;
4141 }
4142 buf = kzalloc(scsi_bufflen(scmd), GFP_ATOMIC);
4143 if (!buf) {
4144 scsi_print_command(scmd);
4145 scmd->result = SAM_STAT_CHECK_CONDITION;
4146 scsi_build_sense_buffer(0, scmd->sense_buffer, ILLEGAL_REQUEST,
4147 0x55, 0x03);
4148 scsi_done(scmd);
4149 return true;
4150 }
4151 scsi_sg_copy_to_buffer(scmd, buf, scsi_bufflen(scmd));
4152 desc_len = get_unaligned_be16(&buf[2]);
4153
4154 if (desc_len < 16) {
4155 ioc_warn(mrioc,
4156 "%s: Invalid descriptor length in param list: %d\n",
4157 __func__, desc_len);
4158 scsi_print_command(scmd);
4159 scmd->result = SAM_STAT_CHECK_CONDITION;
4160 scsi_build_sense_buffer(0, scmd->sense_buffer, ILLEGAL_REQUEST,
4161 0x26, 0);
4162 scsi_done(scmd);
4163 kfree(buf);
4164 return true;
4165 }
4166
4167 if (param_len > (desc_len + 8)) {
4168 trunc_param_len = desc_len + 8;
4169 scsi_print_command(scmd);
4170 dprint_scsi_err(mrioc,
4171 "truncating param_len(%d) to desc_len+8(%d)\n",
4172 param_len, trunc_param_len);
4173 put_unaligned_be16(trunc_param_len, scmd->cmnd + 7);
4174 scsi_print_command(scmd);
4175 }
4176
4177 kfree(buf);
4178 return false;
4179 }
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190 inline bool mpi3mr_allow_scmd_to_fw(struct scsi_cmnd *scmd)
4191 {
4192 switch (scmd->cmnd[0]) {
4193 case SYNCHRONIZE_CACHE:
4194 case START_STOP:
4195 return true;
4196 default:
4197 return false;
4198 }
4199 }
4200
4201
4202
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213 static int mpi3mr_qcmd(struct Scsi_Host *shost,
4214 struct scsi_cmnd *scmd)
4215 {
4216 struct mpi3mr_ioc *mrioc = shost_priv(shost);
4217 struct mpi3mr_stgt_priv_data *stgt_priv_data;
4218 struct mpi3mr_sdev_priv_data *sdev_priv_data;
4219 struct scmd_priv *scmd_priv_data = NULL;
4220 struct mpi3_scsi_io_request *scsiio_req = NULL;
4221 struct op_req_qinfo *op_req_q = NULL;
4222 int retval = 0;
4223 u16 dev_handle;
4224 u16 host_tag;
4225 u32 scsiio_flags = 0, data_len_blks = 0;
4226 struct request *rq = scsi_cmd_to_rq(scmd);
4227 int iprio_class;
4228 u8 is_pcie_dev = 0;
4229 u32 tracked_io_sz = 0;
4230 u32 ioc_pend_data_len = 0, tg_pend_data_len = 0;
4231 struct mpi3mr_throttle_group_info *tg = NULL;
4232
4233 if (mrioc->unrecoverable) {
4234 scmd->result = DID_ERROR << 16;
4235 scsi_done(scmd);
4236 goto out;
4237 }
4238
4239 sdev_priv_data = scmd->device->hostdata;
4240 if (!sdev_priv_data || !sdev_priv_data->tgt_priv_data) {
4241 scmd->result = DID_NO_CONNECT << 16;
4242 scsi_done(scmd);
4243 goto out;
4244 }
4245
4246 if (mrioc->stop_drv_processing &&
4247 !(mpi3mr_allow_scmd_to_fw(scmd))) {
4248 scmd->result = DID_NO_CONNECT << 16;
4249 scsi_done(scmd);
4250 goto out;
4251 }
4252
4253 if (mrioc->reset_in_progress) {
4254 retval = SCSI_MLQUEUE_HOST_BUSY;
4255 goto out;
4256 }
4257
4258 stgt_priv_data = sdev_priv_data->tgt_priv_data;
4259
4260 dev_handle = stgt_priv_data->dev_handle;
4261 if (dev_handle == MPI3MR_INVALID_DEV_HANDLE) {
4262 scmd->result = DID_NO_CONNECT << 16;
4263 scsi_done(scmd);
4264 goto out;
4265 }
4266 if (stgt_priv_data->dev_removed) {
4267 scmd->result = DID_NO_CONNECT << 16;
4268 scsi_done(scmd);
4269 goto out;
4270 }
4271
4272 if (atomic_read(&stgt_priv_data->block_io)) {
4273 if (mrioc->stop_drv_processing) {
4274 scmd->result = DID_NO_CONNECT << 16;
4275 scsi_done(scmd);
4276 goto out;
4277 }
4278 retval = SCSI_MLQUEUE_DEVICE_BUSY;
4279 goto out;
4280 }
4281
4282 if (stgt_priv_data->dev_type == MPI3_DEVICE_DEVFORM_PCIE)
4283 is_pcie_dev = 1;
4284 if ((scmd->cmnd[0] == UNMAP) && is_pcie_dev &&
4285 (mrioc->pdev->device == MPI3_MFGPAGE_DEVID_SAS4116) &&
4286 mpi3mr_check_return_unmap(mrioc, scmd))
4287 goto out;
4288
4289 host_tag = mpi3mr_host_tag_for_scmd(mrioc, scmd);
4290 if (host_tag == MPI3MR_HOSTTAG_INVALID) {
4291 scmd->result = DID_ERROR << 16;
4292 scsi_done(scmd);
4293 goto out;
4294 }
4295
4296 if (scmd->sc_data_direction == DMA_FROM_DEVICE)
4297 scsiio_flags = MPI3_SCSIIO_FLAGS_DATADIRECTION_READ;
4298 else if (scmd->sc_data_direction == DMA_TO_DEVICE)
4299 scsiio_flags = MPI3_SCSIIO_FLAGS_DATADIRECTION_WRITE;
4300 else
4301 scsiio_flags = MPI3_SCSIIO_FLAGS_DATADIRECTION_NO_DATA_TRANSFER;
4302
4303 scsiio_flags |= MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_SIMPLEQ;
4304
4305 if (sdev_priv_data->ncq_prio_enable) {
4306 iprio_class = IOPRIO_PRIO_CLASS(req_get_ioprio(rq));
4307 if (iprio_class == IOPRIO_CLASS_RT)
4308 scsiio_flags |= 1 << MPI3_SCSIIO_FLAGS_CMDPRI_SHIFT;
4309 }
4310
4311 if (scmd->cmd_len > 16)
4312 scsiio_flags |= MPI3_SCSIIO_FLAGS_CDB_GREATER_THAN_16;
4313
4314 scmd_priv_data = scsi_cmd_priv(scmd);
4315 memset(scmd_priv_data->mpi3mr_scsiio_req, 0, MPI3MR_ADMIN_REQ_FRAME_SZ);
4316 scsiio_req = (struct mpi3_scsi_io_request *)scmd_priv_data->mpi3mr_scsiio_req;
4317 scsiio_req->function = MPI3_FUNCTION_SCSI_IO;
4318 scsiio_req->host_tag = cpu_to_le16(host_tag);
4319
4320 mpi3mr_setup_eedp(mrioc, scmd, scsiio_req);
4321
4322 memcpy(scsiio_req->cdb.cdb32, scmd->cmnd, scmd->cmd_len);
4323 scsiio_req->data_length = cpu_to_le32(scsi_bufflen(scmd));
4324 scsiio_req->dev_handle = cpu_to_le16(dev_handle);
4325 scsiio_req->flags = cpu_to_le32(scsiio_flags);
4326 int_to_scsilun(sdev_priv_data->lun_id,
4327 (struct scsi_lun *)scsiio_req->lun);
4328
4329 if (mpi3mr_build_sg_scmd(mrioc, scmd, scsiio_req)) {
4330 mpi3mr_clear_scmd_priv(mrioc, scmd);
4331 retval = SCSI_MLQUEUE_HOST_BUSY;
4332 goto out;
4333 }
4334 op_req_q = &mrioc->req_qinfo[scmd_priv_data->req_q_idx];
4335 data_len_blks = scsi_bufflen(scmd) >> 9;
4336 if ((data_len_blks >= mrioc->io_throttle_data_length) &&
4337 stgt_priv_data->io_throttle_enabled) {
4338 tracked_io_sz = data_len_blks;
4339 tg = stgt_priv_data->throttle_group;
4340 if (tg) {
4341 ioc_pend_data_len = atomic_add_return(data_len_blks,
4342 &mrioc->pend_large_data_sz);
4343 tg_pend_data_len = atomic_add_return(data_len_blks,
4344 &tg->pend_large_data_sz);
4345 if (!tg->io_divert && ((ioc_pend_data_len >=
4346 mrioc->io_throttle_high) ||
4347 (tg_pend_data_len >= tg->high))) {
4348 tg->io_divert = 1;
4349 tg->need_qd_reduction = 1;
4350 mpi3mr_set_io_divert_for_all_vd_in_tg(mrioc,
4351 tg, 1);
4352 mpi3mr_queue_qd_reduction_event(mrioc, tg);
4353 }
4354 } else {
4355 ioc_pend_data_len = atomic_add_return(data_len_blks,
4356 &mrioc->pend_large_data_sz);
4357 if (ioc_pend_data_len >= mrioc->io_throttle_high)
4358 stgt_priv_data->io_divert = 1;
4359 }
4360 }
4361
4362 if (stgt_priv_data->io_divert) {
4363 scsiio_req->msg_flags |=
4364 MPI3_SCSIIO_MSGFLAGS_DIVERT_TO_FIRMWARE;
4365 scsiio_flags |= MPI3_SCSIIO_FLAGS_DIVERT_REASON_IO_THROTTLING;
4366 }
4367 scsiio_req->flags = cpu_to_le32(scsiio_flags);
4368
4369 if (mpi3mr_op_request_post(mrioc, op_req_q,
4370 scmd_priv_data->mpi3mr_scsiio_req)) {
4371 mpi3mr_clear_scmd_priv(mrioc, scmd);
4372 retval = SCSI_MLQUEUE_HOST_BUSY;
4373 if (tracked_io_sz) {
4374 atomic_sub(tracked_io_sz, &mrioc->pend_large_data_sz);
4375 if (tg)
4376 atomic_sub(tracked_io_sz,
4377 &tg->pend_large_data_sz);
4378 }
4379 goto out;
4380 }
4381
4382 out:
4383 return retval;
4384 }
4385
4386 static struct scsi_host_template mpi3mr_driver_template = {
4387 .module = THIS_MODULE,
4388 .name = "MPI3 Storage Controller",
4389 .proc_name = MPI3MR_DRIVER_NAME,
4390 .queuecommand = mpi3mr_qcmd,
4391 .target_alloc = mpi3mr_target_alloc,
4392 .slave_alloc = mpi3mr_slave_alloc,
4393 .slave_configure = mpi3mr_slave_configure,
4394 .target_destroy = mpi3mr_target_destroy,
4395 .slave_destroy = mpi3mr_slave_destroy,
4396 .scan_finished = mpi3mr_scan_finished,
4397 .scan_start = mpi3mr_scan_start,
4398 .change_queue_depth = mpi3mr_change_queue_depth,
4399 .eh_device_reset_handler = mpi3mr_eh_dev_reset,
4400 .eh_target_reset_handler = mpi3mr_eh_target_reset,
4401 .eh_host_reset_handler = mpi3mr_eh_host_reset,
4402 .bios_param = mpi3mr_bios_param,
4403 .map_queues = mpi3mr_map_queues,
4404 .mq_poll = mpi3mr_blk_mq_poll,
4405 .no_write_same = 1,
4406 .can_queue = 1,
4407 .this_id = -1,
4408 .sg_tablesize = MPI3MR_SG_DEPTH,
4409
4410
4411 .max_sectors = 2048,
4412 .cmd_per_lun = MPI3MR_MAX_CMDS_LUN,
4413 .max_segment_size = 0xffffffff,
4414 .track_queue_depth = 1,
4415 .cmd_size = sizeof(struct scmd_priv),
4416 .shost_groups = mpi3mr_host_groups,
4417 .sdev_groups = mpi3mr_dev_groups,
4418 };
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429
4430 static inline void mpi3mr_init_drv_cmd(struct mpi3mr_drv_cmd *cmdptr,
4431 u16 host_tag)
4432 {
4433 mutex_init(&cmdptr->mutex);
4434 cmdptr->reply = NULL;
4435 cmdptr->state = MPI3MR_CMD_NOTUSED;
4436 cmdptr->dev_handle = MPI3MR_INVALID_DEV_HANDLE;
4437 cmdptr->host_tag = host_tag;
4438 }
4439
4440
4441
4442
4443
4444
4445
4446
4447
4448
4449 static int
4450 osintfc_mrioc_security_status(struct pci_dev *pdev)
4451 {
4452 u32 cap_data;
4453 int base;
4454 u32 ctlr_status;
4455 u32 debug_status;
4456 int retval = 0;
4457
4458 base = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DSN);
4459 if (!base) {
4460 dev_err(&pdev->dev,
4461 "%s: PCI_EXT_CAP_ID_DSN is not supported\n", __func__);
4462 return -1;
4463 }
4464
4465 pci_read_config_dword(pdev, base + 4, &cap_data);
4466
4467 debug_status = cap_data & MPI3MR_CTLR_SECURE_DBG_STATUS_MASK;
4468 ctlr_status = cap_data & MPI3MR_CTLR_SECURITY_STATUS_MASK;
4469
4470 switch (ctlr_status) {
4471 case MPI3MR_INVALID_DEVICE:
4472 dev_err(&pdev->dev,
4473 "%s: Non secure ctlr (Invalid) is detected: DID: 0x%x: SVID: 0x%x: SDID: 0x%x\n",
4474 __func__, pdev->device, pdev->subsystem_vendor,
4475 pdev->subsystem_device);
4476 retval = -1;
4477 break;
4478 case MPI3MR_CONFIG_SECURE_DEVICE:
4479 if (!debug_status)
4480 dev_info(&pdev->dev,
4481 "%s: Config secure ctlr is detected\n",
4482 __func__);
4483 break;
4484 case MPI3MR_HARD_SECURE_DEVICE:
4485 break;
4486 case MPI3MR_TAMPERED_DEVICE:
4487 dev_err(&pdev->dev,
4488 "%s: Non secure ctlr (Tampered) is detected: DID: 0x%x: SVID: 0x%x: SDID: 0x%x\n",
4489 __func__, pdev->device, pdev->subsystem_vendor,
4490 pdev->subsystem_device);
4491 retval = -1;
4492 break;
4493 default:
4494 retval = -1;
4495 break;
4496 }
4497
4498 if (!retval && debug_status) {
4499 dev_err(&pdev->dev,
4500 "%s: Non secure ctlr (Secure Dbg) is detected: DID: 0x%x: SVID: 0x%x: SDID: 0x%x\n",
4501 __func__, pdev->device, pdev->subsystem_vendor,
4502 pdev->subsystem_device);
4503 retval = -1;
4504 }
4505
4506 return retval;
4507 }
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
4519
4520
4521
4522
4523
4524 static int
4525 mpi3mr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
4526 {
4527 struct mpi3mr_ioc *mrioc = NULL;
4528 struct Scsi_Host *shost = NULL;
4529 int retval = 0, i;
4530
4531 if (osintfc_mrioc_security_status(pdev)) {
4532 warn_non_secure_ctlr = 1;
4533 return 1;
4534 }
4535
4536 shost = scsi_host_alloc(&mpi3mr_driver_template,
4537 sizeof(struct mpi3mr_ioc));
4538 if (!shost) {
4539 retval = -ENODEV;
4540 goto shost_failed;
4541 }
4542
4543 mrioc = shost_priv(shost);
4544 mrioc->id = mrioc_ids++;
4545 sprintf(mrioc->driver_name, "%s", MPI3MR_DRIVER_NAME);
4546 sprintf(mrioc->name, "%s%d", mrioc->driver_name, mrioc->id);
4547 INIT_LIST_HEAD(&mrioc->list);
4548 spin_lock(&mrioc_list_lock);
4549 list_add_tail(&mrioc->list, &mrioc_list);
4550 spin_unlock(&mrioc_list_lock);
4551
4552 spin_lock_init(&mrioc->admin_req_lock);
4553 spin_lock_init(&mrioc->reply_free_queue_lock);
4554 spin_lock_init(&mrioc->sbq_lock);
4555 spin_lock_init(&mrioc->fwevt_lock);
4556 spin_lock_init(&mrioc->tgtdev_lock);
4557 spin_lock_init(&mrioc->watchdog_lock);
4558 spin_lock_init(&mrioc->chain_buf_lock);
4559
4560 INIT_LIST_HEAD(&mrioc->fwevt_list);
4561 INIT_LIST_HEAD(&mrioc->tgtdev_list);
4562 INIT_LIST_HEAD(&mrioc->delayed_rmhs_list);
4563 INIT_LIST_HEAD(&mrioc->delayed_evtack_cmds_list);
4564
4565 mutex_init(&mrioc->reset_mutex);
4566 mpi3mr_init_drv_cmd(&mrioc->init_cmds, MPI3MR_HOSTTAG_INITCMDS);
4567 mpi3mr_init_drv_cmd(&mrioc->host_tm_cmds, MPI3MR_HOSTTAG_BLK_TMS);
4568 mpi3mr_init_drv_cmd(&mrioc->bsg_cmds, MPI3MR_HOSTTAG_BSG_CMDS);
4569
4570 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++)
4571 mpi3mr_init_drv_cmd(&mrioc->dev_rmhs_cmds[i],
4572 MPI3MR_HOSTTAG_DEVRMCMD_MIN + i);
4573
4574 if (pdev->revision)
4575 mrioc->enable_segqueue = true;
4576
4577 init_waitqueue_head(&mrioc->reset_waitq);
4578 mrioc->logging_level = logging_level;
4579 mrioc->shost = shost;
4580 mrioc->pdev = pdev;
4581 mrioc->stop_bsgs = 1;
4582
4583
4584 shost->max_cmd_len = MPI3MR_MAX_CDB_LENGTH;
4585 shost->max_lun = -1;
4586 shost->unique_id = mrioc->id;
4587
4588 shost->max_channel = 0;
4589 shost->max_id = 0xFFFFFFFF;
4590
4591 shost->host_tagset = 1;
4592
4593 if (prot_mask >= 0)
4594 scsi_host_set_prot(shost, prot_mask);
4595 else {
4596 prot_mask = SHOST_DIF_TYPE1_PROTECTION
4597 | SHOST_DIF_TYPE2_PROTECTION
4598 | SHOST_DIF_TYPE3_PROTECTION;
4599 scsi_host_set_prot(shost, prot_mask);
4600 }
4601
4602 ioc_info(mrioc,
4603 "%s :host protection capabilities enabled %s%s%s%s%s%s%s\n",
4604 __func__,
4605 (prot_mask & SHOST_DIF_TYPE1_PROTECTION) ? " DIF1" : "",
4606 (prot_mask & SHOST_DIF_TYPE2_PROTECTION) ? " DIF2" : "",
4607 (prot_mask & SHOST_DIF_TYPE3_PROTECTION) ? " DIF3" : "",
4608 (prot_mask & SHOST_DIX_TYPE0_PROTECTION) ? " DIX0" : "",
4609 (prot_mask & SHOST_DIX_TYPE1_PROTECTION) ? " DIX1" : "",
4610 (prot_mask & SHOST_DIX_TYPE2_PROTECTION) ? " DIX2" : "",
4611 (prot_mask & SHOST_DIX_TYPE3_PROTECTION) ? " DIX3" : "");
4612
4613 if (prot_guard_mask)
4614 scsi_host_set_guard(shost, (prot_guard_mask & 3));
4615 else
4616 scsi_host_set_guard(shost, SHOST_DIX_GUARD_CRC);
4617
4618 snprintf(mrioc->fwevt_worker_name, sizeof(mrioc->fwevt_worker_name),
4619 "%s%d_fwevt_wrkr", mrioc->driver_name, mrioc->id);
4620 mrioc->fwevt_worker_thread = alloc_ordered_workqueue(
4621 mrioc->fwevt_worker_name, 0);
4622 if (!mrioc->fwevt_worker_thread) {
4623 ioc_err(mrioc, "failure at %s:%d/%s()!\n",
4624 __FILE__, __LINE__, __func__);
4625 retval = -ENODEV;
4626 goto fwevtthread_failed;
4627 }
4628
4629 mrioc->is_driver_loading = 1;
4630 mrioc->cpu_count = num_online_cpus();
4631 if (mpi3mr_setup_resources(mrioc)) {
4632 ioc_err(mrioc, "setup resources failed\n");
4633 retval = -ENODEV;
4634 goto resource_alloc_failed;
4635 }
4636 if (mpi3mr_init_ioc(mrioc)) {
4637 ioc_err(mrioc, "initializing IOC failed\n");
4638 retval = -ENODEV;
4639 goto init_ioc_failed;
4640 }
4641
4642 shost->nr_hw_queues = mrioc->num_op_reply_q;
4643 if (mrioc->active_poll_qcount)
4644 shost->nr_maps = 3;
4645
4646 shost->can_queue = mrioc->max_host_ios;
4647 shost->sg_tablesize = MPI3MR_SG_DEPTH;
4648 shost->max_id = mrioc->facts.max_perids + 1;
4649
4650 retval = scsi_add_host(shost, &pdev->dev);
4651 if (retval) {
4652 ioc_err(mrioc, "failure at %s:%d/%s()!\n",
4653 __FILE__, __LINE__, __func__);
4654 goto addhost_failed;
4655 }
4656
4657 scsi_scan_host(shost);
4658 mpi3mr_bsg_init(mrioc);
4659 return retval;
4660
4661 addhost_failed:
4662 mpi3mr_stop_watchdog(mrioc);
4663 mpi3mr_cleanup_ioc(mrioc);
4664 init_ioc_failed:
4665 mpi3mr_free_mem(mrioc);
4666 mpi3mr_cleanup_resources(mrioc);
4667 resource_alloc_failed:
4668 destroy_workqueue(mrioc->fwevt_worker_thread);
4669 fwevtthread_failed:
4670 spin_lock(&mrioc_list_lock);
4671 list_del(&mrioc->list);
4672 spin_unlock(&mrioc_list_lock);
4673 scsi_host_put(shost);
4674 shost_failed:
4675 return retval;
4676 }
4677
4678
4679
4680
4681
4682
4683
4684
4685
4686
4687
4688 static void mpi3mr_remove(struct pci_dev *pdev)
4689 {
4690 struct Scsi_Host *shost = pci_get_drvdata(pdev);
4691 struct mpi3mr_ioc *mrioc;
4692 struct workqueue_struct *wq;
4693 unsigned long flags;
4694 struct mpi3mr_tgt_dev *tgtdev, *tgtdev_next;
4695
4696 if (!shost)
4697 return;
4698
4699 mrioc = shost_priv(shost);
4700 while (mrioc->reset_in_progress || mrioc->is_driver_loading)
4701 ssleep(1);
4702
4703 mpi3mr_bsg_exit(mrioc);
4704 mrioc->stop_drv_processing = 1;
4705 mpi3mr_cleanup_fwevt_list(mrioc);
4706 spin_lock_irqsave(&mrioc->fwevt_lock, flags);
4707 wq = mrioc->fwevt_worker_thread;
4708 mrioc->fwevt_worker_thread = NULL;
4709 spin_unlock_irqrestore(&mrioc->fwevt_lock, flags);
4710 if (wq)
4711 destroy_workqueue(wq);
4712 scsi_remove_host(shost);
4713
4714 list_for_each_entry_safe(tgtdev, tgtdev_next, &mrioc->tgtdev_list,
4715 list) {
4716 mpi3mr_remove_tgtdev_from_host(mrioc, tgtdev);
4717 mpi3mr_tgtdev_del_from_list(mrioc, tgtdev);
4718 mpi3mr_tgtdev_put(tgtdev);
4719 }
4720 mpi3mr_stop_watchdog(mrioc);
4721 mpi3mr_cleanup_ioc(mrioc);
4722 mpi3mr_free_mem(mrioc);
4723 mpi3mr_cleanup_resources(mrioc);
4724
4725 spin_lock(&mrioc_list_lock);
4726 list_del(&mrioc->list);
4727 spin_unlock(&mrioc_list_lock);
4728
4729 scsi_host_put(shost);
4730 }
4731
4732
4733
4734
4735
4736
4737
4738
4739
4740
4741 static void mpi3mr_shutdown(struct pci_dev *pdev)
4742 {
4743 struct Scsi_Host *shost = pci_get_drvdata(pdev);
4744 struct mpi3mr_ioc *mrioc;
4745 struct workqueue_struct *wq;
4746 unsigned long flags;
4747
4748 if (!shost)
4749 return;
4750
4751 mrioc = shost_priv(shost);
4752 while (mrioc->reset_in_progress || mrioc->is_driver_loading)
4753 ssleep(1);
4754
4755 mrioc->stop_drv_processing = 1;
4756 mpi3mr_cleanup_fwevt_list(mrioc);
4757 spin_lock_irqsave(&mrioc->fwevt_lock, flags);
4758 wq = mrioc->fwevt_worker_thread;
4759 mrioc->fwevt_worker_thread = NULL;
4760 spin_unlock_irqrestore(&mrioc->fwevt_lock, flags);
4761 if (wq)
4762 destroy_workqueue(wq);
4763
4764 mpi3mr_stop_watchdog(mrioc);
4765 mpi3mr_cleanup_ioc(mrioc);
4766 mpi3mr_cleanup_resources(mrioc);
4767 }
4768
4769 #ifdef CONFIG_PM
4770
4771
4772
4773
4774
4775
4776
4777
4778
4779
4780 static int mpi3mr_suspend(struct pci_dev *pdev, pm_message_t state)
4781 {
4782 struct Scsi_Host *shost = pci_get_drvdata(pdev);
4783 struct mpi3mr_ioc *mrioc;
4784 pci_power_t device_state;
4785
4786 if (!shost)
4787 return 0;
4788
4789 mrioc = shost_priv(shost);
4790 while (mrioc->reset_in_progress || mrioc->is_driver_loading)
4791 ssleep(1);
4792 mrioc->stop_drv_processing = 1;
4793 mpi3mr_cleanup_fwevt_list(mrioc);
4794 scsi_block_requests(shost);
4795 mpi3mr_stop_watchdog(mrioc);
4796 mpi3mr_cleanup_ioc(mrioc);
4797
4798 device_state = pci_choose_state(pdev, state);
4799 ioc_info(mrioc, "pdev=0x%p, slot=%s, entering operating state [D%d]\n",
4800 pdev, pci_name(pdev), device_state);
4801 pci_save_state(pdev);
4802 mpi3mr_cleanup_resources(mrioc);
4803 pci_set_power_state(pdev, device_state);
4804
4805 return 0;
4806 }
4807
4808
4809
4810
4811
4812
4813
4814
4815
4816
4817 static int mpi3mr_resume(struct pci_dev *pdev)
4818 {
4819 struct Scsi_Host *shost = pci_get_drvdata(pdev);
4820 struct mpi3mr_ioc *mrioc;
4821 pci_power_t device_state = pdev->current_state;
4822 int r;
4823
4824 if (!shost)
4825 return 0;
4826
4827 mrioc = shost_priv(shost);
4828
4829 ioc_info(mrioc, "pdev=0x%p, slot=%s, previous operating state [D%d]\n",
4830 pdev, pci_name(pdev), device_state);
4831 pci_set_power_state(pdev, PCI_D0);
4832 pci_enable_wake(pdev, PCI_D0, 0);
4833 pci_restore_state(pdev);
4834 mrioc->pdev = pdev;
4835 mrioc->cpu_count = num_online_cpus();
4836 r = mpi3mr_setup_resources(mrioc);
4837 if (r) {
4838 ioc_info(mrioc, "%s: Setup resources failed[%d]\n",
4839 __func__, r);
4840 return r;
4841 }
4842
4843 mrioc->stop_drv_processing = 0;
4844 mpi3mr_memset_buffers(mrioc);
4845 r = mpi3mr_reinit_ioc(mrioc, 1);
4846 if (r) {
4847 ioc_err(mrioc, "resuming controller failed[%d]\n", r);
4848 return r;
4849 }
4850 scsi_unblock_requests(shost);
4851 mpi3mr_start_watchdog(mrioc);
4852
4853 return 0;
4854 }
4855 #endif
4856
4857 static const struct pci_device_id mpi3mr_pci_id_table[] = {
4858 {
4859 PCI_DEVICE_SUB(MPI3_MFGPAGE_VENDORID_BROADCOM,
4860 MPI3_MFGPAGE_DEVID_SAS4116, PCI_ANY_ID, PCI_ANY_ID)
4861 },
4862 { 0 }
4863 };
4864 MODULE_DEVICE_TABLE(pci, mpi3mr_pci_id_table);
4865
4866 static struct pci_driver mpi3mr_pci_driver = {
4867 .name = MPI3MR_DRIVER_NAME,
4868 .id_table = mpi3mr_pci_id_table,
4869 .probe = mpi3mr_probe,
4870 .remove = mpi3mr_remove,
4871 .shutdown = mpi3mr_shutdown,
4872 #ifdef CONFIG_PM
4873 .suspend = mpi3mr_suspend,
4874 .resume = mpi3mr_resume,
4875 #endif
4876 };
4877
4878 static ssize_t event_counter_show(struct device_driver *dd, char *buf)
4879 {
4880 return sprintf(buf, "%llu\n", atomic64_read(&event_counter));
4881 }
4882 static DRIVER_ATTR_RO(event_counter);
4883
4884 static int __init mpi3mr_init(void)
4885 {
4886 int ret_val;
4887
4888 pr_info("Loading %s version %s\n", MPI3MR_DRIVER_NAME,
4889 MPI3MR_DRIVER_VERSION);
4890
4891 ret_val = pci_register_driver(&mpi3mr_pci_driver);
4892 if (ret_val) {
4893 pr_err("%s failed to load due to pci register driver failure\n",
4894 MPI3MR_DRIVER_NAME);
4895 return ret_val;
4896 }
4897
4898 ret_val = driver_create_file(&mpi3mr_pci_driver.driver,
4899 &driver_attr_event_counter);
4900 if (ret_val)
4901 pci_unregister_driver(&mpi3mr_pci_driver);
4902
4903 return ret_val;
4904 }
4905
4906 static void __exit mpi3mr_exit(void)
4907 {
4908 if (warn_non_secure_ctlr)
4909 pr_warn(
4910 "Unloading %s version %s while managing a non secure controller\n",
4911 MPI3MR_DRIVER_NAME, MPI3MR_DRIVER_VERSION);
4912 else
4913 pr_info("Unloading %s version %s\n", MPI3MR_DRIVER_NAME,
4914 MPI3MR_DRIVER_VERSION);
4915
4916 driver_remove_file(&mpi3mr_pci_driver.driver,
4917 &driver_attr_event_counter);
4918 pci_unregister_driver(&mpi3mr_pci_driver);
4919 }
4920
4921 module_init(mpi3mr_init);
4922 module_exit(mpi3mr_exit);