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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Driver for Broadcom MPI3 Storage Controllers
0004  *
0005  * Copyright (C) 2017-2022 Broadcom Inc.
0006  *  (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
0007  *
0008  */
0009 
0010 #ifndef MPI3MR_H_INCLUDED
0011 #define MPI3MR_H_INCLUDED
0012 
0013 #include <linux/blkdev.h>
0014 #include <linux/blk-mq.h>
0015 #include <linux/blk-mq-pci.h>
0016 #include <linux/delay.h>
0017 #include <linux/dmapool.h>
0018 #include <linux/errno.h>
0019 #include <linux/init.h>
0020 #include <linux/io.h>
0021 #include <linux/interrupt.h>
0022 #include <linux/kernel.h>
0023 #include <linux/miscdevice.h>
0024 #include <linux/module.h>
0025 #include <linux/pci.h>
0026 #include <linux/poll.h>
0027 #include <linux/sched.h>
0028 #include <linux/slab.h>
0029 #include <linux/types.h>
0030 #include <linux/uaccess.h>
0031 #include <linux/utsname.h>
0032 #include <linux/version.h>
0033 #include <linux/workqueue.h>
0034 #include <asm/unaligned.h>
0035 #include <scsi/scsi.h>
0036 #include <scsi/scsi_cmnd.h>
0037 #include <scsi/scsi_dbg.h>
0038 #include <scsi/scsi_device.h>
0039 #include <scsi/scsi_host.h>
0040 #include <scsi/scsi_tcq.h>
0041 #include <uapi/scsi/scsi_bsg_mpi3mr.h>
0042 
0043 #include "mpi/mpi30_transport.h"
0044 #include "mpi/mpi30_cnfg.h"
0045 #include "mpi/mpi30_image.h"
0046 #include "mpi/mpi30_init.h"
0047 #include "mpi/mpi30_ioc.h"
0048 #include "mpi/mpi30_sas.h"
0049 #include "mpi/mpi30_pci.h"
0050 #include "mpi3mr_debug.h"
0051 
0052 /* Global list and lock for storing multiple adapters managed by the driver */
0053 extern spinlock_t mrioc_list_lock;
0054 extern struct list_head mrioc_list;
0055 extern int prot_mask;
0056 extern atomic64_t event_counter;
0057 
0058 #define MPI3MR_DRIVER_VERSION   "8.0.0.69.0"
0059 #define MPI3MR_DRIVER_RELDATE   "16-March-2022"
0060 
0061 #define MPI3MR_DRIVER_NAME  "mpi3mr"
0062 #define MPI3MR_DRIVER_LICENSE   "GPL"
0063 #define MPI3MR_DRIVER_AUTHOR    "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>"
0064 #define MPI3MR_DRIVER_DESC  "MPI3 Storage Controller Device Driver"
0065 
0066 #define MPI3MR_NAME_LENGTH  32
0067 #define IOCNAME         "%s: "
0068 
0069 #define MPI3MR_MAX_SECTORS  2048
0070 
0071 /* Definitions for internal SGL and Chain SGL buffers */
0072 #define MPI3MR_PAGE_SIZE_4K     4096
0073 #define MPI3MR_SG_DEPTH     (MPI3MR_PAGE_SIZE_4K / sizeof(struct mpi3_sge_common))
0074 
0075 /* Definitions for MAX values for shost */
0076 #define MPI3MR_MAX_CMDS_LUN 128
0077 #define MPI3MR_MAX_CDB_LENGTH   32
0078 
0079 /* Admin queue management definitions */
0080 #define MPI3MR_ADMIN_REQ_Q_SIZE     (2 * MPI3MR_PAGE_SIZE_4K)
0081 #define MPI3MR_ADMIN_REPLY_Q_SIZE   (4 * MPI3MR_PAGE_SIZE_4K)
0082 #define MPI3MR_ADMIN_REQ_FRAME_SZ   128
0083 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16
0084 
0085 /* Operational queue management definitions */
0086 #define MPI3MR_OP_REQ_Q_QD      512
0087 #define MPI3MR_OP_REP_Q_QD      1024
0088 #define MPI3MR_OP_REP_Q_QD4K        4096
0089 #define MPI3MR_OP_REQ_Q_SEG_SIZE    4096
0090 #define MPI3MR_OP_REP_Q_SEG_SIZE    4096
0091 #define MPI3MR_MAX_SEG_LIST_SIZE    4096
0092 
0093 /* Reserved Host Tag definitions */
0094 #define MPI3MR_HOSTTAG_INVALID      0xFFFF
0095 #define MPI3MR_HOSTTAG_INITCMDS     1
0096 #define MPI3MR_HOSTTAG_BSG_CMDS     2
0097 #define MPI3MR_HOSTTAG_PEL_ABORT    3
0098 #define MPI3MR_HOSTTAG_PEL_WAIT     4
0099 #define MPI3MR_HOSTTAG_BLK_TMS      5
0100 
0101 #define MPI3MR_NUM_DEVRMCMD     16
0102 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_BLK_TMS + 1)
0103 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \
0104                         MPI3MR_NUM_DEVRMCMD - 1)
0105 
0106 #define MPI3MR_INTERNAL_CMDS_RESVD  MPI3MR_HOSTTAG_DEVRMCMD_MAX
0107 #define MPI3MR_NUM_EVTACKCMD        4
0108 #define MPI3MR_HOSTTAG_EVTACKCMD_MIN    (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1)
0109 #define MPI3MR_HOSTTAG_EVTACKCMD_MAX    (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \
0110                     MPI3MR_NUM_EVTACKCMD - 1)
0111 
0112 /* Reduced resource count definition for crash kernel */
0113 #define MPI3MR_HOST_IOS_KDUMP       128
0114 
0115 /* command/controller interaction timeout definitions in seconds */
0116 #define MPI3MR_INTADMCMD_TIMEOUT        60
0117 #define MPI3MR_PORTENABLE_TIMEOUT       300
0118 #define MPI3MR_ABORTTM_TIMEOUT          60
0119 #define MPI3MR_RESETTM_TIMEOUT          60
0120 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT    5
0121 #define MPI3MR_TSUPDATE_INTERVAL        900
0122 #define MPI3MR_DEFAULT_SHUTDOWN_TIME        120
0123 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT    180
0124 #define MPI3MR_PREPARE_FOR_RESET_TIMEOUT    180
0125 #define MPI3MR_RESET_ACK_TIMEOUT        30
0126 
0127 #define MPI3MR_WATCHDOG_INTERVAL        1000 /* in milli seconds */
0128 
0129 #define MPI3MR_SCMD_TIMEOUT    (60 * HZ)
0130 #define MPI3MR_EH_SCMD_TIMEOUT (60 * HZ)
0131 
0132 /* Internal admin command state definitions*/
0133 #define MPI3MR_CMD_NOTUSED  0x8000
0134 #define MPI3MR_CMD_COMPLETE 0x0001
0135 #define MPI3MR_CMD_PENDING  0x0002
0136 #define MPI3MR_CMD_REPLY_VALID  0x0004
0137 #define MPI3MR_CMD_RESET    0x0008
0138 
0139 /* Definitions for Event replies and sense buffer allocated per controller */
0140 #define MPI3MR_NUM_EVT_REPLIES  64
0141 #define MPI3MR_SENSE_BUF_SZ 256
0142 #define MPI3MR_SENSEBUF_FACTOR  3
0143 #define MPI3MR_CHAINBUF_FACTOR  3
0144 #define MPI3MR_CHAINBUFDIX_FACTOR   2
0145 
0146 /* Invalid target device handle */
0147 #define MPI3MR_INVALID_DEV_HANDLE   0xFFFF
0148 
0149 /* Controller Reset related definitions */
0150 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT  5
0151 #define MPI3MR_MAX_RESET_RETRY_COUNT        3
0152 
0153 /* ResponseCode definitions */
0154 #define MPI3MR_RI_MASK_RESPCODE     (0x000000FF)
0155 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \
0156             MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC
0157 
0158 #define MPI3MR_DEFAULT_MDTS (128 * 1024)
0159 #define MPI3MR_DEFAULT_PGSZEXP         (12)
0160 
0161 /* Command retry count definitions */
0162 #define MPI3MR_DEV_RMHS_RETRY_COUNT 3
0163 #define MPI3MR_PEL_RETRY_COUNT 3
0164 
0165 /* Default target device queue depth */
0166 #define MPI3MR_DEFAULT_SDEV_QD  32
0167 
0168 /* Definitions for Threaded IRQ poll*/
0169 #define MPI3MR_IRQ_POLL_SLEEP           2
0170 #define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT     8
0171 
0172 /* Definitions for the controller security status*/
0173 #define MPI3MR_CTLR_SECURITY_STATUS_MASK    0x0C
0174 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK  0x02
0175 
0176 #define MPI3MR_INVALID_DEVICE           0x00
0177 #define MPI3MR_CONFIG_SECURE_DEVICE     0x04
0178 #define MPI3MR_HARD_SECURE_DEVICE       0x08
0179 #define MPI3MR_TAMPERED_DEVICE          0x0C
0180 
0181 /* SGE Flag definition */
0182 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \
0183     (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \
0184     MPI3_SGE_FLAGS_END_OF_LIST)
0185 
0186 /* MSI Index from Reply Queue Index */
0187 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset)   (qidx + offset)
0188 
0189 /*
0190  * Maximum data transfer size definitions for management
0191  * application commands
0192  */
0193 #define MPI3MR_MAX_APP_XFER_SIZE    (1 * 1024 * 1024)
0194 #define MPI3MR_MAX_APP_XFER_SEGMENTS    512
0195 /*
0196  * 2048 sectors are for data buffers and additional 512 sectors for
0197  * other buffers
0198  */
0199 #define MPI3MR_MAX_APP_XFER_SECTORS (2048 + 512)
0200 
0201 /**
0202  * struct mpi3mr_nvme_pt_sge -  Structure to store SGEs for NVMe
0203  * Encapsulated commands.
0204  *
0205  * @base_addr: Physical address
0206  * @length: SGE length
0207  * @rsvd: Reserved
0208  * @rsvd1: Reserved
0209  * @sgl_type: sgl type
0210  */
0211 struct mpi3mr_nvme_pt_sge {
0212     u64 base_addr;
0213     u32 length;
0214     u16 rsvd;
0215     u8 rsvd1;
0216     u8 sgl_type;
0217 };
0218 
0219 /**
0220  * struct mpi3mr_buf_map -  local structure to
0221  * track kernel and user buffers associated with an BSG
0222  * structure.
0223  *
0224  * @bsg_buf: BSG buffer virtual address
0225  * @bsg_buf_len:  BSG buffer length
0226  * @kern_buf: Kernel buffer virtual address
0227  * @kern_buf_len: Kernel buffer length
0228  * @kern_buf_dma: Kernel buffer DMA address
0229  * @data_dir: Data direction.
0230  */
0231 struct mpi3mr_buf_map {
0232     void *bsg_buf;
0233     u32 bsg_buf_len;
0234     void *kern_buf;
0235     u32 kern_buf_len;
0236     dma_addr_t kern_buf_dma;
0237     u8 data_dir;
0238 };
0239 
0240 /* IOC State definitions */
0241 enum mpi3mr_iocstate {
0242     MRIOC_STATE_READY = 1,
0243     MRIOC_STATE_RESET,
0244     MRIOC_STATE_FAULT,
0245     MRIOC_STATE_BECOMING_READY,
0246     MRIOC_STATE_RESET_REQUESTED,
0247     MRIOC_STATE_UNRECOVERABLE,
0248 };
0249 
0250 /* Reset reason code definitions*/
0251 enum mpi3mr_reset_reason {
0252     MPI3MR_RESET_FROM_BRINGUP = 1,
0253     MPI3MR_RESET_FROM_FAULT_WATCH = 2,
0254     MPI3MR_RESET_FROM_APP = 3,
0255     MPI3MR_RESET_FROM_EH_HOS = 4,
0256     MPI3MR_RESET_FROM_TM_TIMEOUT = 5,
0257     MPI3MR_RESET_FROM_APP_TIMEOUT = 6,
0258     MPI3MR_RESET_FROM_MUR_FAILURE = 7,
0259     MPI3MR_RESET_FROM_CTLR_CLEANUP = 8,
0260     MPI3MR_RESET_FROM_CIACTIV_FAULT = 9,
0261     MPI3MR_RESET_FROM_PE_TIMEOUT = 10,
0262     MPI3MR_RESET_FROM_TSU_TIMEOUT = 11,
0263     MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12,
0264     MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13,
0265     MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14,
0266     MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15,
0267     MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16,
0268     MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17,
0269     MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18,
0270     MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19,
0271     MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20,
0272     MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21,
0273     MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22,
0274     MPI3MR_RESET_FROM_SYSFS = 23,
0275     MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24,
0276     MPI3MR_RESET_FROM_FIRMWARE = 27,
0277 };
0278 
0279 /* Queue type definitions */
0280 enum queue_type {
0281     MPI3MR_DEFAULT_QUEUE = 0,
0282     MPI3MR_POLL_QUEUE,
0283 };
0284 
0285 /**
0286  * struct mpi3mr_compimg_ver - replica of component image
0287  * version defined in mpi30_image.h in host endianness
0288  *
0289  */
0290 struct mpi3mr_compimg_ver {
0291     u16 build_num;
0292     u16 cust_id;
0293     u8 ph_minor;
0294     u8 ph_major;
0295     u8 gen_minor;
0296     u8 gen_major;
0297 };
0298 
0299 /**
0300  * struct mpi3mr_ioc_facs - replica of component image version
0301  * defined in mpi30_ioc.h in host endianness
0302  *
0303  */
0304 struct mpi3mr_ioc_facts {
0305     u32 ioc_capabilities;
0306     struct mpi3mr_compimg_ver fw_ver;
0307     u32 mpi_version;
0308     u16 max_reqs;
0309     u16 product_id;
0310     u16 op_req_sz;
0311     u16 reply_sz;
0312     u16 exceptions;
0313     u16 max_perids;
0314     u16 max_pds;
0315     u16 max_sasexpanders;
0316     u16 max_sasinitiators;
0317     u16 max_enclosures;
0318     u16 max_pcie_switches;
0319     u16 max_nvme;
0320     u16 max_vds;
0321     u16 max_hpds;
0322     u16 max_advhpds;
0323     u16 max_raid_pds;
0324     u16 min_devhandle;
0325     u16 max_devhandle;
0326     u16 max_op_req_q;
0327     u16 max_op_reply_q;
0328     u16 shutdown_timeout;
0329     u8 ioc_num;
0330     u8 who_init;
0331     u16 max_msix_vectors;
0332     u8 personality;
0333     u8 dma_mask;
0334     u8 protocol_flags;
0335     u8 sge_mod_mask;
0336     u8 sge_mod_value;
0337     u8 sge_mod_shift;
0338     u8 max_dev_per_tg;
0339     u16 max_io_throttle_group;
0340     u16 io_throttle_data_length;
0341     u16 io_throttle_low;
0342     u16 io_throttle_high;
0343 
0344 };
0345 
0346 /**
0347  * struct segments - memory descriptor structure to store
0348  * virtual and dma addresses for operational queue segments.
0349  *
0350  * @segment: virtual address
0351  * @segment_dma: dma address
0352  */
0353 struct segments {
0354     void *segment;
0355     dma_addr_t segment_dma;
0356 };
0357 
0358 /**
0359  * struct op_req_qinfo -  Operational Request Queue Information
0360  *
0361  * @ci: consumer index
0362  * @pi: producer index
0363  * @num_request: Maximum number of entries in the queue
0364  * @qid: Queue Id starting from 1
0365  * @reply_qid: Associated reply queue Id
0366  * @num_segments: Number of discontiguous memory segments
0367  * @segment_qd: Depth of each segments
0368  * @q_lock: Concurrent queue access lock
0369  * @q_segments: Segment descriptor pointer
0370  * @q_segment_list: Segment list base virtual address
0371  * @q_segment_list_dma: Segment list base DMA address
0372  */
0373 struct op_req_qinfo {
0374     u16 ci;
0375     u16 pi;
0376     u16 num_requests;
0377     u16 qid;
0378     u16 reply_qid;
0379     u16 num_segments;
0380     u16 segment_qd;
0381     spinlock_t q_lock;
0382     struct segments *q_segments;
0383     void *q_segment_list;
0384     dma_addr_t q_segment_list_dma;
0385 };
0386 
0387 /**
0388  * struct op_reply_qinfo -  Operational Reply Queue Information
0389  *
0390  * @ci: consumer index
0391  * @qid: Queue Id starting from 1
0392  * @num_replies: Maximum number of entries in the queue
0393  * @num_segments: Number of discontiguous memory segments
0394  * @segment_qd: Depth of each segments
0395  * @q_segments: Segment descriptor pointer
0396  * @q_segment_list: Segment list base virtual address
0397  * @q_segment_list_dma: Segment list base DMA address
0398  * @ephase: Expected phased identifier for the reply queue
0399  * @pend_ios: Number of IOs pending in HW for this queue
0400  * @enable_irq_poll: Flag to indicate polling is enabled
0401  * @in_use: Queue is handled by poll/ISR
0402  * @qtype: Type of queue (types defined in enum queue_type)
0403  */
0404 struct op_reply_qinfo {
0405     u16 ci;
0406     u16 qid;
0407     u16 num_replies;
0408     u16 num_segments;
0409     u16 segment_qd;
0410     struct segments *q_segments;
0411     void *q_segment_list;
0412     dma_addr_t q_segment_list_dma;
0413     u8 ephase;
0414     atomic_t pend_ios;
0415     bool enable_irq_poll;
0416     atomic_t in_use;
0417     enum queue_type qtype;
0418 };
0419 
0420 /**
0421  * struct mpi3mr_intr_info -  Interrupt cookie information
0422  *
0423  * @mrioc: Adapter instance reference
0424  * @msix_index: MSIx index
0425  * @op_reply_q: Associated operational reply queue
0426  * @name: Dev name for the irq claiming device
0427  */
0428 struct mpi3mr_intr_info {
0429     struct mpi3mr_ioc *mrioc;
0430     u16 msix_index;
0431     struct op_reply_qinfo *op_reply_q;
0432     char name[MPI3MR_NAME_LENGTH];
0433 };
0434 
0435 /**
0436  * struct mpi3mr_throttle_group_info - Throttle group info
0437  *
0438  * @io_divert: Flag indicates io divert is on or off for the TG
0439  * @need_qd_reduction: Flag to indicate QD reduction is needed
0440  * @qd_reduction: Queue Depth reduction in units of 10%
0441  * @fw_qd: QueueDepth value reported by the firmware
0442  * @modified_qd: Modified QueueDepth value due to throttling
0443  * @id: Throttle Group ID.
0444  * @high: High limit to turn on throttling in 512 byte blocks
0445  * @low: Low limit to turn off throttling in 512 byte blocks
0446  * @pend_large_data_sz: Counter to track pending large data
0447  */
0448 struct mpi3mr_throttle_group_info {
0449     u8 io_divert;
0450     u8 need_qd_reduction;
0451     u8 qd_reduction;
0452     u16 fw_qd;
0453     u16 modified_qd;
0454     u16 id;
0455     u32 high;
0456     u32 low;
0457     atomic_t pend_large_data_sz;
0458 };
0459 
0460 /**
0461  * struct tgt_dev_sas_sata - SAS/SATA device specific
0462  * information cached from firmware given data
0463  *
0464  * @sas_address: World wide unique SAS address
0465  * @dev_info: Device information bits
0466  */
0467 struct tgt_dev_sas_sata {
0468     u64 sas_address;
0469     u16 dev_info;
0470 };
0471 
0472 /**
0473  * struct tgt_dev_pcie - PCIe device specific information cached
0474  * from firmware given data
0475  *
0476  * @mdts: Maximum data transfer size
0477  * @capb: Device capabilities
0478  * @pgsz: Device page size
0479  * @abort_to: Timeout for abort TM
0480  * @reset_to: Timeout for Target/LUN reset TM
0481  * @dev_info: Device information bits
0482  */
0483 struct tgt_dev_pcie {
0484     u32 mdts;
0485     u16 capb;
0486     u8 pgsz;
0487     u8 abort_to;
0488     u8 reset_to;
0489     u16 dev_info;
0490 };
0491 
0492 /**
0493  * struct tgt_dev_vd - virtual device specific information
0494  * cached from firmware given data
0495  *
0496  * @state: State of the VD
0497  * @tg_qd_reduction: Queue Depth reduction in units of 10%
0498  * @tg_id: VDs throttle group ID
0499  * @high: High limit to turn on throttling in 512 byte blocks
0500  * @low: Low limit to turn off throttling in 512 byte blocks
0501  * @tg: Pointer to throttle group info
0502  */
0503 struct tgt_dev_vd {
0504     u8 state;
0505     u8 tg_qd_reduction;
0506     u16 tg_id;
0507     u32 tg_high;
0508     u32 tg_low;
0509     struct mpi3mr_throttle_group_info *tg;
0510 };
0511 
0512 
0513 /**
0514  * union _form_spec_inf - union of device specific information
0515  */
0516 union _form_spec_inf {
0517     struct tgt_dev_sas_sata sas_sata_inf;
0518     struct tgt_dev_pcie pcie_inf;
0519     struct tgt_dev_vd vd_inf;
0520 };
0521 
0522 
0523 
0524 /**
0525  * struct mpi3mr_tgt_dev - target device data structure
0526  *
0527  * @list: List pointer
0528  * @starget: Scsi_target pointer
0529  * @dev_handle: FW device handle
0530  * @parent_handle: FW parent device handle
0531  * @slot: Slot number
0532  * @encl_handle: FW enclosure handle
0533  * @perst_id: FW assigned Persistent ID
0534  * @dev_type: SAS/SATA/PCIE device type
0535  * @is_hidden: Should be exposed to upper layers or not
0536  * @host_exposed: Already exposed to host or not
0537  * @io_throttle_enabled: I/O throttling needed or not
0538  * @q_depth: Device specific Queue Depth
0539  * @wwid: World wide ID
0540  * @dev_spec: Device type specific information
0541  * @ref_count: Reference count
0542  */
0543 struct mpi3mr_tgt_dev {
0544     struct list_head list;
0545     struct scsi_target *starget;
0546     u16 dev_handle;
0547     u16 parent_handle;
0548     u16 slot;
0549     u16 encl_handle;
0550     u16 perst_id;
0551     u8 dev_type;
0552     u8 is_hidden;
0553     u8 host_exposed;
0554     u8 io_throttle_enabled;
0555     u16 q_depth;
0556     u64 wwid;
0557     union _form_spec_inf dev_spec;
0558     struct kref ref_count;
0559 };
0560 
0561 /**
0562  * mpi3mr_tgtdev_get - k reference incrementor
0563  * @s: Target device reference
0564  *
0565  * Increment target device reference count.
0566  */
0567 static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s)
0568 {
0569     kref_get(&s->ref_count);
0570 }
0571 
0572 /**
0573  * mpi3mr_free_tgtdev - target device memory dealloctor
0574  * @r: k reference pointer of the target device
0575  *
0576  * Free target device memory when no reference.
0577  */
0578 static inline void mpi3mr_free_tgtdev(struct kref *r)
0579 {
0580     kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count));
0581 }
0582 
0583 /**
0584  * mpi3mr_tgtdev_put - k reference decrementor
0585  * @s: Target device reference
0586  *
0587  * Decrement target device reference count.
0588  */
0589 static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s)
0590 {
0591     kref_put(&s->ref_count, mpi3mr_free_tgtdev);
0592 }
0593 
0594 
0595 /**
0596  * struct mpi3mr_stgt_priv_data - SCSI target private structure
0597  *
0598  * @starget: Scsi_target pointer
0599  * @dev_handle: FW device handle
0600  * @perst_id: FW assigned Persistent ID
0601  * @num_luns: Number of Logical Units
0602  * @block_io: I/O blocked to the device or not
0603  * @dev_removed: Device removed in the Firmware
0604  * @dev_removedelay: Device is waiting to be removed in FW
0605  * @dev_type: Device type
0606  * @io_throttle_enabled: I/O throttling needed or not
0607  * @io_divert: Flag indicates io divert is on or off for the dev
0608  * @throttle_group: Pointer to throttle group info
0609  * @tgt_dev: Internal target device pointer
0610  * @pend_count: Counter to track pending I/Os during error
0611  *      handling
0612  */
0613 struct mpi3mr_stgt_priv_data {
0614     struct scsi_target *starget;
0615     u16 dev_handle;
0616     u16 perst_id;
0617     u32 num_luns;
0618     atomic_t block_io;
0619     u8 dev_removed;
0620     u8 dev_removedelay;
0621     u8 dev_type;
0622     u8 io_throttle_enabled;
0623     u8 io_divert;
0624     struct mpi3mr_throttle_group_info *throttle_group;
0625     struct mpi3mr_tgt_dev *tgt_dev;
0626     u32 pend_count;
0627 };
0628 
0629 /**
0630  * struct mpi3mr_stgt_priv_data - SCSI device private structure
0631  *
0632  * @tgt_priv_data: Scsi_target private data pointer
0633  * @lun_id: LUN ID of the device
0634  * @ncq_prio_enable: NCQ priority enable for SATA device
0635  * @pend_count: Counter to track pending I/Os during error
0636  *      handling
0637  */
0638 struct mpi3mr_sdev_priv_data {
0639     struct mpi3mr_stgt_priv_data *tgt_priv_data;
0640     u32 lun_id;
0641     u8 ncq_prio_enable;
0642     u32 pend_count;
0643 };
0644 
0645 /**
0646  * struct mpi3mr_drv_cmd - Internal command tracker
0647  *
0648  * @mutex: Command mutex
0649  * @done: Completeor for wakeup
0650  * @reply: Firmware reply for internal commands
0651  * @sensebuf: Sensebuf for SCSI IO commands
0652  * @iou_rc: IO Unit control reason code
0653  * @state: Command State
0654  * @dev_handle: Firmware handle for device specific commands
0655  * @ioc_status: IOC status from the firmware
0656  * @ioc_loginfo:IOC log info from the firmware
0657  * @is_waiting: Is the command issued in block mode
0658  * @is_sense: Is Sense data present
0659  * @retry_count: Retry count for retriable commands
0660  * @host_tag: Host tag used by the command
0661  * @callback: Callback for non blocking commands
0662  */
0663 struct mpi3mr_drv_cmd {
0664     struct mutex mutex;
0665     struct completion done;
0666     void *reply;
0667     u8 *sensebuf;
0668     u8 iou_rc;
0669     u16 state;
0670     u16 dev_handle;
0671     u16 ioc_status;
0672     u32 ioc_loginfo;
0673     u8 is_waiting;
0674     u8 is_sense;
0675     u8 retry_count;
0676     u16 host_tag;
0677 
0678     void (*callback)(struct mpi3mr_ioc *mrioc,
0679         struct mpi3mr_drv_cmd *drv_cmd);
0680 };
0681 
0682 
0683 /**
0684  * struct chain_element - memory descriptor structure to store
0685  * virtual and dma addresses for chain elements.
0686  *
0687  * @addr: virtual address
0688  * @dma_addr: dma address
0689  */
0690 struct chain_element {
0691     void *addr;
0692     dma_addr_t dma_addr;
0693 };
0694 
0695 /**
0696  * struct scmd_priv - SCSI command private data
0697  *
0698  * @host_tag: Host tag specific to operational queue
0699  * @in_lld_scope: Command in LLD scope or not
0700  * @meta_sg_valid: DIX command with meta data SGL or not
0701  * @scmd: SCSI Command pointer
0702  * @req_q_idx: Operational request queue index
0703  * @chain_idx: Chain frame index
0704  * @meta_chain_idx: Chain frame index of meta data SGL
0705  * @mpi3mr_scsiio_req: MPI SCSI IO request
0706  */
0707 struct scmd_priv {
0708     u16 host_tag;
0709     u8 in_lld_scope;
0710     u8 meta_sg_valid;
0711     struct scsi_cmnd *scmd;
0712     u16 req_q_idx;
0713     int chain_idx;
0714     int meta_chain_idx;
0715     u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ];
0716 };
0717 
0718 /**
0719  * struct mpi3mr_ioc - Adapter anchor structure stored in shost
0720  * private data
0721  *
0722  * @list: List pointer
0723  * @pdev: PCI device pointer
0724  * @shost: Scsi_Host pointer
0725  * @id: Controller ID
0726  * @cpu_count: Number of online CPUs
0727  * @irqpoll_sleep: usleep unit used in threaded isr irqpoll
0728  * @name: Controller ASCII name
0729  * @driver_name: Driver ASCII name
0730  * @sysif_regs: System interface registers virtual address
0731  * @sysif_regs_phys: System interface registers physical address
0732  * @bars: PCI BARS
0733  * @dma_mask: DMA mask
0734  * @msix_count: Number of MSIX vectors used
0735  * @intr_enabled: Is interrupts enabled
0736  * @num_admin_req: Number of admin requests
0737  * @admin_req_q_sz: Admin request queue size
0738  * @admin_req_pi: Admin request queue producer index
0739  * @admin_req_ci: Admin request queue consumer index
0740  * @admin_req_base: Admin request queue base virtual address
0741  * @admin_req_dma: Admin request queue base dma address
0742  * @admin_req_lock: Admin queue access lock
0743  * @num_admin_replies: Number of admin replies
0744  * @admin_reply_q_sz: Admin reply queue size
0745  * @admin_reply_ci: Admin reply queue consumer index
0746  * @admin_reply_ephase:Admin reply queue expected phase
0747  * @admin_reply_base: Admin reply queue base virtual address
0748  * @admin_reply_dma: Admin reply queue base dma address
0749  * @ready_timeout: Controller ready timeout
0750  * @intr_info: Interrupt cookie pointer
0751  * @intr_info_count: Number of interrupt cookies
0752  * @is_intr_info_set: Flag to indicate intr info is setup
0753  * @num_queues: Number of operational queues
0754  * @num_op_req_q: Number of operational request queues
0755  * @req_qinfo: Operational request queue info pointer
0756  * @num_op_reply_q: Number of operational reply queues
0757  * @op_reply_qinfo: Operational reply queue info pointer
0758  * @init_cmds: Command tracker for initialization commands
0759  * @facts: Cached IOC facts data
0760  * @op_reply_desc_sz: Operational reply descriptor size
0761  * @num_reply_bufs: Number of reply buffers allocated
0762  * @reply_buf_pool: Reply buffer pool
0763  * @reply_buf: Reply buffer base virtual address
0764  * @reply_buf_dma: Reply buffer DMA address
0765  * @reply_buf_dma_max_address: Reply DMA address max limit
0766  * @reply_free_qsz: Reply free queue size
0767  * @reply_free_q_pool: Reply free queue pool
0768  * @reply_free_q: Reply free queue base virtual address
0769  * @reply_free_q_dma: Reply free queue base DMA address
0770  * @reply_free_queue_lock: Reply free queue lock
0771  * @reply_free_queue_host_index: Reply free queue host index
0772  * @num_sense_bufs: Number of sense buffers
0773  * @sense_buf_pool: Sense buffer pool
0774  * @sense_buf: Sense buffer base virtual address
0775  * @sense_buf_dma: Sense buffer base DMA address
0776  * @sense_buf_q_sz: Sense buffer queue size
0777  * @sense_buf_q_pool: Sense buffer queue pool
0778  * @sense_buf_q: Sense buffer queue virtual address
0779  * @sense_buf_q_dma: Sense buffer queue DMA address
0780  * @sbq_lock: Sense buffer queue lock
0781  * @sbq_host_index: Sense buffer queuehost index
0782  * @event_masks: Event mask bitmap
0783  * @fwevt_worker_name: Firmware event worker thread name
0784  * @fwevt_worker_thread: Firmware event worker thread
0785  * @fwevt_lock: Firmware event lock
0786  * @fwevt_list: Firmware event list
0787  * @watchdog_work_q_name: Fault watchdog worker thread name
0788  * @watchdog_work_q: Fault watchdog worker thread
0789  * @watchdog_work: Fault watchdog work
0790  * @watchdog_lock: Fault watchdog lock
0791  * @is_driver_loading: Is driver still loading
0792  * @scan_started: Async scan started
0793  * @scan_failed: Asycn scan failed
0794  * @stop_drv_processing: Stop all command processing
0795  * @max_host_ios: Maximum host I/O count
0796  * @chain_buf_count: Chain buffer count
0797  * @chain_buf_pool: Chain buffer pool
0798  * @chain_sgl_list: Chain SGL list
0799  * @chain_bitmap_sz: Chain buffer allocator bitmap size
0800  * @chain_bitmap: Chain buffer allocator bitmap
0801  * @chain_buf_lock: Chain buffer list lock
0802  * @bsg_cmds: Command tracker for BSG command
0803  * @host_tm_cmds: Command tracker for task management commands
0804  * @dev_rmhs_cmds: Command tracker for device removal commands
0805  * @evtack_cmds: Command tracker for event ack commands
0806  * @devrem_bitmap_sz: Device removal bitmap size
0807  * @devrem_bitmap: Device removal bitmap
0808  * @dev_handle_bitmap_sz: Device handle bitmap size
0809  * @removepend_bitmap: Remove pending bitmap
0810  * @delayed_rmhs_list: Delayed device removal list
0811  * @evtack_cmds_bitmap_sz: Event Ack bitmap size
0812  * @evtack_cmds_bitmap: Event Ack bitmap
0813  * @delayed_evtack_cmds_list: Delayed event acknowledgment list
0814  * @ts_update_counter: Timestamp update counter
0815  * @reset_in_progress: Reset in progress flag
0816  * @unrecoverable: Controller unrecoverable flag
0817  * @prev_reset_result: Result of previous reset
0818  * @reset_mutex: Controller reset mutex
0819  * @reset_waitq: Controller reset  wait queue
0820  * @prepare_for_reset: Prepare for reset event received
0821  * @prepare_for_reset_timeout_counter: Prepare for reset timeout
0822  * @prp_list_virt: NVMe encapsulated PRP list virtual base
0823  * @prp_list_dma: NVMe encapsulated PRP list DMA
0824  * @prp_sz: NVME encapsulated PRP list size
0825  * @diagsave_timeout: Diagnostic information save timeout
0826  * @logging_level: Controller debug logging level
0827  * @flush_io_count: I/O count to flush after reset
0828  * @current_event: Firmware event currently in process
0829  * @driver_info: Driver, Kernel, OS information to firmware
0830  * @change_count: Topology change count
0831  * @pel_enabled: Persistent Event Log(PEL) enabled or not
0832  * @pel_abort_requested: PEL abort is requested or not
0833  * @pel_class: PEL Class identifier
0834  * @pel_locale: PEL Locale identifier
0835  * @pel_cmds: Command tracker for PEL wait command
0836  * @pel_abort_cmd: Command tracker for PEL abort command
0837  * @pel_newest_seqnum: Newest PEL sequenece number
0838  * @pel_seqnum_virt: PEL sequence number virtual address
0839  * @pel_seqnum_dma: PEL sequence number DMA address
0840  * @pel_seqnum_sz: PEL sequenece number size
0841  * @op_reply_q_offset: Operational reply queue offset with MSIx
0842  * @default_qcount: Total Default queues
0843  * @active_poll_qcount: Currently active poll queue count
0844  * @requested_poll_qcount: User requested poll queue count
0845  * @bsg_dev: BSG device structure
0846  * @bsg_queue: Request queue for BSG device
0847  * @stop_bsgs: Stop BSG request flag
0848  * @logdata_buf: Circular buffer to store log data entries
0849  * @logdata_buf_idx: Index of entry in buffer to store
0850  * @logdata_entry_sz: log data entry size
0851  * @pend_large_data_sz: Counter to track pending large data
0852  * @io_throttle_data_length: I/O size to track in 512b blocks
0853  * @io_throttle_high: I/O size to start throttle in 512b blocks
0854  * @io_throttle_low: I/O size to stop throttle in 512b blocks
0855  * @num_io_throttle_group: Maximum number of throttle groups
0856  * @throttle_groups: Pointer to throttle group info structures
0857  */
0858 struct mpi3mr_ioc {
0859     struct list_head list;
0860     struct pci_dev *pdev;
0861     struct Scsi_Host *shost;
0862     u8 id;
0863     int cpu_count;
0864     bool enable_segqueue;
0865     u32 irqpoll_sleep;
0866 
0867     char name[MPI3MR_NAME_LENGTH];
0868     char driver_name[MPI3MR_NAME_LENGTH];
0869 
0870     volatile struct mpi3_sysif_registers __iomem *sysif_regs;
0871     resource_size_t sysif_regs_phys;
0872     int bars;
0873     u64 dma_mask;
0874 
0875     u16 msix_count;
0876     u8 intr_enabled;
0877 
0878     u16 num_admin_req;
0879     u32 admin_req_q_sz;
0880     u16 admin_req_pi;
0881     u16 admin_req_ci;
0882     void *admin_req_base;
0883     dma_addr_t admin_req_dma;
0884     spinlock_t admin_req_lock;
0885 
0886     u16 num_admin_replies;
0887     u32 admin_reply_q_sz;
0888     u16 admin_reply_ci;
0889     u8 admin_reply_ephase;
0890     void *admin_reply_base;
0891     dma_addr_t admin_reply_dma;
0892 
0893     u32 ready_timeout;
0894 
0895     struct mpi3mr_intr_info *intr_info;
0896     u16 intr_info_count;
0897     bool is_intr_info_set;
0898 
0899     u16 num_queues;
0900     u16 num_op_req_q;
0901     struct op_req_qinfo *req_qinfo;
0902 
0903     u16 num_op_reply_q;
0904     struct op_reply_qinfo *op_reply_qinfo;
0905 
0906     struct mpi3mr_drv_cmd init_cmds;
0907     struct mpi3mr_ioc_facts facts;
0908     u16 op_reply_desc_sz;
0909 
0910     u32 num_reply_bufs;
0911     struct dma_pool *reply_buf_pool;
0912     u8 *reply_buf;
0913     dma_addr_t reply_buf_dma;
0914     dma_addr_t reply_buf_dma_max_address;
0915 
0916     u16 reply_free_qsz;
0917     u16 reply_sz;
0918     struct dma_pool *reply_free_q_pool;
0919     __le64 *reply_free_q;
0920     dma_addr_t reply_free_q_dma;
0921     spinlock_t reply_free_queue_lock;
0922     u32 reply_free_queue_host_index;
0923 
0924     u32 num_sense_bufs;
0925     struct dma_pool *sense_buf_pool;
0926     u8 *sense_buf;
0927     dma_addr_t sense_buf_dma;
0928 
0929     u16 sense_buf_q_sz;
0930     struct dma_pool *sense_buf_q_pool;
0931     __le64 *sense_buf_q;
0932     dma_addr_t sense_buf_q_dma;
0933     spinlock_t sbq_lock;
0934     u32 sbq_host_index;
0935     u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS];
0936 
0937     char fwevt_worker_name[MPI3MR_NAME_LENGTH];
0938     struct workqueue_struct *fwevt_worker_thread;
0939     spinlock_t fwevt_lock;
0940     struct list_head fwevt_list;
0941 
0942     char watchdog_work_q_name[20];
0943     struct workqueue_struct *watchdog_work_q;
0944     struct delayed_work watchdog_work;
0945     spinlock_t watchdog_lock;
0946 
0947     u8 is_driver_loading;
0948     u8 scan_started;
0949     u16 scan_failed;
0950     u8 stop_drv_processing;
0951 
0952     u16 max_host_ios;
0953     spinlock_t tgtdev_lock;
0954     struct list_head tgtdev_list;
0955 
0956     u32 chain_buf_count;
0957     struct dma_pool *chain_buf_pool;
0958     struct chain_element *chain_sgl_list;
0959     u16  chain_bitmap_sz;
0960     void *chain_bitmap;
0961     spinlock_t chain_buf_lock;
0962 
0963     struct mpi3mr_drv_cmd bsg_cmds;
0964     struct mpi3mr_drv_cmd host_tm_cmds;
0965     struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD];
0966     struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD];
0967     u16 devrem_bitmap_sz;
0968     void *devrem_bitmap;
0969     u16 dev_handle_bitmap_sz;
0970     void *removepend_bitmap;
0971     struct list_head delayed_rmhs_list;
0972     u16 evtack_cmds_bitmap_sz;
0973     void *evtack_cmds_bitmap;
0974     struct list_head delayed_evtack_cmds_list;
0975 
0976     u32 ts_update_counter;
0977     u8 reset_in_progress;
0978     u8 unrecoverable;
0979     int prev_reset_result;
0980     struct mutex reset_mutex;
0981     wait_queue_head_t reset_waitq;
0982 
0983     u8 prepare_for_reset;
0984     u16 prepare_for_reset_timeout_counter;
0985 
0986     void *prp_list_virt;
0987     dma_addr_t prp_list_dma;
0988     u32 prp_sz;
0989 
0990     u16 diagsave_timeout;
0991     int logging_level;
0992     u16 flush_io_count;
0993 
0994     struct mpi3mr_fwevt *current_event;
0995     struct mpi3_driver_info_layout driver_info;
0996     u16 change_count;
0997 
0998     u8 pel_enabled;
0999     u8 pel_abort_requested;
1000     u8 pel_class;
1001     u16 pel_locale;
1002     struct mpi3mr_drv_cmd pel_cmds;
1003     struct mpi3mr_drv_cmd pel_abort_cmd;
1004 
1005     u32 pel_newest_seqnum;
1006     void *pel_seqnum_virt;
1007     dma_addr_t pel_seqnum_dma;
1008     u32 pel_seqnum_sz;
1009 
1010     u16 op_reply_q_offset;
1011     u16 default_qcount;
1012     u16 active_poll_qcount;
1013     u16 requested_poll_qcount;
1014 
1015     struct device bsg_dev;
1016     struct request_queue *bsg_queue;
1017     u8 stop_bsgs;
1018     u8 *logdata_buf;
1019     u16 logdata_buf_idx;
1020     u16 logdata_entry_sz;
1021 
1022     atomic_t pend_large_data_sz;
1023     u32 io_throttle_data_length;
1024     u32 io_throttle_high;
1025     u32 io_throttle_low;
1026     u16 num_io_throttle_group;
1027     struct mpi3mr_throttle_group_info *throttle_groups;
1028 };
1029 
1030 /**
1031  * struct mpi3mr_fwevt - Firmware event structure.
1032  *
1033  * @list: list head
1034  * @work: Work structure
1035  * @mrioc: Adapter instance reference
1036  * @event_id: MPI3 firmware event ID
1037  * @send_ack: Event acknowledgment required or not
1038  * @process_evt: Bottomhalf processing required or not
1039  * @evt_ctx: Event context to send in Ack
1040  * @event_data_size: size of the event data in bytes
1041  * @pending_at_sml: waiting for device add/remove API to complete
1042  * @discard: discard this event
1043  * @ref_count: kref count
1044  * @event_data: Actual MPI3 event data
1045  */
1046 struct mpi3mr_fwevt {
1047     struct list_head list;
1048     struct work_struct work;
1049     struct mpi3mr_ioc *mrioc;
1050     u16 event_id;
1051     bool send_ack;
1052     bool process_evt;
1053     u32 evt_ctx;
1054     u16 event_data_size;
1055     bool pending_at_sml;
1056     bool discard;
1057     struct kref ref_count;
1058     char event_data[] __aligned(4);
1059 };
1060 
1061 
1062 /**
1063  * struct delayed_dev_rmhs_node - Delayed device removal node
1064  *
1065  * @list: list head
1066  * @handle: Device handle
1067  * @iou_rc: IO Unit Control Reason Code
1068  */
1069 struct delayed_dev_rmhs_node {
1070     struct list_head list;
1071     u16 handle;
1072     u8 iou_rc;
1073 };
1074 
1075 /**
1076  * struct delayed_evt_ack_node - Delayed event ack node
1077  * @list: list head
1078  * @event: MPI3 event ID
1079  * @event_ctx: event context
1080  */
1081 struct delayed_evt_ack_node {
1082     struct list_head list;
1083     u8 event;
1084     u32 event_ctx;
1085 };
1086 
1087 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc);
1088 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc);
1089 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc);
1090 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume);
1091 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc);
1092 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async);
1093 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
1094 u16 admin_req_sz, u8 ignore_reset);
1095 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
1096                struct op_req_qinfo *opreqq, u8 *req);
1097 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
1098               dma_addr_t dma_addr);
1099 void mpi3mr_build_zero_len_sge(void *paddr);
1100 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
1101                      dma_addr_t phys_addr);
1102 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
1103                      dma_addr_t phys_addr);
1104 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
1105                      u64 sense_buf_dma);
1106 
1107 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc);
1108 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc);
1109 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc,
1110                  struct mpi3_event_notification_reply *event_reply);
1111 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc,
1112                   struct mpi3_default_reply_descriptor *reply_desc,
1113                   u64 *reply_dma, u16 qidx);
1114 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc);
1115 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc);
1116 
1117 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
1118                   u32 reset_reason, u8 snapdump);
1119 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc);
1120 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc);
1121 
1122 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc);
1123 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
1124               u32 event_ctx);
1125 
1126 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout);
1127 void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc);
1128 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc);
1129 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc);
1130 void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc);
1131 void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc);
1132 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);
1133 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc);
1134 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);
1135 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
1136     struct op_reply_qinfo *op_reply_q);
1137 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num);
1138 void mpi3mr_bsg_init(struct mpi3mr_ioc *mrioc);
1139 void mpi3mr_bsg_exit(struct mpi3mr_ioc *mrioc);
1140 int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type,
1141     u16 handle, uint lun, u16 htag, ulong timeout,
1142     struct mpi3mr_drv_cmd *drv_cmd,
1143     u8 *resp_code, struct scsi_cmnd *scmd);
1144 struct mpi3mr_tgt_dev *mpi3mr_get_tgtdev_by_handle(
1145     struct mpi3mr_ioc *mrioc, u16 handle);
1146 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc,
1147     struct mpi3mr_drv_cmd *drv_cmd);
1148 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc,
1149     struct mpi3mr_drv_cmd *drv_cmd);
1150 void mpi3mr_app_save_logdata(struct mpi3mr_ioc *mrioc, char *event_data,
1151     u16 event_data_size);
1152 extern const struct attribute_group *mpi3mr_host_groups[];
1153 extern const struct attribute_group *mpi3mr_dev_groups[];
1154 #endif /*MPI3MR_H_INCLUDED*/
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