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0006 #ifndef MPI30_TRANSPORT_H
0007 #define MPI30_TRANSPORT_H 1
0008 struct mpi3_version_struct {
0009 u8 dev;
0010 u8 unit;
0011 u8 minor;
0012 u8 major;
0013 };
0014
0015 union mpi3_version_union {
0016 struct mpi3_version_struct mpi3_version;
0017 __le32 word;
0018 };
0019
0020 #define MPI3_VERSION_MAJOR (3)
0021 #define MPI3_VERSION_MINOR (0)
0022 #define MPI3_VERSION_UNIT (23)
0023 #define MPI3_VERSION_DEV (1)
0024 #define MPI3_DEVHANDLE_INVALID (0xffff)
0025 struct mpi3_sysif_oper_queue_indexes {
0026 __le16 producer_index;
0027 __le16 reserved02;
0028 __le16 consumer_index;
0029 __le16 reserved06;
0030 };
0031
0032 struct mpi3_sysif_registers {
0033 __le64 ioc_information;
0034 union mpi3_version_union version;
0035 __le32 reserved0c[2];
0036 __le32 ioc_configuration;
0037 __le32 reserved18;
0038 __le32 ioc_status;
0039 __le32 reserved20;
0040 __le32 admin_queue_num_entries;
0041 __le64 admin_request_queue_address;
0042 __le64 admin_reply_queue_address;
0043 __le32 reserved38[2];
0044 __le32 coalesce_control;
0045 __le32 reserved44[1007];
0046 __le16 admin_request_queue_pi;
0047 __le16 reserved1002;
0048 __le16 admin_reply_queue_ci;
0049 __le16 reserved1006;
0050 struct mpi3_sysif_oper_queue_indexes oper_queue_indexes[383];
0051 __le32 reserved1c00;
0052 __le32 write_sequence;
0053 __le32 host_diagnostic;
0054 __le32 reserved1c0c;
0055 __le32 fault;
0056 __le32 fault_info[3];
0057 __le32 reserved1c20[4];
0058 __le64 hcb_address;
0059 __le32 hcb_size;
0060 __le32 reserved1c3c;
0061 __le32 reply_free_host_index;
0062 __le32 sense_buffer_free_host_index;
0063 __le32 reserved1c48[2];
0064 __le64 diag_rw_data;
0065 __le64 diag_rw_address;
0066 __le16 diag_rw_control;
0067 __le16 diag_rw_status;
0068 __le32 reserved1c64[35];
0069 __le32 scratchpad[4];
0070 __le32 reserved1d00[192];
0071 __le32 device_assigned_registers[2048];
0072 };
0073
0074 #define MPI3_SYSIF_IOC_INFO_LOW_OFFSET (0x00000000)
0075 #define MPI3_SYSIF_IOC_INFO_HIGH_OFFSET (0x00000004)
0076 #define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK (0xff000000)
0077 #define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT (24)
0078 #define MPI3_SYSIF_IOC_INFO_LOW_HCB_DISABLED (0x00000001)
0079 #define MPI3_SYSIF_IOC_CONFIG_OFFSET (0x00000014)
0080 #define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ (0x00f00000)
0081 #define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT (20)
0082 #define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ (0x000f0000)
0083 #define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT (16)
0084 #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_MASK (0x0000c000)
0085 #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NO (0x00000000)
0086 #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL (0x00004000)
0087 #define MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ (0x00002000)
0088 #define MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE (0x00000010)
0089 #define MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC (0x00000001)
0090 #define MPI3_SYSIF_IOC_STATUS_OFFSET (0x0000001c)
0091 #define MPI3_SYSIF_IOC_STATUS_RESET_HISTORY (0x00000010)
0092 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK (0x0000000c)
0093 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_SHIFT (0x00000002)
0094 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_NONE (0x00000000)
0095 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS (0x00000004)
0096 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE (0x00000008)
0097 #define MPI3_SYSIF_IOC_STATUS_FAULT (0x00000002)
0098 #define MPI3_SYSIF_IOC_STATUS_READY (0x00000001)
0099 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_OFFSET (0x00000024)
0100 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REQ_MASK (0x0fff)
0101 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_OFFSET (0x00000026)
0102 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_MASK (0x0fff0000)
0103 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_SHIFT (16)
0104 #define MPI3_SYSIF_ADMIN_REQ_Q_ADDR_LOW_OFFSET (0x00000028)
0105 #define MPI3_SYSIF_ADMIN_REQ_Q_ADDR_HIGH_OFFSET (0x0000002c)
0106 #define MPI3_SYSIF_ADMIN_REPLY_Q_ADDR_LOW_OFFSET (0x00000030)
0107 #define MPI3_SYSIF_ADMIN_REPLY_Q_ADDR_HIGH_OFFSET (0x00000034)
0108 #define MPI3_SYSIF_COALESCE_CONTROL_OFFSET (0x00000040)
0109 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_MASK (0xc0000000)
0110 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_NO_CHANGE (0x00000000)
0111 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_DISABLE (0x40000000)
0112 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_ENABLE (0xc0000000)
0113 #define MPI3_SYSIF_COALESCE_CONTROL_VALID (0x20000000)
0114 #define MPI3_SYSIF_COALESCE_CONTROL_MSIX_IDX_MASK (0x01ff0000)
0115 #define MPI3_SYSIF_COALESCE_CONTROL_MSIX_IDX_SHIFT (16)
0116 #define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_MASK (0x0000ff00)
0117 #define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_SHIFT (8)
0118 #define MPI3_SYSIF_COALESCE_CONTROL_DEPTH_MASK (0x000000ff)
0119 #define MPI3_SYSIF_COALESCE_CONTROL_DEPTH_SHIFT (0)
0120 #define MPI3_SYSIF_ADMIN_REQ_Q_PI_OFFSET (0x00001000)
0121 #define MPI3_SYSIF_ADMIN_REPLY_Q_CI_OFFSET (0x00001004)
0122 #define MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET (0x00001008)
0123 #define MPI3_SYSIF_OPER_REQ_Q_N_PI_OFFSET(N) (MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET + (((N) - 1) * 8))
0124 #define MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET (0x0000100c)
0125 #define MPI3_SYSIF_OPER_REPLY_Q_N_CI_OFFSET(N) (MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET + (((N) - 1) * 8))
0126 #define MPI3_SYSIF_WRITE_SEQUENCE_OFFSET (0x00001c04)
0127 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_MASK (0x0000000f)
0128 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH (0x0)
0129 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST (0xf)
0130 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND (0x4)
0131 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD (0xb)
0132 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH (0x2)
0133 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH (0x7)
0134 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH (0xd)
0135 #define MPI3_SYSIF_HOST_DIAG_OFFSET (0x00001c08)
0136 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_MASK (0x00000700)
0137 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_NO_RESET (0x00000000)
0138 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET (0x00000100)
0139 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_HOST_CONTROL_BOOT_RESET (0x00000200)
0140 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_COMPLETE_RESET (0x00000300)
0141 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT (0x00000700)
0142 #define MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS (0x00000080)
0143 #define MPI3_SYSIF_HOST_DIAG_SECURE_BOOT (0x00000040)
0144 #define MPI3_SYSIF_HOST_DIAG_CLEAR_INVALID_FW_IMAGE (0x00000020)
0145 #define MPI3_SYSIF_HOST_DIAG_INVALID_FW_IMAGE (0x00000010)
0146 #define MPI3_SYSIF_HOST_DIAG_HCBENABLE (0x00000008)
0147 #define MPI3_SYSIF_HOST_DIAG_HCBMODE (0x00000004)
0148 #define MPI3_SYSIF_HOST_DIAG_DIAG_RW_ENABLE (0x00000002)
0149 #define MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE (0x00000001)
0150 #define MPI3_SYSIF_FAULT_OFFSET (0x00001c10)
0151 #define MPI3_SYSIF_FAULT_FUNC_AREA_MASK (0xff000000)
0152 #define MPI3_SYSIF_FAULT_FUNC_AREA_SHIFT (24)
0153 #define MPI3_SYSIF_FAULT_FUNC_AREA_MPI_DEFINED (0x00000000)
0154 #define MPI3_SYSIF_FAULT_CODE_MASK (0x0000ffff)
0155 #define MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET (0x0000f000)
0156 #define MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET (0x0000f001)
0157 #define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS (0x0000f002)
0158 #define MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED (0x0000f003)
0159 #define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_NEEDED (0x0000f004)
0160 #define MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED (0x0000f005)
0161 #define MPI3_SYSIF_FAULT_CODE_TEMP_THRESHOLD_EXCEEDED (0x0000f006)
0162 #define MPI3_SYSIF_FAULT_INFO0_OFFSET (0x00001c14)
0163 #define MPI3_SYSIF_FAULT_INFO1_OFFSET (0x00001c18)
0164 #define MPI3_SYSIF_FAULT_INFO2_OFFSET (0x00001c1c)
0165 #define MPI3_SYSIF_HCB_ADDRESS_LOW_OFFSET (0x00001c30)
0166 #define MPI3_SYSIF_HCB_ADDRESS_HIGH_OFFSET (0x00001c34)
0167 #define MPI3_SYSIF_HCB_SIZE_OFFSET (0x00001c38)
0168 #define MPI3_SYSIF_HCB_SIZE_SIZE_MASK (0xfffff000)
0169 #define MPI3_SYSIF_HCB_SIZE_SIZE_SHIFT (12)
0170 #define MPI3_SYSIF_HCB_SIZE_HCDW_ENABLE (0x00000001)
0171 #define MPI3_SYSIF_REPLY_FREE_HOST_INDEX_OFFSET (0x00001c40)
0172 #define MPI3_SYSIF_SENSE_BUF_FREE_HOST_INDEX_OFFSET (0x00001c44)
0173 #define MPI3_SYSIF_DIAG_RW_DATA_LOW_OFFSET (0x00001c50)
0174 #define MPI3_SYSIF_DIAG_RW_DATA_HIGH_OFFSET (0x00001c54)
0175 #define MPI3_SYSIF_DIAG_RW_ADDRESS_LOW_OFFSET (0x00001c58)
0176 #define MPI3_SYSIF_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00001c5c)
0177 #define MPI3_SYSIF_DIAG_RW_CONTROL_OFFSET (0x00001c60)
0178 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_MASK (0x00000030)
0179 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_1BYTE (0x00000000)
0180 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_2BYTES (0x00000010)
0181 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_4BYTES (0x00000020)
0182 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_8BYTES (0x00000030)
0183 #define MPI3_SYSIF_DIAG_RW_CONTROL_RESET (0x00000004)
0184 #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_MASK (0x00000002)
0185 #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_READ (0x00000000)
0186 #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_WRITE (0x00000002)
0187 #define MPI3_SYSIF_DIAG_RW_CONTROL_START (0x00000001)
0188 #define MPI3_SYSIF_DIAG_RW_STATUS_OFFSET (0x00001c62)
0189 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_MASK (0x0000000e)
0190 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_SUCCESS (0x00000000)
0191 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_INV_ADDR (0x00000002)
0192 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_ACC_ERR (0x00000004)
0193 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_PAR_ERR (0x00000006)
0194 #define MPI3_SYSIF_DIAG_RW_STATUS_BUSY (0x00000001)
0195 #define MPI3_SYSIF_SCRATCHPAD0_OFFSET (0x00001cf0)
0196 #define MPI3_SYSIF_SCRATCHPAD1_OFFSET (0x00001cf4)
0197 #define MPI3_SYSIF_SCRATCHPAD2_OFFSET (0x00001cf8)
0198 #define MPI3_SYSIF_SCRATCHPAD3_OFFSET (0x00001cfc)
0199 #define MPI3_SYSIF_DEVICE_ASSIGNED_REGS_OFFSET (0x00002000)
0200 #define MPI3_SYSIF_DIAG_SAVE_TIMEOUT (60)
0201 struct mpi3_default_reply_descriptor {
0202 __le32 descriptor_type_dependent1[2];
0203 __le16 request_queue_ci;
0204 __le16 request_queue_id;
0205 __le16 descriptor_type_dependent2;
0206 __le16 reply_flags;
0207 };
0208
0209 #define MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK (0x0001)
0210 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK (0xf000)
0211 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY (0x0000)
0212 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS (0x1000)
0213 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_TARGET_COMMAND_BUFFER (0x2000)
0214 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS (0x3000)
0215 struct mpi3_address_reply_descriptor {
0216 __le64 reply_frame_address;
0217 __le16 request_queue_ci;
0218 __le16 request_queue_id;
0219 __le16 reserved0c;
0220 __le16 reply_flags;
0221 };
0222
0223 struct mpi3_success_reply_descriptor {
0224 __le32 reserved00[2];
0225 __le16 request_queue_ci;
0226 __le16 request_queue_id;
0227 __le16 host_tag;
0228 __le16 reply_flags;
0229 };
0230
0231 struct mpi3_target_command_buffer_reply_descriptor {
0232 __le32 reserved00;
0233 __le16 initiator_dev_handle;
0234 u8 phy_num;
0235 u8 reserved07;
0236 __le16 request_queue_ci;
0237 __le16 request_queue_id;
0238 __le16 io_index;
0239 __le16 reply_flags;
0240 };
0241
0242 struct mpi3_status_reply_descriptor {
0243 __le16 ioc_status;
0244 __le16 reserved02;
0245 __le32 ioc_log_info;
0246 __le16 request_queue_ci;
0247 __le16 request_queue_id;
0248 __le16 host_tag;
0249 __le16 reply_flags;
0250 };
0251
0252 #define MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL (0x8000)
0253 #define MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK (0x7fff)
0254 #define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_MASK (0xf0000000)
0255 #define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_NO_INFO (0x00000000)
0256 #define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_SAS (0x30000000)
0257 #define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_DATA_MASK (0x0fffffff)
0258 union mpi3_reply_descriptors_union {
0259 struct mpi3_default_reply_descriptor default_reply;
0260 struct mpi3_address_reply_descriptor address_reply;
0261 struct mpi3_success_reply_descriptor success;
0262 struct mpi3_target_command_buffer_reply_descriptor target_command_buffer;
0263 struct mpi3_status_reply_descriptor status;
0264 __le32 words[4];
0265 };
0266
0267 struct mpi3_sge_common {
0268 __le64 address;
0269 __le32 length;
0270 u8 reserved0c[3];
0271 u8 flags;
0272 };
0273
0274 struct mpi3_sge_bit_bucket {
0275 __le64 reserved00;
0276 __le32 length;
0277 u8 reserved0c[3];
0278 u8 flags;
0279 };
0280
0281 struct mpi3_sge_extended_eedp {
0282 u8 user_data_size;
0283 u8 reserved01;
0284 __le16 eedp_flags;
0285 __le32 secondary_reference_tag;
0286 __le16 secondary_application_tag;
0287 __le16 application_tag_translation_mask;
0288 __le16 reserved0c;
0289 u8 extended_operation;
0290 u8 flags;
0291 };
0292
0293 union mpi3_sge_union {
0294 struct mpi3_sge_common simple;
0295 struct mpi3_sge_common chain;
0296 struct mpi3_sge_common last_chain;
0297 struct mpi3_sge_bit_bucket bit_bucket;
0298 struct mpi3_sge_extended_eedp eedp;
0299 __le32 words[4];
0300 };
0301
0302 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_MASK (0xf0)
0303 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE (0x00)
0304 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_BIT_BUCKET (0x10)
0305 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_CHAIN (0x20)
0306 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_LAST_CHAIN (0x30)
0307 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_EXTENDED (0xf0)
0308 #define MPI3_SGE_FLAGS_END_OF_LIST (0x08)
0309 #define MPI3_SGE_FLAGS_END_OF_BUFFER (0x04)
0310 #define MPI3_SGE_FLAGS_DLAS_MASK (0x03)
0311 #define MPI3_SGE_FLAGS_DLAS_SYSTEM (0x00)
0312 #define MPI3_SGE_FLAGS_DLAS_IOC_UDP (0x01)
0313 #define MPI3_SGE_FLAGS_DLAS_IOC_CTL (0x02)
0314 #define MPI3_SGE_EXT_OPER_EEDP (0x00)
0315 #define MPI3_EEDPFLAGS_INCR_PRI_REF_TAG (0x8000)
0316 #define MPI3_EEDPFLAGS_INCR_SEC_REF_TAG (0x4000)
0317 #define MPI3_EEDPFLAGS_INCR_PRI_APP_TAG (0x2000)
0318 #define MPI3_EEDPFLAGS_INCR_SEC_APP_TAG (0x1000)
0319 #define MPI3_EEDPFLAGS_ESC_PASSTHROUGH (0x0800)
0320 #define MPI3_EEDPFLAGS_CHK_REF_TAG (0x0400)
0321 #define MPI3_EEDPFLAGS_CHK_APP_TAG (0x0200)
0322 #define MPI3_EEDPFLAGS_CHK_GUARD (0x0100)
0323 #define MPI3_EEDPFLAGS_ESC_MODE_MASK (0x00c0)
0324 #define MPI3_EEDPFLAGS_ESC_MODE_DO_NOT_DISABLE (0x0040)
0325 #define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_DISABLE (0x0080)
0326 #define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_REFTAG_DISABLE (0x00c0)
0327 #define MPI3_EEDPFLAGS_HOST_GUARD_MASK (0x0030)
0328 #define MPI3_EEDPFLAGS_HOST_GUARD_T10_CRC (0x0000)
0329 #define MPI3_EEDPFLAGS_HOST_GUARD_IP_CHKSUM (0x0010)
0330 #define MPI3_EEDPFLAGS_HOST_GUARD_OEM_SPECIFIC (0x0020)
0331 #define MPI3_EEDPFLAGS_PT_REF_TAG (0x0008)
0332 #define MPI3_EEDPFLAGS_EEDP_OP_MASK (0x0007)
0333 #define MPI3_EEDPFLAGS_EEDP_OP_CHECK (0x0001)
0334 #define MPI3_EEDPFLAGS_EEDP_OP_STRIP (0x0002)
0335 #define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REMOVE (0x0003)
0336 #define MPI3_EEDPFLAGS_EEDP_OP_INSERT (0x0004)
0337 #define MPI3_EEDPFLAGS_EEDP_OP_REPLACE (0x0006)
0338 #define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REGEN (0x0007)
0339 #define MPI3_EEDP_UDS_512 (0x01)
0340 #define MPI3_EEDP_UDS_520 (0x02)
0341 #define MPI3_EEDP_UDS_4080 (0x03)
0342 #define MPI3_EEDP_UDS_4088 (0x04)
0343 #define MPI3_EEDP_UDS_4096 (0x05)
0344 #define MPI3_EEDP_UDS_4104 (0x06)
0345 #define MPI3_EEDP_UDS_4160 (0x07)
0346 struct mpi3_request_header {
0347 __le16 host_tag;
0348 u8 ioc_use_only02;
0349 u8 function;
0350 __le16 ioc_use_only04;
0351 u8 ioc_use_only06;
0352 u8 msg_flags;
0353 __le16 change_count;
0354 __le16 function_dependent;
0355 };
0356
0357 struct mpi3_default_reply {
0358 __le16 host_tag;
0359 u8 ioc_use_only02;
0360 u8 function;
0361 __le16 ioc_use_only04;
0362 u8 ioc_use_only06;
0363 u8 msg_flags;
0364 __le16 ioc_use_only08;
0365 __le16 ioc_status;
0366 __le32 ioc_log_info;
0367 };
0368
0369 #define MPI3_HOST_TAG_INVALID (0xffff)
0370 #define MPI3_FUNCTION_IOC_FACTS (0x01)
0371 #define MPI3_FUNCTION_IOC_INIT (0x02)
0372 #define MPI3_FUNCTION_PORT_ENABLE (0x03)
0373 #define MPI3_FUNCTION_EVENT_NOTIFICATION (0x04)
0374 #define MPI3_FUNCTION_EVENT_ACK (0x05)
0375 #define MPI3_FUNCTION_CI_DOWNLOAD (0x06)
0376 #define MPI3_FUNCTION_CI_UPLOAD (0x07)
0377 #define MPI3_FUNCTION_IO_UNIT_CONTROL (0x08)
0378 #define MPI3_FUNCTION_PERSISTENT_EVENT_LOG (0x09)
0379 #define MPI3_FUNCTION_MGMT_PASSTHROUGH (0x0a)
0380 #define MPI3_FUNCTION_CONFIG (0x10)
0381 #define MPI3_FUNCTION_SCSI_IO (0x20)
0382 #define MPI3_FUNCTION_SCSI_TASK_MGMT (0x21)
0383 #define MPI3_FUNCTION_SMP_PASSTHROUGH (0x22)
0384 #define MPI3_FUNCTION_NVME_ENCAPSULATED (0x24)
0385 #define MPI3_FUNCTION_TARGET_ASSIST (0x30)
0386 #define MPI3_FUNCTION_TARGET_STATUS_SEND (0x31)
0387 #define MPI3_FUNCTION_TARGET_MODE_ABORT (0x32)
0388 #define MPI3_FUNCTION_TARGET_CMD_BUF_POST_BASE (0x33)
0389 #define MPI3_FUNCTION_TARGET_CMD_BUF_POST_LIST (0x34)
0390 #define MPI3_FUNCTION_CREATE_REQUEST_QUEUE (0x70)
0391 #define MPI3_FUNCTION_DELETE_REQUEST_QUEUE (0x71)
0392 #define MPI3_FUNCTION_CREATE_REPLY_QUEUE (0x72)
0393 #define MPI3_FUNCTION_DELETE_REPLY_QUEUE (0x73)
0394 #define MPI3_FUNCTION_TOOLBOX (0x80)
0395 #define MPI3_FUNCTION_DIAG_BUFFER_POST (0x81)
0396 #define MPI3_FUNCTION_DIAG_BUFFER_MANAGE (0x82)
0397 #define MPI3_FUNCTION_DIAG_BUFFER_UPLOAD (0x83)
0398 #define MPI3_FUNCTION_MIN_IOC_USE_ONLY (0xc0)
0399 #define MPI3_FUNCTION_MAX_IOC_USE_ONLY (0xef)
0400 #define MPI3_FUNCTION_MIN_PRODUCT_SPECIFIC (0xf0)
0401 #define MPI3_FUNCTION_MAX_PRODUCT_SPECIFIC (0xff)
0402 #define MPI3_IOCSTATUS_LOG_INFO_AVAIL_MASK (0x8000)
0403 #define MPI3_IOCSTATUS_LOG_INFO_AVAILABLE (0x8000)
0404 #define MPI3_IOCSTATUS_STATUS_MASK (0x7fff)
0405 #define MPI3_IOCSTATUS_SUCCESS (0x0000)
0406 #define MPI3_IOCSTATUS_INVALID_FUNCTION (0x0001)
0407 #define MPI3_IOCSTATUS_BUSY (0x0002)
0408 #define MPI3_IOCSTATUS_INVALID_SGL (0x0003)
0409 #define MPI3_IOCSTATUS_INTERNAL_ERROR (0x0004)
0410 #define MPI3_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
0411 #define MPI3_IOCSTATUS_INVALID_FIELD (0x0007)
0412 #define MPI3_IOCSTATUS_INVALID_STATE (0x0008)
0413 #define MPI3_IOCSTATUS_INSUFFICIENT_POWER (0x000a)
0414 #define MPI3_IOCSTATUS_INVALID_CHANGE_COUNT (0x000b)
0415 #define MPI3_IOCSTATUS_ALLOWED_CMD_BLOCK (0x000c)
0416 #define MPI3_IOCSTATUS_SUPERVISOR_ONLY (0x000d)
0417 #define MPI3_IOCSTATUS_FAILURE (0x001f)
0418 #define MPI3_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
0419 #define MPI3_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
0420 #define MPI3_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
0421 #define MPI3_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
0422 #define MPI3_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
0423 #define MPI3_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
0424 #define MPI3_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
0425 #define MPI3_IOCSTATUS_SCSI_TM_NOT_SUPPORTED (0x0041)
0426 #define MPI3_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
0427 #define MPI3_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
0428 #define MPI3_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
0429 #define MPI3_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
0430 #define MPI3_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
0431 #define MPI3_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
0432 #define MPI3_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
0433 #define MPI3_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
0434 #define MPI3_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004a)
0435 #define MPI3_IOCSTATUS_SCSI_IOC_TERMINATED (0x004b)
0436 #define MPI3_IOCSTATUS_SCSI_EXT_TERMINATED (0x004c)
0437 #define MPI3_IOCSTATUS_EEDP_GUARD_ERROR (0x004d)
0438 #define MPI3_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004e)
0439 #define MPI3_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004f)
0440 #define MPI3_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
0441 #define MPI3_IOCSTATUS_TARGET_ABORTED (0x0063)
0442 #define MPI3_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
0443 #define MPI3_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
0444 #define MPI3_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006a)
0445 #define MPI3_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006d)
0446 #define MPI3_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006e)
0447 #define MPI3_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006f)
0448 #define MPI3_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
0449 #define MPI3_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
0450 #define MPI3_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
0451 #define MPI3_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
0452 #define MPI3_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00a0)
0453 #define MPI3_IOCSTATUS_CI_UNSUPPORTED (0x00b0)
0454 #define MPI3_IOCSTATUS_CI_UPDATE_SEQUENCE (0x00b1)
0455 #define MPI3_IOCSTATUS_CI_VALIDATION_FAILED (0x00b2)
0456 #define MPI3_IOCSTATUS_CI_KEY_UPDATE_PENDING (0x00b3)
0457 #define MPI3_IOCSTATUS_CI_KEY_UPDATE_NOT_POSSIBLE (0x00b4)
0458 #define MPI3_IOCSTATUS_SECURITY_KEY_REQUIRED (0x00c0)
0459 #define MPI3_IOCSTATUS_SECURITY_VIOLATION (0x00c1)
0460 #define MPI3_IOCSTATUS_INVALID_QUEUE_ID (0x0f00)
0461 #define MPI3_IOCSTATUS_INVALID_QUEUE_SIZE (0x0f01)
0462 #define MPI3_IOCSTATUS_INVALID_MSIX_VECTOR (0x0f02)
0463 #define MPI3_IOCSTATUS_INVALID_REPLY_QUEUE_ID (0x0f03)
0464 #define MPI3_IOCSTATUS_INVALID_QUEUE_DELETION (0x0f04)
0465 #define MPI3_IOCLOGINFO_TYPE_MASK (0xf0000000)
0466 #define MPI3_IOCLOGINFO_TYPE_SHIFT (28)
0467 #define MPI3_IOCLOGINFO_TYPE_NONE (0x0)
0468 #define MPI3_IOCLOGINFO_TYPE_SAS (0x3)
0469 #define MPI3_IOCLOGINFO_LOG_DATA_MASK (0x0fffffff)
0470 #endif
