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0006 #ifndef MPI30_IOC_H
0007 #define MPI30_IOC_H 1
0008 struct mpi3_ioc_init_request {
0009 __le16 host_tag;
0010 u8 ioc_use_only02;
0011 u8 function;
0012 __le16 ioc_use_only04;
0013 u8 ioc_use_only06;
0014 u8 msg_flags;
0015 __le16 change_count;
0016 __le16 reserved0a;
0017 union mpi3_version_union mpi_version;
0018 __le64 time_stamp;
0019 u8 reserved18;
0020 u8 who_init;
0021 __le16 reserved1a;
0022 __le16 reply_free_queue_depth;
0023 __le16 reserved1e;
0024 __le64 reply_free_queue_address;
0025 __le32 reserved28;
0026 __le16 sense_buffer_free_queue_depth;
0027 __le16 sense_buffer_length;
0028 __le64 sense_buffer_free_queue_address;
0029 __le64 driver_information_address;
0030 };
0031
0032 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_MASK (0x03)
0033 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_NOT_USED (0x00)
0034 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_SEPARATED (0x01)
0035 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_INLINE (0x02)
0036 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_BOTH (0x03)
0037 #define MPI3_WHOINIT_NOT_INITIALIZED (0x00)
0038 #define MPI3_WHOINIT_ROM_BIOS (0x02)
0039 #define MPI3_WHOINIT_HOST_DRIVER (0x03)
0040 #define MPI3_WHOINIT_MANUFACTURER (0x04)
0041
0042 struct mpi3_ioc_facts_request {
0043 __le16 host_tag;
0044 u8 ioc_use_only02;
0045 u8 function;
0046 __le16 ioc_use_only04;
0047 u8 ioc_use_only06;
0048 u8 msg_flags;
0049 __le16 change_count;
0050 __le16 reserved0a;
0051 __le32 reserved0c;
0052 union mpi3_sge_union sgl;
0053 };
0054
0055 struct mpi3_ioc_facts_data {
0056 __le16 ioc_facts_data_length;
0057 __le16 reserved02;
0058 union mpi3_version_union mpi_version;
0059 struct mpi3_comp_image_version fw_version;
0060 __le32 ioc_capabilities;
0061 u8 ioc_number;
0062 u8 who_init;
0063 __le16 max_msix_vectors;
0064 __le16 max_outstanding_requests;
0065 __le16 product_id;
0066 __le16 ioc_request_frame_size;
0067 __le16 reply_frame_size;
0068 __le16 ioc_exceptions;
0069 __le16 max_persistent_id;
0070 u8 sge_modifier_mask;
0071 u8 sge_modifier_value;
0072 u8 sge_modifier_shift;
0073 u8 protocol_flags;
0074 __le16 max_sas_initiators;
0075 __le16 max_data_length;
0076 __le16 max_sas_expanders;
0077 __le16 max_enclosures;
0078 __le16 min_dev_handle;
0079 __le16 max_dev_handle;
0080 __le16 max_pcie_switches;
0081 __le16 max_nvme;
0082 __le16 reserved38;
0083 __le16 max_vds;
0084 __le16 max_host_pds;
0085 __le16 max_adv_host_pds;
0086 __le16 max_raid_pds;
0087 __le16 max_posted_cmd_buffers;
0088 __le32 flags;
0089 __le16 max_operational_request_queues;
0090 __le16 max_operational_reply_queues;
0091 __le16 shutdown_timeout;
0092 __le16 reserved4e;
0093 __le32 diag_trace_size;
0094 __le32 diag_fw_size;
0095 __le32 diag_driver_size;
0096 u8 max_host_pd_ns_count;
0097 u8 max_adv_host_pd_ns_count;
0098 u8 max_raidpd_ns_count;
0099 u8 max_devices_per_throttle_group;
0100 __le16 io_throttle_data_length;
0101 __le16 max_io_throttle_group;
0102 __le16 io_throttle_low;
0103 __le16 io_throttle_high;
0104 };
0105 #define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_MASK (0x80000000)
0106 #define MPI3_IOCFACTS_CAPABILITY_SUPERVISOR_IOC (0x00000000)
0107 #define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_IOC (0x80000000)
0108 #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_MASK (0x00000600)
0109 #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_FIXED_THRESHOLD (0x00000000)
0110 #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_OUTSTANDING_IO (0x00000200)
0111 #define MPI3_IOCFACTS_CAPABILITY_COMPLETE_RESET_CAPABLE (0x00000100)
0112 #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_ENABLED (0x00000080)
0113 #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_FW_ENABLED (0x00000040)
0114 #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_DRIVER_ENABLED (0x00000020)
0115 #define MPI3_IOCFACTS_CAPABILITY_ADVANCED_HOST_PD_ENABLED (0x00000010)
0116 #define MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE (0x00000008)
0117 #define MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED (0x00000002)
0118 #define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_SUPPORTED (0x00000001)
0119 #define MPI3_IOCFACTS_PID_TYPE_MASK (0xf000)
0120 #define MPI3_IOCFACTS_PID_TYPE_SHIFT (12)
0121 #define MPI3_IOCFACTS_PID_PRODUCT_MASK (0x0f00)
0122 #define MPI3_IOCFACTS_PID_PRODUCT_SHIFT (8)
0123 #define MPI3_IOCFACTS_PID_FAMILY_MASK (0x00ff)
0124 #define MPI3_IOCFACTS_PID_FAMILY_SHIFT (0)
0125 #define MPI3_IOCFACTS_EXCEPT_SECURITY_REKEY (0x2000)
0126 #define MPI3_IOCFACTS_EXCEPT_SAS_DISABLED (0x1000)
0127 #define MPI3_IOCFACTS_EXCEPT_SAFE_MODE (0x0800)
0128 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_MASK (0x0700)
0129 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_NONE (0x0000)
0130 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_MGMT (0x0100)
0131 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_MGMT (0x0200)
0132 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_MGMT (0x0300)
0133 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_OOB (0x0400)
0134 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_OOB (0x0500)
0135 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_OOB (0x0600)
0136 #define MPI3_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0080)
0137 #define MPI3_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0040)
0138 #define MPI3_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0020)
0139 #define MPI3_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0010)
0140 #define MPI3_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0008)
0141 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x0001)
0142 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_PRIMARY (0x0000)
0143 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_SECONDARY (0x0001)
0144 #define MPI3_IOCFACTS_PROTOCOL_SAS (0x0010)
0145 #define MPI3_IOCFACTS_PROTOCOL_SATA (0x0008)
0146 #define MPI3_IOCFACTS_PROTOCOL_NVME (0x0004)
0147 #define MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
0148 #define MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
0149 #define MPI3_IOCFACTS_MAX_DATA_LENGTH_NOT_REPORTED (0x0000)
0150 #define MPI3_IOCFACTS_FLAGS_SIGNED_NVDATA_REQUIRED (0x00010000)
0151 #define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK (0x0000ff00)
0152 #define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT (8)
0153 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK (0x00000030)
0154 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_NOT_STARTED (0x00000000)
0155 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_IN_PROGRESS (0x00000010)
0156 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_COMPLETE (0x00000020)
0157 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK (0x0000000f)
0158 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA (0x00000000)
0159 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR (0x00000002)
0160 #define MPI3_IOCFACTS_IO_THROTTLE_DATA_LENGTH_NOT_REQUIRED (0x0000)
0161 struct mpi3_mgmt_passthrough_request {
0162 __le16 host_tag;
0163 u8 ioc_use_only02;
0164 u8 function;
0165 __le16 ioc_use_only04;
0166 u8 ioc_use_only06;
0167 u8 msg_flags;
0168 __le16 change_count;
0169 __le16 reserved0a;
0170 __le32 reserved0c[5];
0171 union mpi3_sge_union command_sgl;
0172 union mpi3_sge_union response_sgl;
0173 };
0174
0175 struct mpi3_create_request_queue_request {
0176 __le16 host_tag;
0177 u8 ioc_use_only02;
0178 u8 function;
0179 __le16 ioc_use_only04;
0180 u8 ioc_use_only06;
0181 u8 msg_flags;
0182 __le16 change_count;
0183 u8 flags;
0184 u8 burst;
0185 __le16 size;
0186 __le16 queue_id;
0187 __le16 reply_queue_id;
0188 __le16 reserved12;
0189 __le32 reserved14;
0190 __le64 base_address;
0191 };
0192
0193 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_MASK (0x80)
0194 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80)
0195 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00)
0196 #define MPI3_CREATE_REQUEST_QUEUE_SIZE_MINIMUM (2)
0197 struct mpi3_delete_request_queue_request {
0198 __le16 host_tag;
0199 u8 ioc_use_only02;
0200 u8 function;
0201 __le16 ioc_use_only04;
0202 u8 ioc_use_only06;
0203 u8 msg_flags;
0204 __le16 change_count;
0205 __le16 queue_id;
0206 };
0207
0208 struct mpi3_create_reply_queue_request {
0209 __le16 host_tag;
0210 u8 ioc_use_only02;
0211 u8 function;
0212 __le16 ioc_use_only04;
0213 u8 ioc_use_only06;
0214 u8 msg_flags;
0215 __le16 change_count;
0216 u8 flags;
0217 u8 reserved0b;
0218 __le16 size;
0219 __le16 queue_id;
0220 __le16 msix_index;
0221 __le16 reserved12;
0222 __le32 reserved14;
0223 __le64 base_address;
0224 };
0225
0226 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_MASK (0x80)
0227 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80)
0228 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00)
0229 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_COALESCE_DISABLE (0x02)
0230 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_MASK (0x01)
0231 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_DISABLE (0x00)
0232 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE (0x01)
0233 #define MPI3_CREATE_REPLY_QUEUE_SIZE_MINIMUM (2)
0234 struct mpi3_delete_reply_queue_request {
0235 __le16 host_tag;
0236 u8 ioc_use_only02;
0237 u8 function;
0238 __le16 ioc_use_only04;
0239 u8 ioc_use_only06;
0240 u8 msg_flags;
0241 __le16 change_count;
0242 __le16 queue_id;
0243 };
0244
0245 struct mpi3_port_enable_request {
0246 __le16 host_tag;
0247 u8 ioc_use_only02;
0248 u8 function;
0249 __le16 ioc_use_only04;
0250 u8 ioc_use_only06;
0251 u8 msg_flags;
0252 __le16 change_count;
0253 __le16 reserved0a;
0254 };
0255
0256 #define MPI3_EVENT_LOG_DATA (0x01)
0257 #define MPI3_EVENT_CHANGE (0x02)
0258 #define MPI3_EVENT_GPIO_INTERRUPT (0x04)
0259 #define MPI3_EVENT_CABLE_MGMT (0x06)
0260 #define MPI3_EVENT_DEVICE_ADDED (0x07)
0261 #define MPI3_EVENT_DEVICE_INFO_CHANGED (0x08)
0262 #define MPI3_EVENT_PREPARE_FOR_RESET (0x09)
0263 #define MPI3_EVENT_COMP_IMAGE_ACT_START (0x0a)
0264 #define MPI3_EVENT_ENCL_DEVICE_ADDED (0x0b)
0265 #define MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE (0x0c)
0266 #define MPI3_EVENT_DEVICE_STATUS_CHANGE (0x0d)
0267 #define MPI3_EVENT_ENERGY_PACK_CHANGE (0x0e)
0268 #define MPI3_EVENT_SAS_DISCOVERY (0x11)
0269 #define MPI3_EVENT_SAS_BROADCAST_PRIMITIVE (0x12)
0270 #define MPI3_EVENT_SAS_NOTIFY_PRIMITIVE (0x13)
0271 #define MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x14)
0272 #define MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW (0x15)
0273 #define MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x16)
0274 #define MPI3_EVENT_SAS_PHY_COUNTER (0x18)
0275 #define MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR (0x19)
0276 #define MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x20)
0277 #define MPI3_EVENT_PCIE_ENUMERATION (0x22)
0278 #define MPI3_EVENT_PCIE_ERROR_THRESHOLD (0x23)
0279 #define MPI3_EVENT_HARD_RESET_RECEIVED (0x40)
0280 #define MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE (0x50)
0281 #define MPI3_EVENT_MIN_PRODUCT_SPECIFIC (0x60)
0282 #define MPI3_EVENT_MAX_PRODUCT_SPECIFIC (0x7f)
0283 #define MPI3_EVENT_NOTIFY_EVENTMASK_WORDS (4)
0284 struct mpi3_event_notification_request {
0285 __le16 host_tag;
0286 u8 ioc_use_only02;
0287 u8 function;
0288 __le16 ioc_use_only04;
0289 u8 ioc_use_only06;
0290 u8 msg_flags;
0291 __le16 change_count;
0292 __le16 reserved0a;
0293 __le16 sas_broadcast_primitive_masks;
0294 __le16 sas_notify_primitive_masks;
0295 __le32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS];
0296 };
0297
0298 struct mpi3_event_notification_reply {
0299 __le16 host_tag;
0300 u8 ioc_use_only02;
0301 u8 function;
0302 __le16 ioc_use_only04;
0303 u8 ioc_use_only06;
0304 u8 msg_flags;
0305 __le16 ioc_use_only08;
0306 __le16 ioc_status;
0307 __le32 ioc_log_info;
0308 u8 event_data_length;
0309 u8 event;
0310 __le16 ioc_change_count;
0311 __le32 event_context;
0312 __le32 event_data[1];
0313 };
0314
0315 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK (0x01)
0316 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_REQUIRED (0x01)
0317 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_NOT_REQUIRED (0x00)
0318 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_MASK (0x02)
0319 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_ORIGINAL (0x00)
0320 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_REPLAY (0x02)
0321 struct mpi3_event_data_gpio_interrupt {
0322 u8 gpio_num;
0323 u8 reserved01[3];
0324 };
0325 struct mpi3_event_data_cable_management {
0326 __le32 active_cable_power_requirement;
0327 u8 status;
0328 u8 receptacle_id;
0329 __le16 reserved06;
0330 };
0331
0332 #define MPI3_EVENT_CABLE_MGMT_ACT_CABLE_PWR_INVALID (0xffffffff)
0333 #define MPI3_EVENT_CABLE_MGMT_STATUS_INSUFFICIENT_POWER (0x00)
0334 #define MPI3_EVENT_CABLE_MGMT_STATUS_PRESENT (0x01)
0335 #define MPI3_EVENT_CABLE_MGMT_STATUS_DEGRADED (0x02)
0336 struct mpi3_event_ack_request {
0337 __le16 host_tag;
0338 u8 ioc_use_only02;
0339 u8 function;
0340 __le16 ioc_use_only04;
0341 u8 ioc_use_only06;
0342 u8 msg_flags;
0343 __le16 change_count;
0344 __le16 reserved0a;
0345 u8 event;
0346 u8 reserved0d[3];
0347 __le32 event_context;
0348 };
0349
0350 struct mpi3_event_data_prepare_for_reset {
0351 u8 reason_code;
0352 u8 reserved01;
0353 __le16 reserved02;
0354 };
0355
0356 #define MPI3_EVENT_PREPARE_RESET_RC_START (0x01)
0357 #define MPI3_EVENT_PREPARE_RESET_RC_ABORT (0x02)
0358 struct mpi3_event_data_comp_image_activation {
0359 __le32 reserved00;
0360 };
0361
0362 struct mpi3_event_data_device_status_change {
0363 __le16 task_tag;
0364 u8 reason_code;
0365 u8 io_unit_port;
0366 __le16 parent_dev_handle;
0367 __le16 dev_handle;
0368 __le64 wwid;
0369 u8 lun[8];
0370 };
0371
0372 #define MPI3_EVENT_DEV_STAT_RC_MOVED (0x01)
0373 #define MPI3_EVENT_DEV_STAT_RC_HIDDEN (0x02)
0374 #define MPI3_EVENT_DEV_STAT_RC_NOT_HIDDEN (0x03)
0375 #define MPI3_EVENT_DEV_STAT_RC_ASYNC_NOTIFICATION (0x04)
0376 #define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_STRT (0x20)
0377 #define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_CMP (0x21)
0378 #define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_STRT (0x22)
0379 #define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_CMP (0x23)
0380 #define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_STRT (0x24)
0381 #define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_CMP (0x25)
0382 #define MPI3_EVENT_DEV_STAT_RC_PCIE_HOT_RESET_FAILED (0x30)
0383 #define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_STRT (0x40)
0384 #define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_CMP (0x41)
0385 #define MPI3_EVENT_DEV_STAT_RC_VD_NOT_RESPONDING (0x50)
0386 struct mpi3_event_data_energy_pack_change {
0387 __le32 reserved00;
0388 __le16 shutdown_timeout;
0389 __le16 reserved06;
0390 };
0391
0392 struct mpi3_event_data_sas_discovery {
0393 u8 flags;
0394 u8 reason_code;
0395 u8 io_unit_port;
0396 u8 reserved03;
0397 __le32 discovery_status;
0398 };
0399
0400 #define MPI3_EVENT_SAS_DISC_FLAGS_DEVICE_CHANGE (0x02)
0401 #define MPI3_EVENT_SAS_DISC_FLAGS_IN_PROGRESS (0x01)
0402 #define MPI3_EVENT_SAS_DISC_RC_STARTED (0x01)
0403 #define MPI3_EVENT_SAS_DISC_RC_COMPLETED (0x02)
0404 #define MPI3_SAS_DISC_STATUS_MAX_ENCLOSURES_EXCEED (0x80000000)
0405 #define MPI3_SAS_DISC_STATUS_MAX_EXPANDERS_EXCEED (0x40000000)
0406 #define MPI3_SAS_DISC_STATUS_MAX_DEVICES_EXCEED (0x20000000)
0407 #define MPI3_SAS_DISC_STATUS_MAX_TOPO_PHYS_EXCEED (0x10000000)
0408 #define MPI3_SAS_DISC_STATUS_INVALID_CEI (0x00010000)
0409 #define MPI3_SAS_DISC_STATUS_FECEI_MISMATCH (0x00008000)
0410 #define MPI3_SAS_DISC_STATUS_MULTIPLE_DEVICES_IN_SLOT (0x00004000)
0411 #define MPI3_SAS_DISC_STATUS_NECEI_MISMATCH (0x00002000)
0412 #define MPI3_SAS_DISC_STATUS_TOO_MANY_SLOTS (0x00001000)
0413 #define MPI3_SAS_DISC_STATUS_EXP_MULTI_SUBTRACTIVE (0x00000800)
0414 #define MPI3_SAS_DISC_STATUS_MULTI_PORT_DOMAIN (0x00000400)
0415 #define MPI3_SAS_DISC_STATUS_TABLE_TO_SUBTRACTIVE_LINK (0x00000200)
0416 #define MPI3_SAS_DISC_STATUS_UNSUPPORTED_DEVICE (0x00000100)
0417 #define MPI3_SAS_DISC_STATUS_TABLE_LINK (0x00000080)
0418 #define MPI3_SAS_DISC_STATUS_SUBTRACTIVE_LINK (0x00000040)
0419 #define MPI3_SAS_DISC_STATUS_SMP_CRC_ERROR (0x00000020)
0420 #define MPI3_SAS_DISC_STATUS_SMP_FUNCTION_FAILED (0x00000010)
0421 #define MPI3_SAS_DISC_STATUS_SMP_TIMEOUT (0x00000008)
0422 #define MPI3_SAS_DISC_STATUS_MULTIPLE_PORTS (0x00000004)
0423 #define MPI3_SAS_DISC_STATUS_INVALID_SAS_ADDRESS (0x00000002)
0424 #define MPI3_SAS_DISC_STATUS_LOOP_DETECTED (0x00000001)
0425 struct mpi3_event_data_sas_broadcast_primitive {
0426 u8 phy_num;
0427 u8 io_unit_port;
0428 u8 port_width;
0429 u8 primitive;
0430 };
0431
0432 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE (0x01)
0433 #define MPI3_EVENT_BROADCAST_PRIMITIVE_SES (0x02)
0434 #define MPI3_EVENT_BROADCAST_PRIMITIVE_EXPANDER (0x03)
0435 #define MPI3_EVENT_BROADCAST_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
0436 #define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED3 (0x05)
0437 #define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED4 (0x06)
0438 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE0_RESERVED (0x07)
0439 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE1_RESERVED (0x08)
0440 struct mpi3_event_data_sas_notify_primitive {
0441 u8 phy_num;
0442 u8 io_unit_port;
0443 u8 reserved02;
0444 u8 primitive;
0445 };
0446
0447 #define MPI3_EVENT_NOTIFY_PRIMITIVE_ENABLE_SPINUP (0x01)
0448 #define MPI3_EVENT_NOTIFY_PRIMITIVE_POWER_LOSS_EXPECTED (0x02)
0449 #define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED1 (0x03)
0450 #define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED2 (0x04)
0451 #ifndef MPI3_EVENT_SAS_TOPO_PHY_COUNT
0452 #define MPI3_EVENT_SAS_TOPO_PHY_COUNT (1)
0453 #endif
0454 struct mpi3_event_sas_topo_phy_entry {
0455 __le16 attached_dev_handle;
0456 u8 link_rate;
0457 u8 status;
0458 };
0459
0460 #define MPI3_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xf0)
0461 #define MPI3_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
0462 #define MPI3_EVENT_SAS_TOPO_LR_PREV_MASK (0x0f)
0463 #define MPI3_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
0464 #define MPI3_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
0465 #define MPI3_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
0466 #define MPI3_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
0467 #define MPI3_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
0468 #define MPI3_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
0469 #define MPI3_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
0470 #define MPI3_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06)
0471 #define MPI3_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0a)
0472 #define MPI3_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0b)
0473 #define MPI3_EVENT_SAS_TOPO_LR_RATE_22_5 (0x0c)
0474 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_MASK (0xc0)
0475 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_SHIFT (6)
0476 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_ACCESSIBLE (0x00)
0477 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_NO_EXIST (0x40)
0478 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_VACANT (0x80)
0479 #define MPI3_EVENT_SAS_TOPO_PHY_RC_MASK (0x0f)
0480 #define MPI3_EVENT_SAS_TOPO_PHY_RC_TARG_NOT_RESPONDING (0x02)
0481 #define MPI3_EVENT_SAS_TOPO_PHY_RC_PHY_CHANGED (0x03)
0482 #define MPI3_EVENT_SAS_TOPO_PHY_RC_NO_CHANGE (0x04)
0483 #define MPI3_EVENT_SAS_TOPO_PHY_RC_DELAY_NOT_RESPONDING (0x05)
0484 #define MPI3_EVENT_SAS_TOPO_PHY_RC_RESPONDING (0x06)
0485 struct mpi3_event_data_sas_topology_change_list {
0486 __le16 enclosure_handle;
0487 __le16 expander_dev_handle;
0488 u8 num_phys;
0489 u8 reserved05[3];
0490 u8 num_entries;
0491 u8 start_phy_num;
0492 u8 exp_status;
0493 u8 io_unit_port;
0494 struct mpi3_event_sas_topo_phy_entry phy_entry[MPI3_EVENT_SAS_TOPO_PHY_COUNT];
0495 };
0496
0497 #define MPI3_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00)
0498 #define MPI3_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
0499 #define MPI3_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
0500 #define MPI3_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
0501 struct mpi3_event_data_sas_phy_counter {
0502 __le64 time_stamp;
0503 __le32 reserved08;
0504 u8 phy_event_code;
0505 u8 phy_num;
0506 __le16 reserved0e;
0507 __le32 phy_event_info;
0508 u8 counter_type;
0509 u8 threshold_window;
0510 u8 time_units;
0511 u8 reserved17;
0512 __le32 event_threshold;
0513 __le16 threshold_flags;
0514 __le16 reserved1e;
0515 };
0516
0517 struct mpi3_event_data_sas_device_disc_err {
0518 __le16 dev_handle;
0519 u8 reason_code;
0520 u8 io_unit_port;
0521 __le32 reserved04;
0522 __le64 sas_address;
0523 };
0524
0525 #define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_FAILED (0x01)
0526 #define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_TIMEOUT (0x02)
0527 struct mpi3_event_data_pcie_enumeration {
0528 u8 flags;
0529 u8 reason_code;
0530 u8 io_unit_port;
0531 u8 reserved03;
0532 __le32 enumeration_status;
0533 };
0534
0535 #define MPI3_EVENT_PCIE_ENUM_FLAGS_DEVICE_CHANGE (0x02)
0536 #define MPI3_EVENT_PCIE_ENUM_FLAGS_IN_PROGRESS (0x01)
0537 #define MPI3_EVENT_PCIE_ENUM_RC_STARTED (0x01)
0538 #define MPI3_EVENT_PCIE_ENUM_RC_COMPLETED (0x02)
0539 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCH_DEPTH_EXCEED (0x80000000)
0540 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0x40000000)
0541 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0x20000000)
0542 #define MPI3_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0x10000000)
0543 #ifndef MPI3_EVENT_PCIE_TOPO_PORT_COUNT
0544 #define MPI3_EVENT_PCIE_TOPO_PORT_COUNT (1)
0545 #endif
0546 struct mpi3_event_pcie_topo_port_entry {
0547 __le16 attached_dev_handle;
0548 u8 port_status;
0549 u8 reserved03;
0550 u8 current_port_info;
0551 u8 reserved05;
0552 u8 previous_port_info;
0553 u8 reserved07;
0554 };
0555
0556 #define MPI3_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0x02)
0557 #define MPI3_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0x03)
0558 #define MPI3_EVENT_PCIE_TOPO_PS_NO_CHANGE (0x04)
0559 #define MPI3_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05)
0560 #define MPI3_EVENT_PCIE_TOPO_PS_RESPONDING (0x06)
0561 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_MASK (0xf0)
0562 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00)
0563 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_1 (0x10)
0564 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_2 (0x20)
0565 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_4 (0x30)
0566 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_8 (0x40)
0567 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_16 (0x50)
0568 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0f)
0569 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00)
0570 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01)
0571 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02)
0572 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_5_0 (0x03)
0573 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_8_0 (0x04)
0574 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_16_0 (0x05)
0575 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_32_0 (0x06)
0576 struct mpi3_event_data_pcie_topology_change_list {
0577 __le16 enclosure_handle;
0578 __le16 switch_dev_handle;
0579 u8 num_ports;
0580 u8 reserved05[3];
0581 u8 num_entries;
0582 u8 start_port_num;
0583 u8 switch_status;
0584 u8 io_unit_port;
0585 __le32 reserved0c;
0586 struct mpi3_event_pcie_topo_port_entry port_entry[MPI3_EVENT_PCIE_TOPO_PORT_COUNT];
0587 };
0588
0589 #define MPI3_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0x00)
0590 #define MPI3_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02)
0591 #define MPI3_EVENT_PCIE_TOPO_SS_RESPONDING (0x03)
0592 #define MPI3_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04)
0593 struct mpi3_event_data_pcie_error_threshold {
0594 __le64 timestamp;
0595 u8 reason_code;
0596 u8 port;
0597 __le16 switch_dev_handle;
0598 u8 error;
0599 u8 action;
0600 __le16 threshold_count;
0601 __le16 attached_dev_handle;
0602 __le16 reserved12;
0603 };
0604
0605 #define MPI3_EVENT_PCI_ERROR_RC_THRESHOLD_EXCEEDED (0x00)
0606 #define MPI3_EVENT_PCI_ERROR_RC_ESCALATION (0x01)
0607 struct mpi3_event_data_sas_init_dev_status_change {
0608 u8 reason_code;
0609 u8 io_unit_port;
0610 __le16 dev_handle;
0611 __le32 reserved04;
0612 __le64 sas_address;
0613 };
0614
0615 #define MPI3_EVENT_SAS_INIT_RC_ADDED (0x01)
0616 #define MPI3_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
0617 struct mpi3_event_data_sas_init_table_overflow {
0618 __le16 max_init;
0619 __le16 current_init;
0620 __le32 reserved04;
0621 __le64 sas_address;
0622 };
0623
0624 struct mpi3_event_data_hard_reset_received {
0625 u8 reserved00;
0626 u8 io_unit_port;
0627 __le16 reserved02;
0628 };
0629
0630 struct mpi3_event_data_diag_buffer_status_change {
0631 u8 type;
0632 u8 reason_code;
0633 __le16 reserved02;
0634 __le32 reserved04;
0635 };
0636
0637 #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RELEASED (0x01)
0638 #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_PAUSED (0x02)
0639 #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RESUMED (0x03)
0640 #define MPI3_PEL_CLEARTYPE_CLEAR (0x00)
0641 #define MPI3_PEL_WAITTIME_INFINITE_WAIT (0x00)
0642 #define MPI3_PEL_ACTION_GET_SEQNUM (0x01)
0643 #define MPI3_PEL_ACTION_MARK_CLEAR (0x02)
0644 #define MPI3_PEL_ACTION_GET_LOG (0x03)
0645 #define MPI3_PEL_ACTION_GET_COUNT (0x04)
0646 #define MPI3_PEL_ACTION_WAIT (0x05)
0647 #define MPI3_PEL_ACTION_ABORT (0x06)
0648 #define MPI3_PEL_ACTION_GET_PRINT_STRINGS (0x07)
0649 #define MPI3_PEL_ACTION_ACKNOWLEDGE (0x08)
0650 #define MPI3_PEL_STATUS_SUCCESS (0x00)
0651 #define MPI3_PEL_STATUS_NOT_FOUND (0x01)
0652 #define MPI3_PEL_STATUS_ABORTED (0x02)
0653 #define MPI3_PEL_STATUS_NOT_READY (0x03)
0654 struct mpi3_pel_seq {
0655 __le32 newest;
0656 __le32 oldest;
0657 __le32 clear;
0658 __le32 shutdown;
0659 __le32 boot;
0660 __le32 last_acknowledged;
0661 };
0662
0663 struct mpi3_pel_entry {
0664 __le64 time_stamp;
0665 __le32 sequence_number;
0666 __le16 log_code;
0667 __le16 arg_type;
0668 __le16 locale;
0669 u8 class;
0670 u8 flags;
0671 u8 ext_num;
0672 u8 num_exts;
0673 u8 arg_data_size;
0674 u8 fixed_format_strings_size;
0675 __le32 reserved18[2];
0676 __le32 pel_info[24];
0677 };
0678
0679 #define MPI3_PEL_FLAGS_COMPLETE_RESET_NEEDED (0x02)
0680 #define MPI3_PEL_FLAGS_ACK_NEEDED (0x01)
0681 struct mpi3_pel_list {
0682 __le32 log_count;
0683 __le32 reserved04;
0684 struct mpi3_pel_entry entry[1];
0685 };
0686
0687 struct mpi3_pel_arg_map {
0688 u8 arg_type;
0689 u8 length;
0690 __le16 start_location;
0691 };
0692
0693 #define MPI3_PEL_ARG_MAP_ARG_TYPE_APPEND_STRING (0x00)
0694 #define MPI3_PEL_ARG_MAP_ARG_TYPE_INTEGER (0x01)
0695 #define MPI3_PEL_ARG_MAP_ARG_TYPE_STRING (0x02)
0696 #define MPI3_PEL_ARG_MAP_ARG_TYPE_BIT_FIELD (0x03)
0697 struct mpi3_pel_print_string {
0698 __le16 log_code;
0699 __le16 string_length;
0700 u8 num_arg_map;
0701 u8 reserved05[3];
0702 struct mpi3_pel_arg_map arg_map[1];
0703 };
0704
0705 struct mpi3_pel_print_string_list {
0706 __le32 num_print_strings;
0707 __le32 residual_bytes_remain;
0708 __le32 reserved08[2];
0709 struct mpi3_pel_print_string print_string[1];
0710 };
0711
0712 #ifndef MPI3_PEL_ACTION_SPECIFIC_MAX
0713 #define MPI3_PEL_ACTION_SPECIFIC_MAX (1)
0714 #endif
0715 struct mpi3_pel_request {
0716 __le16 host_tag;
0717 u8 ioc_use_only02;
0718 u8 function;
0719 __le16 ioc_use_only04;
0720 u8 ioc_use_only06;
0721 u8 msg_flags;
0722 __le16 change_count;
0723 u8 action;
0724 u8 reserved0b;
0725 __le32 action_specific[MPI3_PEL_ACTION_SPECIFIC_MAX];
0726 };
0727
0728 struct mpi3_pel_req_action_get_sequence_numbers {
0729 __le16 host_tag;
0730 u8 ioc_use_only02;
0731 u8 function;
0732 __le16 ioc_use_only04;
0733 u8 ioc_use_only06;
0734 u8 msg_flags;
0735 __le16 change_count;
0736 u8 action;
0737 u8 reserved0b;
0738 __le32 reserved0c[5];
0739 union mpi3_sge_union sgl;
0740 };
0741
0742 struct mpi3_pel_req_action_clear_log_marker {
0743 __le16 host_tag;
0744 u8 ioc_use_only02;
0745 u8 function;
0746 __le16 ioc_use_only04;
0747 u8 ioc_use_only06;
0748 u8 msg_flags;
0749 __le16 change_count;
0750 u8 action;
0751 u8 reserved0b;
0752 u8 clear_type;
0753 u8 reserved0d[3];
0754 };
0755
0756 struct mpi3_pel_req_action_get_log {
0757 __le16 host_tag;
0758 u8 ioc_use_only02;
0759 u8 function;
0760 __le16 ioc_use_only04;
0761 u8 ioc_use_only06;
0762 u8 msg_flags;
0763 __le16 change_count;
0764 u8 action;
0765 u8 reserved0b;
0766 __le32 starting_sequence_number;
0767 __le16 locale;
0768 u8 class;
0769 u8 reserved13;
0770 __le32 reserved14[3];
0771 union mpi3_sge_union sgl;
0772 };
0773
0774 struct mpi3_pel_req_action_get_count {
0775 __le16 host_tag;
0776 u8 ioc_use_only02;
0777 u8 function;
0778 __le16 ioc_use_only04;
0779 u8 ioc_use_only06;
0780 u8 msg_flags;
0781 __le16 change_count;
0782 u8 action;
0783 u8 reserved0b;
0784 __le32 starting_sequence_number;
0785 __le16 locale;
0786 u8 class;
0787 u8 reserved13;
0788 __le32 reserved14[3];
0789 union mpi3_sge_union sgl;
0790 };
0791
0792 struct mpi3_pel_req_action_wait {
0793 __le16 host_tag;
0794 u8 ioc_use_only02;
0795 u8 function;
0796 __le16 ioc_use_only04;
0797 u8 ioc_use_only06;
0798 u8 msg_flags;
0799 __le16 change_count;
0800 u8 action;
0801 u8 reserved0b;
0802 __le32 starting_sequence_number;
0803 __le16 locale;
0804 u8 class;
0805 u8 reserved13;
0806 __le16 wait_time;
0807 __le16 reserved16;
0808 __le32 reserved18[2];
0809 };
0810
0811 struct mpi3_pel_req_action_abort {
0812 __le16 host_tag;
0813 u8 ioc_use_only02;
0814 u8 function;
0815 __le16 ioc_use_only04;
0816 u8 ioc_use_only06;
0817 u8 msg_flags;
0818 __le16 change_count;
0819 u8 action;
0820 u8 reserved0b;
0821 __le32 reserved0c;
0822 __le16 abort_host_tag;
0823 __le16 reserved12;
0824 __le32 reserved14;
0825 };
0826
0827 struct mpi3_pel_req_action_get_print_strings {
0828 __le16 host_tag;
0829 u8 ioc_use_only02;
0830 u8 function;
0831 __le16 ioc_use_only04;
0832 u8 ioc_use_only06;
0833 u8 msg_flags;
0834 __le16 change_count;
0835 u8 action;
0836 u8 reserved0b;
0837 __le32 reserved0c;
0838 __le16 start_log_code;
0839 __le16 reserved12;
0840 __le32 reserved14[3];
0841 union mpi3_sge_union sgl;
0842 };
0843
0844 struct mpi3_pel_req_action_acknowledge {
0845 __le16 host_tag;
0846 u8 ioc_use_only02;
0847 u8 function;
0848 __le16 ioc_use_only04;
0849 u8 ioc_use_only06;
0850 u8 msg_flags;
0851 __le16 change_count;
0852 u8 action;
0853 u8 reserved0b;
0854 __le32 sequence_number;
0855 __le32 reserved10;
0856 };
0857
0858 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_MASK (0x03)
0859 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_NO_GUIDANCE (0x00)
0860 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_CONTINUE_OP (0x01)
0861 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_TRANSITION_TO_FAULT (0x02)
0862 struct mpi3_pel_reply {
0863 __le16 host_tag;
0864 u8 ioc_use_only02;
0865 u8 function;
0866 __le16 ioc_use_only04;
0867 u8 ioc_use_only06;
0868 u8 msg_flags;
0869 __le16 ioc_use_only08;
0870 __le16 ioc_status;
0871 __le32 ioc_log_info;
0872 u8 action;
0873 u8 reserved11;
0874 __le16 reserved12;
0875 __le16 pe_log_status;
0876 __le16 reserved16;
0877 __le32 transfer_length;
0878 };
0879
0880 struct mpi3_ci_download_request {
0881 __le16 host_tag;
0882 u8 ioc_use_only02;
0883 u8 function;
0884 __le16 ioc_use_only04;
0885 u8 ioc_use_only06;
0886 u8 msg_flags;
0887 __le16 change_count;
0888 u8 action;
0889 u8 reserved0b;
0890 __le32 signature1;
0891 __le32 total_image_size;
0892 __le32 image_offset;
0893 __le32 segment_size;
0894 __le32 reserved1c;
0895 union mpi3_sge_union sgl;
0896 };
0897
0898 #define MPI3_CI_DOWNLOAD_MSGFLAGS_LAST_SEGMENT (0x80)
0899 #define MPI3_CI_DOWNLOAD_MSGFLAGS_FORCE_FMC_ENABLE (0x40)
0900 #define MPI3_CI_DOWNLOAD_MSGFLAGS_SIGNED_NVDATA (0x20)
0901 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MASK (0x03)
0902 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_FAST (0x00)
0903 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MEDIUM (0x01)
0904 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_SLOW (0x02)
0905 #define MPI3_CI_DOWNLOAD_ACTION_DOWNLOAD (0x01)
0906 #define MPI3_CI_DOWNLOAD_ACTION_ONLINE_ACTIVATION (0x02)
0907 #define MPI3_CI_DOWNLOAD_ACTION_OFFLINE_ACTIVATION (0x03)
0908 #define MPI3_CI_DOWNLOAD_ACTION_GET_STATUS (0x04)
0909 #define MPI3_CI_DOWNLOAD_ACTION_CANCEL_OFFLINE_ACTIVATION (0x05)
0910 struct mpi3_ci_download_reply {
0911 __le16 host_tag;
0912 u8 ioc_use_only02;
0913 u8 function;
0914 __le16 ioc_use_only04;
0915 u8 ioc_use_only06;
0916 u8 msg_flags;
0917 __le16 ioc_use_only08;
0918 __le16 ioc_status;
0919 __le32 ioc_log_info;
0920 u8 flags;
0921 u8 cache_dirty;
0922 u8 pending_count;
0923 u8 reserved13;
0924 };
0925
0926 #define MPI3_CI_DOWNLOAD_FLAGS_DOWNLOAD_IN_PROGRESS (0x80)
0927 #define MPI3_CI_DOWNLOAD_FLAGS_OFFLINE_ACTIVATION_REQUIRED (0x20)
0928 #define MPI3_CI_DOWNLOAD_FLAGS_KEY_UPDATE_PENDING (0x10)
0929 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_MASK (0x0e)
0930 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_NOT_NEEDED (0x00)
0931 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_AWAITING (0x02)
0932 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_ONLINE_PENDING (0x04)
0933 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_OFFLINE_PENDING (0x06)
0934 #define MPI3_CI_DOWNLOAD_FLAGS_COMPATIBLE (0x01)
0935 struct mpi3_ci_upload_request {
0936 __le16 host_tag;
0937 u8 ioc_use_only02;
0938 u8 function;
0939 __le16 ioc_use_only04;
0940 u8 ioc_use_only06;
0941 u8 msg_flags;
0942 __le16 change_count;
0943 __le16 reserved0a;
0944 __le32 signature1;
0945 __le32 reserved10;
0946 __le32 image_offset;
0947 __le32 segment_size;
0948 __le32 reserved1c;
0949 union mpi3_sge_union sgl;
0950 };
0951
0952 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_MASK (0x01)
0953 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY (0x00)
0954 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_SECONDARY (0x01)
0955 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_MASK (0x02)
0956 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_FLASH (0x00)
0957 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_EXECUTABLE (0x02)
0958 #define MPI3_CTRL_OP_FORCE_FULL_DISCOVERY (0x01)
0959 #define MPI3_CTRL_OP_LOOKUP_MAPPING (0x02)
0960 #define MPI3_CTRL_OP_UPDATE_TIMESTAMP (0x04)
0961 #define MPI3_CTRL_OP_GET_TIMESTAMP (0x05)
0962 #define MPI3_CTRL_OP_GET_IOC_CHANGE_COUNT (0x06)
0963 #define MPI3_CTRL_OP_CHANGE_PROFILE (0x07)
0964 #define MPI3_CTRL_OP_REMOVE_DEVICE (0x10)
0965 #define MPI3_CTRL_OP_CLOSE_PERSISTENT_CONNECTION (0x11)
0966 #define MPI3_CTRL_OP_HIDDEN_ACK (0x12)
0967 #define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS (0x13)
0968 #define MPI3_CTRL_OP_SEND_SAS_PRIMITIVE (0x20)
0969 #define MPI3_CTRL_OP_SAS_PHY_CONTROL (0x21)
0970 #define MPI3_CTRL_OP_READ_INTERNAL_BUS (0x23)
0971 #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS (0x24)
0972 #define MPI3_CTRL_OP_PCIE_LINK_CONTROL (0x30)
0973 #define MPI3_CTRL_OP_LOOKUP_MAPPING_PARAM8_LOOKUP_METHOD_INDEX (0x00)
0974 #define MPI3_CTRL_OP_UPDATE_TIMESTAMP_PARAM64_TIMESTAMP_INDEX (0x00)
0975 #define MPI3_CTRL_OP_CHANGE_PROFILE_PARAM8_PROFILE_ID_INDEX (0x00)
0976 #define MPI3_CTRL_OP_REMOVE_DEVICE_PARAM16_DEVHANDLE_INDEX (0x00)
0977 #define MPI3_CTRL_OP_CLOSE_PERSIST_CONN_PARAM16_DEVHANDLE_INDEX (0x00)
0978 #define MPI3_CTRL_OP_HIDDEN_ACK_PARAM16_DEVHANDLE_INDEX (0x00)
0979 #define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS_PARAM16_DEVHANDLE_INDEX (0x00)
0980 #define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM8_PHY_INDEX (0x00)
0981 #define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM8_PRIMSEQ_INDEX (0x01)
0982 #define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM32_PRIMITIVE_INDEX (0x00)
0983 #define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_ACTION_INDEX (0x00)
0984 #define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_PHY_INDEX (0x01)
0985 #define MPI3_CTRL_OP_READ_INTERNAL_BUS_PARAM64_ADDRESS_INDEX (0x00)
0986 #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM64_ADDRESS_INDEX (0x00)
0987 #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM32_VALUE_INDEX (0x00)
0988 #define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_ACTION_INDEX (0x00)
0989 #define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_LINK_INDEX (0x01)
0990 #define MPI3_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01)
0991 #define MPI3_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02)
0992 #define MPI3_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03)
0993 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTENT_ID (0x04)
0994 #define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM16_DEVH_INDEX (0)
0995 #define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM64_WWID_INDEX (0)
0996 #define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM16_SLOTNUM_INDEX (0)
0997 #define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM64_ENCLOSURELID_INDEX (0)
0998 #define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM16_DEVH_INDEX (0)
0999 #define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM64_DEVNAME_INDEX (0)
1000 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_DEVH_INDEX (0)
1001 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_PERSISTENT_ID_INDEX (1)
1002 #define MPI3_CTRL_LOOKUP_METHOD_VALUE16_DEVH_INDEX (0)
1003 #define MPI3_CTRL_GET_TIMESTAMP_VALUE64_TIMESTAMP_INDEX (0)
1004 #define MPI3_CTRL_GET_IOC_CHANGE_COUNT_VALUE16_CHANGECOUNT_INDEX (0)
1005 #define MPI3_CTRL_READ_INTERNAL_BUS_VALUE32_VALUE_INDEX (0)
1006 #define MPI3_CTRL_PRIMFLAGS_SINGLE (0x01)
1007 #define MPI3_CTRL_PRIMFLAGS_TRIPLE (0x03)
1008 #define MPI3_CTRL_PRIMFLAGS_REDUNDANT (0x06)
1009 #define MPI3_CTRL_ACTION_NOP (0x00)
1010 #define MPI3_CTRL_ACTION_LINK_RESET (0x01)
1011 #define MPI3_CTRL_ACTION_HARD_RESET (0x02)
1012 #define MPI3_CTRL_ACTION_CLEAR_ERROR_LOG (0x05)
1013 struct mpi3_iounit_control_request {
1014 __le16 host_tag;
1015 u8 ioc_use_only02;
1016 u8 function;
1017 __le16 ioc_use_only04;
1018 u8 ioc_use_only06;
1019 u8 msg_flags;
1020 __le16 change_count;
1021 u8 reserved0a;
1022 u8 operation;
1023 __le32 reserved0c;
1024 __le64 param64[2];
1025 __le32 param32[4];
1026 __le16 param16[4];
1027 u8 param8[8];
1028 };
1029
1030 struct mpi3_iounit_control_reply {
1031 __le16 host_tag;
1032 u8 ioc_use_only02;
1033 u8 function;
1034 __le16 ioc_use_only04;
1035 u8 ioc_use_only06;
1036 u8 msg_flags;
1037 __le16 ioc_use_only08;
1038 __le16 ioc_status;
1039 __le32 ioc_log_info;
1040 __le64 value64[2];
1041 __le32 value32[4];
1042 __le16 value16[4];
1043 u8 value8[8];
1044 };
1045 #endif
