drivers/scsi/mesh.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * mesh.h: definitions for the driver for the MESH SCSI bus adaptor
0004  * (Macintosh Enhanced SCSI Hardware) found on Power Macintosh computers.
0005  *
0006  * Copyright (C) 1996 Paul Mackerras.
0007  */
0008 #ifndef _MESH_H
0009 #define _MESH_H
0010
0011 struct mesh_cmd_priv {
0012     int this_residual;
0013     int message;
0014     int status;
0015 };
0016
0017 static inline struct mesh_cmd_priv *mesh_priv(struct scsi_cmnd *cmd)
0018 {
0019     return scsi_cmd_priv(cmd);
0020 }
0021
0022 /*
0023  * Registers in the MESH controller.
0024  */
0025
0026 struct mesh_regs {
0027     unsigned char   count_lo;
0028     char pad0[15];
0029     unsigned char   count_hi;
0030     char pad1[15];
0031     unsigned char   fifo;
0032     char pad2[15];
0033     unsigned char   sequence;
0034     char pad3[15];
0035     unsigned char   bus_status0;
0036     char pad4[15];
0037     unsigned char   bus_status1;
0038     char pad5[15];
0039     unsigned char   fifo_count;
0040     char pad6[15];
0041     unsigned char   exception;
0042     char pad7[15];
0043     unsigned char   error;
0044     char pad8[15];
0045     unsigned char   intr_mask;
0046     char pad9[15];
0047     unsigned char   interrupt;
0048     char pad10[15];
0049     unsigned char   source_id;
0050     char pad11[15];
0051     unsigned char   dest_id;
0052     char pad12[15];
0053     unsigned char   sync_params;
0054     char pad13[15];
0055     unsigned char   mesh_id;
0056     char pad14[15];
0057     unsigned char   sel_timeout;
0058     char pad15[15];
0059 };
0060
0061 /* Bits in the sequence register. */
0062 #define SEQ_DMA_MODE    0x80    /* use DMA for data transfer */
0063 #define SEQ_TARGET  0x40    /* put the controller into target mode */
0064 #define SEQ_ATN     0x20    /* assert ATN signal */
0065 #define SEQ_ACTIVE_NEG  0x10    /* use active negation on REQ/ACK */
0066 #define SEQ_CMD     0x0f    /* command bits: */
0067 #define SEQ_ARBITRATE   1   /*  get the bus */
0068 #define SEQ_SELECT  2   /*  select a target */
0069 #define SEQ_COMMAND 3   /*  send a command */
0070 #define SEQ_STATUS  4   /*  receive status */
0071 #define SEQ_DATAOUT 5   /*  send data */
0072 #define SEQ_DATAIN  6   /*  receive data */
0073 #define SEQ_MSGOUT  7   /*  send a message */
0074 #define SEQ_MSGIN   8   /*  receive a message */
0075 #define SEQ_BUSFREE 9   /*  look for bus free */
0076 #define SEQ_ENBPARITY   0x0a    /*  enable parity checking */
0077 #define SEQ_DISPARITY   0x0b    /*  disable parity checking */
0078 #define SEQ_ENBRESEL    0x0c    /*  enable reselection */
0079 #define SEQ_DISRESEL    0x0d    /*  disable reselection */
0080 #define SEQ_RESETMESH   0x0e    /*  reset the controller */
0081 #define SEQ_FLUSHFIFO   0x0f    /*  clear out the FIFO */
0082
0083 /* Bits in the bus_status0 and bus_status1 registers:
0084    these correspond directly to the SCSI bus control signals. */
0085 #define BS0_REQ     0x20
0086 #define BS0_ACK     0x10
0087 #define BS0_ATN     0x08
0088 #define BS0_MSG     0x04
0089 #define BS0_CD      0x02
0090 #define BS0_IO      0x01
0091 #define BS1_RST     0x80
0092 #define BS1_BSY     0x40
0093 #define BS1_SEL     0x20
0094
0095 /* Bus phases defined by the bits in bus_status0 */
0096 #define BS0_PHASE   (BS0_MSG+BS0_CD+BS0_IO)
0097 #define BP_DATAOUT  0
0098 #define BP_DATAIN   BS0_IO
0099 #define BP_COMMAND  BS0_CD
0100 #define BP_STATUS   (BS0_CD+BS0_IO)
0101 #define BP_MSGOUT   (BS0_MSG+BS0_CD)
0102 #define BP_MSGIN    (BS0_MSG+BS0_CD+BS0_IO)
0103
0104 /* Bits in the exception register. */
0105 #define EXC_SELWATN 0x20    /* (as target) we were selected with ATN */
0106 #define EXC_SELECTED    0x10    /* (as target) we were selected w/o ATN */
0107 #define EXC_RESELECTED  0x08    /* (as initiator) we were reselected */
0108 #define EXC_ARBLOST 0x04    /* we lost arbitration */
0109 #define EXC_PHASEMM 0x02    /* SCSI phase mismatch */
0110 #define EXC_SELTO   0x01    /* selection timeout */
0111
0112 /* Bits in the error register */
0113 #define ERR_UNEXPDISC   0x40    /* target unexpectedly disconnected */
0114 #define ERR_SCSIRESET   0x20    /* SCSI bus got reset on us */
0115 #define ERR_SEQERR  0x10    /* we did something the chip didn't like */
0116 #define ERR_PARITY  0x01    /* parity error was detected */
0117
0118 /* Bits in the interrupt and intr_mask registers */
0119 #define INT_ERROR   0x04    /* error interrupt */
0120 #define INT_EXCEPTION   0x02    /* exception interrupt */
0121 #define INT_CMDDONE 0x01    /* command done interrupt */
0122
0123 /* Fields in the sync_params register */
0124 #define SYNC_OFF(x) ((x) >> 4)  /* offset field */
0125 #define SYNC_PER(x) ((x) & 0xf) /* period field */
0126 #define SYNC_PARAMS(o, p)   (((o) << 4) | (p))
0127 #define ASYNC_PARAMS    2   /* sync_params value for async xfers */
0128
0129 /*
0130  * Assuming a clock frequency of 50MHz:
0131  *
0132  * The transfer period with SYNC_PER(sync_params) == x
0133  * is (x + 2) * 40ns, except that x == 0 gives 100ns.
0134  *
0135  * The units of the sel_timeout register are 10ms.
0136  */
0137
0138
0139 #endif /* _MESH_H */