Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
0004  * bus adaptor found on Power Macintosh computers.
0005  * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
0006  * controller.
0007  *
0008  * Paul Mackerras, August 1996.
0009  * Copyright (C) 1996 Paul Mackerras.
0010  *
0011  * Apr. 21 2002  - BenH     Rework bus reset code for new error handler
0012  *                              Add delay after initial bus reset
0013  *                              Add module parameters
0014  *
0015  * Sep. 27 2003  - BenH     Move to new driver model, fix some write posting
0016  *              issues
0017  * To do:
0018  * - handle aborts correctly
0019  * - retry arbitration if lost (unless higher levels do this for us)
0020  * - power down the chip when no device is detected
0021  */
0022 #include <linux/module.h>
0023 #include <linux/kernel.h>
0024 #include <linux/delay.h>
0025 #include <linux/types.h>
0026 #include <linux/string.h>
0027 #include <linux/blkdev.h>
0028 #include <linux/proc_fs.h>
0029 #include <linux/stat.h>
0030 #include <linux/interrupt.h>
0031 #include <linux/reboot.h>
0032 #include <linux/spinlock.h>
0033 #include <linux/pci.h>
0034 #include <linux/pgtable.h>
0035 #include <asm/dbdma.h>
0036 #include <asm/io.h>
0037 #include <asm/prom.h>
0038 #include <asm/irq.h>
0039 #include <asm/hydra.h>
0040 #include <asm/processor.h>
0041 #include <asm/setup.h>
0042 #include <asm/pmac_feature.h>
0043 #include <asm/macio.h>
0044 
0045 #include <scsi/scsi.h>
0046 #include <scsi/scsi_cmnd.h>
0047 #include <scsi/scsi_device.h>
0048 #include <scsi/scsi_host.h>
0049 
0050 #include "mesh.h"
0051 
0052 #if 1
0053 #undef KERN_DEBUG
0054 #define KERN_DEBUG KERN_WARNING
0055 #endif
0056 
0057 MODULE_AUTHOR("Paul Mackerras (paulus@samba.org)");
0058 MODULE_DESCRIPTION("PowerMac MESH SCSI driver");
0059 MODULE_LICENSE("GPL");
0060 
0061 static int sync_rate = CONFIG_SCSI_MESH_SYNC_RATE;
0062 static int sync_targets = 0xff;
0063 static int resel_targets = 0xff;
0064 static int debug_targets = 0;   /* print debug for these targets */
0065 static int init_reset_delay = CONFIG_SCSI_MESH_RESET_DELAY_MS;
0066 
0067 module_param(sync_rate, int, 0);
0068 MODULE_PARM_DESC(sync_rate, "Synchronous rate (0..10, 0=async)");
0069 module_param(sync_targets, int, 0);
0070 MODULE_PARM_DESC(sync_targets, "Bitmask of targets allowed to set synchronous");
0071 module_param(resel_targets, int, 0);
0072 MODULE_PARM_DESC(resel_targets, "Bitmask of targets allowed to set disconnect");
0073 module_param(debug_targets, int, 0644);
0074 MODULE_PARM_DESC(debug_targets, "Bitmask of debugged targets");
0075 module_param(init_reset_delay, int, 0);
0076 MODULE_PARM_DESC(init_reset_delay, "Initial bus reset delay (0=no reset)");
0077 
0078 static int mesh_sync_period = 100;
0079 static int mesh_sync_offset = 0;
0080 static unsigned char use_active_neg = 0;  /* bit mask for SEQ_ACTIVE_NEG if used */
0081 
0082 #define ALLOW_SYNC(tgt)     ((sync_targets >> (tgt)) & 1)
0083 #define ALLOW_RESEL(tgt)    ((resel_targets >> (tgt)) & 1)
0084 #define ALLOW_DEBUG(tgt)    ((debug_targets >> (tgt)) & 1)
0085 #define DEBUG_TARGET(cmd)   ((cmd) && ALLOW_DEBUG((cmd)->device->id))
0086 
0087 #undef MESH_DBG
0088 #define N_DBG_LOG   50
0089 #define N_DBG_SLOG  20
0090 #define NUM_DBG_EVENTS  13
0091 #undef  DBG_USE_TB      /* bombs on 601 */
0092 
0093 struct dbglog {
0094     char    *fmt;
0095     u32 tb;
0096     u8  phase;
0097     u8  bs0;
0098     u8  bs1;
0099     u8  tgt;
0100     int d;
0101 };
0102 
0103 enum mesh_phase {
0104     idle,
0105     arbitrating,
0106     selecting,
0107     commanding,
0108     dataing,
0109     statusing,
0110     busfreeing,
0111     disconnecting,
0112     reselecting,
0113     sleeping
0114 };
0115 
0116 enum msg_phase {
0117     msg_none,
0118     msg_out,
0119     msg_out_xxx,
0120     msg_out_last,
0121     msg_in,
0122     msg_in_bad,
0123 };
0124 
0125 enum sdtr_phase {
0126     do_sdtr,
0127     sdtr_sent,
0128     sdtr_done
0129 };
0130 
0131 struct mesh_target {
0132     enum sdtr_phase sdtr_state;
0133     int sync_params;
0134     int data_goes_out;      /* guess as to data direction */
0135     struct scsi_cmnd *current_req;
0136     u32 saved_ptr;
0137 #ifdef MESH_DBG
0138     int log_ix;
0139     int n_log;
0140     struct dbglog log[N_DBG_LOG];
0141 #endif
0142 };
0143 
0144 struct mesh_state {
0145     volatile struct mesh_regs __iomem *mesh;
0146     int meshintr;
0147     volatile struct dbdma_regs __iomem *dma;
0148     int dmaintr;
0149     struct  Scsi_Host *host;
0150     struct  mesh_state *next;
0151     struct scsi_cmnd *request_q;
0152     struct scsi_cmnd *request_qtail;
0153     enum mesh_phase phase;      /* what we're currently trying to do */
0154     enum msg_phase msgphase;
0155     int conn_tgt;       /* target we're connected to */
0156     struct scsi_cmnd *current_req;      /* req we're currently working on */
0157     int data_ptr;
0158     int dma_started;
0159     int dma_count;
0160     int stat;
0161     int aborting;
0162     int expect_reply;
0163     int n_msgin;
0164     u8  msgin[16];
0165     int n_msgout;
0166     int last_n_msgout;
0167     u8  msgout[16];
0168     struct dbdma_cmd *dma_cmds; /* space for dbdma commands, aligned */
0169     dma_addr_t dma_cmd_bus;
0170     void    *dma_cmd_space;
0171     int dma_cmd_size;
0172     int clk_freq;
0173     struct mesh_target tgts[8];
0174     struct macio_dev *mdev;
0175     struct pci_dev* pdev;
0176 #ifdef MESH_DBG
0177     int log_ix;
0178     int n_log;
0179     struct dbglog log[N_DBG_SLOG];
0180 #endif
0181 };
0182 
0183 /*
0184  * Driver is too messy, we need a few prototypes...
0185  */
0186 static void mesh_done(struct mesh_state *ms, int start_next);
0187 static void mesh_interrupt(struct mesh_state *ms);
0188 static void cmd_complete(struct mesh_state *ms);
0189 static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd);
0190 static void halt_dma(struct mesh_state *ms);
0191 static void phase_mismatch(struct mesh_state *ms);
0192 
0193 
0194 /*
0195  * Some debugging & logging routines
0196  */
0197 
0198 #ifdef MESH_DBG
0199 
0200 static inline u32 readtb(void)
0201 {
0202     u32 tb;
0203 
0204 #ifdef DBG_USE_TB
0205     /* Beware: if you enable this, it will crash on 601s. */
0206     asm ("mftb %0" : "=r" (tb) : );
0207 #else
0208     tb = 0;
0209 #endif
0210     return tb;
0211 }
0212 
0213 static void dlog(struct mesh_state *ms, char *fmt, int a)
0214 {
0215     struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
0216     struct dbglog *tlp, *slp;
0217 
0218     tlp = &tp->log[tp->log_ix];
0219     slp = &ms->log[ms->log_ix];
0220     tlp->fmt = fmt;
0221     tlp->tb = readtb();
0222     tlp->phase = (ms->msgphase << 4) + ms->phase;
0223     tlp->bs0 = ms->mesh->bus_status0;
0224     tlp->bs1 = ms->mesh->bus_status1;
0225     tlp->tgt = ms->conn_tgt;
0226     tlp->d = a;
0227     *slp = *tlp;
0228     if (++tp->log_ix >= N_DBG_LOG)
0229         tp->log_ix = 0;
0230     if (tp->n_log < N_DBG_LOG)
0231         ++tp->n_log;
0232     if (++ms->log_ix >= N_DBG_SLOG)
0233         ms->log_ix = 0;
0234     if (ms->n_log < N_DBG_SLOG)
0235         ++ms->n_log;
0236 }
0237 
0238 static void dumplog(struct mesh_state *ms, int t)
0239 {
0240     struct mesh_target *tp = &ms->tgts[t];
0241     struct dbglog *lp;
0242     int i;
0243 
0244     if (tp->n_log == 0)
0245         return;
0246     i = tp->log_ix - tp->n_log;
0247     if (i < 0)
0248         i += N_DBG_LOG;
0249     tp->n_log = 0;
0250     do {
0251         lp = &tp->log[i];
0252         printk(KERN_DEBUG "mesh log %d: bs=%.2x%.2x ph=%.2x ",
0253                t, lp->bs1, lp->bs0, lp->phase);
0254 #ifdef DBG_USE_TB
0255         printk("tb=%10u ", lp->tb);
0256 #endif
0257         printk(lp->fmt, lp->d);
0258         printk("\n");
0259         if (++i >= N_DBG_LOG)
0260             i = 0;
0261     } while (i != tp->log_ix);
0262 }
0263 
0264 static void dumpslog(struct mesh_state *ms)
0265 {
0266     struct dbglog *lp;
0267     int i;
0268 
0269     if (ms->n_log == 0)
0270         return;
0271     i = ms->log_ix - ms->n_log;
0272     if (i < 0)
0273         i += N_DBG_SLOG;
0274     ms->n_log = 0;
0275     do {
0276         lp = &ms->log[i];
0277         printk(KERN_DEBUG "mesh log: bs=%.2x%.2x ph=%.2x t%d ",
0278                lp->bs1, lp->bs0, lp->phase, lp->tgt);
0279 #ifdef DBG_USE_TB
0280         printk("tb=%10u ", lp->tb);
0281 #endif
0282         printk(lp->fmt, lp->d);
0283         printk("\n");
0284         if (++i >= N_DBG_SLOG)
0285             i = 0;
0286     } while (i != ms->log_ix);
0287 }
0288 
0289 #else
0290 
0291 static inline void dlog(struct mesh_state *ms, char *fmt, int a)
0292 {}
0293 static inline void dumplog(struct mesh_state *ms, int tgt)
0294 {}
0295 static inline void dumpslog(struct mesh_state *ms)
0296 {}
0297 
0298 #endif /* MESH_DBG */
0299 
0300 #define MKWORD(a, b, c, d)  (((a) << 24) + ((b) << 16) + ((c) << 8) + (d))
0301 
0302 static void
0303 mesh_dump_regs(struct mesh_state *ms)
0304 {
0305     volatile struct mesh_regs __iomem *mr = ms->mesh;
0306     volatile struct dbdma_regs __iomem *md = ms->dma;
0307     int t;
0308     struct mesh_target *tp;
0309 
0310     printk(KERN_DEBUG "mesh: state at %p, regs at %p, dma at %p\n",
0311            ms, mr, md);
0312     printk(KERN_DEBUG "    ct=%4x seq=%2x bs=%4x fc=%2x "
0313            "exc=%2x err=%2x im=%2x int=%2x sp=%2x\n",
0314            (mr->count_hi << 8) + mr->count_lo, mr->sequence,
0315            (mr->bus_status1 << 8) + mr->bus_status0, mr->fifo_count,
0316            mr->exception, mr->error, mr->intr_mask, mr->interrupt,
0317            mr->sync_params);
0318     while(in_8(&mr->fifo_count))
0319         printk(KERN_DEBUG " fifo data=%.2x\n",in_8(&mr->fifo));
0320     printk(KERN_DEBUG "    dma stat=%x cmdptr=%x\n",
0321            in_le32(&md->status), in_le32(&md->cmdptr));
0322     printk(KERN_DEBUG "    phase=%d msgphase=%d conn_tgt=%d data_ptr=%d\n",
0323            ms->phase, ms->msgphase, ms->conn_tgt, ms->data_ptr);
0324     printk(KERN_DEBUG "    dma_st=%d dma_ct=%d n_msgout=%d\n",
0325            ms->dma_started, ms->dma_count, ms->n_msgout);
0326     for (t = 0; t < 8; ++t) {
0327         tp = &ms->tgts[t];
0328         if (tp->current_req == NULL)
0329             continue;
0330         printk(KERN_DEBUG "    target %d: req=%p goes_out=%d saved_ptr=%d\n",
0331                t, tp->current_req, tp->data_goes_out, tp->saved_ptr);
0332     }
0333 }
0334 
0335 
0336 /*
0337  * Flush write buffers on the bus path to the mesh
0338  */
0339 static inline void mesh_flush_io(volatile struct mesh_regs __iomem *mr)
0340 {
0341     (void)in_8(&mr->mesh_id);
0342 }
0343 
0344 
0345 /* Called with  meshinterrupt disabled, initialize the chipset
0346  * and eventually do the initial bus reset. The lock must not be
0347  * held since we can schedule.
0348  */
0349 static void mesh_init(struct mesh_state *ms)
0350 {
0351     volatile struct mesh_regs __iomem *mr = ms->mesh;
0352     volatile struct dbdma_regs __iomem *md = ms->dma;
0353 
0354     mesh_flush_io(mr);
0355     udelay(100);
0356 
0357     /* Reset controller */
0358     out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16);   /* stop dma */
0359     out_8(&mr->exception, 0xff);    /* clear all exception bits */
0360     out_8(&mr->error, 0xff);    /* clear all error bits */
0361     out_8(&mr->sequence, SEQ_RESETMESH);
0362     mesh_flush_io(mr);
0363     udelay(10);
0364     out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
0365     out_8(&mr->source_id, ms->host->this_id);
0366     out_8(&mr->sel_timeout, 25);    /* 250ms */
0367     out_8(&mr->sync_params, ASYNC_PARAMS);
0368 
0369     if (init_reset_delay) {
0370         printk(KERN_INFO "mesh: performing initial bus reset...\n");
0371         
0372         /* Reset bus */
0373         out_8(&mr->bus_status1, BS1_RST);   /* assert RST */
0374         mesh_flush_io(mr);
0375         udelay(30);         /* leave it on for >= 25us */
0376         out_8(&mr->bus_status1, 0); /* negate RST */
0377         mesh_flush_io(mr);
0378 
0379         /* Wait for bus to come back */
0380         msleep(init_reset_delay);
0381     }
0382     
0383     /* Reconfigure controller */
0384     out_8(&mr->interrupt, 0xff);    /* clear all interrupt bits */
0385     out_8(&mr->sequence, SEQ_FLUSHFIFO);
0386     mesh_flush_io(mr);
0387     udelay(1);
0388     out_8(&mr->sync_params, ASYNC_PARAMS);
0389     out_8(&mr->sequence, SEQ_ENBRESEL);
0390 
0391     ms->phase = idle;
0392     ms->msgphase = msg_none;
0393 }
0394 
0395 
0396 static void mesh_start_cmd(struct mesh_state *ms, struct scsi_cmnd *cmd)
0397 {
0398     volatile struct mesh_regs __iomem *mr = ms->mesh;
0399     int t, id;
0400 
0401     id = cmd->device->id;
0402     ms->current_req = cmd;
0403     ms->tgts[id].data_goes_out = cmd->sc_data_direction == DMA_TO_DEVICE;
0404     ms->tgts[id].current_req = cmd;
0405 
0406 #if 1
0407     if (DEBUG_TARGET(cmd)) {
0408         int i;
0409         printk(KERN_DEBUG "mesh_start: %p tgt=%d cmd=", cmd, id);
0410         for (i = 0; i < cmd->cmd_len; ++i)
0411             printk(" %x", cmd->cmnd[i]);
0412         printk(" use_sg=%d buffer=%p bufflen=%u\n",
0413                scsi_sg_count(cmd), scsi_sglist(cmd), scsi_bufflen(cmd));
0414     }
0415 #endif
0416     if (ms->dma_started)
0417         panic("mesh: double DMA start !\n");
0418 
0419     ms->phase = arbitrating;
0420     ms->msgphase = msg_none;
0421     ms->data_ptr = 0;
0422     ms->dma_started = 0;
0423     ms->n_msgout = 0;
0424     ms->last_n_msgout = 0;
0425     ms->expect_reply = 0;
0426     ms->conn_tgt = id;
0427     ms->tgts[id].saved_ptr = 0;
0428     ms->stat = DID_OK;
0429     ms->aborting = 0;
0430 #ifdef MESH_DBG
0431     ms->tgts[id].n_log = 0;
0432     dlog(ms, "start cmd=%x", (int) cmd);
0433 #endif
0434 
0435     /* Off we go */
0436     dlog(ms, "about to arb, intr/exc/err/fc=%.8x",
0437          MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
0438     out_8(&mr->interrupt, INT_CMDDONE);
0439     out_8(&mr->sequence, SEQ_ENBRESEL);
0440     mesh_flush_io(mr);
0441     udelay(1);
0442 
0443     if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) {
0444         /*
0445          * Some other device has the bus or is arbitrating for it -
0446          * probably a target which is about to reselect us.
0447          */
0448         dlog(ms, "busy b4 arb, intr/exc/err/fc=%.8x",
0449              MKWORD(mr->interrupt, mr->exception,
0450                 mr->error, mr->fifo_count));
0451         for (t = 100; t > 0; --t) {
0452             if ((in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) == 0)
0453                 break;
0454             if (in_8(&mr->interrupt) != 0) {
0455                 dlog(ms, "intr b4 arb, intr/exc/err/fc=%.8x",
0456                      MKWORD(mr->interrupt, mr->exception,
0457                         mr->error, mr->fifo_count));
0458                 mesh_interrupt(ms);
0459                 if (ms->phase != arbitrating)
0460                     return;
0461             }
0462             udelay(1);
0463         }
0464         if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) {
0465             /* XXX should try again in a little while */
0466             ms->stat = DID_BUS_BUSY;
0467             ms->phase = idle;
0468             mesh_done(ms, 0);
0469             return;
0470         }
0471     }
0472 
0473     /*
0474      * Apparently the mesh has a bug where it will assert both its
0475      * own bit and the target's bit on the bus during arbitration.
0476      */
0477     out_8(&mr->dest_id, mr->source_id);
0478 
0479     /*
0480      * There appears to be a race with reselection sometimes,
0481      * where a target reselects us just as we issue the
0482      * arbitrate command.  It seems that then the arbitrate
0483      * command just hangs waiting for the bus to be free
0484      * without giving us a reselection exception.
0485      * The only way I have found to get it to respond correctly
0486      * is this: disable reselection before issuing the arbitrate
0487      * command, then after issuing it, if it looks like a target
0488      * is trying to reselect us, reset the mesh and then enable
0489      * reselection.
0490      */
0491     out_8(&mr->sequence, SEQ_DISRESEL);
0492     if (in_8(&mr->interrupt) != 0) {
0493         dlog(ms, "intr after disresel, intr/exc/err/fc=%.8x",
0494              MKWORD(mr->interrupt, mr->exception,
0495                 mr->error, mr->fifo_count));
0496         mesh_interrupt(ms);
0497         if (ms->phase != arbitrating)
0498             return;
0499         dlog(ms, "after intr after disresel, intr/exc/err/fc=%.8x",
0500              MKWORD(mr->interrupt, mr->exception,
0501                 mr->error, mr->fifo_count));
0502     }
0503 
0504     out_8(&mr->sequence, SEQ_ARBITRATE);
0505 
0506     for (t = 230; t > 0; --t) {
0507         if (in_8(&mr->interrupt) != 0)
0508             break;
0509         udelay(1);
0510     }
0511     dlog(ms, "after arb, intr/exc/err/fc=%.8x",
0512          MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
0513     if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL)
0514         && (in_8(&mr->bus_status0) & BS0_IO)) {
0515         /* looks like a reselection - try resetting the mesh */
0516         dlog(ms, "resel? after arb, intr/exc/err/fc=%.8x",
0517              MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
0518         out_8(&mr->sequence, SEQ_RESETMESH);
0519         mesh_flush_io(mr);
0520         udelay(10);
0521         out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
0522         out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
0523         out_8(&mr->sequence, SEQ_ENBRESEL);
0524         mesh_flush_io(mr);
0525         for (t = 10; t > 0 && in_8(&mr->interrupt) == 0; --t)
0526             udelay(1);
0527         dlog(ms, "tried reset after arb, intr/exc/err/fc=%.8x",
0528              MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
0529 #ifndef MESH_MULTIPLE_HOSTS
0530         if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL)
0531             && (in_8(&mr->bus_status0) & BS0_IO)) {
0532             printk(KERN_ERR "mesh: controller not responding"
0533                    " to reselection!\n");
0534             /*
0535              * If this is a target reselecting us, and the
0536              * mesh isn't responding, the higher levels of
0537              * the scsi code will eventually time out and
0538              * reset the bus.
0539              */
0540         }
0541 #endif
0542     }
0543 }
0544 
0545 /*
0546  * Start the next command for a MESH.
0547  * Should be called with interrupts disabled.
0548  */
0549 static void mesh_start(struct mesh_state *ms)
0550 {
0551     struct scsi_cmnd *cmd, *prev, *next;
0552 
0553     if (ms->phase != idle || ms->current_req != NULL) {
0554         printk(KERN_ERR "inappropriate mesh_start (phase=%d, ms=%p)",
0555                ms->phase, ms);
0556         return;
0557     }
0558 
0559     while (ms->phase == idle) {
0560         prev = NULL;
0561         for (cmd = ms->request_q; ; cmd = (struct scsi_cmnd *) cmd->host_scribble) {
0562             if (cmd == NULL)
0563                 return;
0564             if (ms->tgts[cmd->device->id].current_req == NULL)
0565                 break;
0566             prev = cmd;
0567         }
0568         next = (struct scsi_cmnd *) cmd->host_scribble;
0569         if (prev == NULL)
0570             ms->request_q = next;
0571         else
0572             prev->host_scribble = (void *) next;
0573         if (next == NULL)
0574             ms->request_qtail = prev;
0575 
0576         mesh_start_cmd(ms, cmd);
0577     }
0578 }
0579 
0580 static void mesh_done(struct mesh_state *ms, int start_next)
0581 {
0582     struct scsi_cmnd *cmd;
0583     struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
0584 
0585     cmd = ms->current_req;
0586     ms->current_req = NULL;
0587     tp->current_req = NULL;
0588     if (cmd) {
0589         struct mesh_cmd_priv *mcmd = mesh_priv(cmd);
0590 
0591         set_host_byte(cmd, ms->stat);
0592         set_status_byte(cmd, mcmd->status);
0593         if (ms->stat == DID_OK)
0594             scsi_msg_to_host_byte(cmd, mcmd->message);
0595         if (DEBUG_TARGET(cmd)) {
0596             printk(KERN_DEBUG "mesh_done: result = %x, data_ptr=%d, buflen=%d\n",
0597                    cmd->result, ms->data_ptr, scsi_bufflen(cmd));
0598 #if 0
0599             /* needs to use sg? */
0600             if ((cmd->cmnd[0] == 0 || cmd->cmnd[0] == 0x12 || cmd->cmnd[0] == 3)
0601                 && cmd->request_buffer != 0) {
0602                 unsigned char *b = cmd->request_buffer;
0603                 printk(KERN_DEBUG "buffer = %x %x %x %x %x %x %x %x\n",
0604                        b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
0605             }
0606 #endif
0607         }
0608         mcmd->this_residual -= ms->data_ptr;
0609         scsi_done(cmd);
0610     }
0611     if (start_next) {
0612         out_8(&ms->mesh->sequence, SEQ_ENBRESEL);
0613         mesh_flush_io(ms->mesh);
0614         udelay(1);
0615         ms->phase = idle;
0616         mesh_start(ms);
0617     }
0618 }
0619 
0620 static inline void add_sdtr_msg(struct mesh_state *ms)
0621 {
0622     int i = ms->n_msgout;
0623 
0624     ms->msgout[i] = EXTENDED_MESSAGE;
0625     ms->msgout[i+1] = 3;
0626     ms->msgout[i+2] = EXTENDED_SDTR;
0627     ms->msgout[i+3] = mesh_sync_period/4;
0628     ms->msgout[i+4] = (ALLOW_SYNC(ms->conn_tgt)? mesh_sync_offset: 0);
0629     ms->n_msgout = i + 5;
0630 }
0631 
0632 static void set_sdtr(struct mesh_state *ms, int period, int offset)
0633 {
0634     struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
0635     volatile struct mesh_regs __iomem *mr = ms->mesh;
0636     int v, tr;
0637 
0638     tp->sdtr_state = sdtr_done;
0639     if (offset == 0) {
0640         /* asynchronous */
0641         if (SYNC_OFF(tp->sync_params))
0642             printk(KERN_INFO "mesh: target %d now asynchronous\n",
0643                    ms->conn_tgt);
0644         tp->sync_params = ASYNC_PARAMS;
0645         out_8(&mr->sync_params, ASYNC_PARAMS);
0646         return;
0647     }
0648     /*
0649      * We need to compute ceil(clk_freq * period / 500e6) - 2
0650      * without incurring overflow.
0651      */
0652     v = (ms->clk_freq / 5000) * period;
0653     if (v <= 250000) {
0654         /* special case: sync_period == 5 * clk_period */
0655         v = 0;
0656         /* units of tr are 100kB/s */
0657         tr = (ms->clk_freq + 250000) / 500000;
0658     } else {
0659         /* sync_period == (v + 2) * 2 * clk_period */
0660         v = (v + 99999) / 100000 - 2;
0661         if (v > 15)
0662             v = 15; /* oops */
0663         tr = ((ms->clk_freq / (v + 2)) + 199999) / 200000;
0664     }
0665     if (offset > 15)
0666         offset = 15;    /* can't happen */
0667     tp->sync_params = SYNC_PARAMS(offset, v);
0668     out_8(&mr->sync_params, tp->sync_params);
0669     printk(KERN_INFO "mesh: target %d synchronous at %d.%d MB/s\n",
0670            ms->conn_tgt, tr/10, tr%10);
0671 }
0672 
0673 static void start_phase(struct mesh_state *ms)
0674 {
0675     int i, seq, nb;
0676     volatile struct mesh_regs __iomem *mr = ms->mesh;
0677     volatile struct dbdma_regs __iomem *md = ms->dma;
0678     struct scsi_cmnd *cmd = ms->current_req;
0679     struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
0680 
0681     dlog(ms, "start_phase nmo/exc/fc/seq = %.8x",
0682          MKWORD(ms->n_msgout, mr->exception, mr->fifo_count, mr->sequence));
0683     out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
0684     seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
0685     switch (ms->msgphase) {
0686     case msg_none:
0687         break;
0688 
0689     case msg_in:
0690         out_8(&mr->count_hi, 0);
0691         out_8(&mr->count_lo, 1);
0692         out_8(&mr->sequence, SEQ_MSGIN + seq);
0693         ms->n_msgin = 0;
0694         return;
0695 
0696     case msg_out:
0697         /*
0698          * To make sure ATN drops before we assert ACK for
0699          * the last byte of the message, we have to do the
0700          * last byte specially.
0701          */
0702         if (ms->n_msgout <= 0) {
0703             printk(KERN_ERR "mesh: msg_out but n_msgout=%d\n",
0704                    ms->n_msgout);
0705             mesh_dump_regs(ms);
0706             ms->msgphase = msg_none;
0707             break;
0708         }
0709         if (ALLOW_DEBUG(ms->conn_tgt)) {
0710             printk(KERN_DEBUG "mesh: sending %d msg bytes:",
0711                    ms->n_msgout);
0712             for (i = 0; i < ms->n_msgout; ++i)
0713                 printk(" %x", ms->msgout[i]);
0714             printk("\n");
0715         }
0716         dlog(ms, "msgout msg=%.8x", MKWORD(ms->n_msgout, ms->msgout[0],
0717                         ms->msgout[1], ms->msgout[2]));
0718         out_8(&mr->count_hi, 0);
0719         out_8(&mr->sequence, SEQ_FLUSHFIFO);
0720         mesh_flush_io(mr);
0721         udelay(1);
0722         /*
0723          * If ATN is not already asserted, we assert it, then
0724          * issue a SEQ_MSGOUT to get the mesh to drop ACK.
0725          */
0726         if ((in_8(&mr->bus_status0) & BS0_ATN) == 0) {
0727             dlog(ms, "bus0 was %.2x explicitly asserting ATN", mr->bus_status0);
0728             out_8(&mr->bus_status0, BS0_ATN); /* explicit ATN */
0729             mesh_flush_io(mr);
0730             udelay(1);
0731             out_8(&mr->count_lo, 1);
0732             out_8(&mr->sequence, SEQ_MSGOUT + seq);
0733             out_8(&mr->bus_status0, 0); /* release explicit ATN */
0734             dlog(ms,"hace: after explicit ATN bus0=%.2x",mr->bus_status0);
0735         }
0736         if (ms->n_msgout == 1) {
0737             /*
0738              * We can't issue the SEQ_MSGOUT without ATN
0739              * until the target has asserted REQ.  The logic
0740              * in cmd_complete handles both situations:
0741              * REQ already asserted or not.
0742              */
0743             cmd_complete(ms);
0744         } else {
0745             out_8(&mr->count_lo, ms->n_msgout - 1);
0746             out_8(&mr->sequence, SEQ_MSGOUT + seq);
0747             for (i = 0; i < ms->n_msgout - 1; ++i)
0748                 out_8(&mr->fifo, ms->msgout[i]);
0749         }
0750         return;
0751 
0752     default:
0753         printk(KERN_ERR "mesh bug: start_phase msgphase=%d\n",
0754                ms->msgphase);
0755     }
0756 
0757     switch (ms->phase) {
0758     case selecting:
0759         out_8(&mr->dest_id, ms->conn_tgt);
0760         out_8(&mr->sequence, SEQ_SELECT + SEQ_ATN);
0761         break;
0762     case commanding:
0763         out_8(&mr->sync_params, tp->sync_params);
0764         out_8(&mr->count_hi, 0);
0765         if (cmd) {
0766             out_8(&mr->count_lo, cmd->cmd_len);
0767             out_8(&mr->sequence, SEQ_COMMAND + seq);
0768             for (i = 0; i < cmd->cmd_len; ++i)
0769                 out_8(&mr->fifo, cmd->cmnd[i]);
0770         } else {
0771             out_8(&mr->count_lo, 6);
0772             out_8(&mr->sequence, SEQ_COMMAND + seq);
0773             for (i = 0; i < 6; ++i)
0774                 out_8(&mr->fifo, 0);
0775         }
0776         break;
0777     case dataing:
0778         /* transfer data, if any */
0779         if (!ms->dma_started) {
0780             set_dma_cmds(ms, cmd);
0781             out_le32(&md->cmdptr, virt_to_phys(ms->dma_cmds));
0782             out_le32(&md->control, (RUN << 16) | RUN);
0783             ms->dma_started = 1;
0784         }
0785         nb = ms->dma_count;
0786         if (nb > 0xfff0)
0787             nb = 0xfff0;
0788         ms->dma_count -= nb;
0789         ms->data_ptr += nb;
0790         out_8(&mr->count_lo, nb);
0791         out_8(&mr->count_hi, nb >> 8);
0792         out_8(&mr->sequence, (tp->data_goes_out?
0793                 SEQ_DATAOUT: SEQ_DATAIN) + SEQ_DMA_MODE + seq);
0794         break;
0795     case statusing:
0796         out_8(&mr->count_hi, 0);
0797         out_8(&mr->count_lo, 1);
0798         out_8(&mr->sequence, SEQ_STATUS + seq);
0799         break;
0800     case busfreeing:
0801     case disconnecting:
0802         out_8(&mr->sequence, SEQ_ENBRESEL);
0803         mesh_flush_io(mr);
0804         udelay(1);
0805         dlog(ms, "enbresel intr/exc/err/fc=%.8x",
0806              MKWORD(mr->interrupt, mr->exception, mr->error,
0807                 mr->fifo_count));
0808         out_8(&mr->sequence, SEQ_BUSFREE);
0809         break;
0810     default:
0811         printk(KERN_ERR "mesh: start_phase called with phase=%d\n",
0812                ms->phase);
0813         dumpslog(ms);
0814     }
0815 
0816 }
0817 
0818 static inline void get_msgin(struct mesh_state *ms)
0819 {
0820     volatile struct mesh_regs __iomem *mr = ms->mesh;
0821     int i, n;
0822 
0823     n = mr->fifo_count;
0824     if (n != 0) {
0825         i = ms->n_msgin;
0826         ms->n_msgin = i + n;
0827         for (; n > 0; --n)
0828             ms->msgin[i++] = in_8(&mr->fifo);
0829     }
0830 }
0831 
0832 static inline int msgin_length(struct mesh_state *ms)
0833 {
0834     int b, n;
0835 
0836     n = 1;
0837     if (ms->n_msgin > 0) {
0838         b = ms->msgin[0];
0839         if (b == 1) {
0840             /* extended message */
0841             n = ms->n_msgin < 2? 2: ms->msgin[1] + 2;
0842         } else if (0x20 <= b && b <= 0x2f) {
0843             /* 2-byte message */
0844             n = 2;
0845         }
0846     }
0847     return n;
0848 }
0849 
0850 static void reselected(struct mesh_state *ms)
0851 {
0852     volatile struct mesh_regs __iomem *mr = ms->mesh;
0853     struct scsi_cmnd *cmd;
0854     struct mesh_target *tp;
0855     int b, t, prev;
0856 
0857     switch (ms->phase) {
0858     case idle:
0859         break;
0860     case arbitrating:
0861         if ((cmd = ms->current_req) != NULL) {
0862             /* put the command back on the queue */
0863             cmd->host_scribble = (void *) ms->request_q;
0864             if (ms->request_q == NULL)
0865                 ms->request_qtail = cmd;
0866             ms->request_q = cmd;
0867             tp = &ms->tgts[cmd->device->id];
0868             tp->current_req = NULL;
0869         }
0870         break;
0871     case busfreeing:
0872         ms->phase = reselecting;
0873         mesh_done(ms, 0);
0874         break;
0875     case disconnecting:
0876         break;
0877     default:
0878         printk(KERN_ERR "mesh: reselected in phase %d/%d tgt %d\n",
0879                ms->msgphase, ms->phase, ms->conn_tgt);
0880         dumplog(ms, ms->conn_tgt);
0881         dumpslog(ms);
0882     }
0883 
0884     if (ms->dma_started) {
0885         printk(KERN_ERR "mesh: reselected with DMA started !\n");
0886         halt_dma(ms);
0887     }
0888     ms->current_req = NULL;
0889     ms->phase = dataing;
0890     ms->msgphase = msg_in;
0891     ms->n_msgout = 0;
0892     ms->last_n_msgout = 0;
0893     prev = ms->conn_tgt;
0894 
0895     /*
0896      * We seem to get abortive reselections sometimes.
0897      */
0898     while ((in_8(&mr->bus_status1) & BS1_BSY) == 0) {
0899         static int mesh_aborted_resels;
0900         mesh_aborted_resels++;
0901         out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
0902         mesh_flush_io(mr);
0903         udelay(1);
0904         out_8(&mr->sequence, SEQ_ENBRESEL);
0905         mesh_flush_io(mr);
0906         udelay(5);
0907         dlog(ms, "extra resel err/exc/fc = %.6x",
0908              MKWORD(0, mr->error, mr->exception, mr->fifo_count));
0909     }
0910     out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
0911         mesh_flush_io(mr);
0912     udelay(1);
0913     out_8(&mr->sequence, SEQ_ENBRESEL);
0914         mesh_flush_io(mr);
0915     udelay(1);
0916     out_8(&mr->sync_params, ASYNC_PARAMS);
0917 
0918     /*
0919      * Find out who reselected us.
0920      */
0921     if (in_8(&mr->fifo_count) == 0) {
0922         printk(KERN_ERR "mesh: reselection but nothing in fifo?\n");
0923         ms->conn_tgt = ms->host->this_id;
0924         goto bogus;
0925     }
0926     /* get the last byte in the fifo */
0927     do {
0928         b = in_8(&mr->fifo);
0929         dlog(ms, "reseldata %x", b);
0930     } while (in_8(&mr->fifo_count));
0931     for (t = 0; t < 8; ++t)
0932         if ((b & (1 << t)) != 0 && t != ms->host->this_id)
0933             break;
0934     if (b != (1 << t) + (1 << ms->host->this_id)) {
0935         printk(KERN_ERR "mesh: bad reselection data %x\n", b);
0936         ms->conn_tgt = ms->host->this_id;
0937         goto bogus;
0938     }
0939 
0940 
0941     /*
0942      * Set up to continue with that target's transfer.
0943      */
0944     ms->conn_tgt = t;
0945     tp = &ms->tgts[t];
0946     out_8(&mr->sync_params, tp->sync_params);
0947     if (ALLOW_DEBUG(t)) {
0948         printk(KERN_DEBUG "mesh: reselected by target %d\n", t);
0949         printk(KERN_DEBUG "mesh: saved_ptr=%x goes_out=%d cmd=%p\n",
0950                tp->saved_ptr, tp->data_goes_out, tp->current_req);
0951     }
0952     ms->current_req = tp->current_req;
0953     if (tp->current_req == NULL) {
0954         printk(KERN_ERR "mesh: reselected by tgt %d but no cmd!\n", t);
0955         goto bogus;
0956     }
0957     ms->data_ptr = tp->saved_ptr;
0958     dlog(ms, "resel prev tgt=%d", prev);
0959     dlog(ms, "resel err/exc=%.4x", MKWORD(0, 0, mr->error, mr->exception));
0960     start_phase(ms);
0961     return;
0962 
0963 bogus:
0964     dumplog(ms, ms->conn_tgt);
0965     dumpslog(ms);
0966     ms->data_ptr = 0;
0967     ms->aborting = 1;
0968     start_phase(ms);
0969 }
0970 
0971 static void do_abort(struct mesh_state *ms)
0972 {
0973     ms->msgout[0] = ABORT;
0974     ms->n_msgout = 1;
0975     ms->aborting = 1;
0976     ms->stat = DID_ABORT;
0977     dlog(ms, "abort", 0);
0978 }
0979 
0980 static void handle_reset(struct mesh_state *ms)
0981 {
0982     int tgt;
0983     struct mesh_target *tp;
0984     struct scsi_cmnd *cmd;
0985     volatile struct mesh_regs __iomem *mr = ms->mesh;
0986 
0987     for (tgt = 0; tgt < 8; ++tgt) {
0988         tp = &ms->tgts[tgt];
0989         if ((cmd = tp->current_req) != NULL) {
0990             set_host_byte(cmd, DID_RESET);
0991             tp->current_req = NULL;
0992             scsi_done(cmd);
0993         }
0994         ms->tgts[tgt].sdtr_state = do_sdtr;
0995         ms->tgts[tgt].sync_params = ASYNC_PARAMS;
0996     }
0997     ms->current_req = NULL;
0998     while ((cmd = ms->request_q) != NULL) {
0999         ms->request_q = (struct scsi_cmnd *) cmd->host_scribble;
1000         set_host_byte(cmd, DID_RESET);
1001         scsi_done(cmd);
1002     }
1003     ms->phase = idle;
1004     ms->msgphase = msg_none;
1005     out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1006     out_8(&mr->sequence, SEQ_FLUSHFIFO);
1007         mesh_flush_io(mr);
1008     udelay(1);
1009     out_8(&mr->sync_params, ASYNC_PARAMS);
1010     out_8(&mr->sequence, SEQ_ENBRESEL);
1011 }
1012 
1013 static irqreturn_t do_mesh_interrupt(int irq, void *dev_id)
1014 {
1015     unsigned long flags;
1016     struct mesh_state *ms = dev_id;
1017     struct Scsi_Host *dev = ms->host;
1018     
1019     spin_lock_irqsave(dev->host_lock, flags);
1020     mesh_interrupt(ms);
1021     spin_unlock_irqrestore(dev->host_lock, flags);
1022     return IRQ_HANDLED;
1023 }
1024 
1025 static void handle_error(struct mesh_state *ms)
1026 {
1027     int err, exc, count;
1028     volatile struct mesh_regs __iomem *mr = ms->mesh;
1029 
1030     err = in_8(&mr->error);
1031     exc = in_8(&mr->exception);
1032     out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1033     dlog(ms, "error err/exc/fc/cl=%.8x",
1034          MKWORD(err, exc, mr->fifo_count, mr->count_lo));
1035     if (err & ERR_SCSIRESET) {
1036         /* SCSI bus was reset */
1037         printk(KERN_INFO "mesh: SCSI bus reset detected: "
1038                "waiting for end...");
1039         while ((in_8(&mr->bus_status1) & BS1_RST) != 0)
1040             udelay(1);
1041         printk("done\n");
1042         if (ms->dma_started)
1043             halt_dma(ms);
1044         handle_reset(ms);
1045         /* request_q is empty, no point in mesh_start() */
1046         return;
1047     }
1048     if (err & ERR_UNEXPDISC) {
1049         /* Unexpected disconnect */
1050         if (exc & EXC_RESELECTED) {
1051             reselected(ms);
1052             return;
1053         }
1054         if (!ms->aborting) {
1055             printk(KERN_WARNING "mesh: target %d aborted\n",
1056                    ms->conn_tgt);
1057             dumplog(ms, ms->conn_tgt);
1058             dumpslog(ms);
1059         }
1060         out_8(&mr->interrupt, INT_CMDDONE);
1061         ms->stat = DID_ABORT;
1062         mesh_done(ms, 1);
1063         return;
1064     }
1065     if (err & ERR_PARITY) {
1066         if (ms->msgphase == msg_in) {
1067             printk(KERN_ERR "mesh: msg parity error, target %d\n",
1068                    ms->conn_tgt);
1069             ms->msgout[0] = MSG_PARITY_ERROR;
1070             ms->n_msgout = 1;
1071             ms->msgphase = msg_in_bad;
1072             cmd_complete(ms);
1073             return;
1074         }
1075         if (ms->stat == DID_OK) {
1076             printk(KERN_ERR "mesh: parity error, target %d\n",
1077                    ms->conn_tgt);
1078             ms->stat = DID_PARITY;
1079         }
1080         count = (mr->count_hi << 8) + mr->count_lo;
1081         if (count == 0) {
1082             cmd_complete(ms);
1083         } else {
1084             /* reissue the data transfer command */
1085             out_8(&mr->sequence, mr->sequence);
1086         }
1087         return;
1088     }
1089     if (err & ERR_SEQERR) {
1090         if (exc & EXC_RESELECTED) {
1091             /* This can happen if we issue a command to
1092                get the bus just after the target reselects us. */
1093             static int mesh_resel_seqerr;
1094             mesh_resel_seqerr++;
1095             reselected(ms);
1096             return;
1097         }
1098         if (exc == EXC_PHASEMM) {
1099             static int mesh_phasemm_seqerr;
1100             mesh_phasemm_seqerr++;
1101             phase_mismatch(ms);
1102             return;
1103         }
1104         printk(KERN_ERR "mesh: sequence error (err=%x exc=%x)\n",
1105                err, exc);
1106     } else {
1107         printk(KERN_ERR "mesh: unknown error %x (exc=%x)\n", err, exc);
1108     }
1109     mesh_dump_regs(ms);
1110     dumplog(ms, ms->conn_tgt);
1111     if (ms->phase > selecting && (in_8(&mr->bus_status1) & BS1_BSY)) {
1112         /* try to do what the target wants */
1113         do_abort(ms);
1114         phase_mismatch(ms);
1115         return;
1116     }
1117     ms->stat = DID_ERROR;
1118     mesh_done(ms, 1);
1119 }
1120 
1121 static void handle_exception(struct mesh_state *ms)
1122 {
1123     int exc;
1124     volatile struct mesh_regs __iomem *mr = ms->mesh;
1125 
1126     exc = in_8(&mr->exception);
1127     out_8(&mr->interrupt, INT_EXCEPTION | INT_CMDDONE);
1128     if (exc & EXC_RESELECTED) {
1129         static int mesh_resel_exc;
1130         mesh_resel_exc++;
1131         reselected(ms);
1132     } else if (exc == EXC_ARBLOST) {
1133         printk(KERN_DEBUG "mesh: lost arbitration\n");
1134         ms->stat = DID_BUS_BUSY;
1135         mesh_done(ms, 1);
1136     } else if (exc == EXC_SELTO) {
1137         /* selection timed out */
1138         ms->stat = DID_BAD_TARGET;
1139         mesh_done(ms, 1);
1140     } else if (exc == EXC_PHASEMM) {
1141         /* target wants to do something different:
1142            find out what it wants and do it. */
1143         phase_mismatch(ms);
1144     } else {
1145         printk(KERN_ERR "mesh: can't cope with exception %x\n", exc);
1146         mesh_dump_regs(ms);
1147         dumplog(ms, ms->conn_tgt);
1148         do_abort(ms);
1149         phase_mismatch(ms);
1150     }
1151 }
1152 
1153 static void handle_msgin(struct mesh_state *ms)
1154 {
1155     int i, code;
1156     struct scsi_cmnd *cmd = ms->current_req;
1157     struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1158 
1159     if (ms->n_msgin == 0)
1160         return;
1161     code = ms->msgin[0];
1162     if (ALLOW_DEBUG(ms->conn_tgt)) {
1163         printk(KERN_DEBUG "got %d message bytes:", ms->n_msgin);
1164         for (i = 0; i < ms->n_msgin; ++i)
1165             printk(" %x", ms->msgin[i]);
1166         printk("\n");
1167     }
1168     dlog(ms, "msgin msg=%.8x",
1169          MKWORD(ms->n_msgin, code, ms->msgin[1], ms->msgin[2]));
1170 
1171     ms->expect_reply = 0;
1172     ms->n_msgout = 0;
1173     if (ms->n_msgin < msgin_length(ms))
1174         goto reject;
1175     if (cmd)
1176         mesh_priv(cmd)->message = code;
1177     switch (code) {
1178     case COMMAND_COMPLETE:
1179         break;
1180     case EXTENDED_MESSAGE:
1181         switch (ms->msgin[2]) {
1182         case EXTENDED_MODIFY_DATA_POINTER:
1183             ms->data_ptr += (ms->msgin[3] << 24) + ms->msgin[6]
1184                 + (ms->msgin[4] << 16) + (ms->msgin[5] << 8);
1185             break;
1186         case EXTENDED_SDTR:
1187             if (tp->sdtr_state != sdtr_sent) {
1188                 /* reply with an SDTR */
1189                 add_sdtr_msg(ms);
1190                 /* limit period to at least his value,
1191                    offset to no more than his */
1192                 if (ms->msgout[3] < ms->msgin[3])
1193                     ms->msgout[3] = ms->msgin[3];
1194                 if (ms->msgout[4] > ms->msgin[4])
1195                     ms->msgout[4] = ms->msgin[4];
1196                 set_sdtr(ms, ms->msgout[3], ms->msgout[4]);
1197                 ms->msgphase = msg_out;
1198             } else {
1199                 set_sdtr(ms, ms->msgin[3], ms->msgin[4]);
1200             }
1201             break;
1202         default:
1203             goto reject;
1204         }
1205         break;
1206     case SAVE_POINTERS:
1207         tp->saved_ptr = ms->data_ptr;
1208         break;
1209     case RESTORE_POINTERS:
1210         ms->data_ptr = tp->saved_ptr;
1211         break;
1212     case DISCONNECT:
1213         ms->phase = disconnecting;
1214         break;
1215     case ABORT:
1216         break;
1217     case MESSAGE_REJECT:
1218         if (tp->sdtr_state == sdtr_sent)
1219             set_sdtr(ms, 0, 0);
1220         break;
1221     case NOP:
1222         break;
1223     default:
1224         if (IDENTIFY_BASE <= code && code <= IDENTIFY_BASE + 7) {
1225             if (cmd == NULL) {
1226                 do_abort(ms);
1227                 ms->msgphase = msg_out;
1228             } else if (code != cmd->device->lun + IDENTIFY_BASE) {
1229                 printk(KERN_WARNING "mesh: lun mismatch "
1230                        "(%d != %llu) on reselection from "
1231                        "target %d\n", code - IDENTIFY_BASE,
1232                        cmd->device->lun, ms->conn_tgt);
1233             }
1234             break;
1235         }
1236         goto reject;
1237     }
1238     return;
1239 
1240  reject:
1241     printk(KERN_WARNING "mesh: rejecting message from target %d:",
1242            ms->conn_tgt);
1243     for (i = 0; i < ms->n_msgin; ++i)
1244         printk(" %x", ms->msgin[i]);
1245     printk("\n");
1246     ms->msgout[0] = MESSAGE_REJECT;
1247     ms->n_msgout = 1;
1248     ms->msgphase = msg_out;
1249 }
1250 
1251 /*
1252  * Set up DMA commands for transferring data.
1253  */
1254 static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd)
1255 {
1256     int i, dma_cmd, total, off, dtot;
1257     struct scatterlist *scl;
1258     struct dbdma_cmd *dcmds;
1259 
1260     dma_cmd = ms->tgts[ms->conn_tgt].data_goes_out?
1261         OUTPUT_MORE: INPUT_MORE;
1262     dcmds = ms->dma_cmds;
1263     dtot = 0;
1264     if (cmd) {
1265         int nseg;
1266 
1267         mesh_priv(cmd)->this_residual = scsi_bufflen(cmd);
1268 
1269         nseg = scsi_dma_map(cmd);
1270         BUG_ON(nseg < 0);
1271 
1272         if (nseg) {
1273             total = 0;
1274             off = ms->data_ptr;
1275 
1276             scsi_for_each_sg(cmd, scl, nseg, i) {
1277                 u32 dma_addr = sg_dma_address(scl);
1278                 u32 dma_len = sg_dma_len(scl);
1279                 
1280                 total += scl->length;
1281                 if (off >= dma_len) {
1282                     off -= dma_len;
1283                     continue;
1284                 }
1285                 if (dma_len > 0xffff)
1286                     panic("mesh: scatterlist element >= 64k");
1287                 dcmds->req_count = cpu_to_le16(dma_len - off);
1288                 dcmds->command = cpu_to_le16(dma_cmd);
1289                 dcmds->phy_addr = cpu_to_le32(dma_addr + off);
1290                 dcmds->xfer_status = 0;
1291                 ++dcmds;
1292                 dtot += dma_len - off;
1293                 off = 0;
1294             }
1295         }
1296     }
1297     if (dtot == 0) {
1298         /* Either the target has overrun our buffer,
1299            or the caller didn't provide a buffer. */
1300         static char mesh_extra_buf[64];
1301 
1302         dtot = sizeof(mesh_extra_buf);
1303         dcmds->req_count = cpu_to_le16(dtot);
1304         dcmds->phy_addr = cpu_to_le32(virt_to_phys(mesh_extra_buf));
1305         dcmds->xfer_status = 0;
1306         ++dcmds;
1307     }
1308     dma_cmd += OUTPUT_LAST - OUTPUT_MORE;
1309     dcmds[-1].command = cpu_to_le16(dma_cmd);
1310     memset(dcmds, 0, sizeof(*dcmds));
1311     dcmds->command = cpu_to_le16(DBDMA_STOP);
1312     ms->dma_count = dtot;
1313 }
1314 
1315 static void halt_dma(struct mesh_state *ms)
1316 {
1317     volatile struct dbdma_regs __iomem *md = ms->dma;
1318     volatile struct mesh_regs __iomem *mr = ms->mesh;
1319     struct scsi_cmnd *cmd = ms->current_req;
1320     int t, nb;
1321 
1322     if (!ms->tgts[ms->conn_tgt].data_goes_out) {
1323         /* wait a little while until the fifo drains */
1324         t = 50;
1325         while (t > 0 && in_8(&mr->fifo_count) != 0
1326                && (in_le32(&md->status) & ACTIVE) != 0) {
1327             --t;
1328             udelay(1);
1329         }
1330     }
1331     out_le32(&md->control, RUN << 16);  /* turn off RUN bit */
1332     nb = (mr->count_hi << 8) + mr->count_lo;
1333     dlog(ms, "halt_dma fc/count=%.6x",
1334          MKWORD(0, mr->fifo_count, 0, nb));
1335     if (ms->tgts[ms->conn_tgt].data_goes_out)
1336         nb += mr->fifo_count;
1337     /* nb is the number of bytes not yet transferred
1338        to/from the target. */
1339     ms->data_ptr -= nb;
1340     dlog(ms, "data_ptr %x", ms->data_ptr);
1341     if (ms->data_ptr < 0) {
1342         printk(KERN_ERR "mesh: halt_dma: data_ptr=%d (nb=%d, ms=%p)\n",
1343                ms->data_ptr, nb, ms);
1344         ms->data_ptr = 0;
1345 #ifdef MESH_DBG
1346         dumplog(ms, ms->conn_tgt);
1347         dumpslog(ms);
1348 #endif /* MESH_DBG */
1349     } else if (cmd && scsi_bufflen(cmd) &&
1350            ms->data_ptr > scsi_bufflen(cmd)) {
1351         printk(KERN_DEBUG "mesh: target %d overrun, "
1352                "data_ptr=%x total=%x goes_out=%d\n",
1353                ms->conn_tgt, ms->data_ptr, scsi_bufflen(cmd),
1354                ms->tgts[ms->conn_tgt].data_goes_out);
1355     }
1356     if (cmd)
1357         scsi_dma_unmap(cmd);
1358     ms->dma_started = 0;
1359 }
1360 
1361 static void phase_mismatch(struct mesh_state *ms)
1362 {
1363     volatile struct mesh_regs __iomem *mr = ms->mesh;
1364     int phase;
1365 
1366     dlog(ms, "phasemm ch/cl/seq/fc=%.8x",
1367          MKWORD(mr->count_hi, mr->count_lo, mr->sequence, mr->fifo_count));
1368     phase = in_8(&mr->bus_status0) & BS0_PHASE;
1369     if (ms->msgphase == msg_out_xxx && phase == BP_MSGOUT) {
1370         /* output the last byte of the message, without ATN */
1371         out_8(&mr->count_lo, 1);
1372         out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1373         mesh_flush_io(mr);
1374         udelay(1);
1375         out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1376         ms->msgphase = msg_out_last;
1377         return;
1378     }
1379 
1380     if (ms->msgphase == msg_in) {
1381         get_msgin(ms);
1382         if (ms->n_msgin)
1383             handle_msgin(ms);
1384     }
1385 
1386     if (ms->dma_started)
1387         halt_dma(ms);
1388     if (mr->fifo_count) {
1389         out_8(&mr->sequence, SEQ_FLUSHFIFO);
1390         mesh_flush_io(mr);
1391         udelay(1);
1392     }
1393 
1394     ms->msgphase = msg_none;
1395     switch (phase) {
1396     case BP_DATAIN:
1397         ms->tgts[ms->conn_tgt].data_goes_out = 0;
1398         ms->phase = dataing;
1399         break;
1400     case BP_DATAOUT:
1401         ms->tgts[ms->conn_tgt].data_goes_out = 1;
1402         ms->phase = dataing;
1403         break;
1404     case BP_COMMAND:
1405         ms->phase = commanding;
1406         break;
1407     case BP_STATUS:
1408         ms->phase = statusing;
1409         break;
1410     case BP_MSGIN:
1411         ms->msgphase = msg_in;
1412         ms->n_msgin = 0;
1413         break;
1414     case BP_MSGOUT:
1415         ms->msgphase = msg_out;
1416         if (ms->n_msgout == 0) {
1417             if (ms->aborting) {
1418                 do_abort(ms);
1419             } else {
1420                 if (ms->last_n_msgout == 0) {
1421                     printk(KERN_DEBUG
1422                            "mesh: no msg to repeat\n");
1423                     ms->msgout[0] = NOP;
1424                     ms->last_n_msgout = 1;
1425                 }
1426                 ms->n_msgout = ms->last_n_msgout;
1427             }
1428         }
1429         break;
1430     default:
1431         printk(KERN_DEBUG "mesh: unknown scsi phase %x\n", phase);
1432         ms->stat = DID_ERROR;
1433         mesh_done(ms, 1);
1434         return;
1435     }
1436 
1437     start_phase(ms);
1438 }
1439 
1440 static void cmd_complete(struct mesh_state *ms)
1441 {
1442     volatile struct mesh_regs __iomem *mr = ms->mesh;
1443     struct scsi_cmnd *cmd = ms->current_req;
1444     struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1445     int seq, n, t;
1446 
1447     dlog(ms, "cmd_complete fc=%x", mr->fifo_count);
1448     seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
1449     switch (ms->msgphase) {
1450     case msg_out_xxx:
1451         /* huh?  we expected a phase mismatch */
1452         ms->n_msgin = 0;
1453         ms->msgphase = msg_in;
1454         fallthrough;
1455 
1456     case msg_in:
1457         /* should have some message bytes in fifo */
1458         get_msgin(ms);
1459         n = msgin_length(ms);
1460         if (ms->n_msgin < n) {
1461             out_8(&mr->count_lo, n - ms->n_msgin);
1462             out_8(&mr->sequence, SEQ_MSGIN + seq);
1463         } else {
1464             ms->msgphase = msg_none;
1465             handle_msgin(ms);
1466             start_phase(ms);
1467         }
1468         break;
1469 
1470     case msg_in_bad:
1471         out_8(&mr->sequence, SEQ_FLUSHFIFO);
1472         mesh_flush_io(mr);
1473         udelay(1);
1474         out_8(&mr->count_lo, 1);
1475         out_8(&mr->sequence, SEQ_MSGIN + SEQ_ATN + use_active_neg);
1476         break;
1477 
1478     case msg_out:
1479         /*
1480          * To get the right timing on ATN wrt ACK, we have
1481          * to get the MESH to drop ACK, wait until REQ gets
1482          * asserted, then drop ATN.  To do this we first
1483          * issue a SEQ_MSGOUT with ATN and wait for REQ,
1484          * then change the command to a SEQ_MSGOUT w/o ATN.
1485          * If we don't see REQ in a reasonable time, we
1486          * change the command to SEQ_MSGIN with ATN,
1487          * wait for the phase mismatch interrupt, then
1488          * issue the SEQ_MSGOUT without ATN.
1489          */
1490         out_8(&mr->count_lo, 1);
1491         out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg + SEQ_ATN);
1492         t = 30;     /* wait up to 30us */
1493         while ((in_8(&mr->bus_status0) & BS0_REQ) == 0 && --t >= 0)
1494             udelay(1);
1495         dlog(ms, "last_mbyte err/exc/fc/cl=%.8x",
1496              MKWORD(mr->error, mr->exception,
1497                 mr->fifo_count, mr->count_lo));
1498         if (in_8(&mr->interrupt) & (INT_ERROR | INT_EXCEPTION)) {
1499             /* whoops, target didn't do what we expected */
1500             ms->last_n_msgout = ms->n_msgout;
1501             ms->n_msgout = 0;
1502             if (in_8(&mr->interrupt) & INT_ERROR) {
1503                 printk(KERN_ERR "mesh: error %x in msg_out\n",
1504                        in_8(&mr->error));
1505                 handle_error(ms);
1506                 return;
1507             }
1508             if (in_8(&mr->exception) != EXC_PHASEMM)
1509                 printk(KERN_ERR "mesh: exc %x in msg_out\n",
1510                        in_8(&mr->exception));
1511             else
1512                 printk(KERN_DEBUG "mesh: bs0=%x in msg_out\n",
1513                        in_8(&mr->bus_status0));
1514             handle_exception(ms);
1515             return;
1516         }
1517         if (in_8(&mr->bus_status0) & BS0_REQ) {
1518             out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1519             mesh_flush_io(mr);
1520             udelay(1);
1521             out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1522             ms->msgphase = msg_out_last;
1523         } else {
1524             out_8(&mr->sequence, SEQ_MSGIN + use_active_neg + SEQ_ATN);
1525             ms->msgphase = msg_out_xxx;
1526         }
1527         break;
1528 
1529     case msg_out_last:
1530         ms->last_n_msgout = ms->n_msgout;
1531         ms->n_msgout = 0;
1532         ms->msgphase = ms->expect_reply? msg_in: msg_none;
1533         start_phase(ms);
1534         break;
1535 
1536     case msg_none:
1537         switch (ms->phase) {
1538         case idle:
1539             printk(KERN_ERR "mesh: interrupt in idle phase?\n");
1540             dumpslog(ms);
1541             return;
1542         case selecting:
1543             dlog(ms, "Selecting phase at command completion",0);
1544             ms->msgout[0] = IDENTIFY(ALLOW_RESEL(ms->conn_tgt),
1545                          (cmd? cmd->device->lun: 0));
1546             ms->n_msgout = 1;
1547             ms->expect_reply = 0;
1548             if (ms->aborting) {
1549                 ms->msgout[0] = ABORT;
1550                 ms->n_msgout++;
1551             } else if (tp->sdtr_state == do_sdtr) {
1552                 /* add SDTR message */
1553                 add_sdtr_msg(ms);
1554                 ms->expect_reply = 1;
1555                 tp->sdtr_state = sdtr_sent;
1556             }
1557             ms->msgphase = msg_out;
1558             /*
1559              * We need to wait for REQ before dropping ATN.
1560              * We wait for at most 30us, then fall back to
1561              * a scheme where we issue a SEQ_COMMAND with ATN,
1562              * which will give us a phase mismatch interrupt
1563              * when REQ does come, and then we send the message.
1564              */
1565             t = 230;        /* wait up to 230us */
1566             while ((in_8(&mr->bus_status0) & BS0_REQ) == 0) {
1567                 if (--t < 0) {
1568                     dlog(ms, "impatient for req", ms->n_msgout);
1569                     ms->msgphase = msg_none;
1570                     break;
1571                 }
1572                 udelay(1);
1573             }
1574             break;
1575         case dataing:
1576             if (ms->dma_count != 0) {
1577                 start_phase(ms);
1578                 return;
1579             }
1580             /*
1581              * We can get a phase mismatch here if the target
1582              * changes to the status phase, even though we have
1583              * had a command complete interrupt.  Then, if we
1584              * issue the SEQ_STATUS command, we'll get a sequence
1585              * error interrupt.  Which isn't so bad except that
1586              * occasionally the mesh actually executes the
1587              * SEQ_STATUS *as well as* giving us the sequence
1588              * error and phase mismatch exception.
1589              */
1590             out_8(&mr->sequence, 0);
1591             out_8(&mr->interrupt,
1592                   INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1593             halt_dma(ms);
1594             break;
1595         case statusing:
1596             if (cmd) {
1597                 struct mesh_cmd_priv *mcmd = mesh_priv(cmd);
1598 
1599                 mcmd->status = mr->fifo;
1600                 if (DEBUG_TARGET(cmd))
1601                     printk(KERN_DEBUG "mesh: status is %x\n",
1602                            mcmd->status);
1603             }
1604             ms->msgphase = msg_in;
1605             break;
1606         case busfreeing:
1607             mesh_done(ms, 1);
1608             return;
1609         case disconnecting:
1610             ms->current_req = NULL;
1611             ms->phase = idle;
1612             mesh_start(ms);
1613             return;
1614         default:
1615             break;
1616         }
1617         ++ms->phase;
1618         start_phase(ms);
1619         break;
1620     }
1621 }
1622 
1623 
1624 /*
1625  * Called by midlayer with host locked to queue a new
1626  * request
1627  */
1628 static int mesh_queue_lck(struct scsi_cmnd *cmd)
1629 {
1630     struct mesh_state *ms;
1631 
1632     cmd->host_scribble = NULL;
1633 
1634     ms = (struct mesh_state *) cmd->device->host->hostdata;
1635 
1636     if (ms->request_q == NULL)
1637         ms->request_q = cmd;
1638     else
1639         ms->request_qtail->host_scribble = (void *) cmd;
1640     ms->request_qtail = cmd;
1641 
1642     if (ms->phase == idle)
1643         mesh_start(ms);
1644 
1645     return 0;
1646 }
1647 
1648 static DEF_SCSI_QCMD(mesh_queue)
1649 
1650 /*
1651  * Called to handle interrupts, either call by the interrupt
1652  * handler (do_mesh_interrupt) or by other functions in
1653  * exceptional circumstances
1654  */
1655 static void mesh_interrupt(struct mesh_state *ms)
1656 {
1657     volatile struct mesh_regs __iomem *mr = ms->mesh;
1658     int intr;
1659 
1660 #if 0
1661     if (ALLOW_DEBUG(ms->conn_tgt))
1662         printk(KERN_DEBUG "mesh_intr, bs0=%x int=%x exc=%x err=%x "
1663                "phase=%d msgphase=%d\n", mr->bus_status0,
1664                mr->interrupt, mr->exception, mr->error,
1665                ms->phase, ms->msgphase);
1666 #endif
1667     while ((intr = in_8(&mr->interrupt)) != 0) {
1668         dlog(ms, "interrupt intr/err/exc/seq=%.8x", 
1669              MKWORD(intr, mr->error, mr->exception, mr->sequence));
1670         if (intr & INT_ERROR) {
1671             handle_error(ms);
1672         } else if (intr & INT_EXCEPTION) {
1673             handle_exception(ms);
1674         } else if (intr & INT_CMDDONE) {
1675             out_8(&mr->interrupt, INT_CMDDONE);
1676             cmd_complete(ms);
1677         }
1678     }
1679 }
1680 
1681 /* Todo: here we can at least try to remove the command from the
1682  * queue if it isn't connected yet, and for pending command, assert
1683  * ATN until the bus gets freed.
1684  */
1685 static int mesh_abort(struct scsi_cmnd *cmd)
1686 {
1687     struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata;
1688 
1689     printk(KERN_DEBUG "mesh_abort(%p)\n", cmd);
1690     mesh_dump_regs(ms);
1691     dumplog(ms, cmd->device->id);
1692     dumpslog(ms);
1693     return FAILED;
1694 }
1695 
1696 /*
1697  * Called by the midlayer with the lock held to reset the
1698  * SCSI host and bus.
1699  * The midlayer will wait for devices to come back, we don't need
1700  * to do that ourselves
1701  */
1702 static int mesh_host_reset(struct scsi_cmnd *cmd)
1703 {
1704     struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata;
1705     volatile struct mesh_regs __iomem *mr = ms->mesh;
1706     volatile struct dbdma_regs __iomem *md = ms->dma;
1707     unsigned long flags;
1708 
1709     printk(KERN_DEBUG "mesh_host_reset\n");
1710 
1711     spin_lock_irqsave(ms->host->host_lock, flags);
1712 
1713     if (ms->dma_started)
1714         halt_dma(ms);
1715 
1716     /* Reset the controller & dbdma channel */
1717     out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16);   /* stop dma */
1718     out_8(&mr->exception, 0xff);    /* clear all exception bits */
1719     out_8(&mr->error, 0xff);    /* clear all error bits */
1720     out_8(&mr->sequence, SEQ_RESETMESH);
1721         mesh_flush_io(mr);
1722     udelay(1);
1723     out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1724     out_8(&mr->source_id, ms->host->this_id);
1725     out_8(&mr->sel_timeout, 25);    /* 250ms */
1726     out_8(&mr->sync_params, ASYNC_PARAMS);
1727 
1728     /* Reset the bus */
1729     out_8(&mr->bus_status1, BS1_RST);   /* assert RST */
1730         mesh_flush_io(mr);
1731     udelay(30);         /* leave it on for >= 25us */
1732     out_8(&mr->bus_status1, 0); /* negate RST */
1733 
1734     /* Complete pending commands */
1735     handle_reset(ms);
1736     
1737     spin_unlock_irqrestore(ms->host->host_lock, flags);
1738     return SUCCESS;
1739 }
1740 
1741 static void set_mesh_power(struct mesh_state *ms, int state)
1742 {
1743     if (!machine_is(powermac))
1744         return;
1745     if (state) {
1746         pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 1);
1747         msleep(200);
1748     } else {
1749         pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 0);
1750         msleep(10);
1751     }
1752 }
1753 
1754 
1755 #ifdef CONFIG_PM
1756 static int mesh_suspend(struct macio_dev *mdev, pm_message_t mesg)
1757 {
1758     struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1759     unsigned long flags;
1760 
1761     switch (mesg.event) {
1762     case PM_EVENT_SUSPEND:
1763     case PM_EVENT_HIBERNATE:
1764     case PM_EVENT_FREEZE:
1765         break;
1766     default:
1767         return 0;
1768     }
1769     if (ms->phase == sleeping)
1770         return 0;
1771 
1772     scsi_block_requests(ms->host);
1773     spin_lock_irqsave(ms->host->host_lock, flags);
1774     while(ms->phase != idle) {
1775         spin_unlock_irqrestore(ms->host->host_lock, flags);
1776         msleep(10);
1777         spin_lock_irqsave(ms->host->host_lock, flags);
1778     }
1779     ms->phase = sleeping;
1780     spin_unlock_irqrestore(ms->host->host_lock, flags);
1781     disable_irq(ms->meshintr);
1782     set_mesh_power(ms, 0);
1783 
1784     return 0;
1785 }
1786 
1787 static int mesh_resume(struct macio_dev *mdev)
1788 {
1789     struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1790     unsigned long flags;
1791 
1792     if (ms->phase != sleeping)
1793         return 0;
1794 
1795     set_mesh_power(ms, 1);
1796     mesh_init(ms);
1797     spin_lock_irqsave(ms->host->host_lock, flags);
1798     mesh_start(ms);
1799     spin_unlock_irqrestore(ms->host->host_lock, flags);
1800     enable_irq(ms->meshintr);
1801     scsi_unblock_requests(ms->host);
1802 
1803     return 0;
1804 }
1805 
1806 #endif /* CONFIG_PM */
1807 
1808 /*
1809  * If we leave drives set for synchronous transfers (especially
1810  * CDROMs), and reboot to MacOS, it gets confused, poor thing.
1811  * So, on reboot we reset the SCSI bus.
1812  */
1813 static int mesh_shutdown(struct macio_dev *mdev)
1814 {
1815     struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1816     volatile struct mesh_regs __iomem *mr;
1817     unsigned long flags;
1818 
1819         printk(KERN_INFO "resetting MESH scsi bus(es)\n");
1820     spin_lock_irqsave(ms->host->host_lock, flags);
1821         mr = ms->mesh;
1822     out_8(&mr->intr_mask, 0);
1823     out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1824     out_8(&mr->bus_status1, BS1_RST);
1825     mesh_flush_io(mr);
1826     udelay(30);
1827     out_8(&mr->bus_status1, 0);
1828     spin_unlock_irqrestore(ms->host->host_lock, flags);
1829 
1830     return 0;
1831 }
1832 
1833 static struct scsi_host_template mesh_template = {
1834     .proc_name          = "mesh",
1835     .name               = "MESH",
1836     .queuecommand           = mesh_queue,
1837     .eh_abort_handler       = mesh_abort,
1838     .eh_host_reset_handler      = mesh_host_reset,
1839     .can_queue          = 20,
1840     .this_id            = 7,
1841     .sg_tablesize           = SG_ALL,
1842     .cmd_per_lun            = 2,
1843     .max_segment_size       = 65535,
1844     .cmd_size           = sizeof(struct mesh_cmd_priv),
1845 };
1846 
1847 static int mesh_probe(struct macio_dev *mdev, const struct of_device_id *match)
1848 {
1849     struct device_node *mesh = macio_get_of_node(mdev);
1850     struct pci_dev* pdev = macio_get_pci_dev(mdev);
1851     int tgt, minper;
1852     const int *cfp;
1853     struct mesh_state *ms;
1854     struct Scsi_Host *mesh_host;
1855     void *dma_cmd_space;
1856     dma_addr_t dma_cmd_bus;
1857 
1858     switch (mdev->bus->chip->type) {
1859     case macio_heathrow:
1860     case macio_gatwick:
1861     case macio_paddington:
1862         use_active_neg = 0;
1863         break;
1864     default:
1865         use_active_neg = SEQ_ACTIVE_NEG;
1866     }
1867 
1868     if (macio_resource_count(mdev) != 2 || macio_irq_count(mdev) != 2) {
1869             printk(KERN_ERR "mesh: expected 2 addrs and 2 intrs"
1870                    " (got %d,%d)\n", macio_resource_count(mdev),
1871                macio_irq_count(mdev));
1872         return -ENODEV;
1873     }
1874 
1875     if (macio_request_resources(mdev, "mesh") != 0) {
1876             printk(KERN_ERR "mesh: unable to request memory resources");
1877         return -EBUSY;
1878     }
1879         mesh_host = scsi_host_alloc(&mesh_template, sizeof(struct mesh_state));
1880     if (mesh_host == NULL) {
1881         printk(KERN_ERR "mesh: couldn't register host");
1882         goto out_release;
1883     }
1884     
1885     mesh_host->base = macio_resource_start(mdev, 0);
1886     mesh_host->irq = macio_irq(mdev, 0);
1887         ms = (struct mesh_state *) mesh_host->hostdata;
1888     macio_set_drvdata(mdev, ms);
1889     ms->host = mesh_host;
1890     ms->mdev = mdev;
1891     ms->pdev = pdev;
1892     
1893     ms->mesh = ioremap(macio_resource_start(mdev, 0), 0x1000);
1894     if (ms->mesh == NULL) {
1895         printk(KERN_ERR "mesh: can't map registers\n");
1896         goto out_free;
1897     }       
1898     ms->dma = ioremap(macio_resource_start(mdev, 1), 0x1000);
1899     if (ms->dma == NULL) {
1900         printk(KERN_ERR "mesh: can't map registers\n");
1901         iounmap(ms->mesh);
1902         goto out_free;
1903     }
1904 
1905         ms->meshintr = macio_irq(mdev, 0);
1906         ms->dmaintr = macio_irq(mdev, 1);
1907 
1908         /* Space for dma command list: +1 for stop command,
1909          * +1 to allow for aligning.
1910      */
1911     ms->dma_cmd_size = (mesh_host->sg_tablesize + 2) * sizeof(struct dbdma_cmd);
1912 
1913     /* We use the PCI APIs for now until the generic one gets fixed
1914      * enough or until we get some macio-specific versions
1915      */
1916     dma_cmd_space = dma_alloc_coherent(&macio_get_pci_dev(mdev)->dev,
1917                        ms->dma_cmd_size, &dma_cmd_bus,
1918                        GFP_KERNEL);
1919     if (dma_cmd_space == NULL) {
1920         printk(KERN_ERR "mesh: can't allocate DMA table\n");
1921         goto out_unmap;
1922     }
1923 
1924     ms->dma_cmds = (struct dbdma_cmd *) DBDMA_ALIGN(dma_cmd_space);
1925         ms->dma_cmd_space = dma_cmd_space;
1926     ms->dma_cmd_bus = dma_cmd_bus + ((unsigned long)ms->dma_cmds)
1927         - (unsigned long)dma_cmd_space;
1928     ms->current_req = NULL;
1929         for (tgt = 0; tgt < 8; ++tgt) {
1930             ms->tgts[tgt].sdtr_state = do_sdtr;
1931             ms->tgts[tgt].sync_params = ASYNC_PARAMS;
1932             ms->tgts[tgt].current_req = NULL;
1933         }
1934 
1935     if ((cfp = of_get_property(mesh, "clock-frequency", NULL)))
1936             ms->clk_freq = *cfp;
1937     else {
1938             printk(KERN_INFO "mesh: assuming 50MHz clock frequency\n");
1939             ms->clk_freq = 50000000;
1940         }
1941 
1942         /* The maximum sync rate is clock / 5; increase
1943          * mesh_sync_period if necessary.
1944      */
1945     minper = 1000000000 / (ms->clk_freq / 5); /* ns */
1946     if (mesh_sync_period < minper)
1947         mesh_sync_period = minper;
1948 
1949     /* Power up the chip */
1950     set_mesh_power(ms, 1);
1951 
1952     /* Set it up */
1953         mesh_init(ms);
1954 
1955     /* Request interrupt */
1956         if (request_irq(ms->meshintr, do_mesh_interrupt, 0, "MESH", ms)) {
1957             printk(KERN_ERR "MESH: can't get irq %d\n", ms->meshintr);
1958         goto out_shutdown;
1959     }
1960 
1961     /* Add scsi host & scan */
1962     if (scsi_add_host(mesh_host, &mdev->ofdev.dev))
1963         goto out_release_irq;
1964     scsi_scan_host(mesh_host);
1965 
1966     return 0;
1967 
1968  out_release_irq:
1969     free_irq(ms->meshintr, ms);
1970  out_shutdown:
1971     /* shutdown & reset bus in case of error or macos can be confused
1972      * at reboot if the bus was set to synchronous mode already
1973      */
1974     mesh_shutdown(mdev);
1975     set_mesh_power(ms, 0);
1976     dma_free_coherent(&macio_get_pci_dev(mdev)->dev, ms->dma_cmd_size,
1977                 ms->dma_cmd_space, ms->dma_cmd_bus);
1978  out_unmap:
1979     iounmap(ms->dma);
1980     iounmap(ms->mesh);
1981  out_free:
1982     scsi_host_put(mesh_host);
1983  out_release:
1984     macio_release_resources(mdev);
1985 
1986     return -ENODEV;
1987 }
1988 
1989 static int mesh_remove(struct macio_dev *mdev)
1990 {
1991     struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1992     struct Scsi_Host *mesh_host = ms->host;
1993 
1994     scsi_remove_host(mesh_host);
1995 
1996     free_irq(ms->meshintr, ms);
1997 
1998     /* Reset scsi bus */
1999     mesh_shutdown(mdev);
2000 
2001     /* Shut down chip & termination */
2002     set_mesh_power(ms, 0);
2003 
2004     /* Unmap registers & dma controller */
2005     iounmap(ms->mesh);
2006         iounmap(ms->dma);
2007 
2008     /* Free DMA commands memory */
2009     dma_free_coherent(&macio_get_pci_dev(mdev)->dev, ms->dma_cmd_size,
2010                 ms->dma_cmd_space, ms->dma_cmd_bus);
2011 
2012     /* Release memory resources */
2013     macio_release_resources(mdev);
2014 
2015     scsi_host_put(mesh_host);
2016 
2017     return 0;
2018 }
2019 
2020 
2021 static struct of_device_id mesh_match[] = 
2022 {
2023     {
2024     .name       = "mesh",
2025     },
2026     {
2027     .type       = "scsi",
2028     .compatible = "chrp,mesh0"
2029     },
2030     {},
2031 };
2032 MODULE_DEVICE_TABLE (of, mesh_match);
2033 
2034 static struct macio_driver mesh_driver = 
2035 {
2036     .driver = {
2037         .name       = "mesh",
2038         .owner      = THIS_MODULE,
2039         .of_match_table = mesh_match,
2040     },
2041     .probe      = mesh_probe,
2042     .remove     = mesh_remove,
2043     .shutdown   = mesh_shutdown,
2044 #ifdef CONFIG_PM
2045     .suspend    = mesh_suspend,
2046     .resume     = mesh_resume,
2047 #endif
2048 };
2049 
2050 
2051 static int __init init_mesh(void)
2052 {
2053 
2054     /* Calculate sync rate from module parameters */
2055     if (sync_rate > 10)
2056         sync_rate = 10;
2057     if (sync_rate > 0) {
2058         printk(KERN_INFO "mesh: configured for synchronous %d MB/s\n", sync_rate);
2059         mesh_sync_period = 1000 / sync_rate;    /* ns */
2060         mesh_sync_offset = 15;
2061     } else
2062         printk(KERN_INFO "mesh: configured for asynchronous\n");
2063 
2064     return macio_register_driver(&mesh_driver);
2065 }
2066 
2067 static void __exit exit_mesh(void)
2068 {
2069     return macio_unregister_driver(&mesh_driver);
2070 }
2071 
2072 module_init(init_mesh);
2073 module_exit(exit_mesh);
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!