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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  Linux MegaRAID driver for SAS based RAID controllers
0004  *
0005  *  Copyright (c) 2009-2013  LSI Corporation
0006  *  Copyright (c) 2013-2016  Avago Technologies
0007  *  Copyright (c) 2016-2018  Broadcom Inc.
0008  *
0009  *  FILE: megaraid_sas_fusion.h
0010  *
0011  *  Authors: Broadcom Inc.
0012  *           Manoj Jose
0013  *           Sumant Patro
0014  *           Kashyap Desai <kashyap.desai@broadcom.com>
0015  *           Sumit Saxena <sumit.saxena@broadcom.com>
0016  *
0017  *  Send feedback to: megaraidlinux.pdl@broadcom.com
0018  */
0019 
0020 #ifndef _MEGARAID_SAS_FUSION_H_
0021 #define _MEGARAID_SAS_FUSION_H_
0022 
0023 /* Fusion defines */
0024 #define MEGASAS_CHAIN_FRAME_SZ_MIN 1024
0025 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009)
0026 #define MEGASAS_MAX_CHAIN_SHIFT         5
0027 #define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK   0x400000
0028 #define MEGASAS_MAX_CHAIN_SIZE_MASK     0x3E0
0029 #define MEGASAS_256K_IO             128
0030 #define MEGASAS_1MB_IO              (MEGASAS_256K_IO * 4)
0031 #define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256
0032 #define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST   0xF0
0033 #define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST         0xF1
0034 #define MEGASAS_LOAD_BALANCE_FLAG           0x1
0035 #define MEGASAS_DCMD_MBOX_PEND_FLAG         0x1
0036 #define HOST_DIAG_WRITE_ENABLE              0x80
0037 #define HOST_DIAG_RESET_ADAPTER             0x4
0038 #define MEGASAS_FUSION_MAX_RESET_TRIES          3
0039 #define MAX_MSIX_QUEUES_FUSION              128
0040 #define RDPQ_MAX_INDEX_IN_ONE_CHUNK         16
0041 #define RDPQ_MAX_CHUNK_COUNT (MAX_MSIX_QUEUES_FUSION / RDPQ_MAX_INDEX_IN_ONE_CHUNK)
0042 
0043 /* Invader defines */
0044 #define MPI2_TYPE_CUDA                  0x2
0045 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH   0x4000
0046 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0      0x00
0047 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1      0x10
0048 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA      0x80
0049 #define MR_RL_FLAGS_SEQ_NUM_ENABLE          0x8
0050 #define MR_RL_WRITE_THROUGH_MODE            0x00
0051 #define MR_RL_WRITE_BACK_MODE               0x01
0052 
0053 /* T10 PI defines */
0054 #define MR_PROT_INFO_TYPE_CONTROLLER                0x8
0055 #define MEGASAS_SCSI_VARIABLE_LENGTH_CMD            0x7f
0056 #define MEGASAS_SCSI_SERVICE_ACTION_READ32          0x9
0057 #define MEGASAS_SCSI_SERVICE_ACTION_WRITE32         0xB
0058 #define MEGASAS_SCSI_ADDL_CDB_LEN                   0x18
0059 #define MEGASAS_RD_WR_PROTECT_CHECK_ALL         0x20
0060 #define MEGASAS_RD_WR_PROTECT_CHECK_NONE        0x60
0061 
0062 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET   (0x0000030C)
0063 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET   (0x0000006C)
0064 
0065 /*
0066  * Raid context flags
0067  */
0068 
0069 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT   0x4
0070 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK    0x30
0071 enum MR_RAID_FLAGS_IO_SUB_TYPE {
0072     MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
0073     MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
0074     MR_RAID_FLAGS_IO_SUB_TYPE_RMW_DATA     = 2,
0075     MR_RAID_FLAGS_IO_SUB_TYPE_RMW_P        = 3,
0076     MR_RAID_FLAGS_IO_SUB_TYPE_RMW_Q        = 4,
0077     MR_RAID_FLAGS_IO_SUB_TYPE_CACHE_BYPASS = 6,
0078     MR_RAID_FLAGS_IO_SUB_TYPE_LDIO_BW_LIMIT = 7,
0079     MR_RAID_FLAGS_IO_SUB_TYPE_R56_DIV_OFFLOAD = 8
0080 };
0081 
0082 /*
0083  * Request descriptor types
0084  */
0085 #define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO           0x7
0086 #define MEGASAS_REQ_DESCRIPT_FLAGS_MFA             0x1
0087 #define MEGASAS_REQ_DESCRIPT_FLAGS_NO_LOCK     0x2
0088 #define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT      1
0089 
0090 #define MEGASAS_FP_CMD_LEN  16
0091 #define MEGASAS_FUSION_IN_RESET 0
0092 #define MEGASAS_FUSION_OCR_NOT_POSSIBLE 1
0093 #define RAID_1_PEER_CMDS 2
0094 #define JBOD_MAPS_COUNT 2
0095 #define MEGASAS_REDUCE_QD_COUNT 64
0096 #define IOC_INIT_FRAME_SIZE 4096
0097 
0098 /*
0099  * Raid Context structure which describes MegaRAID specific IO Parameters
0100  * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
0101  */
0102 
0103 struct RAID_CONTEXT {
0104 #if   defined(__BIG_ENDIAN_BITFIELD)
0105     u8 nseg:4;
0106     u8 type:4;
0107 #else
0108     u8 type:4;
0109     u8 nseg:4;
0110 #endif
0111     u8 resvd0;
0112     __le16 timeout_value;
0113     u8 reg_lock_flags;
0114     u8 resvd1;
0115     __le16 virtual_disk_tgt_id;
0116     __le64 reg_lock_row_lba;
0117     __le32 reg_lock_length;
0118     __le16 next_lmid;
0119     u8 ex_status;
0120     u8 status;
0121     u8 raid_flags;
0122     u8 num_sge;
0123     __le16 config_seq_num;
0124     u8 span_arm;
0125     u8 priority;
0126     u8 num_sge_ext;
0127     u8 resvd2;
0128 };
0129 
0130 /*
0131  * Raid Context structure which describes ventura MegaRAID specific
0132  * IO Paramenters ,This resides at offset 0x60 where the SGL normally
0133  * starts in MPT IO Frames
0134  */
0135 struct RAID_CONTEXT_G35 {
0136     #define RAID_CONTEXT_NSEG_MASK  0x00F0
0137     #define RAID_CONTEXT_NSEG_SHIFT 4
0138     #define RAID_CONTEXT_TYPE_MASK  0x000F
0139     #define RAID_CONTEXT_TYPE_SHIFT 0
0140     u16     nseg_type;
0141     u16 timeout_value; /* 0x02 -0x03 */
0142     u16     routing_flags;  // 0x04 -0x05 routing flags
0143     u16 virtual_disk_tgt_id;   /* 0x06 -0x07 */
0144     __le64 reg_lock_row_lba;      /* 0x08 - 0x0F */
0145     u32 reg_lock_length;      /* 0x10 - 0x13 */
0146     union {                     // flow specific
0147         u16 rmw_op_index;   /* 0x14 - 0x15, R5/6 RMW: rmw operation index*/
0148         u16 peer_smid;      /* 0x14 - 0x15, R1 Write: peer smid*/
0149         u16 r56_arm_map;    /* 0x14 - 0x15, Unused [15], LogArm[14:10], P-Arm[9:5], Q-Arm[4:0] */
0150 
0151     } flow_specific;
0152 
0153     u8 ex_status;       /* 0x16 : OUT */
0154     u8 status;          /* 0x17 status */
0155     u8 raid_flags;      /* 0x18 resvd[7:6], ioSubType[5:4],
0156                  * resvd[3:1], preferredCpu[0]
0157                  */
0158     u8 span_arm;            /* 0x1C span[7:5], arm[4:0] */
0159     u16 config_seq_num;           /* 0x1A -0x1B */
0160     union {
0161         /*
0162          * Bit format:
0163          *   ---------------------------------
0164          *   | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0165          *   ---------------------------------
0166          * Byte0 |    numSGE[7]- numSGE[0]   |
0167          *   ---------------------------------
0168          * Byte1 |SD | resvd     | numSGE 8-11   |
0169          *        --------------------------------
0170          */
0171         #define NUM_SGE_MASK_LOWER  0xFF
0172         #define NUM_SGE_MASK_UPPER  0x0F
0173         #define NUM_SGE_SHIFT_UPPER 8
0174         #define STREAM_DETECT_SHIFT 7
0175         #define STREAM_DETECT_MASK  0x80
0176         struct {
0177 #if   defined(__BIG_ENDIAN_BITFIELD) /* 0x1C - 0x1D */
0178             u16 stream_detected:1;
0179             u16 reserved:3;
0180             u16 num_sge:12;
0181 #else
0182             u16 num_sge:12;
0183             u16 reserved:3;
0184             u16 stream_detected:1;
0185 #endif
0186         } bits;
0187         u8 bytes[2];
0188     } u;
0189     u8 resvd2[2];          /* 0x1E-0x1F */
0190 };
0191 
0192 #define MR_RAID_CTX_ROUTINGFLAGS_SLD_SHIFT  1
0193 #define MR_RAID_CTX_ROUTINGFLAGS_C2D_SHIFT  2
0194 #define MR_RAID_CTX_ROUTINGFLAGS_FWD_SHIFT  3
0195 #define MR_RAID_CTX_ROUTINGFLAGS_SQN_SHIFT  4
0196 #define MR_RAID_CTX_ROUTINGFLAGS_SBS_SHIFT  5
0197 #define MR_RAID_CTX_ROUTINGFLAGS_RW_SHIFT   6
0198 #define MR_RAID_CTX_ROUTINGFLAGS_LOG_SHIFT  7
0199 #define MR_RAID_CTX_ROUTINGFLAGS_CPUSEL_SHIFT   8
0200 #define MR_RAID_CTX_ROUTINGFLAGS_CPUSEL_MASK    0x0F00
0201 #define MR_RAID_CTX_ROUTINGFLAGS_SETDIVERT_SHIFT    12
0202 #define MR_RAID_CTX_ROUTINGFLAGS_SETDIVERT_MASK 0xF000
0203 
0204 static inline void set_num_sge(struct RAID_CONTEXT_G35 *rctx_g35,
0205                    u16 sge_count)
0206 {
0207     rctx_g35->u.bytes[0] = (u8)(sge_count & NUM_SGE_MASK_LOWER);
0208     rctx_g35->u.bytes[1] |= (u8)((sge_count >> NUM_SGE_SHIFT_UPPER)
0209                             & NUM_SGE_MASK_UPPER);
0210 }
0211 
0212 static inline u16 get_num_sge(struct RAID_CONTEXT_G35 *rctx_g35)
0213 {
0214     u16 sge_count;
0215 
0216     sge_count = (u16)(((rctx_g35->u.bytes[1] & NUM_SGE_MASK_UPPER)
0217             << NUM_SGE_SHIFT_UPPER) | (rctx_g35->u.bytes[0]));
0218     return sge_count;
0219 }
0220 
0221 #define SET_STREAM_DETECTED(rctx_g35) \
0222     (rctx_g35.u.bytes[1] |= STREAM_DETECT_MASK)
0223 
0224 #define CLEAR_STREAM_DETECTED(rctx_g35) \
0225     (rctx_g35.u.bytes[1] &= ~(STREAM_DETECT_MASK))
0226 
0227 static inline bool is_stream_detected(struct RAID_CONTEXT_G35 *rctx_g35)
0228 {
0229     return ((rctx_g35->u.bytes[1] & STREAM_DETECT_MASK));
0230 }
0231 
0232 union RAID_CONTEXT_UNION {
0233     struct RAID_CONTEXT raid_context;
0234     struct RAID_CONTEXT_G35 raid_context_g35;
0235 };
0236 
0237 #define RAID_CTX_SPANARM_ARM_SHIFT  (0)
0238 #define RAID_CTX_SPANARM_ARM_MASK   (0x1f)
0239 
0240 #define RAID_CTX_SPANARM_SPAN_SHIFT (5)
0241 #define RAID_CTX_SPANARM_SPAN_MASK  (0xE0)
0242 
0243 /* LogArm[14:10], P-Arm[9:5], Q-Arm[4:0] */
0244 #define RAID_CTX_R56_Q_ARM_MASK     (0x1F)
0245 #define RAID_CTX_R56_P_ARM_SHIFT    (5)
0246 #define RAID_CTX_R56_P_ARM_MASK     (0x3E0)
0247 #define RAID_CTX_R56_LOG_ARM_SHIFT  (10)
0248 #define RAID_CTX_R56_LOG_ARM_MASK   (0x7C00)
0249 
0250 /* number of bits per index in U32 TrackStream */
0251 #define BITS_PER_INDEX_STREAM       4
0252 #define INVALID_STREAM_NUM              16
0253 #define MR_STREAM_BITMAP        0x76543210
0254 #define STREAM_MASK         ((1 << BITS_PER_INDEX_STREAM) - 1)
0255 #define ZERO_LAST_STREAM        0x0fffffff
0256 #define MAX_STREAMS_TRACKED     8
0257 
0258 /*
0259  * define region lock types
0260  */
0261 enum REGION_TYPE {
0262     REGION_TYPE_UNUSED       = 0,
0263     REGION_TYPE_SHARED_READ  = 1,
0264     REGION_TYPE_SHARED_WRITE = 2,
0265     REGION_TYPE_EXCLUSIVE    = 3,
0266 };
0267 
0268 /* MPI2 defines */
0269 #define MPI2_FUNCTION_IOC_INIT              (0x02) /* IOC Init */
0270 #define MPI2_WHOINIT_HOST_DRIVER            (0x04)
0271 #define MPI2_VERSION_MAJOR                  (0x02)
0272 #define MPI2_VERSION_MINOR                  (0x00)
0273 #define MPI2_VERSION_MAJOR_MASK             (0xFF00)
0274 #define MPI2_VERSION_MAJOR_SHIFT            (8)
0275 #define MPI2_VERSION_MINOR_MASK             (0x00FF)
0276 #define MPI2_VERSION_MINOR_SHIFT            (0)
0277 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
0278               MPI2_VERSION_MINOR)
0279 #define MPI2_HEADER_VERSION_UNIT            (0x10)
0280 #define MPI2_HEADER_VERSION_DEV             (0x00)
0281 #define MPI2_HEADER_VERSION_UNIT_MASK       (0xFF00)
0282 #define MPI2_HEADER_VERSION_UNIT_SHIFT      (8)
0283 #define MPI2_HEADER_VERSION_DEV_MASK        (0x00FF)
0284 #define MPI2_HEADER_VERSION_DEV_SHIFT       (0)
0285 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
0286                  MPI2_HEADER_VERSION_DEV)
0287 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR      (0x03)
0288 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG        (0x8000)
0289 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG          (0x0400)
0290 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP       (0x0003)
0291 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG          (0x0200)
0292 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD           (0x0100)
0293 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP             (0x0004)
0294 /* EEDP escape mode */
0295 #define MPI25_SCSIIO_EEDPFLAGS_DO_NOT_DISABLE_MODE  (0x0040)
0296 #define MPI2_FUNCTION_SCSI_IO_REQUEST               (0x00) /* SCSI IO */
0297 #define MPI2_FUNCTION_SCSI_TASK_MGMT                (0x01)
0298 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY       (0x03)
0299 #define MPI2_REQ_DESCRIPT_FLAGS_FP_IO               (0x06)
0300 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO                 (0x00)
0301 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING        (0x02)
0302 #define MPI2_SCSIIO_CONTROL_WRITE               (0x01000000)
0303 #define MPI2_SCSIIO_CONTROL_READ                (0x02000000)
0304 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK       (0x0E)
0305 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED          (0x0F)
0306 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
0307 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK       (0x0F)
0308 #define MPI2_WRSEQ_FLUSH_KEY_VALUE              (0x0)
0309 #define MPI2_WRITE_SEQUENCE_OFFSET              (0x00000004)
0310 #define MPI2_WRSEQ_1ST_KEY_VALUE                (0xF)
0311 #define MPI2_WRSEQ_2ND_KEY_VALUE                (0x4)
0312 #define MPI2_WRSEQ_3RD_KEY_VALUE                (0xB)
0313 #define MPI2_WRSEQ_4TH_KEY_VALUE                (0x2)
0314 #define MPI2_WRSEQ_5TH_KEY_VALUE                (0x7)
0315 #define MPI2_WRSEQ_6TH_KEY_VALUE                (0xD)
0316 
0317 struct MPI25_IEEE_SGE_CHAIN64 {
0318     __le64          Address;
0319     __le32          Length;
0320     __le16          Reserved1;
0321     u8                      NextChainOffset;
0322     u8                      Flags;
0323 };
0324 
0325 struct MPI2_SGE_SIMPLE_UNION {
0326     __le32                     FlagsLength;
0327     union {
0328         __le32                 Address32;
0329         __le64                 Address64;
0330     } u;
0331 };
0332 
0333 struct MPI2_SCSI_IO_CDB_EEDP32 {
0334     u8                      CDB[20];                    /* 0x00 */
0335     __be32          PrimaryReferenceTag;        /* 0x14 */
0336     __be16          PrimaryApplicationTag;      /* 0x18 */
0337     __be16          PrimaryApplicationTagMask;  /* 0x1A */
0338     __le32          TransferLength;             /* 0x1C */
0339 };
0340 
0341 struct MPI2_SGE_CHAIN_UNION {
0342     __le16          Length;
0343     u8                      NextChainOffset;
0344     u8                      Flags;
0345     union {
0346         __le32      Address32;
0347         __le64      Address64;
0348     } u;
0349 };
0350 
0351 struct MPI2_IEEE_SGE_SIMPLE32 {
0352     __le32          Address;
0353     __le32          FlagsLength;
0354 };
0355 
0356 struct MPI2_IEEE_SGE_CHAIN32 {
0357     __le32          Address;
0358     __le32          FlagsLength;
0359 };
0360 
0361 struct MPI2_IEEE_SGE_SIMPLE64 {
0362     __le64          Address;
0363     __le32          Length;
0364     __le16          Reserved1;
0365     u8                      Reserved2;
0366     u8                      Flags;
0367 };
0368 
0369 struct MPI2_IEEE_SGE_CHAIN64 {
0370     __le64          Address;
0371     __le32          Length;
0372     __le16          Reserved1;
0373     u8                      Reserved2;
0374     u8                      Flags;
0375 };
0376 
0377 union MPI2_IEEE_SGE_SIMPLE_UNION {
0378     struct MPI2_IEEE_SGE_SIMPLE32  Simple32;
0379     struct MPI2_IEEE_SGE_SIMPLE64  Simple64;
0380 };
0381 
0382 union MPI2_IEEE_SGE_CHAIN_UNION {
0383     struct MPI2_IEEE_SGE_CHAIN32   Chain32;
0384     struct MPI2_IEEE_SGE_CHAIN64   Chain64;
0385 };
0386 
0387 union MPI2_SGE_IO_UNION {
0388     struct MPI2_SGE_SIMPLE_UNION       MpiSimple;
0389     struct MPI2_SGE_CHAIN_UNION        MpiChain;
0390     union MPI2_IEEE_SGE_SIMPLE_UNION  IeeeSimple;
0391     union MPI2_IEEE_SGE_CHAIN_UNION   IeeeChain;
0392 };
0393 
0394 union MPI2_SCSI_IO_CDB_UNION {
0395     u8                      CDB32[32];
0396     struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
0397     struct MPI2_SGE_SIMPLE_UNION SGE;
0398 };
0399 
0400 /****************************************************************************
0401 *  SCSI Task Management messages
0402 ****************************************************************************/
0403 
0404 /*SCSI Task Management Request Message */
0405 struct MPI2_SCSI_TASK_MANAGE_REQUEST {
0406     u16 DevHandle;      /*0x00 */
0407     u8 ChainOffset;     /*0x02 */
0408     u8 Function;        /*0x03 */
0409     u8 Reserved1;       /*0x04 */
0410     u8 TaskType;        /*0x05 */
0411     u8 Reserved2;       /*0x06 */
0412     u8 MsgFlags;        /*0x07 */
0413     u8 VP_ID;       /*0x08 */
0414     u8 VF_ID;       /*0x09 */
0415     u16 Reserved3;      /*0x0A */
0416     u8 LUN[8];      /*0x0C */
0417     u32 Reserved4[7];   /*0x14 */
0418     u16 TaskMID;        /*0x30 */
0419     u16 Reserved5;      /*0x32 */
0420 };
0421 
0422 
0423 /*SCSI Task Management Reply Message */
0424 struct MPI2_SCSI_TASK_MANAGE_REPLY {
0425     u16 DevHandle;      /*0x00 */
0426     u8 MsgLength;       /*0x02 */
0427     u8 Function;        /*0x03 */
0428     u8 ResponseCode;    /*0x04 */
0429     u8 TaskType;        /*0x05 */
0430     u8 Reserved1;       /*0x06 */
0431     u8 MsgFlags;        /*0x07 */
0432     u8 VP_ID;       /*0x08 */
0433     u8 VF_ID;       /*0x09 */
0434     u16 Reserved2;      /*0x0A */
0435     u16 Reserved3;      /*0x0C */
0436     u16 IOCStatus;      /*0x0E */
0437     u32 IOCLogInfo;     /*0x10 */
0438     u32 TerminationCount;   /*0x14 */
0439     u32 ResponseInfo;   /*0x18 */
0440 };
0441 
0442 struct MR_TM_REQUEST {
0443     char request[128];
0444 };
0445 
0446 struct MR_TM_REPLY {
0447     char reply[128];
0448 };
0449 
0450 /* SCSI Task Management Request Message */
0451 struct MR_TASK_MANAGE_REQUEST {
0452     /*To be type casted to struct MPI2_SCSI_TASK_MANAGE_REQUEST */
0453     struct MR_TM_REQUEST         TmRequest;
0454     union {
0455         struct {
0456 #if   defined(__BIG_ENDIAN_BITFIELD)
0457             u32 reserved1:30;
0458             u32 isTMForPD:1;
0459             u32 isTMForLD:1;
0460 #else
0461             u32 isTMForLD:1;
0462             u32 isTMForPD:1;
0463             u32 reserved1:30;
0464 #endif
0465             u32 reserved2;
0466         } tmReqFlags;
0467         struct MR_TM_REPLY   TMReply;
0468     };
0469 };
0470 
0471 /* TaskType values */
0472 
0473 #define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK           (0x01)
0474 #define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET        (0x02)
0475 #define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET         (0x03)
0476 #define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET   (0x05)
0477 #define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET       (0x06)
0478 #define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK           (0x07)
0479 #define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA              (0x08)
0480 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET         (0x09)
0481 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT      (0x0A)
0482 
0483 /* ResponseCode values */
0484 
0485 #define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE               (0x00)
0486 #define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME             (0x02)
0487 #define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED          (0x04)
0488 #define MPI2_SCSITASKMGMT_RSP_TM_FAILED                 (0x05)
0489 #define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED              (0x08)
0490 #define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN            (0x09)
0491 #define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG         (0x0A)
0492 #define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC          (0x80)
0493 
0494 /*
0495  * RAID SCSI IO Request Message
0496  * Total SGE count will be one less than  _MPI2_SCSI_IO_REQUEST
0497  */
0498 struct MPI2_RAID_SCSI_IO_REQUEST {
0499     __le16          DevHandle;                      /* 0x00 */
0500     u8                      ChainOffset;                    /* 0x02 */
0501     u8                      Function;                       /* 0x03 */
0502     __le16          Reserved1;                      /* 0x04 */
0503     u8                      Reserved2;                      /* 0x06 */
0504     u8                      MsgFlags;                       /* 0x07 */
0505     u8                      VP_ID;                          /* 0x08 */
0506     u8                      VF_ID;                          /* 0x09 */
0507     __le16          Reserved3;                      /* 0x0A */
0508     __le32          SenseBufferLowAddress;          /* 0x0C */
0509     __le16          SGLFlags;                       /* 0x10 */
0510     u8                      SenseBufferLength;              /* 0x12 */
0511     u8                      Reserved4;                      /* 0x13 */
0512     u8                      SGLOffset0;                     /* 0x14 */
0513     u8                      SGLOffset1;                     /* 0x15 */
0514     u8                      SGLOffset2;                     /* 0x16 */
0515     u8                      SGLOffset3;                     /* 0x17 */
0516     __le32          SkipCount;                      /* 0x18 */
0517     __le32          DataLength;                     /* 0x1C */
0518     __le32          BidirectionalDataLength;        /* 0x20 */
0519     __le16          IoFlags;                        /* 0x24 */
0520     __le16          EEDPFlags;                      /* 0x26 */
0521     __le32          EEDPBlockSize;                  /* 0x28 */
0522     __le32          SecondaryReferenceTag;          /* 0x2C */
0523     __le16          SecondaryApplicationTag;        /* 0x30 */
0524     __le16          ApplicationTagTranslationMask;  /* 0x32 */
0525     u8                      LUN[8];                         /* 0x34 */
0526     __le32          Control;                        /* 0x3C */
0527     union MPI2_SCSI_IO_CDB_UNION  CDB;          /* 0x40 */
0528     union RAID_CONTEXT_UNION RaidContext;  /* 0x60 */
0529     union MPI2_SGE_IO_UNION       SGL;          /* 0x80 */
0530 };
0531 
0532 /*
0533  * MPT RAID MFA IO Descriptor.
0534  */
0535 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR {
0536     u32     RequestFlags:8;
0537     u32     MessageAddress1:24;
0538     u32     MessageAddress2;
0539 };
0540 
0541 /* Default Request Descriptor */
0542 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR {
0543     u8              RequestFlags;               /* 0x00 */
0544     u8              MSIxIndex;                  /* 0x01 */
0545     __le16      SMID;                       /* 0x02 */
0546     __le16      LMID;                       /* 0x04 */
0547     __le16      DescriptorTypeDependent;    /* 0x06 */
0548 };
0549 
0550 /* High Priority Request Descriptor */
0551 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
0552     u8              RequestFlags;               /* 0x00 */
0553     u8              MSIxIndex;                  /* 0x01 */
0554     __le16      SMID;                       /* 0x02 */
0555     __le16      LMID;                       /* 0x04 */
0556     __le16      Reserved1;                  /* 0x06 */
0557 };
0558 
0559 /* SCSI IO Request Descriptor */
0560 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
0561     u8              RequestFlags;               /* 0x00 */
0562     u8              MSIxIndex;                  /* 0x01 */
0563     __le16      SMID;                       /* 0x02 */
0564     __le16      LMID;                       /* 0x04 */
0565     __le16      DevHandle;                  /* 0x06 */
0566 };
0567 
0568 /* SCSI Target Request Descriptor */
0569 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
0570     u8              RequestFlags;               /* 0x00 */
0571     u8              MSIxIndex;                  /* 0x01 */
0572     __le16      SMID;                       /* 0x02 */
0573     __le16      LMID;                       /* 0x04 */
0574     __le16      IoIndex;                    /* 0x06 */
0575 };
0576 
0577 /* RAID Accelerator Request Descriptor */
0578 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
0579     u8              RequestFlags;               /* 0x00 */
0580     u8              MSIxIndex;                  /* 0x01 */
0581     __le16      SMID;                       /* 0x02 */
0582     __le16      LMID;                       /* 0x04 */
0583     __le16      Reserved;                   /* 0x06 */
0584 };
0585 
0586 /* union of Request Descriptors */
0587 union MEGASAS_REQUEST_DESCRIPTOR_UNION {
0588     struct MPI2_DEFAULT_REQUEST_DESCRIPTOR             Default;
0589     struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR       HighPriority;
0590     struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR             SCSIIO;
0591     struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR         SCSITarget;
0592     struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR          RAIDAccelerator;
0593     struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR      MFAIo;
0594     union {
0595         struct {
0596             __le32 low;
0597             __le32 high;
0598         } u;
0599         __le64 Words;
0600     };
0601 };
0602 
0603 /* Default Reply Descriptor */
0604 struct MPI2_DEFAULT_REPLY_DESCRIPTOR {
0605     u8              ReplyFlags;                 /* 0x00 */
0606     u8              MSIxIndex;                  /* 0x01 */
0607     __le16      DescriptorTypeDependent1;   /* 0x02 */
0608     __le32      DescriptorTypeDependent2;   /* 0x04 */
0609 };
0610 
0611 /* Address Reply Descriptor */
0612 struct MPI2_ADDRESS_REPLY_DESCRIPTOR {
0613     u8              ReplyFlags;                 /* 0x00 */
0614     u8              MSIxIndex;                  /* 0x01 */
0615     __le16      SMID;                       /* 0x02 */
0616     __le32      ReplyFrameAddress;          /* 0x04 */
0617 };
0618 
0619 /* SCSI IO Success Reply Descriptor */
0620 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
0621     u8              ReplyFlags;                 /* 0x00 */
0622     u8              MSIxIndex;                  /* 0x01 */
0623     __le16      SMID;                       /* 0x02 */
0624     __le16      TaskTag;                    /* 0x04 */
0625     __le16      Reserved1;                  /* 0x06 */
0626 };
0627 
0628 /* TargetAssist Success Reply Descriptor */
0629 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
0630     u8              ReplyFlags;                 /* 0x00 */
0631     u8              MSIxIndex;                  /* 0x01 */
0632     __le16      SMID;                       /* 0x02 */
0633     u8              SequenceNumber;             /* 0x04 */
0634     u8              Reserved1;                  /* 0x05 */
0635     __le16      IoIndex;                    /* 0x06 */
0636 };
0637 
0638 /* Target Command Buffer Reply Descriptor */
0639 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
0640     u8              ReplyFlags;                 /* 0x00 */
0641     u8              MSIxIndex;                  /* 0x01 */
0642     u8              VP_ID;                      /* 0x02 */
0643     u8              Flags;                      /* 0x03 */
0644     __le16      InitiatorDevHandle;         /* 0x04 */
0645     __le16      IoIndex;                    /* 0x06 */
0646 };
0647 
0648 /* RAID Accelerator Success Reply Descriptor */
0649 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
0650     u8              ReplyFlags;                 /* 0x00 */
0651     u8              MSIxIndex;                  /* 0x01 */
0652     __le16      SMID;                       /* 0x02 */
0653     __le32      Reserved;                   /* 0x04 */
0654 };
0655 
0656 /* union of Reply Descriptors */
0657 union MPI2_REPLY_DESCRIPTORS_UNION {
0658     struct MPI2_DEFAULT_REPLY_DESCRIPTOR                   Default;
0659     struct MPI2_ADDRESS_REPLY_DESCRIPTOR                   AddressReply;
0660     struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR           SCSIIOSuccess;
0661     struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
0662     struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
0663     struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
0664     RAIDAcceleratorSuccess;
0665     __le64                                             Words;
0666 };
0667 
0668 /* IOCInit Request message */
0669 struct MPI2_IOC_INIT_REQUEST {
0670     u8                      WhoInit;                        /* 0x00 */
0671     u8                      Reserved1;                      /* 0x01 */
0672     u8                      ChainOffset;                    /* 0x02 */
0673     u8                      Function;                       /* 0x03 */
0674     __le16          Reserved2;                      /* 0x04 */
0675     u8                      Reserved3;                      /* 0x06 */
0676     u8                      MsgFlags;                       /* 0x07 */
0677     u8                      VP_ID;                          /* 0x08 */
0678     u8                      VF_ID;                          /* 0x09 */
0679     __le16          Reserved4;                      /* 0x0A */
0680     __le16          MsgVersion;                     /* 0x0C */
0681     __le16          HeaderVersion;                  /* 0x0E */
0682     u32                     Reserved5;                      /* 0x10 */
0683     __le16          Reserved6;                      /* 0x14 */
0684     u8                      HostPageSize;                   /* 0x16 */
0685     u8                      HostMSIxVectors;                /* 0x17 */
0686     __le16          Reserved8;                      /* 0x18 */
0687     __le16          SystemRequestFrameSize;         /* 0x1A */
0688     __le16          ReplyDescriptorPostQueueDepth;  /* 0x1C */
0689     __le16          ReplyFreeQueueDepth;            /* 0x1E */
0690     __le32          SenseBufferAddressHigh;         /* 0x20 */
0691     __le32          SystemReplyAddressHigh;         /* 0x24 */
0692     __le64          SystemRequestFrameBaseAddress;  /* 0x28 */
0693     __le64          ReplyDescriptorPostQueueAddress;/* 0x30 */
0694     __le64          ReplyFreeQueueAddress;          /* 0x38 */
0695     __le64          TimeStamp;                      /* 0x40 */
0696 };
0697 
0698 /* mrpriv defines */
0699 #define MR_PD_INVALID 0xFFFF
0700 #define MR_DEVHANDLE_INVALID 0xFFFF
0701 #define MAX_SPAN_DEPTH 8
0702 #define MAX_QUAD_DEPTH  MAX_SPAN_DEPTH
0703 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
0704 #define MAX_ROW_SIZE 32
0705 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
0706 #define MAX_LOGICAL_DRIVES 64
0707 #define MAX_LOGICAL_DRIVES_EXT 256
0708 #define MAX_LOGICAL_DRIVES_DYN 512
0709 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
0710 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
0711 #define MAX_ARRAYS 128
0712 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
0713 #define MAX_ARRAYS_EXT  256
0714 #define MAX_API_ARRAYS_EXT (MAX_ARRAYS_EXT)
0715 #define MAX_API_ARRAYS_DYN 512
0716 #define MAX_PHYSICAL_DEVICES 256
0717 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
0718 #define MAX_RAIDMAP_PHYSICAL_DEVICES_DYN 512
0719 #define MR_DCMD_LD_MAP_GET_INFO             0x0300e101
0720 #define MR_DCMD_SYSTEM_PD_MAP_GET_INFO      0x0200e102
0721 #define MR_DCMD_DRV_GET_TARGET_PROP         0x0200e103
0722 #define MR_DCMD_CTRL_SHARED_HOST_MEM_ALLOC  0x010e8485   /* SR-IOV HB alloc*/
0723 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS_111   0x03200200
0724 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS       0x03150200
0725 #define MR_DCMD_CTRL_SNAPDUMP_GET_PROPERTIES    0x01200100
0726 #define MR_DCMD_CTRL_DEVICE_LIST_GET        0x01190600
0727 
0728 struct MR_DEV_HANDLE_INFO {
0729     __le16  curDevHdl;
0730     u8      validHandles;
0731     u8      interfaceType;
0732     __le16  devHandle[2];
0733 };
0734 
0735 struct MR_ARRAY_INFO {
0736     __le16  pd[MAX_RAIDMAP_ROW_SIZE];
0737 };
0738 
0739 struct MR_QUAD_ELEMENT {
0740     __le64     logStart;
0741     __le64     logEnd;
0742     __le64     offsetInSpan;
0743     __le32     diff;
0744     __le32     reserved1;
0745 };
0746 
0747 struct MR_SPAN_INFO {
0748     __le32             noElements;
0749     __le32             reserved1;
0750     struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH];
0751 };
0752 
0753 struct MR_LD_SPAN {
0754     __le64   startBlk;
0755     __le64   numBlks;
0756     __le16   arrayRef;
0757     u8       spanRowSize;
0758     u8       spanRowDataSize;
0759     u8       reserved[4];
0760 };
0761 
0762 struct MR_SPAN_BLOCK_INFO {
0763     __le64          num_rows;
0764     struct MR_LD_SPAN   span;
0765     struct MR_SPAN_INFO block_span_info;
0766 };
0767 
0768 #define MR_RAID_CTX_CPUSEL_0        0
0769 #define MR_RAID_CTX_CPUSEL_1        1
0770 #define MR_RAID_CTX_CPUSEL_2        2
0771 #define MR_RAID_CTX_CPUSEL_3        3
0772 #define MR_RAID_CTX_CPUSEL_FCFS     0xF
0773 
0774 struct MR_CPU_AFFINITY_MASK {
0775     union {
0776         struct {
0777 #ifndef __BIG_ENDIAN_BITFIELD
0778         u8 hw_path:1;
0779         u8 cpu0:1;
0780         u8 cpu1:1;
0781         u8 cpu2:1;
0782         u8 cpu3:1;
0783         u8 reserved:3;
0784 #else
0785         u8 reserved:3;
0786         u8 cpu3:1;
0787         u8 cpu2:1;
0788         u8 cpu1:1;
0789         u8 cpu0:1;
0790         u8 hw_path:1;
0791 #endif
0792         };
0793         u8 core_mask;
0794     };
0795 };
0796 
0797 struct MR_IO_AFFINITY {
0798     union {
0799         struct {
0800             struct MR_CPU_AFFINITY_MASK pdRead;
0801             struct MR_CPU_AFFINITY_MASK pdWrite;
0802             struct MR_CPU_AFFINITY_MASK ldRead;
0803             struct MR_CPU_AFFINITY_MASK ldWrite;
0804             };
0805         u32 word;
0806         };
0807     u8 maxCores;    /* Total cores + HW Path in ROC */
0808     u8 reserved[3];
0809 };
0810 
0811 struct MR_LD_RAID {
0812     struct {
0813 #if   defined(__BIG_ENDIAN_BITFIELD)
0814         u32 reserved4:2;
0815         u32 fp_cache_bypass_capable:1;
0816         u32 fp_rmw_capable:1;
0817         u32 disable_coalescing:1;
0818         u32     fpBypassRegionLock:1;
0819         u32     tmCapable:1;
0820         u32 fpNonRWCapable:1;
0821         u32     fpReadAcrossStripe:1;
0822         u32     fpWriteAcrossStripe:1;
0823         u32     fpReadCapable:1;
0824         u32     fpWriteCapable:1;
0825         u32     encryptionType:8;
0826         u32     pdPiMode:4;
0827         u32     ldPiMode:4;
0828         u32 reserved5:2;
0829         u32 ra_capable:1;
0830         u32     fpCapable:1;
0831 #else
0832         u32     fpCapable:1;
0833         u32 ra_capable:1;
0834         u32 reserved5:2;
0835         u32     ldPiMode:4;
0836         u32     pdPiMode:4;
0837         u32     encryptionType:8;
0838         u32     fpWriteCapable:1;
0839         u32     fpReadCapable:1;
0840         u32     fpWriteAcrossStripe:1;
0841         u32     fpReadAcrossStripe:1;
0842         u32 fpNonRWCapable:1;
0843         u32     tmCapable:1;
0844         u32     fpBypassRegionLock:1;
0845         u32 disable_coalescing:1;
0846         u32 fp_rmw_capable:1;
0847         u32 fp_cache_bypass_capable:1;
0848         u32 reserved4:2;
0849 #endif
0850     } capability;
0851     __le32     reserved6;
0852     __le64     size;
0853     u8      spanDepth;
0854     u8      level;
0855     u8      stripeShift;
0856     u8      rowSize;
0857     u8      rowDataSize;
0858     u8      writeMode;
0859     u8      PRL;
0860     u8      SRL;
0861     __le16     targetId;
0862     u8      ldState;
0863     u8      regTypeReqOnWrite;
0864     u8      modFactor;
0865     u8  regTypeReqOnRead;
0866     __le16     seqNum;
0867 
0868 struct {
0869 #ifndef __BIG_ENDIAN_BITFIELD
0870     u32 ldSyncRequired:1;
0871     u32 regTypeReqOnReadIsValid:1;
0872     u32 isEPD:1;
0873     u32 enableSLDOnAllRWIOs:1;
0874     u32 reserved:28;
0875 #else
0876     u32 reserved:28;
0877     u32 enableSLDOnAllRWIOs:1;
0878     u32 isEPD:1;
0879     u32 regTypeReqOnReadIsValid:1;
0880     u32 ldSyncRequired:1;
0881 #endif
0882     } flags;
0883 
0884     u8  LUN[8]; /* 0x24 8 byte LUN field used for SCSI IO's */
0885     u8  fpIoTimeoutForLd;/*0x2C timeout value used by driver in FP IO*/
0886     /* Ox2D This LD accept priority boost of this type */
0887     u8 ld_accept_priority_type;
0888     u8 reserved2[2];            /* 0x2E - 0x2F */
0889     /* 0x30 - 0x33, Logical block size for the LD */
0890     u32 logical_block_length;
0891     struct {
0892 #ifndef __BIG_ENDIAN_BITFIELD
0893     /* 0x34, P_I_EXPONENT from READ CAPACITY 16 */
0894     u32 ld_pi_exp:4;
0895     /* 0x34, LOGICAL BLOCKS PER PHYSICAL
0896      *  BLOCK EXPONENT from READ CAPACITY 16
0897      */
0898     u32 ld_logical_block_exp:4;
0899     u32 reserved1:24;           /* 0x34 */
0900 #else
0901     u32 reserved1:24;           /* 0x34 */
0902     /* 0x34, LOGICAL BLOCKS PER PHYSICAL
0903      *  BLOCK EXPONENT from READ CAPACITY 16
0904      */
0905     u32 ld_logical_block_exp:4;
0906     /* 0x34, P_I_EXPONENT from READ CAPACITY 16 */
0907     u32 ld_pi_exp:4;
0908 #endif
0909     };                               /* 0x34 - 0x37 */
0910      /* 0x38 - 0x3f, This will determine which
0911       *  core will process LD IO and PD IO.
0912       */
0913     struct MR_IO_AFFINITY cpuAffinity;
0914      /* Bit definiations are specified by MR_IO_AFFINITY */
0915     u8 reserved3[0x80 - 0x40];    /* 0x40 - 0x7f */
0916 };
0917 
0918 struct MR_LD_SPAN_MAP {
0919     struct MR_LD_RAID          ldRaid;
0920     u8                  dataArmMap[MAX_RAIDMAP_ROW_SIZE];
0921     struct MR_SPAN_BLOCK_INFO  spanBlock[MAX_RAIDMAP_SPAN_DEPTH];
0922 };
0923 
0924 struct MR_FW_RAID_MAP {
0925     __le32                 totalSize;
0926     union {
0927         struct {
0928             __le32         maxLd;
0929             __le32         maxSpanDepth;
0930             __le32         maxRowSize;
0931             __le32         maxPdCount;
0932             __le32         maxArrays;
0933         } validationInfo;
0934         __le32             version[5];
0935     };
0936 
0937     __le32                 ldCount;
0938     __le32                 Reserved1;
0939     u8                  ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+
0940                     MAX_RAIDMAP_VIEWS];
0941     u8                  fpPdIoTimeoutSec;
0942     u8                  reserved2[7];
0943     struct MR_ARRAY_INFO       arMapInfo[MAX_RAIDMAP_ARRAYS];
0944     struct MR_DEV_HANDLE_INFO  devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
0945     struct MR_LD_SPAN_MAP      ldSpanMap[1];
0946 };
0947 
0948 struct IO_REQUEST_INFO {
0949     u64 ldStartBlock;
0950     u32 numBlocks;
0951     u16 ldTgtId;
0952     u8 isRead;
0953     __le16 devHandle;
0954     u8 pd_interface;
0955     u64 pdBlock;
0956     u8 fpOkForIo;
0957     u8 IoforUnevenSpan;
0958     u8 start_span;
0959     u8 do_fp_rlbypass;
0960     u64 start_row;
0961     u8  span_arm;   /* span[7:5], arm[4:0] */
0962     u8  pd_after_lb;
0963     u16 r1_alt_dev_handle; /* raid 1/10 only */
0964     bool ra_capable;
0965     u8 data_arms;
0966 };
0967 
0968 struct MR_LD_TARGET_SYNC {
0969     u8  targetId;
0970     u8  reserved;
0971     __le16 seqNum;
0972 };
0973 
0974 /*
0975  * RAID Map descriptor Types.
0976  * Each element should uniquely idetify one data structure in the RAID map
0977  */
0978 enum MR_RAID_MAP_DESC_TYPE {
0979     /* MR_DEV_HANDLE_INFO data */
0980     RAID_MAP_DESC_TYPE_DEVHDL_INFO    = 0x0,
0981     /* target to Ld num Index map */
0982     RAID_MAP_DESC_TYPE_TGTID_INFO     = 0x1,
0983     /* MR_ARRAY_INFO data */
0984     RAID_MAP_DESC_TYPE_ARRAY_INFO     = 0x2,
0985     /* MR_LD_SPAN_MAP data */
0986     RAID_MAP_DESC_TYPE_SPAN_INFO      = 0x3,
0987     RAID_MAP_DESC_TYPE_COUNT,
0988 };
0989 
0990 /*
0991  * This table defines the offset, size and num elements  of each descriptor
0992  * type in the RAID Map buffer
0993  */
0994 struct MR_RAID_MAP_DESC_TABLE {
0995     /* Raid map descriptor type */
0996     u32 raid_map_desc_type;
0997     /* Offset into the RAID map buffer where
0998      *  descriptor data is saved
0999      */
1000     u32 raid_map_desc_offset;
1001     /* total size of the
1002      * descriptor buffer
1003      */
1004     u32 raid_map_desc_buffer_size;
1005     /* Number of elements contained in the
1006      *  descriptor buffer
1007      */
1008     u32 raid_map_desc_elements;
1009 };
1010 
1011 /*
1012  * Dynamic Raid Map Structure.
1013  */
1014 struct MR_FW_RAID_MAP_DYNAMIC {
1015     u32 raid_map_size;   /* total size of RAID Map structure */
1016     u32 desc_table_offset;/* Offset of desc table into RAID map*/
1017     u32 desc_table_size;  /* Total Size of desc table */
1018     /* Total Number of elements in the desc table */
1019     u32 desc_table_num_elements;
1020     u64 reserved1;
1021     u32 reserved2[3];   /*future use */
1022     /* timeout value used by driver in FP IOs */
1023     u8 fp_pd_io_timeout_sec;
1024     u8 reserved3[3];
1025     /* when this seqNum increments, driver needs to
1026      *  release RMW buffers asap
1027      */
1028     u32 rmw_fp_seq_num;
1029     u16 ld_count;   /* count of lds. */
1030     u16 ar_count;   /* count of arrays */
1031     u16 span_count; /* count of spans */
1032     u16 reserved4[3];
1033 /*
1034  * The below structure of pointers is only to be used by the driver.
1035  * This is added in the ,API to reduce the amount of code changes
1036  * needed in the driver to support dynamic RAID map Firmware should
1037  * not update these pointers while preparing the raid map
1038  */
1039     union {
1040         struct {
1041             struct MR_DEV_HANDLE_INFO  *dev_hndl_info;
1042             u16 *ld_tgt_id_to_ld;
1043             struct MR_ARRAY_INFO *ar_map_info;
1044             struct MR_LD_SPAN_MAP *ld_span_map;
1045             };
1046         u64 ptr_structure_size[RAID_MAP_DESC_TYPE_COUNT];
1047         };
1048 /*
1049  * RAID Map descriptor table defines the layout of data in the RAID Map.
1050  * The size of the descriptor table itself could change.
1051  */
1052     /* Variable Size descriptor Table. */
1053     struct MR_RAID_MAP_DESC_TABLE
1054             raid_map_desc_table[RAID_MAP_DESC_TYPE_COUNT];
1055     /* Variable Size buffer containing all data */
1056     u32 raid_map_desc_data[1];
1057 }; /* Dynamicaly sized RAID MAp structure */
1058 
1059 #define IEEE_SGE_FLAGS_ADDR_MASK            (0x03)
1060 #define IEEE_SGE_FLAGS_SYSTEM_ADDR          (0x00)
1061 #define IEEE_SGE_FLAGS_IOCDDR_ADDR          (0x01)
1062 #define IEEE_SGE_FLAGS_IOCPLB_ADDR          (0x02)
1063 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR       (0x03)
1064 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT        (0x80)
1065 #define IEEE_SGE_FLAGS_END_OF_LIST          (0x40)
1066 
1067 #define MPI2_SGE_FLAGS_SHIFT                (0x02)
1068 #define IEEE_SGE_FLAGS_FORMAT_MASK          (0xC0)
1069 #define IEEE_SGE_FLAGS_FORMAT_IEEE          (0x00)
1070 #define IEEE_SGE_FLAGS_FORMAT_NVME          (0x02)
1071 
1072 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK           (0x1C)
1073 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE       (0x00)
1074 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP       (0x08)
1075 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL       (0x10)
1076 
1077 #define MEGASAS_DEFAULT_SNAP_DUMP_WAIT_TIME 15
1078 #define MEGASAS_MAX_SNAP_DUMP_WAIT_TIME 60
1079 
1080 struct megasas_register_set;
1081 struct megasas_instance;
1082 
1083 union desc_word {
1084     u64 word;
1085     struct {
1086         u32 low;
1087         u32 high;
1088     } u;
1089 };
1090 
1091 struct megasas_cmd_fusion {
1092     struct MPI2_RAID_SCSI_IO_REQUEST    *io_request;
1093     dma_addr_t          io_request_phys_addr;
1094 
1095     union MPI2_SGE_IO_UNION *sg_frame;
1096     dma_addr_t      sg_frame_phys_addr;
1097 
1098     u8 *sense;
1099     dma_addr_t sense_phys_addr;
1100 
1101     struct list_head list;
1102     struct scsi_cmnd *scmd;
1103     struct megasas_instance *instance;
1104 
1105     u8 retry_for_fw_reset;
1106     union MEGASAS_REQUEST_DESCRIPTOR_UNION  *request_desc;
1107 
1108     /*
1109      * Context for a MFI frame.
1110      * Used to get the mfi cmd from list when a MFI cmd is completed
1111      */
1112     u32 sync_cmd_idx;
1113     u32 index;
1114     u8 pd_r1_lb;
1115     struct completion done;
1116     u8 pd_interface;
1117     u16 r1_alt_dev_handle; /* raid 1/10 only*/
1118     bool cmd_completed;  /* raid 1/10 fp writes status holder */
1119 
1120 };
1121 
1122 struct LD_LOAD_BALANCE_INFO {
1123     u8  loadBalanceFlag;
1124     u8  reserved1;
1125     atomic_t     scsi_pending_cmds[MAX_PHYSICAL_DEVICES];
1126     u64     last_accessed_block[MAX_PHYSICAL_DEVICES];
1127 };
1128 
1129 /* SPAN_SET is info caclulated from span info from Raid map per LD */
1130 typedef struct _LD_SPAN_SET {
1131     u64  log_start_lba;
1132     u64  log_end_lba;
1133     u64  span_row_start;
1134     u64  span_row_end;
1135     u64  data_strip_start;
1136     u64  data_strip_end;
1137     u64  data_row_start;
1138     u64  data_row_end;
1139     u8   strip_offset[MAX_SPAN_DEPTH];
1140     u32    span_row_data_width;
1141     u32    diff;
1142     u32    reserved[2];
1143 } LD_SPAN_SET, *PLD_SPAN_SET;
1144 
1145 typedef struct LOG_BLOCK_SPAN_INFO {
1146     LD_SPAN_SET  span_set[MAX_SPAN_DEPTH];
1147 } LD_SPAN_INFO, *PLD_SPAN_INFO;
1148 
1149 struct MR_FW_RAID_MAP_ALL {
1150     struct MR_FW_RAID_MAP raidMap;
1151     struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
1152 } __attribute__ ((packed));
1153 
1154 struct MR_DRV_RAID_MAP {
1155     /* total size of this structure, including this field.
1156      * This feild will be manupulated by driver for ext raid map,
1157      * else pick the value from firmware raid map.
1158      */
1159     __le32                 totalSize;
1160 
1161     union {
1162     struct {
1163         __le32         maxLd;
1164         __le32         maxSpanDepth;
1165         __le32         maxRowSize;
1166         __le32         maxPdCount;
1167         __le32         maxArrays;
1168     } validationInfo;
1169     __le32             version[5];
1170     };
1171 
1172     /* timeout value used by driver in FP IOs*/
1173     u8                  fpPdIoTimeoutSec;
1174     u8                  reserved2[7];
1175 
1176     __le16                 ldCount;
1177     __le16                 arCount;
1178     __le16                 spanCount;
1179     __le16                 reserve3;
1180 
1181     struct MR_DEV_HANDLE_INFO
1182         devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES_DYN];
1183     u16 ldTgtIdToLd[MAX_LOGICAL_DRIVES_DYN];
1184     struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_DYN];
1185     struct MR_LD_SPAN_MAP      ldSpanMap[1];
1186 
1187 };
1188 
1189 /* Driver raid map size is same as raid map ext
1190  * MR_DRV_RAID_MAP_ALL is created to sync with old raid.
1191  * And it is mainly for code re-use purpose.
1192  */
1193 struct MR_DRV_RAID_MAP_ALL {
1194 
1195     struct MR_DRV_RAID_MAP raidMap;
1196     struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_DYN - 1];
1197 } __packed;
1198 
1199 
1200 
1201 struct MR_FW_RAID_MAP_EXT {
1202     /* Not usred in new map */
1203     u32                 reserved;
1204 
1205     union {
1206     struct {
1207         u32         maxLd;
1208         u32         maxSpanDepth;
1209         u32         maxRowSize;
1210         u32         maxPdCount;
1211         u32         maxArrays;
1212     } validationInfo;
1213     u32             version[5];
1214     };
1215 
1216     u8                  fpPdIoTimeoutSec;
1217     u8                  reserved2[7];
1218 
1219     __le16                 ldCount;
1220     __le16                 arCount;
1221     __le16                 spanCount;
1222     __le16                 reserve3;
1223 
1224     struct MR_DEV_HANDLE_INFO  devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
1225     u8                  ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
1226     struct MR_ARRAY_INFO       arMapInfo[MAX_API_ARRAYS_EXT];
1227     struct MR_LD_SPAN_MAP      ldSpanMap[MAX_LOGICAL_DRIVES_EXT];
1228 };
1229 
1230 /*
1231  *  * define MR_PD_CFG_SEQ structure for system PDs
1232  *   */
1233 struct MR_PD_CFG_SEQ {
1234     u16 seqNum;
1235     u16 devHandle;
1236     struct {
1237 #if   defined(__BIG_ENDIAN_BITFIELD)
1238         u8     reserved:7;
1239         u8     tmCapable:1;
1240 #else
1241         u8     tmCapable:1;
1242         u8     reserved:7;
1243 #endif
1244     } capability;
1245     u8  reserved;
1246     u16 pd_target_id;
1247 } __packed;
1248 
1249 struct MR_PD_CFG_SEQ_NUM_SYNC {
1250     __le32 size;
1251     __le32 count;
1252     struct MR_PD_CFG_SEQ seq[1];
1253 } __packed;
1254 
1255 /* stream detection */
1256 struct STREAM_DETECT {
1257     u64 next_seq_lba; /* next LBA to match sequential access */
1258     struct megasas_cmd_fusion *first_cmd_fusion; /* first cmd in group */
1259     struct megasas_cmd_fusion *last_cmd_fusion; /* last cmd in group */
1260     u32 count_cmds_in_stream; /* count of host commands in this stream */
1261     u16 num_sges_in_group; /* total number of SGEs in grouped IOs */
1262     u8 is_read; /* SCSI OpCode for this stream */
1263     u8 group_depth; /* total number of host commands in group */
1264     /* TRUE if cannot add any more commands to this group */
1265     bool group_flush;
1266     u8 reserved[7]; /* pad to 64-bit alignment */
1267 };
1268 
1269 struct LD_STREAM_DETECT {
1270     bool write_back; /* TRUE if WB, FALSE if WT */
1271     bool fp_write_enabled;
1272     bool members_ssds;
1273     bool fp_cache_bypass_capable;
1274     u32 mru_bit_map; /* bitmap used to track MRU and LRU stream indicies */
1275     /* this is the array of stream detect structures (one per stream) */
1276     struct STREAM_DETECT stream_track[MAX_STREAMS_TRACKED];
1277 };
1278 
1279 struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
1280     u64 RDPQBaseAddress;
1281     u32 Reserved1;
1282     u32 Reserved2;
1283 };
1284 
1285 struct rdpq_alloc_detail {
1286     struct dma_pool *dma_pool_ptr;
1287     dma_addr_t  pool_entry_phys;
1288     union MPI2_REPLY_DESCRIPTORS_UNION *pool_entry_virt;
1289 };
1290 
1291 struct fusion_context {
1292     struct megasas_cmd_fusion **cmd_list;
1293     dma_addr_t req_frames_desc_phys;
1294     u8 *req_frames_desc;
1295 
1296     struct dma_pool *io_request_frames_pool;
1297     dma_addr_t io_request_frames_phys;
1298     u8 *io_request_frames;
1299 
1300     struct dma_pool *sg_dma_pool;
1301     struct dma_pool *sense_dma_pool;
1302 
1303     u8 *sense;
1304     dma_addr_t sense_phys_addr;
1305 
1306     atomic_t   busy_mq_poll[MAX_MSIX_QUEUES_FUSION];
1307 
1308     dma_addr_t reply_frames_desc_phys[MAX_MSIX_QUEUES_FUSION];
1309     union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc[MAX_MSIX_QUEUES_FUSION];
1310     struct rdpq_alloc_detail rdpq_tracker[RDPQ_MAX_CHUNK_COUNT];
1311     struct dma_pool *reply_frames_desc_pool;
1312     struct dma_pool *reply_frames_desc_pool_align;
1313 
1314     u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION];
1315 
1316     u32 reply_q_depth;
1317     u32 request_alloc_sz;
1318     u32 reply_alloc_sz;
1319     u32 io_frames_alloc_sz;
1320 
1321     struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY *rdpq_virt;
1322     dma_addr_t rdpq_phys;
1323     u16 max_sge_in_main_msg;
1324     u16 max_sge_in_chain;
1325 
1326     u8  chain_offset_io_request;
1327     u8  chain_offset_mfi_pthru;
1328 
1329     struct MR_FW_RAID_MAP_DYNAMIC *ld_map[2];
1330     dma_addr_t ld_map_phys[2];
1331 
1332     /*Non dma-able memory. Driver local copy.*/
1333     struct MR_DRV_RAID_MAP_ALL *ld_drv_map[2];
1334 
1335     u32 max_map_sz;
1336     u32 current_map_sz;
1337     u32 old_map_sz;
1338     u32 new_map_sz;
1339     u32 drv_map_sz;
1340     u32 drv_map_pages;
1341     struct MR_PD_CFG_SEQ_NUM_SYNC   *pd_seq_sync[JBOD_MAPS_COUNT];
1342     dma_addr_t pd_seq_phys[JBOD_MAPS_COUNT];
1343     u8 fast_path_io;
1344     struct LD_LOAD_BALANCE_INFO *load_balance_info;
1345     u32 load_balance_info_pages;
1346     LD_SPAN_INFO *log_to_span;
1347     u32 log_to_span_pages;
1348     struct LD_STREAM_DETECT **stream_detect_by_ld;
1349     dma_addr_t ioc_init_request_phys;
1350     struct MPI2_IOC_INIT_REQUEST *ioc_init_request;
1351     struct megasas_cmd *ioc_init_cmd;
1352     bool pcie_bw_limitation;
1353     bool r56_div_offload;
1354 };
1355 
1356 union desc_value {
1357     __le64 word;
1358     struct {
1359         __le32 low;
1360         __le32 high;
1361     } u;
1362 };
1363 
1364 enum CMD_RET_VALUES {
1365     REFIRE_CMD = 1,
1366     COMPLETE_CMD = 2,
1367     RETURN_CMD = 3,
1368 };
1369 
1370 struct  MR_SNAPDUMP_PROPERTIES {
1371     u8       offload_num;
1372     u8       max_num_supported;
1373     u8       cur_num_supported;
1374     u8       trigger_min_num_sec_before_ocr;
1375     u8       reserved[12];
1376 };
1377 
1378 struct megasas_debugfs_buffer {
1379     void *buf;
1380     u32 len;
1381 };
1382 
1383 void megasas_free_cmds_fusion(struct megasas_instance *instance);
1384 int megasas_ioc_init_fusion(struct megasas_instance *instance);
1385 u8 megasas_get_map_info(struct megasas_instance *instance);
1386 int megasas_sync_map_info(struct megasas_instance *instance);
1387 void megasas_release_fusion(struct megasas_instance *instance);
1388 void megasas_reset_reply_desc(struct megasas_instance *instance);
1389 int megasas_check_mpio_paths(struct megasas_instance *instance,
1390                   struct scsi_cmnd *scmd);
1391 void megasas_fusion_ocr_wq(struct work_struct *work);
1392 
1393 #endif /* _MEGARAID_SAS_FUSION_H_ */
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