scsi/megaraid/megaraid_mbox.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *
0004  *          Linux MegaRAID device driver
0005  *
0006  * Copyright (c) 2003-2004  LSI Logic Corporation.
0007  *
0008  * FILE     : megaraid_mbox.h
0009  */
0010
0011 #ifndef _MEGARAID_H_
0012 #define _MEGARAID_H_
0013
0014
0015 #include "mega_common.h"
0016 #include "mbox_defs.h"
0017 #include "megaraid_ioctl.h"
0018
0019
0020 #define MEGARAID_VERSION    "2.20.5.1"
0021 #define MEGARAID_EXT_VERSION    "(Release Date: Thu Nov 16 15:32:35 EST 2006)"
0022
0023
0024 /*
0025  * Define some PCI values here until they are put in the kernel
0026  */
0027 #define PCI_DEVICE_ID_PERC4_DI_DISCOVERY        0x000E
0028 #define PCI_SUBSYS_ID_PERC4_DI_DISCOVERY        0x0123
0029
0030 #define PCI_DEVICE_ID_PERC4_SC              0x1960
0031 #define PCI_SUBSYS_ID_PERC4_SC              0x0520
0032
0033 #define PCI_DEVICE_ID_PERC4_DC              0x1960
0034 #define PCI_SUBSYS_ID_PERC4_DC              0x0518
0035
0036 #define PCI_DEVICE_ID_VERDE             0x0407
0037
0038 #define PCI_DEVICE_ID_PERC4_DI_EVERGLADES       0x000F
0039 #define PCI_SUBSYS_ID_PERC4_DI_EVERGLADES       0x014A
0040
0041 #define PCI_DEVICE_ID_PERC4E_SI_BIGBEND         0x0013
0042 #define PCI_SUBSYS_ID_PERC4E_SI_BIGBEND         0x016c
0043
0044 #define PCI_DEVICE_ID_PERC4E_DI_KOBUK           0x0013
0045 #define PCI_SUBSYS_ID_PERC4E_DI_KOBUK           0x016d
0046
0047 #define PCI_DEVICE_ID_PERC4E_DI_CORVETTE        0x0013
0048 #define PCI_SUBSYS_ID_PERC4E_DI_CORVETTE        0x016e
0049
0050 #define PCI_DEVICE_ID_PERC4E_DI_EXPEDITION      0x0013
0051 #define PCI_SUBSYS_ID_PERC4E_DI_EXPEDITION      0x016f
0052
0053 #define PCI_DEVICE_ID_PERC4E_DI_GUADALUPE       0x0013
0054 #define PCI_SUBSYS_ID_PERC4E_DI_GUADALUPE       0x0170
0055
0056 #define PCI_DEVICE_ID_DOBSON                0x0408
0057
0058 #define PCI_DEVICE_ID_MEGARAID_SCSI_320_0       0x1960
0059 #define PCI_SUBSYS_ID_MEGARAID_SCSI_320_0       0xA520
0060
0061 #define PCI_DEVICE_ID_MEGARAID_SCSI_320_1       0x1960
0062 #define PCI_SUBSYS_ID_MEGARAID_SCSI_320_1       0x0520
0063
0064 #define PCI_DEVICE_ID_MEGARAID_SCSI_320_2       0x1960
0065 #define PCI_SUBSYS_ID_MEGARAID_SCSI_320_2       0x0518
0066
0067 #define PCI_DEVICE_ID_MEGARAID_I4_133_RAID      0x1960
0068 #define PCI_SUBSYS_ID_MEGARAID_I4_133_RAID      0x0522
0069
0070 #define PCI_DEVICE_ID_MEGARAID_SATA_150_4       0x1960
0071 #define PCI_SUBSYS_ID_MEGARAID_SATA_150_4       0x4523
0072
0073 #define PCI_DEVICE_ID_MEGARAID_SATA_150_6       0x1960
0074 #define PCI_SUBSYS_ID_MEGARAID_SATA_150_6       0x0523
0075
0076 #define PCI_DEVICE_ID_LINDSAY               0x0409
0077
0078 #define PCI_DEVICE_ID_INTEL_RAID_SRCS16         0x1960
0079 #define PCI_SUBSYS_ID_INTEL_RAID_SRCS16         0x0523
0080
0081 #define PCI_DEVICE_ID_INTEL_RAID_SRCU41L_LAKE_SHETEK    0x1960
0082 #define PCI_SUBSYS_ID_INTEL_RAID_SRCU41L_LAKE_SHETEK    0x0520
0083
0084 #define PCI_SUBSYS_ID_PERC3_QC              0x0471
0085 #define PCI_SUBSYS_ID_PERC3_DC              0x0493
0086 #define PCI_SUBSYS_ID_PERC3_SC              0x0475
0087 #define PCI_SUBSYS_ID_CERC_ATA100_4CH           0x0511
0088
0089
0090 #define MBOX_MAX_SCSI_CMDS  128 // number of cmds reserved for kernel
0091 #define MBOX_MAX_USER_CMDS  32  // number of cmds for applications
0092 #define MBOX_DEF_CMD_PER_LUN    64  // default commands per lun
0093 #define MBOX_DEFAULT_SG_SIZE    26  // default sg size supported by all fw
0094 #define MBOX_MAX_SG_SIZE    32  // maximum scatter-gather list size
0095 #define MBOX_MAX_SECTORS    128 // maximum sectors per IO
0096 #define MBOX_TIMEOUT        30  // timeout value for internal cmds
0097 #define MBOX_BUSY_WAIT      10  // max usec to wait for busy mailbox
0098 #define MBOX_RESET_WAIT     180 // wait these many seconds in reset
0099 #define MBOX_RESET_EXT_WAIT 120 // extended wait reset
0100 #define MBOX_SYNC_WAIT_CNT  0xFFFF  // wait loop index for synchronous mode
0101
0102 #define MBOX_SYNC_DELAY_200 200 // 200 micro-seconds
0103
0104 /*
0105  * maximum transfer that can happen through the firmware commands issued
0106  * internnaly from the driver.
0107  */
0108 #define MBOX_IBUF_SIZE      4096
0109
0110
0111 /**
0112  * mbox_ccb_t - command control block specific to mailbox based controllers
0113  * @raw_mbox        : raw mailbox pointer
0114  * @mbox        : mailbox
0115  * @mbox64      : extended mailbox
0116  * @mbox_dma_h      : mailbox dma address
0117  * @sgl64       : 64-bit scatter-gather list
0118  * @sgl32       : 32-bit scatter-gather list
0119  * @sgl_dma_h       : dma handle for the scatter-gather list
0120  * @pthru       : passthru structure
0121  * @pthru_dma_h     : dma handle for the passthru structure
0122  * @epthru      : extended passthru structure
0123  * @epthru_dma_h    : dma handle for extended passthru structure
0124  * @buf_dma_h       : dma handle for buffers w/o sg list
0125  *
0126  * command control block specific to the mailbox based controllers
0127  */
0128 typedef struct {
0129     uint8_t         *raw_mbox;
0130     mbox_t          *mbox;
0131     mbox64_t        *mbox64;
0132     dma_addr_t      mbox_dma_h;
0133     mbox_sgl64      *sgl64;
0134     mbox_sgl32      *sgl32;
0135     dma_addr_t      sgl_dma_h;
0136     mraid_passthru_t    *pthru;
0137     dma_addr_t      pthru_dma_h;
0138     mraid_epassthru_t   *epthru;
0139     dma_addr_t      epthru_dma_h;
0140     dma_addr_t      buf_dma_h;
0141 } mbox_ccb_t;
0142
0143
0144 /**
0145  * mraid_device_t - adapter soft state structure for mailbox controllers
0146  * @una_mbox64          : 64-bit mbox - unaligned
0147  * @una_mbox64_dma      : mbox dma addr - unaligned
0148  * @mbox            : 32-bit mbox - aligned
0149  * @mbox64          : 64-bit mbox - aligned
0150  * @mbox_dma            : mbox dma addr - aligned
0151  * @mailbox_lock        : exclusion lock for the mailbox
0152  * @baseport            : base port of hba memory
0153  * @baseaddr            : mapped addr of hba memory
0154  * @mbox_pool           : pool of mailboxes
0155  * @mbox_pool_handle        : handle for the mailbox pool memory
0156  * @epthru_pool         : a pool for extended passthru commands
0157  * @epthru_pool_handle      : handle to the pool above
0158  * @sg_pool         : pool of scatter-gather lists for this driver
0159  * @sg_pool_handle      : handle to the pool above
0160  * @ccb_list            : list of our command control blocks
0161  * @uccb_list           : list of cmd control blocks for mgmt module
0162  * @umbox64         : array of mailbox for user commands (cmm)
0163  * @pdrv_state          : array for state of each physical drive.
0164  * @last_disp           : flag used to show device scanning
0165  * @hw_error            : set if FW not responding
0166  * @fast_load           : If set, skip physical device scanning
0167  * @channel_class       : channel class, RAID or SCSI
0168  * @sysfs_mtx           : mutex to serialize access to sysfs res.
0169  * @sysfs_uioc          : management packet to issue FW calls from sysfs
0170  * @sysfs_mbox64        : mailbox packet to issue FW calls from sysfs
0171  * @sysfs_buffer        : data buffer for FW commands issued from sysfs
0172  * @sysfs_buffer_dma        : DMA buffer for FW commands issued from sysfs
0173  * @sysfs_wait_q        : wait queue for sysfs operations
0174  * @random_del_supported    : set if the random deletion is supported
0175  * @curr_ldmap          : current LDID map
0176  *
0177  * Initialization structure for mailbox controllers: memory based and IO based
0178  * All the fields in this structure are LLD specific and may be discovered at
0179  * init() or start() time.
0180  *
0181  * NOTE: The fields of this structures are placed to minimize cache misses
0182  */
0183 #define MAX_LD_EXTENDED64   64
0184 typedef struct {
0185     mbox64_t            *una_mbox64;
0186     dma_addr_t          una_mbox64_dma;
0187     mbox_t              *mbox;
0188     mbox64_t            *mbox64;
0189     dma_addr_t          mbox_dma;
0190     spinlock_t          mailbox_lock;
0191     unsigned long           baseport;
0192     void __iomem *          baseaddr;
0193     struct mraid_pci_blk        mbox_pool[MBOX_MAX_SCSI_CMDS];
0194     struct dma_pool         *mbox_pool_handle;
0195     struct mraid_pci_blk        epthru_pool[MBOX_MAX_SCSI_CMDS];
0196     struct dma_pool         *epthru_pool_handle;
0197     struct mraid_pci_blk        sg_pool[MBOX_MAX_SCSI_CMDS];
0198     struct dma_pool         *sg_pool_handle;
0199     mbox_ccb_t          ccb_list[MBOX_MAX_SCSI_CMDS];
0200     mbox_ccb_t          uccb_list[MBOX_MAX_USER_CMDS];
0201     mbox64_t            umbox64[MBOX_MAX_USER_CMDS];
0202
0203     uint8_t             pdrv_state[MBOX_MAX_PHYSICAL_DRIVES];
0204     uint32_t            last_disp;
0205     int             hw_error;
0206     int             fast_load;
0207     uint8_t             channel_class;
0208     struct mutex            sysfs_mtx;
0209     uioc_t              *sysfs_uioc;
0210     mbox64_t            *sysfs_mbox64;
0211     caddr_t             sysfs_buffer;
0212     dma_addr_t          sysfs_buffer_dma;
0213     wait_queue_head_t       sysfs_wait_q;
0214     int             random_del_supported;
0215     uint16_t            curr_ldmap[MAX_LD_EXTENDED64];
0216 } mraid_device_t;
0217
0218 // route to raid device from adapter
0219 #define ADAP2RAIDDEV(adp)   ((mraid_device_t *)((adp)->raid_device))
0220
0221 #define MAILBOX_LOCK(rdev)  (&(rdev)->mailbox_lock)
0222
0223 // Find out if this channel is a RAID or SCSI
0224 #define IS_RAID_CH(rdev, ch)    (((rdev)->channel_class >> (ch)) & 0x01)
0225
0226
0227 #define RDINDOOR(rdev)      readl((rdev)->baseaddr + 0x20)
0228 #define RDOUTDOOR(rdev)     readl((rdev)->baseaddr + 0x2C)
0229 #define WRINDOOR(rdev, value)   writel(value, (rdev)->baseaddr + 0x20)
0230 #define WROUTDOOR(rdev, value)  writel(value, (rdev)->baseaddr + 0x2C)
0231
0232 #endif // _MEGARAID_H_