drivers/scsi/mac53c94.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * mac53c94.h: definitions for the driver for the 53c94 SCSI bus adaptor
0004  * found on Power Macintosh computers, controlling the external SCSI chain.
0005  *
0006  * Copyright (C) 1996 Paul Mackerras.
0007  */
0008 #ifndef _MAC53C94_H
0009 #define _MAC53C94_H
0010
0011 /*
0012  * Registers in the 53C94 controller.
0013  */
0014
0015 struct mac53c94_regs {
0016     unsigned char   count_lo;
0017     char pad0[15];
0018     unsigned char   count_mid;
0019     char pad1[15];
0020     unsigned char   fifo;
0021     char pad2[15];
0022     unsigned char   command;
0023     char pad3[15];
0024     unsigned char   status;
0025     char pad4[15];
0026     unsigned char   interrupt;
0027     char pad5[15];
0028     unsigned char   seqstep;
0029     char pad6[15];
0030     unsigned char   flags;
0031     char pad7[15];
0032     unsigned char   config1;
0033     char pad8[15];
0034     unsigned char   clk_factor;
0035     char pad9[15];
0036     unsigned char   test;
0037     char pad10[15];
0038     unsigned char   config2;
0039     char pad11[15];
0040     unsigned char   config3;
0041     char pad12[15];
0042     unsigned char   config4;
0043     char pad13[15];
0044     unsigned char   count_hi;
0045     char pad14[15];
0046     unsigned char   fifo_res;
0047     char pad15[15];
0048 };
0049
0050 /*
0051  * Alternate functions for some registers.
0052  */
0053 #define dest_id     status
0054 #define sel_timeout interrupt
0055 #define sync_period seqstep
0056 #define sync_offset flags
0057
0058 /*
0059  * Bits in command register.
0060  */
0061 #define CMD_DMA_MODE    0x80
0062 #define CMD_MODE_MASK   0x70
0063 #define CMD_MODE_INIT   0x10
0064 #define CMD_MODE_TARG   0x20
0065 #define CMD_MODE_DISC   0x40
0066
0067 #define CMD_NOP     0
0068 #define CMD_FLUSH   1
0069 #define CMD_RESET   2
0070 #define CMD_SCSI_RESET  3
0071
0072 #define CMD_XFER_DATA   0x10
0073 #define CMD_I_COMPLETE  0x11
0074 #define CMD_ACCEPT_MSG  0x12
0075 #define CMD_XFER_PAD    0x18
0076 #define CMD_SET_ATN 0x1a
0077 #define CMD_CLR_ATN 0x1b
0078
0079 #define CMD_SEND_MSG    0x20
0080 #define CMD_SEND_STATUS 0x21
0081 #define CMD_SEND_DATA   0x22
0082 #define CMD_DISC_SEQ    0x23
0083 #define CMD_TERMINATE   0x24
0084 #define CMD_T_COMPLETE  0x25
0085 #define CMD_DISCONNECT  0x27
0086 #define CMD_RECV_MSG    0x28
0087 #define CMD_RECV_CDB    0x29
0088 #define CMD_RECV_DATA   0x2a
0089 #define CMD_RECV_CMD    0x2b
0090 #define CMD_ABORT_DMA   0x04
0091
0092 #define CMD_RESELECT    0x40
0093 #define CMD_SELECT  0x41
0094 #define CMD_SELECT_ATN  0x42
0095 #define CMD_SELATN_STOP 0x43
0096 #define CMD_ENABLE_SEL  0x44
0097 #define CMD_DISABLE_SEL 0x45
0098 #define CMD_SEL_ATN3    0x46
0099 #define CMD_RESEL_ATN3  0x47
0100
0101 /*
0102  * Bits in status register.
0103  */
0104 #define STAT_IRQ    0x80
0105 #define STAT_ERROR  0x40
0106 #define STAT_PARITY 0x20
0107 #define STAT_TC_ZERO    0x10
0108 #define STAT_DONE   0x08
0109 #define STAT_PHASE  0x07
0110 #define STAT_MSG    0x04
0111 #define STAT_CD     0x02
0112 #define STAT_IO     0x01
0113
0114 /*
0115  * Bits in interrupt register.
0116  */
0117 #define INTR_RESET  0x80    /* SCSI bus was reset */
0118 #define INTR_ILL_CMD    0x40    /* illegal command */
0119 #define INTR_DISCONNECT 0x20    /* we got disconnected */
0120 #define INTR_BUS_SERV   0x10    /* bus service requested */
0121 #define INTR_DONE   0x08    /* function completed */
0122 #define INTR_RESELECTED 0x04    /* we were reselected */
0123 #define INTR_SEL_ATN    0x02    /* we were selected, ATN asserted */
0124 #define INTR_SELECT 0x01    /* we were selected, ATN negated */
0125
0126 /*
0127  * Encoding for the select timeout.
0128  */
0129 #define TIMO_VAL(x) ((x) * 5000 / 7682)
0130
0131 /*
0132  * Bits in sequence step register.
0133  */
0134 #define SS_MASK     7
0135 #define SS_ARB_SEL  0   /* Selection & arbitration complete */
0136 #define SS_MSG_SENT 1   /* One message byte sent */
0137 #define SS_NOT_CMD  2   /* Not in command phase */
0138 #define SS_PHASE_CHG    3   /* Early phase change, cmd bytes lost */
0139 #define SS_DONE     4   /* Command was sent OK */
0140
0141 /*
0142  * Encoding for sync transfer period.
0143  */
0144 #define SYNCP_MASK  0x1f
0145 #define SYNCP_MIN   4
0146 #define SYNCP_MAX   31
0147
0148 /*
0149  * Bits in flags register.
0150  */
0151 #define FLAGS_FIFO_LEV  0x1f
0152 #define FLAGS_SEQ_STEP  0xe0
0153
0154 /*
0155  * Encoding for sync offset.
0156  */
0157 #define SYNCO_MASK  0x0f
0158 #define SYNCO_ASS_CTRL  0x30    /* REQ/ACK assertion control */
0159 #define SYNCO_NEG_CTRL  0xc0    /* REQ/ACK negation control */
0160
0161 /*
0162  * Bits in config1 register.
0163  */
0164 #define CF1_SLOW_CABLE  0x80    /* Slow cable mode */
0165 #define CF1_NO_RES_REP  0x40    /* Disable SCSI reset reports */
0166 #define CF1_PAR_TEST    0x20    /* Parity test mode enable */
0167 #define CF1_PAR_ENABLE  0x10    /* Enable parity checks */
0168 #define CF1_TEST    0x08    /* Chip tests */
0169 #define CF1_MY_ID   0x07    /* Controller's address on bus */
0170
0171 /*
0172  * Encoding for clk_factor register.
0173  */
0174 #define CLKF_MASK   7
0175 #define CLKF_VAL(freq)  ((((freq) + 4999999) / 5000000) & CLKF_MASK)
0176
0177 /*
0178  * Bits in test mode register.
0179  */
0180 #define TEST_TARGET 1   /* target test mode */
0181 #define TEST_INITIATOR  2   /* initiator test mode */
0182 #define TEST_TRISTATE   4   /* tristate (hi-z) test mode */
0183
0184 /*
0185  * Bits in config2 register.
0186  */
0187 #define CF2_RFB     0x80
0188 #define CF2_FEATURE_EN  0x40    /* enable features / phase latch */
0189 #define CF2_BYTECTRL    0x20
0190 #define CF2_DREQ_HIZ    0x10
0191 #define CF2_SCSI2   0x08
0192 #define CF2_PAR_ABORT   0x04    /* bad parity target abort */
0193 #define CF2_REG_PARERR  0x02    /* register parity error */
0194 #define CF2_DMA_PARERR  0x01    /* DMA parity error */
0195
0196 /*
0197  * Bits in the config3 register.
0198  */
0199 #define CF3_ID_MSG_CHK  0x80
0200 #define CF3_3B_MSGS 0x40
0201 #define CF3_CDB10   0x20
0202 #define CF3_FASTSCSI    0x10    /* enable fast SCSI support */
0203 #define CF3_FASTCLOCK   0x08
0204 #define CF3_SAVERESID   0x04
0205 #define CF3_ALT_DMA 0x02
0206 #define CF3_THRESH_8    0x01
0207
0208 /*
0209  * Bits in the config4 register.
0210  */
0211 #define CF4_EAN     0x04
0212 #define CF4_TEST    0x02
0213 #define CF4_BBTE    0x01
0214
0215 struct mac53c94_cmd_priv {
0216     int this_residual;
0217     int status;
0218     int message;
0219 };
0220
0221 static inline struct mac53c94_cmd_priv *mac53c94_priv(struct scsi_cmnd *cmd)
0222 {
0223     return scsi_cmd_priv(cmd);
0224 }
0225
0226 #endif /* _MAC53C94_H */