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0001 /*******************************************************************
0002  * This file is part of the Emulex Linux Device Driver for         *
0003  * Fibre Channel Host Bus Adapters.                                *
0004  * Copyright (C) 2017-2022 Broadcom. All Rights Reserved. The term *
0005  * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.     *
0006  * Copyright (C) 2004-2016 Emulex.  All rights reserved.           *
0007  * EMULEX and SLI are trademarks of Emulex.                        *
0008  * www.broadcom.com                                                *
0009  *                                                                 *
0010  * This program is free software; you can redistribute it and/or   *
0011  * modify it under the terms of version 2 of the GNU General       *
0012  * Public License as published by the Free Software Foundation.    *
0013  * This program is distributed in the hope that it will be useful. *
0014  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
0015  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
0016  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
0017  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
0018  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
0019  * more details, a copy of which can be found in the file COPYING  *
0020  * included with this package.                                     *
0021  *******************************************************************/
0022 
0023 #define FDMI_DID        0xfffffaU
0024 #define NameServer_DID  0xfffffcU
0025 #define Fabric_Cntl_DID 0xfffffdU
0026 #define Fabric_DID      0xfffffeU
0027 #define Bcast_DID       0xffffffU
0028 #define Mask_DID        0xffffffU
0029 #define CT_DID_MASK     0xffff00U
0030 #define Fabric_DID_MASK 0xfff000U
0031 #define WELL_KNOWN_DID_MASK 0xfffff0U
0032 
0033 #define PT2PT_LocalID   1
0034 #define PT2PT_RemoteID  2
0035 
0036 #define FF_DEF_EDTOV          2000  /* Default E_D_TOV (2000ms) */
0037 #define FF_DEF_ALTOV            15  /* Default AL_TIME (15ms) */
0038 #define FF_DEF_RATOV            10  /* Default RA_TOV (10s) */
0039 #define FF_DEF_ARBTOV         1900  /* Default ARB_TOV (1900ms) */
0040 
0041 #define LPFC_BUF_RING0        64    /* Number of buffers to post to RING
0042                        0 */
0043 
0044 #define FCELSSIZE             1024  /* maximum ELS transfer size */
0045 
0046 #define LPFC_FCP_RING            0  /* ring 0 for FCP initiator commands */
0047 #define LPFC_EXTRA_RING          1  /* ring 1 for other protocols */
0048 #define LPFC_ELS_RING            2  /* ring 2 for ELS commands */
0049 
0050 #define SLI2_IOCB_CMD_R0_ENTRIES    172 /* SLI-2 FCP command ring entries */
0051 #define SLI2_IOCB_RSP_R0_ENTRIES    134 /* SLI-2 FCP response ring entries */
0052 #define SLI2_IOCB_CMD_R1_ENTRIES      4 /* SLI-2 extra command ring entries */
0053 #define SLI2_IOCB_RSP_R1_ENTRIES      4 /* SLI-2 extra response ring entries */
0054 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
0055 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
0056 #define SLI2_IOCB_CMD_R2_ENTRIES     20 /* SLI-2 ELS command ring entries */
0057 #define SLI2_IOCB_RSP_R2_ENTRIES     20 /* SLI-2 ELS response ring entries */
0058 #define SLI2_IOCB_CMD_R3_ENTRIES      0
0059 #define SLI2_IOCB_RSP_R3_ENTRIES      0
0060 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
0061 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
0062 
0063 #define SLI2_IOCB_CMD_SIZE  32
0064 #define SLI2_IOCB_RSP_SIZE  32
0065 #define SLI3_IOCB_CMD_SIZE  128
0066 #define SLI3_IOCB_RSP_SIZE  64
0067 
0068 #define LPFC_UNREG_ALL_RPIS_VPORT   0xffff
0069 #define LPFC_UNREG_ALL_DFLT_RPIS    0xffffffff
0070 
0071 /* vendor ID used in SCSI netlink calls */
0072 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
0073 
0074 #define FW_REV_STR_SIZE 32
0075 /* Common Transport structures and definitions */
0076 
0077 union CtRevisionId {
0078     /* Structure is in Big Endian format */
0079     struct {
0080         uint32_t Revision:8;
0081         uint32_t InId:24;
0082     } bits;
0083     uint32_t word;
0084 };
0085 
0086 union CtCommandResponse {
0087     /* Structure is in Big Endian format */
0088     struct {
0089         uint32_t CmdRsp:16;
0090         uint32_t Size:16;
0091     } bits;
0092     uint32_t word;
0093 };
0094 
0095 /* FC4 Feature bits for RFF_ID */
0096 #define FC4_FEATURE_TARGET  0x1
0097 #define FC4_FEATURE_INIT    0x2
0098 #define FC4_FEATURE_NVME_DISC   0x4
0099 
0100 enum rft_word0 {
0101     RFT_FCP_REG = (0x1 << 8),
0102 };
0103 
0104 enum rft_word1 {
0105     RFT_NVME_REG    = (0x1 << 8),
0106 };
0107 
0108 enum rft_word3 {
0109     RFT_APP_SERV_REG    = (0x1 << 0),
0110 };
0111 
0112 struct lpfc_sli_ct_request {
0113     /* Structure is in Big Endian format */
0114     union CtRevisionId RevisionId;
0115     uint8_t FsType;
0116     uint8_t FsSubType;
0117     uint8_t Options;
0118     uint8_t Rsrvd1;
0119     union CtCommandResponse CommandResponse;
0120     uint8_t Rsrvd2;
0121     uint8_t ReasonCode;
0122     uint8_t Explanation;
0123     uint8_t VendorUnique;
0124 #define LPFC_CT_PREAMBLE    20  /* Size of CTReq + 4 up to here */
0125 
0126     union {
0127         uint32_t PortID;
0128         struct gid {
0129             uint8_t PortType;   /* for GID_PT requests */
0130 #define GID_PT_N_PORT   1
0131             uint8_t DomainScope;
0132             uint8_t AreaScope;
0133             uint8_t Fc4Type;    /* for GID_FT requests */
0134         } gid;
0135         struct gid_ff {
0136             uint8_t Flags;
0137             uint8_t DomainScope;
0138             uint8_t AreaScope;
0139             uint8_t rsvd1;
0140             uint8_t rsvd2;
0141             uint8_t rsvd3;
0142             uint8_t Fc4FBits;
0143             uint8_t Fc4Type;
0144         } gid_ff;
0145         struct rft {
0146             __be32 port_id; /* For RFT_ID requests */
0147 
0148             __be32 fcp_reg; /* rsvd 31:9, fcp_reg 8, rsvd 7:0 */
0149             __be32 nvme_reg; /* rsvd 31:9, nvme_reg 8, rsvd 7:0 */
0150             __be32 word2;
0151             __be32 app_serv_reg; /* rsvd 31:1, app_serv_reg 0 */
0152             __be32 word[4];
0153         } rft;
0154         struct rnn {
0155             uint32_t PortId;    /* For RNN_ID requests */
0156             uint8_t wwnn[8];
0157         } rnn;
0158         struct rsnn {   /* For RSNN_ID requests */
0159             uint8_t wwnn[8];
0160             uint8_t len;
0161             uint8_t symbname[255];
0162         } rsnn;
0163         struct da_id { /* For DA_ID requests */
0164             uint32_t port_id;
0165         } da_id;
0166         struct rspn {   /* For RSPN_ID requests */
0167             uint32_t PortId;
0168             uint8_t len;
0169             uint8_t symbname[255];
0170         } rspn;
0171         struct gff {
0172             uint32_t PortId;
0173         } gff;
0174         struct gff_acc {
0175             uint8_t fbits[128];
0176         } gff_acc;
0177         struct gft {
0178             uint32_t PortId;
0179         } gft;
0180         struct gft_acc {
0181             uint32_t fc4_types[8];
0182         } gft_acc;
0183 #define FCP_TYPE_FEATURE_OFFSET 7
0184         struct rff {
0185             uint32_t PortId;
0186             uint8_t reserved[2];
0187             uint8_t fbits;
0188             uint8_t type_code;     /* type=8 for FCP */
0189         } rff;
0190     } un;
0191 };
0192 
0193 #define LPFC_MAX_CT_SIZE    (60 * 4096)
0194 
0195 #define  SLI_CT_REVISION        1
0196 #define  GID_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
0197                sizeof(struct gid))
0198 #define  GIDFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
0199                sizeof(struct gid_ff))
0200 #define  GFF_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
0201                sizeof(struct gff))
0202 #define  GFT_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
0203                sizeof(struct gft))
0204 #define  RFT_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
0205                sizeof(struct rft))
0206 #define  RFF_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
0207                sizeof(struct rff))
0208 #define  RNN_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
0209                sizeof(struct rnn))
0210 #define  RSNN_REQUEST_SZ  (offsetof(struct lpfc_sli_ct_request, un) + \
0211                sizeof(struct rsnn))
0212 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
0213               sizeof(struct da_id))
0214 #define  RSPN_REQUEST_SZ  (offsetof(struct lpfc_sli_ct_request, un) + \
0215                sizeof(struct rspn))
0216 
0217 /*
0218  * FsType Definitions
0219  */
0220 
0221 #define  SLI_CT_MANAGEMENT_SERVICE        0xFA
0222 #define  SLI_CT_TIME_SERVICE              0xFB
0223 #define  SLI_CT_DIRECTORY_SERVICE         0xFC
0224 #define  SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
0225 
0226 /*
0227  * Directory Service Subtypes
0228  */
0229 
0230 #define  SLI_CT_DIRECTORY_NAME_SERVER     0x02
0231 
0232 /*
0233  * Response Codes
0234  */
0235 
0236 #define  SLI_CT_RESPONSE_FS_RJT           0x8001
0237 #define  SLI_CT_RESPONSE_FS_ACC           0x8002
0238 
0239 /*
0240  * Reason Codes
0241  */
0242 
0243 #define  SLI_CT_NO_ADDITIONAL_EXPL    0x0
0244 #define  SLI_CT_INVALID_COMMAND           0x01
0245 #define  SLI_CT_INVALID_VERSION           0x02
0246 #define  SLI_CT_LOGICAL_ERROR             0x03
0247 #define  SLI_CT_INVALID_IU_SIZE           0x04
0248 #define  SLI_CT_LOGICAL_BUSY              0x05
0249 #define  SLI_CT_PROTOCOL_ERROR            0x07
0250 #define  SLI_CT_UNABLE_TO_PERFORM_REQ     0x09
0251 #define  SLI_CT_REQ_NOT_SUPPORTED         0x0b
0252 #define  SLI_CT_HBA_INFO_NOT_REGISTERED   0x10
0253 #define  SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE  0x11
0254 #define  SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN      0x12
0255 #define  SLI_CT_HBA_ATTR_NOT_PRESENT      0x13
0256 #define  SLI_CT_PORT_INFO_NOT_REGISTERED  0x20
0257 #define  SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
0258 #define  SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN     0x22
0259 #define  SLI_CT_VENDOR_UNIQUE             0xff
0260 
0261 /*
0262  * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
0263  */
0264 
0265 #define  SLI_CT_NO_PORT_ID                0x01
0266 #define  SLI_CT_NO_PORT_NAME              0x02
0267 #define  SLI_CT_NO_NODE_NAME              0x03
0268 #define  SLI_CT_NO_CLASS_OF_SERVICE       0x04
0269 #define  SLI_CT_NO_IP_ADDRESS             0x05
0270 #define  SLI_CT_NO_IPA                    0x06
0271 #define  SLI_CT_NO_FC4_TYPES              0x07
0272 #define  SLI_CT_NO_SYMBOLIC_PORT_NAME     0x08
0273 #define  SLI_CT_NO_SYMBOLIC_NODE_NAME     0x09
0274 #define  SLI_CT_NO_PORT_TYPE              0x0A
0275 #define  SLI_CT_ACCESS_DENIED             0x10
0276 #define  SLI_CT_INVALID_PORT_ID           0x11
0277 #define  SLI_CT_DATABASE_EMPTY            0x12
0278 #define  SLI_CT_APP_ID_NOT_AVAILABLE      0x40
0279 
0280 /*
0281  * Name Server Command Codes
0282  */
0283 
0284 #define  SLI_CTNS_GA_NXT      0x0100
0285 #define  SLI_CTNS_GPN_ID      0x0112
0286 #define  SLI_CTNS_GNN_ID      0x0113
0287 #define  SLI_CTNS_GCS_ID      0x0114
0288 #define  SLI_CTNS_GFT_ID      0x0117
0289 #define  SLI_CTNS_GSPN_ID     0x0118
0290 #define  SLI_CTNS_GPT_ID      0x011A
0291 #define  SLI_CTNS_GFF_ID      0x011F
0292 #define  SLI_CTNS_GID_PN      0x0121
0293 #define  SLI_CTNS_GID_NN      0x0131
0294 #define  SLI_CTNS_GIP_NN      0x0135
0295 #define  SLI_CTNS_GIPA_NN     0x0136
0296 #define  SLI_CTNS_GSNN_NN     0x0139
0297 #define  SLI_CTNS_GNN_IP      0x0153
0298 #define  SLI_CTNS_GIPA_IP     0x0156
0299 #define  SLI_CTNS_GID_FT      0x0171
0300 #define  SLI_CTNS_GID_FF      0x01F1
0301 #define  SLI_CTNS_GID_PT      0x01A1
0302 #define  SLI_CTNS_RPN_ID      0x0212
0303 #define  SLI_CTNS_RNN_ID      0x0213
0304 #define  SLI_CTNS_RCS_ID      0x0214
0305 #define  SLI_CTNS_RFT_ID      0x0217
0306 #define  SLI_CTNS_RSPN_ID     0x0218
0307 #define  SLI_CTNS_RPT_ID      0x021A
0308 #define  SLI_CTNS_RFF_ID      0x021F
0309 #define  SLI_CTNS_RIP_NN      0x0235
0310 #define  SLI_CTNS_RIPA_NN     0x0236
0311 #define  SLI_CTNS_RSNN_NN     0x0239
0312 #define  SLI_CTNS_DA_ID       0x0300
0313 
0314 /*
0315  * Port Types
0316  */
0317 
0318 #define SLI_CTPT_N_PORT     0x01
0319 #define SLI_CTPT_NL_PORT    0x02
0320 #define SLI_CTPT_FNL_PORT   0x03
0321 #define SLI_CTPT_IP     0x04
0322 #define SLI_CTPT_FCP        0x08
0323 #define SLI_CTPT_NVME       0x28
0324 #define SLI_CTPT_NX_PORT    0x7F
0325 #define SLI_CTPT_F_PORT     0x81
0326 #define SLI_CTPT_FL_PORT    0x82
0327 #define SLI_CTPT_E_PORT     0x84
0328 
0329 #define SLI_CT_LAST_ENTRY     0x80000000
0330 
0331 /* Fibre Channel Service Parameter definitions */
0332 
0333 #define FC_PH_4_0   6       /* FC-PH version 4.0 */
0334 #define FC_PH_4_1   7       /* FC-PH version 4.1 */
0335 #define FC_PH_4_2   8       /* FC-PH version 4.2 */
0336 #define FC_PH_4_3   9       /* FC-PH version 4.3 */
0337 
0338 #define FC_PH_LOW   8       /* Lowest supported FC-PH version */
0339 #define FC_PH_HIGH  9       /* Highest supported FC-PH version */
0340 #define FC_PH3   0x20       /* FC-PH-3 version */
0341 
0342 #define FF_FRAME_SIZE     2048
0343 
0344 struct lpfc_name {
0345     union {
0346         struct {
0347 #ifdef __BIG_ENDIAN_BITFIELD
0348             uint8_t nameType:4; /* FC Word 0, bit 28:31 */
0349             uint8_t IEEEextMsn:4;   /* FC Word 0, bit 24:27, bit
0350                            8:11 of IEEE ext */
0351 #else   /*  __LITTLE_ENDIAN_BITFIELD */
0352             uint8_t IEEEextMsn:4;   /* FC Word 0, bit 24:27, bit
0353                            8:11 of IEEE ext */
0354             uint8_t nameType:4; /* FC Word 0, bit 28:31 */
0355 #endif
0356 
0357 #define NAME_IEEE           0x1 /* IEEE name - nameType */
0358 #define NAME_IEEE_EXT       0x2 /* IEEE extended name */
0359 #define NAME_FC_TYPE        0x3 /* FC native name type */
0360 #define NAME_IP_TYPE        0x4 /* IP address */
0361 #define NAME_CCITT_TYPE     0xC
0362 #define NAME_CCITT_GR_TYPE  0xE
0363             uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
0364                            extended Lsb */
0365             uint8_t IEEE[6];    /* FC IEEE address */
0366         } s;
0367         uint8_t wwn[8];
0368         uint64_t name;
0369     } u;
0370 };
0371 
0372 struct csp {
0373     uint8_t fcphHigh;   /* FC Word 0, byte 0 */
0374     uint8_t fcphLow;
0375     uint8_t bbCreditMsb;
0376     uint8_t bbCreditLsb;    /* FC Word 0, byte 3 */
0377 
0378 /*
0379  * Word 1 Bit 31 in common service parameter is overloaded.
0380  * Word 1 Bit 31 in FLOGI request is multiple NPort request
0381  * Word 1 Bit 31 in FLOGI response is clean address bit
0382  */
0383 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
0384 /*
0385  * Word 1 Bit 30 in common service parameter is overloaded.
0386  * Word 1 Bit 30 in FLOGI request is Virtual Fabrics
0387  * Word 1 Bit 30 in PLOGI request is random offset
0388  */
0389 #define virtual_fabric_support randomOffset /* Word 1, bit 30 */
0390 /*
0391  * Word 1 Bit 29 in common service parameter is overloaded.
0392  * Word 1 Bit 29 in FLOGI response is multiple NPort assignment
0393  * Word 1 Bit 29 in FLOGI/PLOGI request is Valid Vendor Version Level
0394  */
0395 #define valid_vendor_ver_level response_multiple_NPort /* Word 1, bit 29 */
0396 #ifdef __BIG_ENDIAN_BITFIELD
0397     uint16_t request_multiple_Nport:1;  /* FC Word 1, bit 31 */
0398     uint16_t randomOffset:1;    /* FC Word 1, bit 30 */
0399     uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
0400     uint16_t fPort:1;   /* FC Word 1, bit 28 */
0401     uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
0402     uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
0403     uint16_t multicast:1;   /* FC Word 1, bit 25 */
0404     uint16_t app_hdr_support:1; /* FC Word 1, bit 24 */
0405 
0406     uint16_t priority_tagging:1;    /* FC Word 1, bit 23 */
0407     uint16_t simplex:1; /* FC Word 1, bit 22 */
0408     uint16_t word1Reserved1:3;  /* FC Word 1, bit 21:19 */
0409     uint16_t dhd:1;     /* FC Word 1, bit 18 */
0410     uint16_t contIncSeqCnt:1;   /* FC Word 1, bit 17 */
0411     uint16_t payloadlength:1;   /* FC Word 1, bit 16 */
0412 #else   /*  __LITTLE_ENDIAN_BITFIELD */
0413     uint16_t app_hdr_support:1; /* FC Word 1, bit 24 */
0414     uint16_t multicast:1;   /* FC Word 1, bit 25 */
0415     uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
0416     uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
0417     uint16_t fPort:1;   /* FC Word 1, bit 28 */
0418     uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
0419     uint16_t randomOffset:1;    /* FC Word 1, bit 30 */
0420     uint16_t request_multiple_Nport:1;  /* FC Word 1, bit 31 */
0421 
0422     uint16_t payloadlength:1;   /* FC Word 1, bit 16 */
0423     uint16_t contIncSeqCnt:1;   /* FC Word 1, bit 17 */
0424     uint16_t dhd:1;     /* FC Word 1, bit 18 */
0425     uint16_t word1Reserved1:3;  /* FC Word 1, bit 21:19 */
0426     uint16_t simplex:1; /* FC Word 1, bit 22 */
0427     uint16_t priority_tagging:1;    /* FC Word 1, bit 23 */
0428 #endif
0429 
0430     uint8_t bbRcvSizeMsb;   /* Upper nibble is reserved */
0431     uint8_t bbRcvSizeLsb;   /* FC Word 1, byte 3 */
0432     union {
0433         struct {
0434             uint8_t word2Reserved1; /* FC Word 2 byte 0 */
0435 
0436             uint8_t totalConcurrSeq;    /* FC Word 2 byte 1 */
0437             uint8_t roByCategoryMsb;    /* FC Word 2 byte 2 */
0438 
0439             uint8_t roByCategoryLsb;    /* FC Word 2 byte 3 */
0440         } nPort;
0441         uint32_t r_a_tov;   /* R_A_TOV must be in B.E. format */
0442     } w2;
0443 
0444     uint32_t e_d_tov;   /* E_D_TOV must be in B.E. format */
0445 };
0446 
0447 struct class_parms {
0448 #ifdef __BIG_ENDIAN_BITFIELD
0449     uint8_t classValid:1;   /* FC Word 0, bit 31 */
0450     uint8_t intermix:1; /* FC Word 0, bit 30 */
0451     uint8_t stackedXparent:1;   /* FC Word 0, bit 29 */
0452     uint8_t stackedLockDown:1;  /* FC Word 0, bit 28 */
0453     uint8_t seqDelivery:1;  /* FC Word 0, bit 27 */
0454     uint8_t word0Reserved1:3;   /* FC Word 0, bit 24:26 */
0455 #else   /*  __LITTLE_ENDIAN_BITFIELD */
0456     uint8_t word0Reserved1:3;   /* FC Word 0, bit 24:26 */
0457     uint8_t seqDelivery:1;  /* FC Word 0, bit 27 */
0458     uint8_t stackedLockDown:1;  /* FC Word 0, bit 28 */
0459     uint8_t stackedXparent:1;   /* FC Word 0, bit 29 */
0460     uint8_t intermix:1; /* FC Word 0, bit 30 */
0461     uint8_t classValid:1;   /* FC Word 0, bit 31 */
0462 
0463 #endif
0464 
0465     uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
0466 
0467 #ifdef __BIG_ENDIAN_BITFIELD
0468     uint8_t iCtlXidReAssgn:2;   /* FC Word 0, Bit 14:15 */
0469     uint8_t iCtlInitialPa:2;    /* FC Word 0, bit 12:13 */
0470     uint8_t iCtlAck0capable:1;  /* FC Word 0, bit 11 */
0471     uint8_t iCtlAckNcapable:1;  /* FC Word 0, bit 10 */
0472     uint8_t word0Reserved3:2;   /* FC Word 0, bit  8: 9 */
0473 #else   /*  __LITTLE_ENDIAN_BITFIELD */
0474     uint8_t word0Reserved3:2;   /* FC Word 0, bit  8: 9 */
0475     uint8_t iCtlAckNcapable:1;  /* FC Word 0, bit 10 */
0476     uint8_t iCtlAck0capable:1;  /* FC Word 0, bit 11 */
0477     uint8_t iCtlInitialPa:2;    /* FC Word 0, bit 12:13 */
0478     uint8_t iCtlXidReAssgn:2;   /* FC Word 0, Bit 14:15 */
0479 #endif
0480 
0481     uint8_t word0Reserved4; /* FC Word 0, bit  0: 7 */
0482 
0483 #ifdef __BIG_ENDIAN_BITFIELD
0484     uint8_t rCtlAck0capable:1;  /* FC Word 1, bit 31 */
0485     uint8_t rCtlAckNcapable:1;  /* FC Word 1, bit 30 */
0486     uint8_t rCtlXidInterlck:1;  /* FC Word 1, bit 29 */
0487     uint8_t rCtlErrorPolicy:2;  /* FC Word 1, bit 27:28 */
0488     uint8_t word1Reserved1:1;   /* FC Word 1, bit 26 */
0489     uint8_t rCtlCatPerSeq:2;    /* FC Word 1, bit 24:25 */
0490 #else   /*  __LITTLE_ENDIAN_BITFIELD */
0491     uint8_t rCtlCatPerSeq:2;    /* FC Word 1, bit 24:25 */
0492     uint8_t word1Reserved1:1;   /* FC Word 1, bit 26 */
0493     uint8_t rCtlErrorPolicy:2;  /* FC Word 1, bit 27:28 */
0494     uint8_t rCtlXidInterlck:1;  /* FC Word 1, bit 29 */
0495     uint8_t rCtlAckNcapable:1;  /* FC Word 1, bit 30 */
0496     uint8_t rCtlAck0capable:1;  /* FC Word 1, bit 31 */
0497 #endif
0498 
0499     uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
0500     uint8_t rcvDataSizeMsb; /* FC Word 1, bit  8:15 */
0501     uint8_t rcvDataSizeLsb; /* FC Word 1, bit  0: 7 */
0502 
0503     uint8_t concurrentSeqMsb;   /* FC Word 2, bit 24:31 */
0504     uint8_t concurrentSeqLsb;   /* FC Word 2, bit 16:23 */
0505     uint8_t EeCreditSeqMsb; /* FC Word 2, bit  8:15 */
0506     uint8_t EeCreditSeqLsb; /* FC Word 2, bit  0: 7 */
0507 
0508     uint8_t openSeqPerXchgMsb;  /* FC Word 3, bit 24:31 */
0509     uint8_t openSeqPerXchgLsb;  /* FC Word 3, bit 16:23 */
0510     uint8_t word3Reserved1; /* Fc Word 3, bit  8:15 */
0511     uint8_t word3Reserved2; /* Fc Word 3, bit  0: 7 */
0512 };
0513 
0514 struct serv_parm {  /* Structure is in Big Endian format */
0515     struct csp cmn;
0516     struct lpfc_name portName;
0517     struct lpfc_name nodeName;
0518     struct class_parms cls1;
0519     struct class_parms cls2;
0520     struct class_parms cls3;
0521     struct class_parms cls4;
0522     union {
0523         uint8_t vendorVersion[16];
0524         struct {
0525             uint32_t vid;
0526 #define LPFC_VV_EMLX_ID 0x454d4c58  /* EMLX */
0527             uint32_t flags;
0528 #define LPFC_VV_SUPPRESS_RSP    1
0529         } vv;
0530     } un;
0531 };
0532 
0533 /*
0534  * Virtual Fabric Tagging Header
0535  */
0536 struct fc_vft_header {
0537      uint32_t word0;
0538 #define fc_vft_hdr_r_ctl_SHIFT      24
0539 #define fc_vft_hdr_r_ctl_MASK       0xFF
0540 #define fc_vft_hdr_r_ctl_WORD       word0
0541 #define fc_vft_hdr_ver_SHIFT        22
0542 #define fc_vft_hdr_ver_MASK     0x3
0543 #define fc_vft_hdr_ver_WORD     word0
0544 #define fc_vft_hdr_type_SHIFT       18
0545 #define fc_vft_hdr_type_MASK        0xF
0546 #define fc_vft_hdr_type_WORD        word0
0547 #define fc_vft_hdr_e_SHIFT      16
0548 #define fc_vft_hdr_e_MASK       0x1
0549 #define fc_vft_hdr_e_WORD       word0
0550 #define fc_vft_hdr_priority_SHIFT   13
0551 #define fc_vft_hdr_priority_MASK    0x7
0552 #define fc_vft_hdr_priority_WORD    word0
0553 #define fc_vft_hdr_vf_id_SHIFT      1
0554 #define fc_vft_hdr_vf_id_MASK       0xFFF
0555 #define fc_vft_hdr_vf_id_WORD       word0
0556     uint32_t word1;
0557 #define fc_vft_hdr_hopct_SHIFT      24
0558 #define fc_vft_hdr_hopct_MASK       0xFF
0559 #define fc_vft_hdr_hopct_WORD       word1
0560 };
0561 
0562 #include <uapi/scsi/fc/fc_els.h>
0563 
0564 /*
0565  *  Extended Link Service LS_COMMAND codes (Payload Word 0)
0566  */
0567 #ifdef __BIG_ENDIAN_BITFIELD
0568 #define ELS_CMD_MASK      0xffff0000
0569 #define ELS_RSP_MASK      0xff000000
0570 #define ELS_CMD_LS_RJT    0x01000000
0571 #define ELS_CMD_ACC       0x02000000
0572 #define ELS_CMD_PLOGI     0x03000000
0573 #define ELS_CMD_FLOGI     0x04000000
0574 #define ELS_CMD_LOGO      0x05000000
0575 #define ELS_CMD_ABTX      0x06000000
0576 #define ELS_CMD_RCS       0x07000000
0577 #define ELS_CMD_RES       0x08000000
0578 #define ELS_CMD_RSS       0x09000000
0579 #define ELS_CMD_RSI       0x0A000000
0580 #define ELS_CMD_ESTS      0x0B000000
0581 #define ELS_CMD_ESTC      0x0C000000
0582 #define ELS_CMD_ADVC      0x0D000000
0583 #define ELS_CMD_RTV       0x0E000000
0584 #define ELS_CMD_RLS       0x0F000000
0585 #define ELS_CMD_ECHO      0x10000000
0586 #define ELS_CMD_TEST      0x11000000
0587 #define ELS_CMD_RRQ       0x12000000
0588 #define ELS_CMD_REC       0x13000000
0589 #define ELS_CMD_RDP       0x18000000
0590 #define ELS_CMD_RDF       0x19000000
0591 #define ELS_CMD_PRLI      0x20100014
0592 #define ELS_CMD_NVMEPRLI  0x20140018
0593 #define ELS_CMD_PRLO      0x21100014
0594 #define ELS_CMD_PRLO_ACC  0x02100014
0595 #define ELS_CMD_PDISC     0x50000000
0596 #define ELS_CMD_FDISC     0x51000000
0597 #define ELS_CMD_ADISC     0x52000000
0598 #define ELS_CMD_FARP      0x54000000
0599 #define ELS_CMD_FARPR     0x55000000
0600 #define ELS_CMD_RPL       0x57000000
0601 #define ELS_CMD_FAN       0x60000000
0602 #define ELS_CMD_RSCN      0x61040000
0603 #define ELS_CMD_RSCN_XMT  0x61040008
0604 #define ELS_CMD_SCR       0x62000000
0605 #define ELS_CMD_RNID      0x78000000
0606 #define ELS_CMD_LIRR      0x7A000000
0607 #define ELS_CMD_LCB   0x81000000
0608 #define ELS_CMD_FPIN      0x16000000
0609 #define ELS_CMD_EDC   0x17000000
0610 #define ELS_CMD_QFPA      0xB0000000
0611 #define ELS_CMD_UVEM      0xB1000000
0612 #else   /*  __LITTLE_ENDIAN_BITFIELD */
0613 #define ELS_CMD_MASK      0xffff
0614 #define ELS_RSP_MASK      0xff
0615 #define ELS_CMD_LS_RJT    0x01
0616 #define ELS_CMD_ACC       0x02
0617 #define ELS_CMD_PLOGI     0x03
0618 #define ELS_CMD_FLOGI     0x04
0619 #define ELS_CMD_LOGO      0x05
0620 #define ELS_CMD_ABTX      0x06
0621 #define ELS_CMD_RCS       0x07
0622 #define ELS_CMD_RES       0x08
0623 #define ELS_CMD_RSS       0x09
0624 #define ELS_CMD_RSI       0x0A
0625 #define ELS_CMD_ESTS      0x0B
0626 #define ELS_CMD_ESTC      0x0C
0627 #define ELS_CMD_ADVC      0x0D
0628 #define ELS_CMD_RTV       0x0E
0629 #define ELS_CMD_RLS       0x0F
0630 #define ELS_CMD_ECHO      0x10
0631 #define ELS_CMD_TEST      0x11
0632 #define ELS_CMD_RRQ       0x12
0633 #define ELS_CMD_REC       0x13
0634 #define ELS_CMD_RDP   0x18
0635 #define ELS_CMD_RDF   0x19
0636 #define ELS_CMD_PRLI      0x14001020
0637 #define ELS_CMD_NVMEPRLI  0x18001420
0638 #define ELS_CMD_PRLO      0x14001021
0639 #define ELS_CMD_PRLO_ACC  0x14001002
0640 #define ELS_CMD_PDISC     0x50
0641 #define ELS_CMD_FDISC     0x51
0642 #define ELS_CMD_ADISC     0x52
0643 #define ELS_CMD_FARP      0x54
0644 #define ELS_CMD_FARPR     0x55
0645 #define ELS_CMD_RPL       0x57
0646 #define ELS_CMD_FAN       0x60
0647 #define ELS_CMD_RSCN      0x0461
0648 #define ELS_CMD_RSCN_XMT  0x08000461
0649 #define ELS_CMD_SCR       0x62
0650 #define ELS_CMD_RNID      0x78
0651 #define ELS_CMD_LIRR      0x7A
0652 #define ELS_CMD_LCB   0x81
0653 #define ELS_CMD_FPIN      ELS_FPIN
0654 #define ELS_CMD_EDC   ELS_EDC
0655 #define ELS_CMD_QFPA      0xB0
0656 #define ELS_CMD_UVEM      0xB1
0657 #endif
0658 
0659 /*
0660  *  LS_RJT Payload Definition
0661  */
0662 
0663 struct ls_rjt { /* Structure is in Big Endian format */
0664     union {
0665         __be32 ls_rjt_error_be;
0666         uint32_t lsRjtError;
0667         struct {
0668             uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
0669 
0670             uint8_t lsRjtRsnCode;   /* FC Word 0, bit 16:23 */
0671             /* LS_RJT reason codes */
0672 #define LSRJT_INVALID_CMD     0x01
0673 #define LSRJT_LOGICAL_ERR     0x03
0674 #define LSRJT_LOGICAL_BSY     0x05
0675 #define LSRJT_PROTOCOL_ERR    0x07
0676 #define LSRJT_UNABLE_TPC      0x09  /* Unable to perform command */
0677 #define LSRJT_CMD_UNSUPPORTED 0x0B
0678 #define LSRJT_VENDOR_UNIQUE   0xFF  /* See Byte 3 */
0679 
0680             uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
0681             /* LS_RJT reason explanation */
0682 #define LSEXP_NOTHING_MORE      0x00
0683 #define LSEXP_SPARM_OPTIONS     0x01
0684 #define LSEXP_SPARM_ICTL        0x03
0685 #define LSEXP_SPARM_RCTL        0x05
0686 #define LSEXP_SPARM_RCV_SIZE    0x07
0687 #define LSEXP_SPARM_CONCUR_SEQ  0x09
0688 #define LSEXP_SPARM_CREDIT      0x0B
0689 #define LSEXP_INVALID_PNAME     0x0D
0690 #define LSEXP_INVALID_NNAME     0x0E
0691 #define LSEXP_INVALID_CSP       0x0F
0692 #define LSEXP_INVALID_ASSOC_HDR 0x11
0693 #define LSEXP_ASSOC_HDR_REQ     0x13
0694 #define LSEXP_INVALID_O_SID     0x15
0695 #define LSEXP_INVALID_OX_RX     0x17
0696 #define LSEXP_CMD_IN_PROGRESS   0x19
0697 #define LSEXP_PORT_LOGIN_REQ    0x1E
0698 #define LSEXP_INVALID_NPORT_ID  0x1F
0699 #define LSEXP_INVALID_SEQ_ID    0x21
0700 #define LSEXP_INVALID_XCHG      0x23
0701 #define LSEXP_INACTIVE_XCHG     0x25
0702 #define LSEXP_RQ_REQUIRED       0x27
0703 #define LSEXP_OUT_OF_RESOURCE   0x29
0704 #define LSEXP_CANT_GIVE_DATA    0x2A
0705 #define LSEXP_REQ_UNSUPPORTED   0x2C
0706             uint8_t vendorUnique;   /* FC Word 0, bit  0: 7 */
0707         } b;
0708     } un;
0709 };
0710 
0711 /*
0712  *  N_Port Login (FLOGO/PLOGO Request) Payload Definition
0713  */
0714 
0715 typedef struct _LOGO {      /* Structure is in Big Endian format */
0716     union {
0717         uint32_t nPortId32; /* Access nPortId as a word */
0718         struct {
0719             uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
0720             uint8_t nPortIdByte0;   /* N_port  ID bit 16:23 */
0721             uint8_t nPortIdByte1;   /* N_port  ID bit  8:15 */
0722             uint8_t nPortIdByte2;   /* N_port  ID bit  0: 7 */
0723         } b;
0724     } un;
0725     struct lpfc_name portName;  /* N_port name field */
0726 } LOGO;
0727 
0728 /*
0729  *  FCP Login (PRLI Request / ACC) Payload Definition
0730  */
0731 
0732 #define PRLX_PAGE_LEN   0x10
0733 #define TPRLO_PAGE_LEN  0x14
0734 
0735 typedef struct _PRLI {      /* Structure is in Big Endian format */
0736     uint8_t prliType;   /* FC Parm Word 0, bit 24:31 */
0737 
0738 #define PRLI_FCP_TYPE 0x08
0739 #define PRLI_NVME_TYPE 0x28
0740     uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
0741 
0742 #ifdef __BIG_ENDIAN_BITFIELD
0743     uint8_t origProcAssocV:1;   /* FC Parm Word 0, bit 15 */
0744     uint8_t respProcAssocV:1;   /* FC Parm Word 0, bit 14 */
0745     uint8_t estabImagePair:1;   /* FC Parm Word 0, bit 13 */
0746 
0747     /*    ACC = imagePairEstablished */
0748     uint8_t word0Reserved2:1;   /* FC Parm Word 0, bit 12 */
0749     uint8_t acceptRspCode:4;    /* FC Parm Word 0, bit 8:11, ACC ONLY */
0750 #else   /*  __LITTLE_ENDIAN_BITFIELD */
0751     uint8_t acceptRspCode:4;    /* FC Parm Word 0, bit 8:11, ACC ONLY */
0752     uint8_t word0Reserved2:1;   /* FC Parm Word 0, bit 12 */
0753     uint8_t estabImagePair:1;   /* FC Parm Word 0, bit 13 */
0754     uint8_t respProcAssocV:1;   /* FC Parm Word 0, bit 14 */
0755     uint8_t origProcAssocV:1;   /* FC Parm Word 0, bit 15 */
0756     /*    ACC = imagePairEstablished */
0757 #endif
0758 
0759 #define PRLI_REQ_EXECUTED     0x1   /* acceptRspCode */
0760 #define PRLI_NO_RESOURCES     0x2
0761 #define PRLI_INIT_INCOMPLETE  0x3
0762 #define PRLI_NO_SUCH_PA       0x4
0763 #define PRLI_PREDEF_CONFIG    0x5
0764 #define PRLI_PARTIAL_SUCCESS  0x6
0765 #define PRLI_INVALID_PAGE_CNT 0x7
0766     uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
0767 
0768     uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
0769 
0770     uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
0771 
0772     uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
0773     uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
0774 
0775 #ifdef __BIG_ENDIAN_BITFIELD
0776     uint16_t Word3bit15Resved:1;    /* FC Parm Word 3, bit 15 */
0777     uint16_t Word3bit14Resved:1;    /* FC Parm Word 3, bit 14 */
0778     uint16_t Word3bit13Resved:1;    /* FC Parm Word 3, bit 13 */
0779     uint16_t Word3bit12Resved:1;    /* FC Parm Word 3, bit 12 */
0780     uint16_t Word3bit11Resved:1;    /* FC Parm Word 3, bit 11 */
0781     uint16_t Word3bit10Resved:1;    /* FC Parm Word 3, bit 10 */
0782     uint16_t TaskRetryIdReq:1;  /* FC Parm Word 3, bit  9 */
0783     uint16_t Retry:1;   /* FC Parm Word 3, bit  8 */
0784     uint16_t ConfmComplAllowed:1;   /* FC Parm Word 3, bit  7 */
0785     uint16_t dataOverLay:1; /* FC Parm Word 3, bit  6 */
0786     uint16_t initiatorFunc:1;   /* FC Parm Word 3, bit  5 */
0787     uint16_t targetFunc:1;  /* FC Parm Word 3, bit  4 */
0788     uint16_t cmdDataMixEna:1;   /* FC Parm Word 3, bit  3 */
0789     uint16_t dataRspMixEna:1;   /* FC Parm Word 3, bit  2 */
0790     uint16_t readXferRdyDis:1;  /* FC Parm Word 3, bit  1 */
0791     uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit  0 */
0792 #else   /*  __LITTLE_ENDIAN_BITFIELD */
0793     uint16_t Retry:1;   /* FC Parm Word 3, bit  8 */
0794     uint16_t TaskRetryIdReq:1;  /* FC Parm Word 3, bit  9 */
0795     uint16_t Word3bit10Resved:1;    /* FC Parm Word 3, bit 10 */
0796     uint16_t Word3bit11Resved:1;    /* FC Parm Word 3, bit 11 */
0797     uint16_t Word3bit12Resved:1;    /* FC Parm Word 3, bit 12 */
0798     uint16_t Word3bit13Resved:1;    /* FC Parm Word 3, bit 13 */
0799     uint16_t Word3bit14Resved:1;    /* FC Parm Word 3, bit 14 */
0800     uint16_t Word3bit15Resved:1;    /* FC Parm Word 3, bit 15 */
0801     uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit  0 */
0802     uint16_t readXferRdyDis:1;  /* FC Parm Word 3, bit  1 */
0803     uint16_t dataRspMixEna:1;   /* FC Parm Word 3, bit  2 */
0804     uint16_t cmdDataMixEna:1;   /* FC Parm Word 3, bit  3 */
0805     uint16_t targetFunc:1;  /* FC Parm Word 3, bit  4 */
0806     uint16_t initiatorFunc:1;   /* FC Parm Word 3, bit  5 */
0807     uint16_t dataOverLay:1; /* FC Parm Word 3, bit  6 */
0808     uint16_t ConfmComplAllowed:1;   /* FC Parm Word 3, bit  7 */
0809 #endif
0810 } PRLI;
0811 
0812 /*
0813  *  FCP Logout (PRLO Request / ACC) Payload Definition
0814  */
0815 
0816 typedef struct _PRLO {      /* Structure is in Big Endian format */
0817     uint8_t prloType;   /* FC Parm Word 0, bit 24:31 */
0818 
0819 #define PRLO_FCP_TYPE  0x08
0820     uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
0821 
0822 #ifdef __BIG_ENDIAN_BITFIELD
0823     uint8_t origProcAssocV:1;   /* FC Parm Word 0, bit 15 */
0824     uint8_t respProcAssocV:1;   /* FC Parm Word 0, bit 14 */
0825     uint8_t word0Reserved2:2;   /* FC Parm Word 0, bit 12:13 */
0826     uint8_t acceptRspCode:4;    /* FC Parm Word 0, bit 8:11, ACC ONLY */
0827 #else   /*  __LITTLE_ENDIAN_BITFIELD */
0828     uint8_t acceptRspCode:4;    /* FC Parm Word 0, bit 8:11, ACC ONLY */
0829     uint8_t word0Reserved2:2;   /* FC Parm Word 0, bit 12:13 */
0830     uint8_t respProcAssocV:1;   /* FC Parm Word 0, bit 14 */
0831     uint8_t origProcAssocV:1;   /* FC Parm Word 0, bit 15 */
0832 #endif
0833 
0834 #define PRLO_REQ_EXECUTED     0x1   /* acceptRspCode */
0835 #define PRLO_NO_SUCH_IMAGE    0x4
0836 #define PRLO_INVALID_PAGE_CNT 0x7
0837 
0838     uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
0839 
0840     uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
0841 
0842     uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
0843 
0844     uint32_t word3Reserved1;    /* FC Parm Word 3, bit 0:31 */
0845 } PRLO;
0846 
0847 typedef struct _ADISC {     /* Structure is in Big Endian format */
0848     uint32_t hardAL_PA;
0849     struct lpfc_name portName;
0850     struct lpfc_name nodeName;
0851     uint32_t DID;
0852 } __packed ADISC;
0853 
0854 typedef struct _FARP {      /* Structure is in Big Endian format */
0855     uint32_t Mflags:8;
0856     uint32_t Odid:24;
0857 #define FARP_NO_ACTION          0   /* FARP information enclosed, no
0858                        action */
0859 #define FARP_MATCH_PORT         0x1 /* Match on Responder Port Name */
0860 #define FARP_MATCH_NODE         0x2 /* Match on Responder Node Name */
0861 #define FARP_MATCH_IP           0x4 /* Match on IP address, not supported */
0862 #define FARP_MATCH_IPV4         0x5 /* Match on IPV4 address, not
0863                        supported */
0864 #define FARP_MATCH_IPV6         0x6 /* Match on IPV6 address, not
0865                        supported */
0866     uint32_t Rflags:8;
0867     uint32_t Rdid:24;
0868 #define FARP_REQUEST_PLOGI      0x1 /* Request for PLOGI */
0869 #define FARP_REQUEST_FARPR      0x2 /* Request for FARP Response */
0870     struct lpfc_name OportName;
0871     struct lpfc_name OnodeName;
0872     struct lpfc_name RportName;
0873     struct lpfc_name RnodeName;
0874     uint8_t Oipaddr[16];
0875     uint8_t Ripaddr[16];
0876 } FARP;
0877 
0878 typedef struct _FAN {       /* Structure is in Big Endian format */
0879     uint32_t Fdid;
0880     struct lpfc_name FportName;
0881     struct lpfc_name FnodeName;
0882 } __packed FAN;
0883 
0884 typedef struct _SCR {       /* Structure is in Big Endian format */
0885     uint8_t resvd1;
0886     uint8_t resvd2;
0887     uint8_t resvd3;
0888     uint8_t Function;
0889 #define  SCR_FUNC_FABRIC     0x01
0890 #define  SCR_FUNC_NPORT      0x02
0891 #define  SCR_FUNC_FULL       0x03
0892 #define  SCR_CLEAR           0xff
0893 } SCR;
0894 
0895 typedef struct _RNID_TOP_DISC {
0896     struct lpfc_name portName;
0897     uint8_t resvd[8];
0898     uint32_t unitType;
0899 #define RNID_HBA            0x7
0900 #define RNID_HOST           0xa
0901 #define RNID_DRIVER         0xd
0902     uint32_t physPort;
0903     uint32_t attachedNodes;
0904     uint16_t ipVersion;
0905 #define RNID_IPV4           0x1
0906 #define RNID_IPV6           0x2
0907     uint16_t UDPport;
0908     uint8_t ipAddr[16];
0909     uint16_t resvd1;
0910     uint16_t flags;
0911 #define RNID_TD_SUPPORT     0x1
0912 #define RNID_LP_VALID       0x2
0913 } RNID_TOP_DISC;
0914 
0915 typedef struct _RNID {      /* Structure is in Big Endian format */
0916     uint8_t Format;
0917 #define RNID_TOPOLOGY_DISC  0xdf
0918     uint8_t CommonLen;
0919     uint8_t resvd1;
0920     uint8_t SpecificLen;
0921     struct lpfc_name portName;
0922     struct lpfc_name nodeName;
0923     union {
0924         RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
0925     } un;
0926 } __packed RNID;
0927 
0928 struct RLS {            /* Structure is in Big Endian format */
0929     uint32_t rls;
0930 #define rls_rsvd_SHIFT      24
0931 #define rls_rsvd_MASK       0x000000ff
0932 #define rls_rsvd_WORD       rls
0933 #define rls_did_SHIFT       0
0934 #define rls_did_MASK        0x00ffffff
0935 #define rls_did_WORD        rls
0936 };
0937 
0938 struct  RLS_RSP {       /* Structure is in Big Endian format */
0939     uint32_t linkFailureCnt;
0940     uint32_t lossSyncCnt;
0941     uint32_t lossSignalCnt;
0942     uint32_t primSeqErrCnt;
0943     uint32_t invalidXmitWord;
0944     uint32_t crcCnt;
0945 };
0946 
0947 struct RRQ {            /* Structure is in Big Endian format */
0948     uint32_t rrq;
0949 #define rrq_rsvd_SHIFT      24
0950 #define rrq_rsvd_MASK       0x000000ff
0951 #define rrq_rsvd_WORD       rrq
0952 #define rrq_did_SHIFT       0
0953 #define rrq_did_MASK        0x00ffffff
0954 #define rrq_did_WORD        rrq
0955     uint32_t rrq_exchg;
0956 #define rrq_oxid_SHIFT      16
0957 #define rrq_oxid_MASK       0xffff
0958 #define rrq_oxid_WORD       rrq_exchg
0959 #define rrq_rxid_SHIFT      0
0960 #define rrq_rxid_MASK       0xffff
0961 #define rrq_rxid_WORD       rrq_exchg
0962 };
0963 
0964 #define LPFC_MAX_VFN_PER_PFN    255 /* Maximum VFs allowed per ARI */
0965 #define LPFC_DEF_VFN_PER_PFN    0   /* Default VFs due to platform limitation*/
0966 
0967 struct RTV_RSP {        /* Structure is in Big Endian format */
0968     uint32_t ratov;
0969     uint32_t edtov;
0970     uint32_t qtov;
0971 #define qtov_rsvd0_SHIFT    28
0972 #define qtov_rsvd0_MASK     0x0000000f
0973 #define qtov_rsvd0_WORD     qtov        /* reserved */
0974 #define qtov_edtovres_SHIFT 27
0975 #define qtov_edtovres_MASK  0x00000001
0976 #define qtov_edtovres_WORD  qtov        /* E_D_TOV Resolution */
0977 #define qtov__rsvd1_SHIFT   19
0978 #define qtov_rsvd1_MASK     0x0000003f
0979 #define qtov_rsvd1_WORD     qtov        /* reserved */
0980 #define qtov_rttov_SHIFT    18
0981 #define qtov_rttov_MASK     0x00000001
0982 #define qtov_rttov_WORD     qtov        /* R_T_TOV value */
0983 #define qtov_rsvd2_SHIFT    0
0984 #define qtov_rsvd2_MASK     0x0003ffff
0985 #define qtov_rsvd2_WORD     qtov        /* reserved */
0986 };
0987 
0988 
0989 typedef struct  _RPL {      /* Structure is in Big Endian format */
0990     uint32_t maxsize;
0991     uint32_t index;
0992 } RPL;
0993 
0994 typedef struct  _PORT_NUM_BLK {
0995     uint32_t portNum;
0996     uint32_t portID;
0997     struct lpfc_name portName;
0998 } PORT_NUM_BLK;
0999 
1000 typedef struct  _RPL_RSP {  /* Structure is in Big Endian format */
1001     uint32_t listLen;
1002     uint32_t index;
1003     PORT_NUM_BLK port_num_blk;
1004 } RPL_RSP;
1005 
1006 /* This is used for RSCN command */
1007 typedef struct _D_ID {      /* Structure is in Big Endian format */
1008     union {
1009         uint32_t word;
1010         struct {
1011 #ifdef __BIG_ENDIAN_BITFIELD
1012             uint8_t resv;
1013             uint8_t domain;
1014             uint8_t area;
1015             uint8_t id;
1016 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1017             uint8_t id;
1018             uint8_t area;
1019             uint8_t domain;
1020             uint8_t resv;
1021 #endif
1022         } b;
1023     } un;
1024 } D_ID;
1025 
1026 #define RSCN_ADDRESS_FORMAT_PORT    0x0
1027 #define RSCN_ADDRESS_FORMAT_AREA    0x1
1028 #define RSCN_ADDRESS_FORMAT_DOMAIN  0x2
1029 #define RSCN_ADDRESS_FORMAT_FABRIC  0x3
1030 #define RSCN_ADDRESS_FORMAT_MASK    0x3
1031 
1032 /*
1033  *  Structure to define all ELS Payload types
1034  */
1035 
1036 typedef struct _ELS_PKT {   /* Structure is in Big Endian format */
1037     uint8_t elsCode;    /* FC Word 0, bit 24:31 */
1038     uint8_t elsByte1;
1039     uint8_t elsByte2;
1040     uint8_t elsByte3;
1041     union {
1042         struct ls_rjt lsRjt;    /* Payload for LS_RJT ELS response */
1043         struct serv_parm logi;  /* Payload for PLOGI/FLOGI/PDISC/ACC */
1044         LOGO logo;  /* Payload for PLOGO/FLOGO/ACC */
1045         PRLI prli;  /* Payload for PRLI/ACC */
1046         PRLO prlo;  /* Payload for PRLO/ACC */
1047         ADISC adisc;    /* Payload for ADISC/ACC */
1048         FARP farp;  /* Payload for FARP/ACC */
1049         FAN fan;    /* Payload for FAN */
1050         SCR scr;    /* Payload for SCR/ACC */
1051         RNID rnid;  /* Payload for RNID */
1052         uint8_t pad[128 - 4];   /* Pad out to payload of 128 bytes */
1053     } un;
1054 } ELS_PKT;
1055 
1056 /*
1057  * Link Cable Beacon (LCB) ELS Frame
1058  */
1059 
1060 struct fc_lcb_request_frame {
1061     uint32_t      lcb_command;      /* ELS command opcode (0x81)     */
1062     uint8_t       lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1063 #define LPFC_LCB_ON     0x1
1064 #define LPFC_LCB_OFF        0x2
1065     uint8_t       reserved[2];
1066     uint8_t       capability;   /* LCB Payload Word 1, bit 0:7 */
1067     uint8_t       lcb_type; /* LCB Payload Word 2, bit 24:31 */
1068 #define LPFC_LCB_GREEN      0x1
1069 #define LPFC_LCB_AMBER      0x2
1070     uint8_t       lcb_frequency;    /* LCB Payload Word 2, bit 16:23 */
1071 #define LCB_CAPABILITY_DURATION 1
1072 #define BEACON_VERSION_V1   1
1073 #define BEACON_VERSION_V0   0
1074     uint16_t      lcb_duration;     /* LCB Payload Word 2, bit 15:0  */
1075 };
1076 
1077 /*
1078  * Link Cable Beacon (LCB) ELS Response Frame
1079  */
1080 struct fc_lcb_res_frame {
1081     uint32_t      lcb_ls_acc;       /* Acceptance of LCB request (0x02) */
1082     uint8_t       lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1083     uint8_t       reserved[2];
1084     uint8_t       capability;   /* LCB Payload Word 1, bit 0:7 */
1085     uint8_t       lcb_type; /* LCB Payload Word 2, bit 24:31 */
1086     uint8_t       lcb_frequency;    /* LCB Payload Word 2, bit 16:23 */
1087     uint16_t      lcb_duration;     /* LCB Payload Word 2, bit 15:0  */
1088 };
1089 
1090 /*
1091  * Read Diagnostic Parameters (RDP) ELS frame.
1092  */
1093 #define SFF_PG0_IDENT_SFP              0x3
1094 
1095 #define SFP_FLAG_PT_OPTICAL            0x0
1096 #define SFP_FLAG_PT_SWLASER            0x01
1097 #define SFP_FLAG_PT_LWLASER_LC1310     0x02
1098 #define SFP_FLAG_PT_LWLASER_LL1550     0x03
1099 #define SFP_FLAG_PT_MASK               0x0F
1100 #define SFP_FLAG_PT_SHIFT              0
1101 
1102 #define SFP_FLAG_IS_OPTICAL_PORT       0x01
1103 #define SFP_FLAG_IS_OPTICAL_MASK       0x010
1104 #define SFP_FLAG_IS_OPTICAL_SHIFT      4
1105 
1106 #define SFP_FLAG_IS_DESC_VALID         0x01
1107 #define SFP_FLAG_IS_DESC_VALID_MASK    0x020
1108 #define SFP_FLAG_IS_DESC_VALID_SHIFT   5
1109 
1110 #define SFP_FLAG_CT_UNKNOWN            0x0
1111 #define SFP_FLAG_CT_SFP_PLUS           0x01
1112 #define SFP_FLAG_CT_MASK               0x3C
1113 #define SFP_FLAG_CT_SHIFT              6
1114 
1115 struct fc_rdp_port_name_info {
1116     uint8_t wwnn[8];
1117     uint8_t wwpn[8];
1118 };
1119 
1120 
1121 /*
1122  * Link Error Status Block Structure (FC-FS-3) for RDP
1123  * This similar to RPS ELS
1124  */
1125 struct fc_link_status {
1126     uint32_t      link_failure_cnt;
1127     uint32_t      loss_of_synch_cnt;
1128     uint32_t      loss_of_signal_cnt;
1129     uint32_t      primitive_seq_proto_err;
1130     uint32_t      invalid_trans_word;
1131     uint32_t      invalid_crc_cnt;
1132 
1133 };
1134 
1135 #define RDP_PORT_NAMES_DESC_TAG  0x00010003
1136 struct fc_rdp_port_name_desc {
1137     uint32_t    tag;     /* 0001 0003h */
1138     uint32_t    length;  /* set to size of payload struct */
1139     struct fc_rdp_port_name_info  port_names;
1140 };
1141 
1142 
1143 struct fc_rdp_fec_info {
1144     uint32_t CorrectedBlocks;
1145     uint32_t UncorrectableBlocks;
1146 };
1147 
1148 #define RDP_FEC_DESC_TAG  0x00010005
1149 struct fc_fec_rdp_desc {
1150     uint32_t tag;
1151     uint32_t length;
1152     struct fc_rdp_fec_info info;
1153 };
1154 
1155 struct fc_rdp_link_error_status_payload_info {
1156     struct fc_link_status link_status; /* 24 bytes */
1157     uint32_t  port_type;             /* bits 31-30 only */
1158 };
1159 
1160 #define RDP_LINK_ERROR_STATUS_DESC_TAG  0x00010002
1161 struct fc_rdp_link_error_status_desc {
1162     uint32_t         tag;     /* 0001 0002h */
1163     uint32_t         length;  /* set to size of payload struct */
1164     struct fc_rdp_link_error_status_payload_info info;
1165 };
1166 
1167 #define VN_PT_PHY_UNKNOWN      0x00
1168 #define VN_PT_PHY_PF_PORT      0x01
1169 #define VN_PT_PHY_ETH_MAC      0x10
1170 #define VN_PT_PHY_SHIFT                30
1171 
1172 #define RDP_PS_1GB             0x8000
1173 #define RDP_PS_2GB             0x4000
1174 #define RDP_PS_4GB             0x2000
1175 #define RDP_PS_10GB            0x1000
1176 #define RDP_PS_8GB             0x0800
1177 #define RDP_PS_16GB            0x0400
1178 #define RDP_PS_32GB            0x0200
1179 #define RDP_PS_64GB            0x0100
1180 #define RDP_PS_128GB           0x0080
1181 #define RDP_PS_256GB           0x0040
1182 
1183 #define RDP_CAP_USER_CONFIGURED 0x0002
1184 #define RDP_CAP_UNKNOWN         0x0001
1185 #define RDP_PS_UNKNOWN          0x0002
1186 #define RDP_PS_NOT_ESTABLISHED  0x0001
1187 
1188 struct fc_rdp_port_speed {
1189     uint16_t   capabilities;
1190     uint16_t   speed;
1191 };
1192 
1193 struct fc_rdp_port_speed_info {
1194     struct fc_rdp_port_speed   port_speed;
1195 };
1196 
1197 #define RDP_PORT_SPEED_DESC_TAG  0x00010001
1198 struct fc_rdp_port_speed_desc {
1199     uint32_t         tag;            /* 00010001h */
1200     uint32_t         length;         /* set to size of payload struct */
1201     struct fc_rdp_port_speed_info info;
1202 };
1203 
1204 #define RDP_NPORT_ID_SIZE      4
1205 #define RDP_N_PORT_DESC_TAG    0x00000003
1206 struct fc_rdp_nport_desc {
1207     uint32_t         tag;          /* 0000 0003h, big endian */
1208     uint32_t         length;       /* size of RDP_N_PORT_ID struct */
1209     uint32_t         nport_id : 12;
1210     uint32_t         reserved : 8;
1211 };
1212 
1213 
1214 struct fc_rdp_link_service_info {
1215     uint32_t         els_req;    /* Request payload word 0 value.*/
1216 };
1217 
1218 #define RDP_LINK_SERVICE_DESC_TAG  0x00000001
1219 struct fc_rdp_link_service_desc {
1220     uint32_t         tag;     /* Descriptor tag  1 */
1221     uint32_t         length;  /* set to size of payload struct. */
1222     struct fc_rdp_link_service_info  payload;
1223                   /* must be ELS req Word 0(0x18) */
1224 };
1225 
1226 struct fc_rdp_sfp_info {
1227     uint16_t    temperature;
1228     uint16_t    vcc;
1229     uint16_t    tx_bias;
1230     uint16_t    tx_power;
1231     uint16_t    rx_power;
1232     uint16_t    flags;
1233 };
1234 
1235 #define RDP_SFP_DESC_TAG  0x00010000
1236 struct fc_rdp_sfp_desc {
1237     uint32_t         tag;
1238     uint32_t         length;  /* set to size of sfp_info struct */
1239     struct fc_rdp_sfp_info sfp_info;
1240 };
1241 
1242 /* Buffer Credit Descriptor */
1243 struct fc_rdp_bbc_info {
1244     uint32_t              port_bbc; /* FC_Port buffer-to-buffer credit */
1245     uint32_t              attached_port_bbc;
1246     uint32_t              rtt;      /* Round trip time */
1247 };
1248 #define RDP_BBC_DESC_TAG  0x00010006
1249 struct fc_rdp_bbc_desc {
1250     uint32_t              tag;
1251     uint32_t              length;
1252     struct fc_rdp_bbc_info  bbc_info;
1253 };
1254 
1255 /* Optical Element Type Transgression Flags */
1256 #define RDP_OET_LOW_WARNING  0x1
1257 #define RDP_OET_HIGH_WARNING 0x2
1258 #define RDP_OET_LOW_ALARM    0x4
1259 #define RDP_OET_HIGH_ALARM   0x8
1260 
1261 #define RDP_OED_TEMPERATURE  0x1
1262 #define RDP_OED_VOLTAGE      0x2
1263 #define RDP_OED_TXBIAS       0x3
1264 #define RDP_OED_TXPOWER      0x4
1265 #define RDP_OED_RXPOWER      0x5
1266 
1267 #define RDP_OED_TYPE_SHIFT   28
1268 /* Optical Element Data descriptor */
1269 struct fc_rdp_oed_info {
1270     uint16_t            hi_alarm;
1271     uint16_t            lo_alarm;
1272     uint16_t            hi_warning;
1273     uint16_t            lo_warning;
1274     uint32_t            function_flags;
1275 };
1276 #define RDP_OED_DESC_TAG  0x00010007
1277 struct fc_rdp_oed_sfp_desc {
1278     uint32_t             tag;
1279     uint32_t             length;
1280     struct fc_rdp_oed_info oed_info;
1281 };
1282 
1283 /* Optical Product Data descriptor */
1284 struct fc_rdp_opd_sfp_info {
1285     uint8_t            vendor_name[16];
1286     uint8_t            model_number[16];
1287     uint8_t            serial_number[16];
1288     uint8_t            revision[4];
1289     uint8_t            date[8];
1290 };
1291 
1292 #define RDP_OPD_DESC_TAG  0x00010008
1293 struct fc_rdp_opd_sfp_desc {
1294     uint32_t             tag;
1295     uint32_t             length;
1296     struct fc_rdp_opd_sfp_info opd_info;
1297 };
1298 
1299 struct fc_rdp_req_frame {
1300     uint32_t         rdp_command;           /* ELS command opcode (0x18)*/
1301     uint32_t         rdp_des_length;        /* RDP Payload Word 1 */
1302     struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */
1303 };
1304 
1305 
1306 struct fc_rdp_res_frame {
1307     uint32_t    reply_sequence;     /* FC word0 LS_ACC or LS_RJT */
1308     uint32_t   length;          /* FC Word 1      */
1309     struct fc_rdp_link_service_desc link_service_desc;    /* Word 2 -4   */
1310     struct fc_rdp_sfp_desc sfp_desc;                      /* Word 5 -9   */
1311     struct fc_rdp_port_speed_desc portspeed_desc;         /* Word 10 -12 */
1312     struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13 -21 */
1313     struct fc_rdp_port_name_desc diag_port_names_desc;    /* Word 22 -27 */
1314     struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28 -33 */
1315     struct fc_fec_rdp_desc fec_desc;                      /* FC word 34-37*/
1316     struct fc_rdp_bbc_desc bbc_desc;                      /* FC Word 38-42*/
1317     struct fc_rdp_oed_sfp_desc oed_temp_desc;             /* FC Word 43-47*/
1318     struct fc_rdp_oed_sfp_desc oed_voltage_desc;          /* FC word 48-52*/
1319     struct fc_rdp_oed_sfp_desc oed_txbias_desc;           /* FC word 53-57*/
1320     struct fc_rdp_oed_sfp_desc oed_txpower_desc;          /* FC word 58-62*/
1321     struct fc_rdp_oed_sfp_desc oed_rxpower_desc;          /* FC word 63-67*/
1322     struct fc_rdp_opd_sfp_desc opd_desc;                  /* FC word 68-84*/
1323 };
1324 
1325 
1326 /* UVEM */
1327 
1328 #define LPFC_UVEM_SIZE 60
1329 #define LPFC_UVEM_VEM_ID_DESC_SIZE 16
1330 #define LPFC_UVEM_VE_MAP_DESC_SIZE 20
1331 
1332 #define VEM_ID_DESC_TAG  0x0001000A
1333 struct lpfc_vem_id_desc {
1334     uint32_t tag;
1335     uint32_t length;
1336     uint8_t vem_id[16];
1337 };
1338 
1339 #define LPFC_QFPA_SIZE  4
1340 
1341 #define INSTANTIATED_VE_DESC_TAG  0x0001000B
1342 struct instantiated_ve_desc {
1343     uint32_t tag;
1344     uint32_t length;
1345     uint8_t global_vem_id[16];
1346     uint32_t word6;
1347 #define lpfc_instantiated_local_id_SHIFT   0
1348 #define lpfc_instantiated_local_id_MASK    0x000000ff
1349 #define lpfc_instantiated_local_id_WORD    word6
1350 #define lpfc_instantiated_nport_id_SHIFT   8
1351 #define lpfc_instantiated_nport_id_MASK    0x00ffffff
1352 #define lpfc_instantiated_nport_id_WORD    word6
1353 };
1354 
1355 #define DEINSTANTIATED_VE_DESC_TAG  0x0001000C
1356 struct deinstantiated_ve_desc {
1357     uint32_t tag;
1358     uint32_t length;
1359     uint8_t global_vem_id[16];
1360     uint32_t word6;
1361 #define lpfc_deinstantiated_nport_id_SHIFT   0
1362 #define lpfc_deinstantiated_nport_id_MASK    0x000000ff
1363 #define lpfc_deinstantiated_nport_id_WORD    word6
1364 #define lpfc_deinstantiated_local_id_SHIFT   24
1365 #define lpfc_deinstantiated_local_id_MASK    0x00ffffff
1366 #define lpfc_deinstantiated_local_id_WORD    word6
1367 };
1368 
1369 /* Query Fabric Priority Allocation Response */
1370 #define LPFC_PRIORITY_RANGE_DESC_SIZE 12
1371 
1372 struct priority_range_desc {
1373     uint32_t tag;
1374     uint32_t length;
1375     uint8_t lo_range;
1376     uint8_t hi_range;
1377     uint8_t qos_priority;
1378     uint8_t local_ve_id;
1379 };
1380 
1381 struct fc_qfpa_res {
1382     uint32_t reply_sequence;    /* LS_ACC or LS_RJT */
1383     uint32_t length;    /* FC Word 1    */
1384     struct priority_range_desc desc[1];
1385 };
1386 
1387 /* Application Server command code */
1388 /* VMID               */
1389 
1390 #define SLI_CT_APP_SEV_Subtypes     0x20    /* Application Server subtype */
1391 
1392 #define SLI_CTAS_GAPPIA_ENT    0x0100   /* Get Application Identifier */
1393 #define SLI_CTAS_GALLAPPIA     0x0101   /* Get All Application Identifier */
1394 #define SLI_CTAS_GALLAPPIA_ID  0x0102   /* Get All Application Identifier */
1395                     /* for Nport */
1396 #define SLI_CTAS_GAPPIA_IDAPP  0x0103   /* Get Application Identifier */
1397                     /* for Nport */
1398 #define SLI_CTAS_RAPP_IDENT    0x0200   /* Register Application Identifier */
1399 #define SLI_CTAS_DAPP_IDENT    0x0300   /* Deregister Application */
1400                     /* Identifier */
1401 #define SLI_CTAS_DALLAPP_ID    0x0301   /* Deregister All Application */
1402                     /* Identifier */
1403 
1404 struct entity_id_object {
1405     uint8_t entity_id_len;
1406     uint8_t entity_id[255]; /* VM UUID */
1407 };
1408 
1409 struct app_id_object {
1410     uint32_t port_id;
1411     uint32_t app_id;
1412     struct entity_id_object obj;
1413 };
1414 
1415 struct lpfc_vmid_rapp_ident_list {
1416     uint32_t no_of_objects;
1417     struct entity_id_object obj[1];
1418 };
1419 
1420 struct lpfc_vmid_dapp_ident_list {
1421     uint32_t no_of_objects;
1422     struct entity_id_object obj[1];
1423 };
1424 
1425 #define GALLAPPIA_ID_LAST  0x80
1426 struct lpfc_vmid_gallapp_ident_list {
1427     uint8_t control;
1428     uint8_t reserved[3];
1429     struct app_id_object app_id;
1430 };
1431 
1432 #define RAPP_IDENT_OFFSET  (offsetof(struct lpfc_sli_ct_request, un) + 4)
1433 #define DAPP_IDENT_OFFSET  (offsetof(struct lpfc_sli_ct_request, un) + 4)
1434 #define GALLAPPIA_ID_SIZE  (offsetof(struct lpfc_sli_ct_request, un) + 4)
1435 #define DALLAPP_ID_SIZE    (offsetof(struct lpfc_sli_ct_request, un) + 4)
1436 
1437 /******** FDMI ********/
1438 
1439 /* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */
1440 #define  SLI_CT_FDMI_Subtypes     0x10  /* Management Service Subtype */
1441 
1442 /* Definitions for HBA / Port attribute entries */
1443 
1444 /* Attribute Entry */
1445 struct lpfc_fdmi_attr_entry {
1446     union {
1447         uint32_t AttrInt;
1448         uint8_t  AttrTypes[32];
1449         uint8_t  AttrString[256];
1450         struct lpfc_name AttrWWN;
1451     } un;
1452 };
1453 
1454 struct lpfc_fdmi_attr_def { /* Defined in TLV format */
1455     /* Structure is in Big Endian format */
1456     uint32_t AttrType:16;
1457     uint32_t AttrLen:16;
1458     /* Marks start of Value (ATTRIBUTE_ENTRY) */
1459     struct lpfc_fdmi_attr_entry AttrValue;
1460 } __packed;
1461 
1462 /*
1463  * HBA Attribute Block
1464  */
1465 struct lpfc_fdmi_attr_block {
1466     uint32_t EntryCnt;      /* Number of HBA attribute entries */
1467     struct lpfc_fdmi_attr_entry Entry;  /* Variable-length array */
1468 };
1469 
1470 /*
1471  * Port Entry
1472  */
1473 struct lpfc_fdmi_port_entry {
1474     struct lpfc_name PortName;
1475 };
1476 
1477 /*
1478  * HBA Identifier
1479  */
1480 struct lpfc_fdmi_hba_ident {
1481     struct lpfc_name PortName;
1482 };
1483 
1484 /*
1485  * Registered Port List Format
1486  */
1487 struct lpfc_fdmi_reg_port_list {
1488     uint32_t EntryCnt;
1489     struct lpfc_fdmi_port_entry pe;
1490 } __packed;
1491 
1492 /*
1493  * Register HBA(RHBA)
1494  */
1495 struct lpfc_fdmi_reg_hba {
1496     struct lpfc_fdmi_hba_ident hi;
1497     struct lpfc_fdmi_reg_port_list rpl;
1498 };
1499 
1500 /******** MI MIB ********/
1501 #define SLI_CT_MIB_Subtypes 0x11
1502 
1503 /*
1504  * Register HBA Attributes (RHAT)
1505  */
1506 struct lpfc_fdmi_reg_hbaattr {
1507     struct lpfc_name HBA_PortName;
1508     struct lpfc_fdmi_attr_block ab;
1509 };
1510 
1511 /*
1512  * Register Port Attributes (RPA)
1513  */
1514 struct lpfc_fdmi_reg_portattr {
1515     struct lpfc_name PortName;
1516     struct lpfc_fdmi_attr_block ab;
1517 };
1518 
1519 /*
1520  * HBA MAnagement Operations Command Codes
1521  */
1522 #define  SLI_MGMT_GRHL     0x100    /* Get registered HBA list */
1523 #define  SLI_MGMT_GHAT     0x101    /* Get HBA attributes */
1524 #define  SLI_MGMT_GRPL     0x102    /* Get registered Port list */
1525 #define  SLI_MGMT_GPAT     0x110    /* Get Port attributes */
1526 #define  SLI_MGMT_GPAS     0x120    /* Get Port Statistics */
1527 #define  SLI_MGMT_RHBA     0x200    /* Register HBA */
1528 #define  SLI_MGMT_RHAT     0x201    /* Register HBA attributes */
1529 #define  SLI_MGMT_RPRT     0x210    /* Register Port */
1530 #define  SLI_MGMT_RPA      0x211    /* Register Port attributes */
1531 #define  SLI_MGMT_DHBA     0x300    /* De-register HBA */
1532 #define  SLI_MGMT_DHAT     0x301    /* De-register HBA attributes */
1533 #define  SLI_MGMT_DPRT     0x310    /* De-register Port */
1534 #define  SLI_MGMT_DPA      0x311    /* De-register Port attributes */
1535 
1536 #define LPFC_FDMI_MAX_RETRY     3  /* Max retries for a FDMI command */
1537 
1538 /*
1539  * HBA Attribute Types
1540  */
1541 #define  RHBA_NODENAME           0x1 /* 8 byte WWNN */
1542 #define  RHBA_MANUFACTURER       0x2 /* 4 to 64 byte ASCII string */
1543 #define  RHBA_SERIAL_NUMBER      0x3 /* 4 to 64 byte ASCII string */
1544 #define  RHBA_MODEL              0x4 /* 4 to 256 byte ASCII string */
1545 #define  RHBA_MODEL_DESCRIPTION  0x5 /* 4 to 256 byte ASCII string */
1546 #define  RHBA_HARDWARE_VERSION   0x6 /* 4 to 256 byte ASCII string */
1547 #define  RHBA_DRIVER_VERSION     0x7 /* 4 to 256 byte ASCII string */
1548 #define  RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */
1549 #define  RHBA_FIRMWARE_VERSION   0x9 /* 4 to 256 byte ASCII string */
1550 #define  RHBA_OS_NAME_VERSION    0xa /* 4 to 256 byte ASCII string */
1551 #define  RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */
1552 #define  RHBA_SYM_NODENAME       0xc /* 4 to 256 byte ASCII string */
1553 #define  RHBA_VENDOR_INFO        0xd  /* 32-bit unsigned int */
1554 #define  RHBA_NUM_PORTS          0xe  /* 32-bit unsigned int */
1555 #define  RHBA_FABRIC_WWNN        0xf  /* 8 byte WWNN */
1556 #define  RHBA_BIOS_VERSION       0x10 /* 4 to 256 byte ASCII string */
1557 #define  RHBA_BIOS_STATE         0x11 /* 32-bit unsigned int */
1558 #define  RHBA_VENDOR_ID          0xe0 /* 8 byte ASCII string */
1559 
1560 /* Bit mask for all individual HBA attributes */
1561 #define LPFC_FDMI_HBA_ATTR_wwnn         0x00000001
1562 #define LPFC_FDMI_HBA_ATTR_manufacturer     0x00000002
1563 #define LPFC_FDMI_HBA_ATTR_sn           0x00000004
1564 #define LPFC_FDMI_HBA_ATTR_model        0x00000008
1565 #define LPFC_FDMI_HBA_ATTR_description      0x00000010
1566 #define LPFC_FDMI_HBA_ATTR_hdw_ver      0x00000020
1567 #define LPFC_FDMI_HBA_ATTR_drvr_ver     0x00000040
1568 #define LPFC_FDMI_HBA_ATTR_rom_ver      0x00000080
1569 #define LPFC_FDMI_HBA_ATTR_fmw_ver      0x00000100
1570 #define LPFC_FDMI_HBA_ATTR_os_ver       0x00000200
1571 #define LPFC_FDMI_HBA_ATTR_ct_len       0x00000400
1572 #define LPFC_FDMI_HBA_ATTR_symbolic_name    0x00000800
1573 #define LPFC_FDMI_HBA_ATTR_vendor_info      0x00001000 /* Not used */
1574 #define LPFC_FDMI_HBA_ATTR_num_ports        0x00002000
1575 #define LPFC_FDMI_HBA_ATTR_fabric_wwnn      0x00004000
1576 #define LPFC_FDMI_HBA_ATTR_bios_ver     0x00008000
1577 #define LPFC_FDMI_HBA_ATTR_bios_state       0x00010000 /* Not used */
1578 #define LPFC_FDMI_HBA_ATTR_vendor_id        0x00020000
1579 
1580 /* Bit mask for FDMI-1 defined HBA attributes */
1581 #define LPFC_FDMI1_HBA_ATTR         0x000007ff
1582 
1583 /* Bit mask for FDMI-2 defined HBA attributes */
1584 /* Skip vendor_info and bios_state */
1585 #define LPFC_FDMI2_HBA_ATTR         0x0002efff
1586 
1587 /*
1588  * Port Attribute Types
1589  */
1590 #define  RPRT_SUPPORTED_FC4_TYPES     0x1 /* 32 byte binary array */
1591 #define  RPRT_SUPPORTED_SPEED         0x2 /* 32-bit unsigned int */
1592 #define  RPRT_PORT_SPEED              0x3 /* 32-bit unsigned int */
1593 #define  RPRT_MAX_FRAME_SIZE          0x4 /* 32-bit unsigned int */
1594 #define  RPRT_OS_DEVICE_NAME          0x5 /* 4 to 256 byte ASCII string */
1595 #define  RPRT_HOST_NAME               0x6 /* 4 to 256 byte ASCII string */
1596 #define  RPRT_NODENAME                0x7 /* 8 byte WWNN */
1597 #define  RPRT_PORTNAME                0x8 /* 8 byte WWPN */
1598 #define  RPRT_SYM_PORTNAME            0x9 /* 4 to 256 byte ASCII string */
1599 #define  RPRT_PORT_TYPE               0xa /* 32-bit unsigned int */
1600 #define  RPRT_SUPPORTED_CLASS         0xb /* 32-bit unsigned int */
1601 #define  RPRT_FABRICNAME              0xc /* 8 byte Fabric WWPN */
1602 #define  RPRT_ACTIVE_FC4_TYPES        0xd /* 32 byte binary array */
1603 #define  RPRT_PORT_STATE              0x101 /* 32-bit unsigned int */
1604 #define  RPRT_DISC_PORT               0x102 /* 32-bit unsigned int */
1605 #define  RPRT_PORT_ID                 0x103 /* 32-bit unsigned int */
1606 #define  RPRT_VENDOR_MI               0xf047 /* vendor ascii string */
1607 #define  RPRT_SMART_SERVICE           0xf100 /* 4 to 256 byte ASCII string */
1608 #define  RPRT_SMART_GUID              0xf101 /* 8 byte WWNN + 8 byte WWPN */
1609 #define  RPRT_SMART_VERSION           0xf102 /* 4 to 256 byte ASCII string */
1610 #define  RPRT_SMART_MODEL             0xf103 /* 4 to 256 byte ASCII string */
1611 #define  RPRT_SMART_PORT_INFO         0xf104 /* 32-bit unsigned int */
1612 #define  RPRT_SMART_QOS               0xf105 /* 32-bit unsigned int */
1613 #define  RPRT_SMART_SECURITY          0xf106 /* 32-bit unsigned int */
1614 
1615 /* Bit mask for all individual PORT attributes */
1616 #define LPFC_FDMI_PORT_ATTR_fc4type     0x00000001
1617 #define LPFC_FDMI_PORT_ATTR_support_speed   0x00000002
1618 #define LPFC_FDMI_PORT_ATTR_speed       0x00000004
1619 #define LPFC_FDMI_PORT_ATTR_max_frame       0x00000008
1620 #define LPFC_FDMI_PORT_ATTR_os_devname      0x00000010
1621 #define LPFC_FDMI_PORT_ATTR_host_name       0x00000020
1622 #define LPFC_FDMI_PORT_ATTR_wwnn        0x00000040
1623 #define LPFC_FDMI_PORT_ATTR_wwpn        0x00000080
1624 #define LPFC_FDMI_PORT_ATTR_symbolic_name   0x00000100
1625 #define LPFC_FDMI_PORT_ATTR_port_type       0x00000200
1626 #define LPFC_FDMI_PORT_ATTR_class       0x00000400
1627 #define LPFC_FDMI_PORT_ATTR_fabric_wwpn     0x00000800
1628 #define LPFC_FDMI_PORT_ATTR_port_state      0x00001000
1629 #define LPFC_FDMI_PORT_ATTR_active_fc4type  0x00002000
1630 #define LPFC_FDMI_PORT_ATTR_num_disc        0x00004000
1631 #define LPFC_FDMI_PORT_ATTR_nportid     0x00008000
1632 #define LPFC_FDMI_SMART_ATTR_service        0x00010000 /* Vendor specific */
1633 #define LPFC_FDMI_SMART_ATTR_guid       0x00020000 /* Vendor specific */
1634 #define LPFC_FDMI_SMART_ATTR_version        0x00040000 /* Vendor specific */
1635 #define LPFC_FDMI_SMART_ATTR_model      0x00080000 /* Vendor specific */
1636 #define LPFC_FDMI_SMART_ATTR_port_info      0x00100000 /* Vendor specific */
1637 #define LPFC_FDMI_SMART_ATTR_qos        0x00200000 /* Vendor specific */
1638 #define LPFC_FDMI_SMART_ATTR_security       0x00400000 /* Vendor specific */
1639 #define LPFC_FDMI_VENDOR_ATTR_mi        0x00800000 /* Vendor specific */
1640 
1641 /* Bit mask for FDMI-1 defined PORT attributes */
1642 #define LPFC_FDMI1_PORT_ATTR            0x0000003f
1643 
1644 /* Bit mask for FDMI-2 defined PORT attributes */
1645 #define LPFC_FDMI2_PORT_ATTR            0x0000ffff
1646 
1647 /* Bit mask for Smart SAN defined PORT attributes */
1648 #define LPFC_FDMI2_SMART_ATTR           0x007fffff
1649 
1650 /* Defines for PORT port state attribute */
1651 #define LPFC_FDMI_PORTSTATE_UNKNOWN 1
1652 #define LPFC_FDMI_PORTSTATE_ONLINE  2
1653 
1654 /* Defines for PORT port type attribute */
1655 #define LPFC_FDMI_PORTTYPE_UNKNOWN  0
1656 #define LPFC_FDMI_PORTTYPE_NPORT    1
1657 #define LPFC_FDMI_PORTTYPE_NLPORT   2
1658 
1659 /*
1660  *  Begin HBA configuration parameters.
1661  *  The PCI configuration register BAR assignments are:
1662  *  BAR0, offset 0x10 - SLIM base memory address
1663  *  BAR1, offset 0x14 - SLIM base memory high address
1664  *  BAR2, offset 0x18 - REGISTER base memory address
1665  *  BAR3, offset 0x1c - REGISTER base memory high address
1666  *  BAR4, offset 0x20 - BIU I/O registers
1667  *  BAR5, offset 0x24 - REGISTER base io high address
1668  */
1669 
1670 /* Number of rings currently used and available. */
1671 #define MAX_SLI3_CONFIGURED_RINGS     3
1672 #define MAX_SLI3_RINGS                4
1673 
1674 /* IOCB / Mailbox is owned by FireFly */
1675 #define OWN_CHIP        1
1676 
1677 /* IOCB / Mailbox is owned by Host */
1678 #define OWN_HOST        0
1679 
1680 /* Number of 4-byte words in an IOCB. */
1681 #define IOCB_WORD_SZ    8
1682 
1683 /* network headers for Dfctl field */
1684 #define FC_NET_HDR      0x20
1685 
1686 /* Start FireFly Register definitions */
1687 #define PCI_VENDOR_ID_EMULEX        0x10df
1688 #define PCI_DEVICE_ID_FIREFLY       0x1ae5
1689 #define PCI_DEVICE_ID_PROTEUS_VF    0xe100
1690 #define PCI_DEVICE_ID_BALIUS        0xe131
1691 #define PCI_DEVICE_ID_PROTEUS_PF    0xe180
1692 #define PCI_DEVICE_ID_LANCER_FC     0xe200
1693 #define PCI_DEVICE_ID_LANCER_FC_VF  0xe208
1694 #define PCI_DEVICE_ID_LANCER_FCOE   0xe260
1695 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
1696 #define PCI_DEVICE_ID_LANCER_G6_FC  0xe300
1697 #define PCI_DEVICE_ID_LANCER_G7_FC  0xf400
1698 #define PCI_DEVICE_ID_LANCER_G7P_FC 0xf500
1699 #define PCI_DEVICE_ID_SAT_SMB       0xf011
1700 #define PCI_DEVICE_ID_SAT_MID       0xf015
1701 #define PCI_DEVICE_ID_RFLY          0xf095
1702 #define PCI_DEVICE_ID_PFLY          0xf098
1703 #define PCI_DEVICE_ID_LP101         0xf0a1
1704 #define PCI_DEVICE_ID_TFLY          0xf0a5
1705 #define PCI_DEVICE_ID_BSMB          0xf0d1
1706 #define PCI_DEVICE_ID_BMID          0xf0d5
1707 #define PCI_DEVICE_ID_ZSMB          0xf0e1
1708 #define PCI_DEVICE_ID_ZMID          0xf0e5
1709 #define PCI_DEVICE_ID_NEPTUNE       0xf0f5
1710 #define PCI_DEVICE_ID_NEPTUNE_SCSP  0xf0f6
1711 #define PCI_DEVICE_ID_NEPTUNE_DCSP  0xf0f7
1712 #define PCI_DEVICE_ID_SAT           0xf100
1713 #define PCI_DEVICE_ID_SAT_SCSP      0xf111
1714 #define PCI_DEVICE_ID_SAT_DCSP      0xf112
1715 #define PCI_DEVICE_ID_FALCON        0xf180
1716 #define PCI_DEVICE_ID_SUPERFLY      0xf700
1717 #define PCI_DEVICE_ID_DRAGONFLY     0xf800
1718 #define PCI_DEVICE_ID_CENTAUR       0xf900
1719 #define PCI_DEVICE_ID_PEGASUS       0xf980
1720 #define PCI_DEVICE_ID_THOR          0xfa00
1721 #define PCI_DEVICE_ID_VIPER         0xfb00
1722 #define PCI_DEVICE_ID_LP10000S      0xfc00
1723 #define PCI_DEVICE_ID_LP11000S      0xfc10
1724 #define PCI_DEVICE_ID_LPE11000S     0xfc20
1725 #define PCI_DEVICE_ID_SAT_S         0xfc40
1726 #define PCI_DEVICE_ID_PROTEUS_S     0xfc50
1727 #define PCI_DEVICE_ID_HELIOS        0xfd00
1728 #define PCI_DEVICE_ID_HELIOS_SCSP   0xfd11
1729 #define PCI_DEVICE_ID_HELIOS_DCSP   0xfd12
1730 #define PCI_DEVICE_ID_ZEPHYR        0xfe00
1731 #define PCI_DEVICE_ID_ZEPHYR_SCSP   0xfe11
1732 #define PCI_DEVICE_ID_ZEPHYR_DCSP   0xfe12
1733 #define PCI_VENDOR_ID_SERVERENGINE  0x19a2
1734 #define PCI_DEVICE_ID_TIGERSHARK    0x0704
1735 #define PCI_DEVICE_ID_TOMCAT        0x0714
1736 #define PCI_DEVICE_ID_SKYHAWK       0x0724
1737 #define PCI_DEVICE_ID_SKYHAWK_VF    0x072c
1738 #define PCI_VENDOR_ID_ATTO          0x117c
1739 #define PCI_DEVICE_ID_CLRY_16XE     0x0064
1740 #define PCI_DEVICE_ID_CLRY_161E     0x0063
1741 #define PCI_DEVICE_ID_CLRY_162E     0x0064
1742 #define PCI_DEVICE_ID_CLRY_164E     0x0065
1743 #define PCI_DEVICE_ID_CLRY_16XP     0x0094
1744 #define PCI_DEVICE_ID_CLRY_161P     0x00a0
1745 #define PCI_DEVICE_ID_CLRY_162P     0x0094
1746 #define PCI_DEVICE_ID_CLRY_164P     0x00a1
1747 #define PCI_DEVICE_ID_CLRY_32XE     0x0094
1748 #define PCI_DEVICE_ID_CLRY_321E     0x00a2
1749 #define PCI_DEVICE_ID_CLRY_322E     0x00a3
1750 #define PCI_DEVICE_ID_CLRY_324E     0x00ac
1751 #define PCI_DEVICE_ID_CLRY_32XP     0x00bb
1752 #define PCI_DEVICE_ID_CLRY_321P     0x00bc
1753 #define PCI_DEVICE_ID_CLRY_322P     0x00bd
1754 #define PCI_DEVICE_ID_CLRY_324P     0x00be
1755 #define PCI_DEVICE_ID_TLFC_2        0x0064
1756 #define PCI_DEVICE_ID_TLFC_2XX2     0x4064
1757 #define PCI_DEVICE_ID_TLFC_3        0x0094
1758 #define PCI_DEVICE_ID_TLFC_3162     0x40a6
1759 #define PCI_DEVICE_ID_TLFC_3322     0x40a7
1760 
1761 #define JEDEC_ID_ADDRESS            0x0080001c
1762 #define FIREFLY_JEDEC_ID            0x1ACC
1763 #define SUPERFLY_JEDEC_ID           0x0020
1764 #define DRAGONFLY_JEDEC_ID          0x0021
1765 #define DRAGONFLY_V2_JEDEC_ID       0x0025
1766 #define CENTAUR_2G_JEDEC_ID         0x0026
1767 #define CENTAUR_1G_JEDEC_ID         0x0028
1768 #define PEGASUS_ORION_JEDEC_ID      0x0036
1769 #define PEGASUS_JEDEC_ID            0x0038
1770 #define THOR_JEDEC_ID               0x0012
1771 #define HELIOS_JEDEC_ID             0x0364
1772 #define ZEPHYR_JEDEC_ID             0x0577
1773 #define VIPER_JEDEC_ID              0x4838
1774 #define SATURN_JEDEC_ID             0x1004
1775 
1776 #define JEDEC_ID_MASK               0x0FFFF000
1777 #define JEDEC_ID_SHIFT              12
1778 #define FC_JEDEC_ID(id)             ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1779 
1780 typedef struct {        /* FireFly BIU registers */
1781     uint32_t hostAtt;   /* See definitions for Host Attention
1782                    register */
1783     uint32_t chipAtt;   /* See definitions for Chip Attention
1784                    register */
1785     uint32_t hostStatus;    /* See definitions for Host Status register */
1786     uint32_t hostControl;   /* See definitions for Host Control register */
1787     uint32_t buiConfig; /* See definitions for BIU configuration
1788                    register */
1789 } FF_REGS;
1790 
1791 /* IO Register size in bytes */
1792 #define FF_REG_AREA_SIZE       256
1793 
1794 /* Host Attention Register */
1795 
1796 #define HA_REG_OFFSET  0    /* Byte offset from register base address */
1797 
1798 #define HA_R0RE_REQ    0x00000001   /* Bit  0 */
1799 #define HA_R0CE_RSP    0x00000002   /* Bit  1 */
1800 #define HA_R0ATT       0x00000008   /* Bit  3 */
1801 #define HA_R1RE_REQ    0x00000010   /* Bit  4 */
1802 #define HA_R1CE_RSP    0x00000020   /* Bit  5 */
1803 #define HA_R1ATT       0x00000080   /* Bit  7 */
1804 #define HA_R2RE_REQ    0x00000100   /* Bit  8 */
1805 #define HA_R2CE_RSP    0x00000200   /* Bit  9 */
1806 #define HA_R2ATT       0x00000800   /* Bit 11 */
1807 #define HA_R3RE_REQ    0x00001000   /* Bit 12 */
1808 #define HA_R3CE_RSP    0x00002000   /* Bit 13 */
1809 #define HA_R3ATT       0x00008000   /* Bit 15 */
1810 #define HA_LATT        0x20000000   /* Bit 29 */
1811 #define HA_MBATT       0x40000000   /* Bit 30 */
1812 #define HA_ERATT       0x80000000   /* Bit 31 */
1813 
1814 #define HA_RXRE_REQ    0x00000001   /* Bit  0 */
1815 #define HA_RXCE_RSP    0x00000002   /* Bit  1 */
1816 #define HA_RXATT       0x00000008   /* Bit  3 */
1817 #define HA_RXMASK      0x0000000f
1818 
1819 #define HA_R0_CLR_MSK   (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1820 #define HA_R1_CLR_MSK   (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1821 #define HA_R2_CLR_MSK   (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1822 #define HA_R3_CLR_MSK   (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1823 
1824 #define HA_R0_POS   3
1825 #define HA_R1_POS   7
1826 #define HA_R2_POS   11
1827 #define HA_R3_POS   15
1828 #define HA_LE_POS   29
1829 #define HA_MB_POS   30
1830 #define HA_ER_POS   31
1831 /* Chip Attention Register */
1832 
1833 #define CA_REG_OFFSET  4    /* Byte offset from register base address */
1834 
1835 #define CA_R0CE_REQ    0x00000001   /* Bit  0 */
1836 #define CA_R0RE_RSP    0x00000002   /* Bit  1 */
1837 #define CA_R0ATT       0x00000008   /* Bit  3 */
1838 #define CA_R1CE_REQ    0x00000010   /* Bit  4 */
1839 #define CA_R1RE_RSP    0x00000020   /* Bit  5 */
1840 #define CA_R1ATT       0x00000080   /* Bit  7 */
1841 #define CA_R2CE_REQ    0x00000100   /* Bit  8 */
1842 #define CA_R2RE_RSP    0x00000200   /* Bit  9 */
1843 #define CA_R2ATT       0x00000800   /* Bit 11 */
1844 #define CA_R3CE_REQ    0x00001000   /* Bit 12 */
1845 #define CA_R3RE_RSP    0x00002000   /* Bit 13 */
1846 #define CA_R3ATT       0x00008000   /* Bit 15 */
1847 #define CA_MBATT       0x40000000   /* Bit 30 */
1848 
1849 /* Host Status Register */
1850 
1851 #define HS_REG_OFFSET  8    /* Byte offset from register base address */
1852 
1853 #define HS_MBRDY       0x00400000   /* Bit 22 */
1854 #define HS_FFRDY       0x00800000   /* Bit 23 */
1855 #define HS_FFER8       0x01000000   /* Bit 24 */
1856 #define HS_FFER7       0x02000000   /* Bit 25 */
1857 #define HS_FFER6       0x04000000   /* Bit 26 */
1858 #define HS_FFER5       0x08000000   /* Bit 27 */
1859 #define HS_FFER4       0x10000000   /* Bit 28 */
1860 #define HS_FFER3       0x20000000   /* Bit 29 */
1861 #define HS_FFER2       0x40000000   /* Bit 30 */
1862 #define HS_FFER1       0x80000000   /* Bit 31 */
1863 #define HS_CRIT_TEMP   0x00000100   /* Bit 8  */
1864 #define HS_FFERM       0xFF000100   /* Mask for error bits 31:24 and 8 */
1865 #define UNPLUG_ERR     0x00000001   /* Indicate pci hot unplug */
1866 /* Host Control Register */
1867 
1868 #define HC_REG_OFFSET  12   /* Byte offset from register base address */
1869 
1870 #define HC_MBINT_ENA   0x00000001   /* Bit  0 */
1871 #define HC_R0INT_ENA   0x00000002   /* Bit  1 */
1872 #define HC_R1INT_ENA   0x00000004   /* Bit  2 */
1873 #define HC_R2INT_ENA   0x00000008   /* Bit  3 */
1874 #define HC_R3INT_ENA   0x00000010   /* Bit  4 */
1875 #define HC_INITHBI     0x02000000   /* Bit 25 */
1876 #define HC_INITMB      0x04000000   /* Bit 26 */
1877 #define HC_INITFF      0x08000000   /* Bit 27 */
1878 #define HC_LAINT_ENA   0x20000000   /* Bit 29 */
1879 #define HC_ERINT_ENA   0x80000000   /* Bit 31 */
1880 
1881 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1882 #define MSIX_DFLT_ID    0
1883 #define MSIX_RNG0_ID    0
1884 #define MSIX_RNG1_ID    1
1885 #define MSIX_RNG2_ID    2
1886 #define MSIX_RNG3_ID    3
1887 
1888 #define MSIX_LINK_ID    4
1889 #define MSIX_MBOX_ID    5
1890 
1891 #define MSIX_SPARE0_ID  6
1892 #define MSIX_SPARE1_ID  7
1893 
1894 /* Mailbox Commands */
1895 #define MBX_SHUTDOWN        0x00    /* terminate testing */
1896 #define MBX_LOAD_SM         0x01
1897 #define MBX_READ_NV         0x02
1898 #define MBX_WRITE_NV        0x03
1899 #define MBX_RUN_BIU_DIAG    0x04
1900 #define MBX_INIT_LINK       0x05
1901 #define MBX_DOWN_LINK       0x06
1902 #define MBX_CONFIG_LINK     0x07
1903 #define MBX_CONFIG_RING     0x09
1904 #define MBX_RESET_RING      0x0A
1905 #define MBX_READ_CONFIG     0x0B
1906 #define MBX_READ_RCONFIG    0x0C
1907 #define MBX_READ_SPARM      0x0D
1908 #define MBX_READ_STATUS     0x0E
1909 #define MBX_READ_RPI        0x0F
1910 #define MBX_READ_XRI        0x10
1911 #define MBX_READ_REV        0x11
1912 #define MBX_READ_LNK_STAT   0x12
1913 #define MBX_REG_LOGIN       0x13
1914 #define MBX_UNREG_LOGIN     0x14
1915 #define MBX_CLEAR_LA        0x16
1916 #define MBX_DUMP_MEMORY     0x17
1917 #define MBX_DUMP_CONTEXT    0x18
1918 #define MBX_RUN_DIAGS       0x19
1919 #define MBX_RESTART         0x1A
1920 #define MBX_UPDATE_CFG      0x1B
1921 #define MBX_DOWN_LOAD       0x1C
1922 #define MBX_DEL_LD_ENTRY    0x1D
1923 #define MBX_RUN_PROGRAM     0x1E
1924 #define MBX_SET_MASK        0x20
1925 #define MBX_SET_VARIABLE    0x21
1926 #define MBX_UNREG_D_ID      0x23
1927 #define MBX_KILL_BOARD      0x24
1928 #define MBX_CONFIG_FARP     0x25
1929 #define MBX_BEACON          0x2A
1930 #define MBX_CONFIG_MSI      0x30
1931 #define MBX_HEARTBEAT       0x31
1932 #define MBX_WRITE_VPARMS    0x32
1933 #define MBX_ASYNCEVT_ENABLE 0x33
1934 #define MBX_READ_EVENT_LOG_STATUS 0x37
1935 #define MBX_READ_EVENT_LOG  0x38
1936 #define MBX_WRITE_EVENT_LOG 0x39
1937 
1938 #define MBX_PORT_CAPABILITIES 0x3B
1939 #define MBX_PORT_IOV_CONTROL 0x3C
1940 
1941 #define MBX_CONFIG_HBQ      0x7C
1942 #define MBX_LOAD_AREA       0x81
1943 #define MBX_RUN_BIU_DIAG64  0x84
1944 #define MBX_CONFIG_PORT     0x88
1945 #define MBX_READ_SPARM64    0x8D
1946 #define MBX_READ_RPI64      0x8F
1947 #define MBX_REG_LOGIN64     0x93
1948 #define MBX_READ_TOPOLOGY   0x95
1949 #define MBX_REG_VPI     0x96
1950 #define MBX_UNREG_VPI       0x97
1951 
1952 #define MBX_WRITE_WWN       0x98
1953 #define MBX_SET_DEBUG       0x99
1954 #define MBX_LOAD_EXP_ROM    0x9C
1955 #define MBX_SLI4_CONFIG     0x9B
1956 #define MBX_SLI4_REQ_FTRS   0x9D
1957 #define MBX_MAX_CMDS        0x9E
1958 #define MBX_RESUME_RPI      0x9E
1959 #define MBX_SLI2_CMD_MASK   0x80
1960 #define MBX_REG_VFI         0x9F
1961 #define MBX_REG_FCFI        0xA0
1962 #define MBX_UNREG_VFI       0xA1
1963 #define MBX_UNREG_FCFI      0xA2
1964 #define MBX_INIT_VFI        0xA3
1965 #define MBX_INIT_VPI        0xA4
1966 #define MBX_ACCESS_VDATA    0xA5
1967 #define MBX_REG_FCFI_MRQ    0xAF
1968 
1969 #define MBX_AUTH_PORT       0xF8
1970 #define MBX_SECURITY_MGMT   0xF9
1971 
1972 /* IOCB Commands */
1973 
1974 #define CMD_RCV_SEQUENCE_CX     0x01
1975 #define CMD_XMIT_SEQUENCE_CR    0x02
1976 #define CMD_XMIT_SEQUENCE_CX    0x03
1977 #define CMD_XMIT_BCAST_CN       0x04
1978 #define CMD_XMIT_BCAST_CX       0x05
1979 #define CMD_QUE_RING_BUF_CN     0x06
1980 #define CMD_QUE_XRI_BUF_CX      0x07
1981 #define CMD_IOCB_CONTINUE_CN    0x08
1982 #define CMD_RET_XRI_BUF_CX      0x09
1983 #define CMD_ELS_REQUEST_CR      0x0A
1984 #define CMD_ELS_REQUEST_CX      0x0B
1985 #define CMD_RCV_ELS_REQ_CX      0x0D
1986 #define CMD_ABORT_XRI_CN        0x0E
1987 #define CMD_ABORT_XRI_CX        0x0F
1988 #define CMD_CLOSE_XRI_CN        0x10
1989 #define CMD_CLOSE_XRI_CX        0x11
1990 #define CMD_CREATE_XRI_CR       0x12
1991 #define CMD_CREATE_XRI_CX       0x13
1992 #define CMD_GET_RPI_CN          0x14
1993 #define CMD_XMIT_ELS_RSP_CX     0x15
1994 #define CMD_GET_RPI_CR          0x16
1995 #define CMD_XRI_ABORTED_CX      0x17
1996 #define CMD_FCP_IWRITE_CR       0x18
1997 #define CMD_FCP_IWRITE_CX       0x19
1998 #define CMD_FCP_IREAD_CR        0x1A
1999 #define CMD_FCP_IREAD_CX        0x1B
2000 #define CMD_FCP_ICMND_CR        0x1C
2001 #define CMD_FCP_ICMND_CX        0x1D
2002 #define CMD_FCP_TSEND_CX        0x1F
2003 #define CMD_FCP_TRECEIVE_CX     0x21
2004 #define CMD_FCP_TRSP_CX         0x23
2005 #define CMD_FCP_AUTO_TRSP_CX    0x29
2006 
2007 #define CMD_ADAPTER_MSG         0x20
2008 #define CMD_ADAPTER_DUMP        0x22
2009 
2010 /*  SLI_2 IOCB Command Set */
2011 
2012 #define CMD_ASYNC_STATUS        0x7C
2013 #define CMD_RCV_SEQUENCE64_CX   0x81
2014 #define CMD_XMIT_SEQUENCE64_CR  0x82
2015 #define CMD_XMIT_SEQUENCE64_CX  0x83
2016 #define CMD_XMIT_BCAST64_CN     0x84
2017 #define CMD_XMIT_BCAST64_CX     0x85
2018 #define CMD_QUE_RING_BUF64_CN   0x86
2019 #define CMD_QUE_XRI_BUF64_CX    0x87
2020 #define CMD_IOCB_CONTINUE64_CN  0x88
2021 #define CMD_RET_XRI_BUF64_CX    0x89
2022 #define CMD_ELS_REQUEST64_CR    0x8A
2023 #define CMD_ELS_REQUEST64_CX    0x8B
2024 #define CMD_ABORT_MXRI64_CN     0x8C
2025 #define CMD_RCV_ELS_REQ64_CX    0x8D
2026 #define CMD_XMIT_ELS_RSP64_CX   0x95
2027 #define CMD_XMIT_BLS_RSP64_CX   0x97
2028 #define CMD_FCP_IWRITE64_CR     0x98
2029 #define CMD_FCP_IWRITE64_CX     0x99
2030 #define CMD_FCP_IREAD64_CR      0x9A
2031 #define CMD_FCP_IREAD64_CX      0x9B
2032 #define CMD_FCP_ICMND64_CR      0x9C
2033 #define CMD_FCP_ICMND64_CX      0x9D
2034 #define CMD_FCP_TSEND64_CX      0x9F
2035 #define CMD_FCP_TRECEIVE64_CX   0xA1
2036 #define CMD_FCP_TRSP64_CX       0xA3
2037 
2038 #define CMD_QUE_XRI64_CX    0xB3
2039 #define CMD_IOCB_RCV_SEQ64_CX   0xB5
2040 #define CMD_IOCB_RCV_ELS64_CX   0xB7
2041 #define CMD_IOCB_RET_XRI64_CX   0xB9
2042 #define CMD_IOCB_RCV_CONT64_CX  0xBB
2043 
2044 #define CMD_GEN_REQUEST64_CR    0xC2
2045 #define CMD_GEN_REQUEST64_CX    0xC3
2046 
2047 /* Unhandled SLI-3 Commands */
2048 #define CMD_IOCB_XMIT_MSEQ64_CR     0xB0
2049 #define CMD_IOCB_XMIT_MSEQ64_CX     0xB1
2050 #define CMD_IOCB_RCV_SEQ_LIST64_CX  0xC1
2051 #define CMD_IOCB_RCV_ELS_LIST64_CX  0xCD
2052 #define CMD_IOCB_CLOSE_EXTENDED_CN  0xB6
2053 #define CMD_IOCB_ABORT_EXTENDED_CN  0xBA
2054 #define CMD_IOCB_RET_HBQE64_CN      0xCA
2055 #define CMD_IOCB_FCP_IBIDIR64_CR    0xAC
2056 #define CMD_IOCB_FCP_IBIDIR64_CX    0xAD
2057 #define CMD_IOCB_FCP_ITASKMGT64_CX  0xAF
2058 #define CMD_IOCB_LOGENTRY_CN        0x94
2059 #define CMD_IOCB_LOGENTRY_ASYNC_CN  0x96
2060 
2061 /* Data Security SLI Commands */
2062 #define DSSCMD_IWRITE64_CR      0xF8
2063 #define DSSCMD_IWRITE64_CX      0xF9
2064 #define DSSCMD_IREAD64_CR       0xFA
2065 #define DSSCMD_IREAD64_CX       0xFB
2066 
2067 #define CMD_MAX_IOCB_CMD        0xFB
2068 #define CMD_IOCB_MASK           0xff
2069 
2070 #define MAX_MSG_DATA            28  /* max msg data in CMD_ADAPTER_MSG
2071                        iocb */
2072 #define LPFC_MAX_ADPTMSG         32 /* max msg data */
2073 /*
2074  *  Define Status
2075  */
2076 #define MBX_SUCCESS                 0
2077 #define MBXERR_NUM_RINGS            1
2078 #define MBXERR_NUM_IOCBS            2
2079 #define MBXERR_IOCBS_EXCEEDED       3
2080 #define MBXERR_BAD_RING_NUMBER      4
2081 #define MBXERR_MASK_ENTRIES_RANGE   5
2082 #define MBXERR_MASKS_EXCEEDED       6
2083 #define MBXERR_BAD_PROFILE          7
2084 #define MBXERR_BAD_DEF_CLASS        8
2085 #define MBXERR_BAD_MAX_RESPONDER    9
2086 #define MBXERR_BAD_MAX_ORIGINATOR   10
2087 #define MBXERR_RPI_REGISTERED       11
2088 #define MBXERR_RPI_FULL             12
2089 #define MBXERR_NO_RESOURCES         13
2090 #define MBXERR_BAD_RCV_LENGTH       14
2091 #define MBXERR_DMA_ERROR            15
2092 #define MBXERR_ERROR                16
2093 #define MBXERR_LINK_DOWN            0x33
2094 #define MBXERR_SEC_NO_PERMISSION    0xF02
2095 #define MBX_NOT_FINISHED            255
2096 
2097 #define MBX_BUSY                   0xffffff /* Attempted cmd to busy Mailbox */
2098 #define MBX_TIMEOUT                0xfffffe /* time-out expired waiting for */
2099 
2100 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
2101 
2102 /*
2103  * return code Fail
2104  */
2105 #define FAILURE 1
2106 
2107 /*
2108  *    Begin Structure Definitions for Mailbox Commands
2109  */
2110 
2111 typedef struct {
2112 #ifdef __BIG_ENDIAN_BITFIELD
2113     uint8_t tval;
2114     uint8_t tmask;
2115     uint8_t rval;
2116     uint8_t rmask;
2117 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2118     uint8_t rmask;
2119     uint8_t rval;
2120     uint8_t tmask;
2121     uint8_t tval;
2122 #endif
2123 } RR_REG;
2124 
2125 struct ulp_bde {
2126     uint32_t bdeAddress;
2127 #ifdef __BIG_ENDIAN_BITFIELD
2128     uint32_t bdeReserved:4;
2129     uint32_t bdeAddrHigh:4;
2130     uint32_t bdeSize:24;
2131 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2132     uint32_t bdeSize:24;
2133     uint32_t bdeAddrHigh:4;
2134     uint32_t bdeReserved:4;
2135 #endif
2136 };
2137 
2138 typedef struct ULP_BDL {    /* SLI-2 */
2139 #ifdef __BIG_ENDIAN_BITFIELD
2140     uint32_t bdeFlags:8;    /* BDL Flags */
2141     uint32_t bdeSize:24;    /* Size of BDL array in host memory (bytes) */
2142 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2143     uint32_t bdeSize:24;    /* Size of BDL array in host memory (bytes) */
2144     uint32_t bdeFlags:8;    /* BDL Flags */
2145 #endif
2146 
2147     uint32_t addrLow;   /* Address 0:31 */
2148     uint32_t addrHigh;  /* Address 32:63 */
2149     uint32_t ulpIoTag32;    /* Can be used for 32 bit I/O Tag */
2150 } ULP_BDL;
2151 
2152 /*
2153  * BlockGuard Definitions
2154  */
2155 
2156 enum lpfc_protgrp_type {
2157     LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors                  */
2158     LPFC_PG_TYPE_NO_DIF,      /* no DIF data pointed to by prot grp       */
2159     LPFC_PG_TYPE_EMBD_DIF,    /* DIF is embedded (inline) with data       */
2160     LPFC_PG_TYPE_DIF_BUF      /* DIF has its own scatter/gather list      */
2161 };
2162 
2163 /* PDE Descriptors */
2164 #define LPFC_PDE5_DESCRIPTOR        0x85
2165 #define LPFC_PDE6_DESCRIPTOR        0x86
2166 #define LPFC_PDE7_DESCRIPTOR        0x87
2167 
2168 /* BlockGuard Opcodes */
2169 #define BG_OP_IN_NODIF_OUT_CRC      0x0
2170 #define BG_OP_IN_CRC_OUT_NODIF      0x1
2171 #define BG_OP_IN_NODIF_OUT_CSUM     0x2
2172 #define BG_OP_IN_CSUM_OUT_NODIF     0x3
2173 #define BG_OP_IN_CRC_OUT_CRC        0x4
2174 #define BG_OP_IN_CSUM_OUT_CSUM      0x5
2175 #define BG_OP_IN_CRC_OUT_CSUM       0x6
2176 #define BG_OP_IN_CSUM_OUT_CRC       0x7
2177 #define BG_OP_RAW_MODE          0x8
2178 
2179 struct lpfc_pde5 {
2180     uint32_t word0;
2181 #define pde5_type_SHIFT     24
2182 #define pde5_type_MASK      0x000000ff
2183 #define pde5_type_WORD      word0
2184 #define pde5_rsvd0_SHIFT    0
2185 #define pde5_rsvd0_MASK     0x00ffffff
2186 #define pde5_rsvd0_WORD     word0
2187     uint32_t reftag;    /* Reference Tag Value          */
2188     uint32_t reftagtr;  /* Reference Tag Translation Value  */
2189 };
2190 
2191 struct lpfc_pde6 {
2192     uint32_t word0;
2193 #define pde6_type_SHIFT     24
2194 #define pde6_type_MASK      0x000000ff
2195 #define pde6_type_WORD      word0
2196 #define pde6_rsvd0_SHIFT    0
2197 #define pde6_rsvd0_MASK     0x00ffffff
2198 #define pde6_rsvd0_WORD     word0
2199     uint32_t word1;
2200 #define pde6_rsvd1_SHIFT    26
2201 #define pde6_rsvd1_MASK     0x0000003f
2202 #define pde6_rsvd1_WORD     word1
2203 #define pde6_na_SHIFT       25
2204 #define pde6_na_MASK        0x00000001
2205 #define pde6_na_WORD        word1
2206 #define pde6_rsvd2_SHIFT    16
2207 #define pde6_rsvd2_MASK     0x000001FF
2208 #define pde6_rsvd2_WORD     word1
2209 #define pde6_apptagtr_SHIFT 0
2210 #define pde6_apptagtr_MASK  0x0000ffff
2211 #define pde6_apptagtr_WORD  word1
2212     uint32_t word2;
2213 #define pde6_optx_SHIFT     28
2214 #define pde6_optx_MASK      0x0000000f
2215 #define pde6_optx_WORD      word2
2216 #define pde6_oprx_SHIFT     24
2217 #define pde6_oprx_MASK      0x0000000f
2218 #define pde6_oprx_WORD      word2
2219 #define pde6_nr_SHIFT       23
2220 #define pde6_nr_MASK        0x00000001
2221 #define pde6_nr_WORD        word2
2222 #define pde6_ce_SHIFT       22
2223 #define pde6_ce_MASK        0x00000001
2224 #define pde6_ce_WORD        word2
2225 #define pde6_re_SHIFT       21
2226 #define pde6_re_MASK        0x00000001
2227 #define pde6_re_WORD        word2
2228 #define pde6_ae_SHIFT       20
2229 #define pde6_ae_MASK        0x00000001
2230 #define pde6_ae_WORD        word2
2231 #define pde6_ai_SHIFT       19
2232 #define pde6_ai_MASK        0x00000001
2233 #define pde6_ai_WORD        word2
2234 #define pde6_bs_SHIFT       16
2235 #define pde6_bs_MASK        0x00000007
2236 #define pde6_bs_WORD        word2
2237 #define pde6_apptagval_SHIFT    0
2238 #define pde6_apptagval_MASK 0x0000ffff
2239 #define pde6_apptagval_WORD word2
2240 };
2241 
2242 struct lpfc_pde7 {
2243     uint32_t word0;
2244 #define pde7_type_SHIFT     24
2245 #define pde7_type_MASK      0x000000ff
2246 #define pde7_type_WORD      word0
2247 #define pde7_rsvd0_SHIFT    0
2248 #define pde7_rsvd0_MASK     0x00ffffff
2249 #define pde7_rsvd0_WORD     word0
2250     uint32_t addrHigh;
2251     uint32_t addrLow;
2252 };
2253 
2254 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
2255 
2256 typedef struct {
2257 #ifdef __BIG_ENDIAN_BITFIELD
2258     uint32_t rsvd2:25;
2259     uint32_t acknowledgment:1;
2260     uint32_t version:1;
2261     uint32_t erase_or_prog:1;
2262     uint32_t update_flash:1;
2263     uint32_t update_ram:1;
2264     uint32_t method:1;
2265     uint32_t load_cmplt:1;
2266 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2267     uint32_t load_cmplt:1;
2268     uint32_t method:1;
2269     uint32_t update_ram:1;
2270     uint32_t update_flash:1;
2271     uint32_t erase_or_prog:1;
2272     uint32_t version:1;
2273     uint32_t acknowledgment:1;
2274     uint32_t rsvd2:25;
2275 #endif
2276 
2277     uint32_t dl_to_adr_low;
2278     uint32_t dl_to_adr_high;
2279     uint32_t dl_len;
2280     union {
2281         uint32_t dl_from_mbx_offset;
2282         struct ulp_bde dl_from_bde;
2283         struct ulp_bde64 dl_from_bde64;
2284     } un;
2285 
2286 } LOAD_SM_VAR;
2287 
2288 /* Structure for MB Command READ_NVPARM (02) */
2289 
2290 typedef struct {
2291     uint32_t rsvd1[3];  /* Read as all one's */
2292     uint32_t rsvd2;     /* Read as all zero's */
2293     uint32_t portname[2];   /* N_PORT name */
2294     uint32_t nodename[2];   /* NODE name */
2295 
2296 #ifdef __BIG_ENDIAN_BITFIELD
2297     uint32_t pref_DID:24;
2298     uint32_t hardAL_PA:8;
2299 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2300     uint32_t hardAL_PA:8;
2301     uint32_t pref_DID:24;
2302 #endif
2303 
2304     uint32_t rsvd3[21]; /* Read as all one's */
2305 } READ_NV_VAR;
2306 
2307 /* Structure for MB Command WRITE_NVPARMS (03) */
2308 
2309 typedef struct {
2310     uint32_t rsvd1[3];  /* Must be all one's */
2311     uint32_t rsvd2;     /* Must be all zero's */
2312     uint32_t portname[2];   /* N_PORT name */
2313     uint32_t nodename[2];   /* NODE name */
2314 
2315 #ifdef __BIG_ENDIAN_BITFIELD
2316     uint32_t pref_DID:24;
2317     uint32_t hardAL_PA:8;
2318 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2319     uint32_t hardAL_PA:8;
2320     uint32_t pref_DID:24;
2321 #endif
2322 
2323     uint32_t rsvd3[21]; /* Must be all one's */
2324 } WRITE_NV_VAR;
2325 
2326 /* Structure for MB Command RUN_BIU_DIAG (04) */
2327 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
2328 
2329 typedef struct {
2330     uint32_t rsvd1;
2331     union {
2332         struct {
2333             struct ulp_bde xmit_bde;
2334             struct ulp_bde rcv_bde;
2335         } s1;
2336         struct {
2337             struct ulp_bde64 xmit_bde64;
2338             struct ulp_bde64 rcv_bde64;
2339         } s2;
2340     } un;
2341 } BIU_DIAG_VAR;
2342 
2343 /* Structure for MB command READ_EVENT_LOG (0x38) */
2344 struct READ_EVENT_LOG_VAR {
2345     uint32_t word1;
2346 #define lpfc_event_log_SHIFT    29
2347 #define lpfc_event_log_MASK 0x00000001
2348 #define lpfc_event_log_WORD word1
2349 #define USE_MAILBOX_RESPONSE    1
2350     uint32_t offset;
2351     struct ulp_bde64 rcv_bde64;
2352 };
2353 
2354 /* Structure for MB Command INIT_LINK (05) */
2355 
2356 typedef struct {
2357 #ifdef __BIG_ENDIAN_BITFIELD
2358     uint32_t rsvd1:24;
2359     uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2360 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2361     uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2362     uint32_t rsvd1:24;
2363 #endif
2364 
2365 #ifdef __BIG_ENDIAN_BITFIELD
2366     uint8_t fabric_AL_PA;   /* If using a Fabric Assigned AL_PA */
2367     uint8_t rsvd2;
2368     uint16_t link_flags;
2369 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2370     uint16_t link_flags;
2371     uint8_t rsvd2;
2372     uint8_t fabric_AL_PA;   /* If using a Fabric Assigned AL_PA */
2373 #endif
2374 
2375 #define FLAGS_TOPOLOGY_MODE_LOOP_PT  0x00 /* Attempt loop then pt-pt */
2376 #define FLAGS_LOCAL_LB               0x01 /* link_flags (=1) ENDEC loopback */
2377 #define FLAGS_TOPOLOGY_MODE_PT_PT    0x02 /* Attempt pt-pt only */
2378 #define FLAGS_TOPOLOGY_MODE_LOOP     0x04 /* Attempt loop only */
2379 #define FLAGS_TOPOLOGY_MODE_PT_LOOP  0x06 /* Attempt pt-pt then loop */
2380 #define FLAGS_UNREG_LOGIN_ALL        0x08 /* UNREG_LOGIN all on link down */
2381 #define FLAGS_LIRP_LILP              0x80 /* LIRP / LILP is disabled */
2382 
2383 #define FLAGS_TOPOLOGY_FAILOVER      0x0400 /* Bit 10 */
2384 #define FLAGS_LINK_SPEED             0x0800 /* Bit 11 */
2385 #define FLAGS_IMED_ABORT             0x04000    /* Bit 14 */
2386 
2387     uint32_t link_speed;
2388 #define LINK_SPEED_AUTO 0x0     /* Auto selection */
2389 #define LINK_SPEED_1G   0x1     /* 1 Gigabaud */
2390 #define LINK_SPEED_2G   0x2     /* 2 Gigabaud */
2391 #define LINK_SPEED_4G   0x4     /* 4 Gigabaud */
2392 #define LINK_SPEED_8G   0x8     /* 8 Gigabaud */
2393 #define LINK_SPEED_10G  0x10    /* 10 Gigabaud */
2394 #define LINK_SPEED_16G  0x11    /* 16 Gigabaud */
2395 #define LINK_SPEED_32G  0x14    /* 32 Gigabaud */
2396 #define LINK_SPEED_64G  0x17    /* 64 Gigabaud */
2397 #define LINK_SPEED_128G 0x1A    /* 128 Gigabaud */
2398 #define LINK_SPEED_256G 0x1D    /* 256 Gigabaud */
2399 
2400 } INIT_LINK_VAR;
2401 
2402 /* Structure for MB Command DOWN_LINK (06) */
2403 
2404 typedef struct {
2405     uint32_t rsvd1;
2406 } DOWN_LINK_VAR;
2407 
2408 /* Structure for MB Command CONFIG_LINK (07) */
2409 
2410 typedef struct {
2411 #ifdef __BIG_ENDIAN_BITFIELD
2412     uint32_t cr:1;
2413     uint32_t ci:1;
2414     uint32_t cr_delay:6;
2415     uint32_t cr_count:8;
2416     uint32_t rsvd1:8;
2417     uint32_t MaxBBC:8;
2418 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2419     uint32_t MaxBBC:8;
2420     uint32_t rsvd1:8;
2421     uint32_t cr_count:8;
2422     uint32_t cr_delay:6;
2423     uint32_t ci:1;
2424     uint32_t cr:1;
2425 #endif
2426 
2427     uint32_t myId;
2428     uint32_t rsvd2;
2429     uint32_t edtov;
2430     uint32_t arbtov;
2431     uint32_t ratov;
2432     uint32_t rttov;
2433     uint32_t altov;
2434     uint32_t crtov;
2435 
2436 #ifdef __BIG_ENDIAN_BITFIELD
2437     uint32_t rsvd4:19;
2438     uint32_t cscn:1;
2439     uint32_t bbscn:4;
2440     uint32_t rsvd3:8;
2441 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2442     uint32_t rsvd3:8;
2443     uint32_t bbscn:4;
2444     uint32_t cscn:1;
2445     uint32_t rsvd4:19;
2446 #endif
2447 
2448 #ifdef __BIG_ENDIAN_BITFIELD
2449     uint32_t rrq_enable:1;
2450     uint32_t rrq_immed:1;
2451     uint32_t rsvd5:29;
2452     uint32_t ack0_enable:1;
2453 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2454     uint32_t ack0_enable:1;
2455     uint32_t rsvd5:29;
2456     uint32_t rrq_immed:1;
2457     uint32_t rrq_enable:1;
2458 #endif
2459 } CONFIG_LINK;
2460 
2461 /* Structure for MB Command PART_SLIM (08)
2462  * will be removed since SLI1 is no longer supported!
2463  */
2464 typedef struct {
2465 #ifdef __BIG_ENDIAN_BITFIELD
2466     uint16_t offCiocb;
2467     uint16_t numCiocb;
2468     uint16_t offRiocb;
2469     uint16_t numRiocb;
2470 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2471     uint16_t numCiocb;
2472     uint16_t offCiocb;
2473     uint16_t numRiocb;
2474     uint16_t offRiocb;
2475 #endif
2476 } RING_DEF;
2477 
2478 typedef struct {
2479 #ifdef __BIG_ENDIAN_BITFIELD
2480     uint32_t unused1:24;
2481     uint32_t numRing:8;
2482 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2483     uint32_t numRing:8;
2484     uint32_t unused1:24;
2485 #endif
2486 
2487     RING_DEF ringdef[4];
2488     uint32_t hbainit;
2489 } PART_SLIM_VAR;
2490 
2491 /* Structure for MB Command CONFIG_RING (09) */
2492 
2493 typedef struct {
2494 #ifdef __BIG_ENDIAN_BITFIELD
2495     uint32_t unused2:6;
2496     uint32_t recvSeq:1;
2497     uint32_t recvNotify:1;
2498     uint32_t numMask:8;
2499     uint32_t profile:8;
2500     uint32_t unused1:4;
2501     uint32_t ring:4;
2502 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2503     uint32_t ring:4;
2504     uint32_t unused1:4;
2505     uint32_t profile:8;
2506     uint32_t numMask:8;
2507     uint32_t recvNotify:1;
2508     uint32_t recvSeq:1;
2509     uint32_t unused2:6;
2510 #endif
2511 
2512 #ifdef __BIG_ENDIAN_BITFIELD
2513     uint16_t maxRespXchg;
2514     uint16_t maxOrigXchg;
2515 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2516     uint16_t maxOrigXchg;
2517     uint16_t maxRespXchg;
2518 #endif
2519 
2520     RR_REG rrRegs[6];
2521 } CONFIG_RING_VAR;
2522 
2523 /* Structure for MB Command RESET_RING (10) */
2524 
2525 typedef struct {
2526     uint32_t ring_no;
2527 } RESET_RING_VAR;
2528 
2529 /* Structure for MB Command READ_CONFIG (11) */
2530 
2531 typedef struct {
2532 #ifdef __BIG_ENDIAN_BITFIELD
2533     uint32_t cr:1;
2534     uint32_t ci:1;
2535     uint32_t cr_delay:6;
2536     uint32_t cr_count:8;
2537     uint32_t InitBBC:8;
2538     uint32_t MaxBBC:8;
2539 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2540     uint32_t MaxBBC:8;
2541     uint32_t InitBBC:8;
2542     uint32_t cr_count:8;
2543     uint32_t cr_delay:6;
2544     uint32_t ci:1;
2545     uint32_t cr:1;
2546 #endif
2547 
2548 #ifdef __BIG_ENDIAN_BITFIELD
2549     uint32_t topology:8;
2550     uint32_t myDid:24;
2551 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2552     uint32_t myDid:24;
2553     uint32_t topology:8;
2554 #endif
2555 
2556     /* Defines for topology (defined previously) */
2557 #ifdef __BIG_ENDIAN_BITFIELD
2558     uint32_t AR:1;
2559     uint32_t IR:1;
2560     uint32_t rsvd1:29;
2561     uint32_t ack0:1;
2562 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2563     uint32_t ack0:1;
2564     uint32_t rsvd1:29;
2565     uint32_t IR:1;
2566     uint32_t AR:1;
2567 #endif
2568 
2569     uint32_t edtov;
2570     uint32_t arbtov;
2571     uint32_t ratov;
2572     uint32_t rttov;
2573     uint32_t altov;
2574     uint32_t lmt;
2575 #define LMT_RESERVED  0x000    /* Not used */
2576 #define LMT_1Gb       0x004
2577 #define LMT_2Gb       0x008
2578 #define LMT_4Gb       0x040
2579 #define LMT_8Gb       0x080
2580 #define LMT_10Gb      0x100
2581 #define LMT_16Gb      0x200
2582 #define LMT_32Gb      0x400
2583 #define LMT_64Gb      0x800
2584 #define LMT_128Gb     0x1000
2585 #define LMT_256Gb     0x2000
2586     uint32_t rsvd2;
2587     uint32_t rsvd3;
2588     uint32_t max_xri;
2589     uint32_t max_iocb;
2590     uint32_t max_rpi;
2591     uint32_t avail_xri;
2592     uint32_t avail_iocb;
2593     uint32_t avail_rpi;
2594     uint32_t max_vpi;
2595     uint32_t rsvd4;
2596     uint32_t rsvd5;
2597     uint32_t avail_vpi;
2598 } READ_CONFIG_VAR;
2599 
2600 /* Structure for MB Command READ_RCONFIG (12) */
2601 
2602 typedef struct {
2603 #ifdef __BIG_ENDIAN_BITFIELD
2604     uint32_t rsvd2:7;
2605     uint32_t recvNotify:1;
2606     uint32_t numMask:8;
2607     uint32_t profile:8;
2608     uint32_t rsvd1:4;
2609     uint32_t ring:4;
2610 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2611     uint32_t ring:4;
2612     uint32_t rsvd1:4;
2613     uint32_t profile:8;
2614     uint32_t numMask:8;
2615     uint32_t recvNotify:1;
2616     uint32_t rsvd2:7;
2617 #endif
2618 
2619 #ifdef __BIG_ENDIAN_BITFIELD
2620     uint16_t maxResp;
2621     uint16_t maxOrig;
2622 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2623     uint16_t maxOrig;
2624     uint16_t maxResp;
2625 #endif
2626 
2627     RR_REG rrRegs[6];
2628 
2629 #ifdef __BIG_ENDIAN_BITFIELD
2630     uint16_t cmdRingOffset;
2631     uint16_t cmdEntryCnt;
2632     uint16_t rspRingOffset;
2633     uint16_t rspEntryCnt;
2634     uint16_t nextCmdOffset;
2635     uint16_t rsvd3;
2636     uint16_t nextRspOffset;
2637     uint16_t rsvd4;
2638 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2639     uint16_t cmdEntryCnt;
2640     uint16_t cmdRingOffset;
2641     uint16_t rspEntryCnt;
2642     uint16_t rspRingOffset;
2643     uint16_t rsvd3;
2644     uint16_t nextCmdOffset;
2645     uint16_t rsvd4;
2646     uint16_t nextRspOffset;
2647 #endif
2648 } READ_RCONF_VAR;
2649 
2650 /* Structure for MB Command READ_SPARM (13) */
2651 /* Structure for MB Command READ_SPARM64 (0x8D) */
2652 
2653 typedef struct {
2654     uint32_t rsvd1;
2655     uint32_t rsvd2;
2656     union {
2657         struct ulp_bde sp; /* This BDE points to struct serv_parm
2658                       structure */
2659         struct ulp_bde64 sp64;
2660     } un;
2661 #ifdef __BIG_ENDIAN_BITFIELD
2662     uint16_t rsvd3;
2663     uint16_t vpi;
2664 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2665     uint16_t vpi;
2666     uint16_t rsvd3;
2667 #endif
2668 } READ_SPARM_VAR;
2669 
2670 /* Structure for MB Command READ_STATUS (14) */
2671 enum read_status_word1 {
2672     RD_ST_CC    = 0x01,
2673     RD_ST_XKB   = 0x80,
2674 };
2675 
2676 enum read_status_word17 {
2677     RD_ST_XMIT_XKB_MASK = 0x3fffff,
2678 };
2679 
2680 enum read_status_word18 {
2681     RD_ST_RCV_XKB_MASK = 0x3fffff,
2682 };
2683 
2684 typedef struct {
2685     u8 clear_counters; /* rsvd 7:1, cc 0 */
2686     u8 rsvd5;
2687     u8 rsvd6;
2688     u8 xkb; /* xkb 7, rsvd 6:0 */
2689 
2690     u32 rsvd8;
2691 
2692     uint32_t xmitByteCnt;
2693     uint32_t rcvByteCnt;
2694     uint32_t xmitFrameCnt;
2695     uint32_t rcvFrameCnt;
2696     uint32_t xmitSeqCnt;
2697     uint32_t rcvSeqCnt;
2698     uint32_t totalOrigExchanges;
2699     uint32_t totalRespExchanges;
2700     uint32_t rcvPbsyCnt;
2701     uint32_t rcvFbsyCnt;
2702 
2703     u32 drop_frame_no_rq;
2704     u32 empty_rq;
2705     u32 drop_frame_no_xri;
2706     u32 empty_xri;
2707 
2708     u32 xmit_xkb; /* rsvd 31:22, xmit_xkb 21:0 */
2709     u32 rcv_xkb; /* rsvd 31:22, rcv_xkb 21:0 */
2710 } READ_STATUS_VAR;
2711 
2712 /* Structure for MB Command READ_RPI (15) */
2713 /* Structure for MB Command READ_RPI64 (0x8F) */
2714 
2715 typedef struct {
2716 #ifdef __BIG_ENDIAN_BITFIELD
2717     uint16_t nextRpi;
2718     uint16_t reqRpi;
2719     uint32_t rsvd2:8;
2720     uint32_t DID:24;
2721 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2722     uint16_t reqRpi;
2723     uint16_t nextRpi;
2724     uint32_t DID:24;
2725     uint32_t rsvd2:8;
2726 #endif
2727 
2728     union {
2729         struct ulp_bde sp;
2730         struct ulp_bde64 sp64;
2731     } un;
2732 
2733 } READ_RPI_VAR;
2734 
2735 /* Structure for MB Command READ_XRI (16) */
2736 
2737 typedef struct {
2738 #ifdef __BIG_ENDIAN_BITFIELD
2739     uint16_t nextXri;
2740     uint16_t reqXri;
2741     uint16_t rsvd1;
2742     uint16_t rpi;
2743     uint32_t rsvd2:8;
2744     uint32_t DID:24;
2745     uint32_t rsvd3:8;
2746     uint32_t SID:24;
2747     uint32_t rsvd4;
2748     uint8_t seqId;
2749     uint8_t rsvd5;
2750     uint16_t seqCount;
2751     uint16_t oxId;
2752     uint16_t rxId;
2753     uint32_t rsvd6:30;
2754     uint32_t si:1;
2755     uint32_t exchOrig:1;
2756 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2757     uint16_t reqXri;
2758     uint16_t nextXri;
2759     uint16_t rpi;
2760     uint16_t rsvd1;
2761     uint32_t DID:24;
2762     uint32_t rsvd2:8;
2763     uint32_t SID:24;
2764     uint32_t rsvd3:8;
2765     uint32_t rsvd4;
2766     uint16_t seqCount;
2767     uint8_t rsvd5;
2768     uint8_t seqId;
2769     uint16_t rxId;
2770     uint16_t oxId;
2771     uint32_t exchOrig:1;
2772     uint32_t si:1;
2773     uint32_t rsvd6:30;
2774 #endif
2775 } READ_XRI_VAR;
2776 
2777 /* Structure for MB Command READ_REV (17) */
2778 
2779 typedef struct {
2780 #ifdef __BIG_ENDIAN_BITFIELD
2781     uint32_t cv:1;
2782     uint32_t rr:1;
2783     uint32_t rsvd2:2;
2784     uint32_t v3req:1;
2785     uint32_t v3rsp:1;
2786     uint32_t rsvd1:25;
2787     uint32_t rv:1;
2788 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2789     uint32_t rv:1;
2790     uint32_t rsvd1:25;
2791     uint32_t v3rsp:1;
2792     uint32_t v3req:1;
2793     uint32_t rsvd2:2;
2794     uint32_t rr:1;
2795     uint32_t cv:1;
2796 #endif
2797 
2798     uint32_t biuRev;
2799     uint32_t smRev;
2800     union {
2801         uint32_t smFwRev;
2802         struct {
2803 #ifdef __BIG_ENDIAN_BITFIELD
2804             uint8_t ProgType;
2805             uint8_t ProgId;
2806             uint16_t ProgVer:4;
2807             uint16_t ProgRev:4;
2808             uint16_t ProgFixLvl:2;
2809             uint16_t ProgDistType:2;
2810             uint16_t DistCnt:4;
2811 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2812             uint16_t DistCnt:4;
2813             uint16_t ProgDistType:2;
2814             uint16_t ProgFixLvl:2;
2815             uint16_t ProgRev:4;
2816             uint16_t ProgVer:4;
2817             uint8_t ProgId;
2818             uint8_t ProgType;
2819 #endif
2820 
2821         } b;
2822     } un;
2823     uint32_t endecRev;
2824 #ifdef __BIG_ENDIAN_BITFIELD
2825     uint8_t feaLevelHigh;
2826     uint8_t feaLevelLow;
2827     uint8_t fcphHigh;
2828     uint8_t fcphLow;
2829 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2830     uint8_t fcphLow;
2831     uint8_t fcphHigh;
2832     uint8_t feaLevelLow;
2833     uint8_t feaLevelHigh;
2834 #endif
2835 
2836     uint32_t postKernRev;
2837     uint32_t opFwRev;
2838     uint8_t opFwName[16];
2839     uint32_t sli1FwRev;
2840     uint8_t sli1FwName[16];
2841     uint32_t sli2FwRev;
2842     uint8_t sli2FwName[16];
2843     uint32_t sli3Feat;
2844     uint32_t RandomData[6];
2845 } READ_REV_VAR;
2846 
2847 /* Structure for MB Command READ_LINK_STAT (18) */
2848 
2849 typedef struct {
2850     uint32_t word0;
2851 
2852 #define lpfc_read_link_stat_rec_SHIFT   0
2853 #define lpfc_read_link_stat_rec_MASK   0x1
2854 #define lpfc_read_link_stat_rec_WORD   word0
2855 
2856 #define lpfc_read_link_stat_gec_SHIFT   1
2857 #define lpfc_read_link_stat_gec_MASK   0x1
2858 #define lpfc_read_link_stat_gec_WORD   word0
2859 
2860 #define lpfc_read_link_stat_w02oftow23of_SHIFT  2
2861 #define lpfc_read_link_stat_w02oftow23of_MASK   0x3FFFFF
2862 #define lpfc_read_link_stat_w02oftow23of_WORD   word0
2863 
2864 #define lpfc_read_link_stat_rsvd_SHIFT  24
2865 #define lpfc_read_link_stat_rsvd_MASK   0x1F
2866 #define lpfc_read_link_stat_rsvd_WORD   word0
2867 
2868 #define lpfc_read_link_stat_gec2_SHIFT  29
2869 #define lpfc_read_link_stat_gec2_MASK   0x1
2870 #define lpfc_read_link_stat_gec2_WORD   word0
2871 
2872 #define lpfc_read_link_stat_clrc_SHIFT  30
2873 #define lpfc_read_link_stat_clrc_MASK   0x1
2874 #define lpfc_read_link_stat_clrc_WORD   word0
2875 
2876 #define lpfc_read_link_stat_clof_SHIFT  31
2877 #define lpfc_read_link_stat_clof_MASK   0x1
2878 #define lpfc_read_link_stat_clof_WORD   word0
2879 
2880     uint32_t linkFailureCnt;
2881     uint32_t lossSyncCnt;
2882     uint32_t lossSignalCnt;
2883     uint32_t primSeqErrCnt;
2884     uint32_t invalidXmitWord;
2885     uint32_t crcCnt;
2886     uint32_t primSeqTimeout;
2887     uint32_t elasticOverrun;
2888     uint32_t arbTimeout;
2889     uint32_t advRecBufCredit;
2890     uint32_t curRecBufCredit;
2891     uint32_t advTransBufCredit;
2892     uint32_t curTransBufCredit;
2893     uint32_t recEofCount;
2894     uint32_t recEofdtiCount;
2895     uint32_t recEofniCount;
2896     uint32_t recSofcount;
2897     uint32_t rsvd1;
2898     uint32_t rsvd2;
2899     uint32_t recDrpXriCount;
2900     uint32_t fecCorrBlkCount;
2901     uint32_t fecUncorrBlkCount;
2902 } READ_LNK_VAR;
2903 
2904 /* Structure for MB Command REG_LOGIN (19) */
2905 /* Structure for MB Command REG_LOGIN64 (0x93) */
2906 
2907 typedef struct {
2908 #ifdef __BIG_ENDIAN_BITFIELD
2909     uint16_t rsvd1;
2910     uint16_t rpi;
2911     uint32_t rsvd2:8;
2912     uint32_t did:24;
2913 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2914     uint16_t rpi;
2915     uint16_t rsvd1;
2916     uint32_t did:24;
2917     uint32_t rsvd2:8;
2918 #endif
2919 
2920     union {
2921         struct ulp_bde sp;
2922         struct ulp_bde64 sp64;
2923     } un;
2924 
2925 #ifdef __BIG_ENDIAN_BITFIELD
2926     uint16_t rsvd6;
2927     uint16_t vpi;
2928 #else /* __LITTLE_ENDIAN_BITFIELD */
2929     uint16_t vpi;
2930     uint16_t rsvd6;
2931 #endif
2932 
2933 } REG_LOGIN_VAR;
2934 
2935 /* Word 30 contents for REG_LOGIN */
2936 typedef union {
2937     struct {
2938 #ifdef __BIG_ENDIAN_BITFIELD
2939         uint16_t rsvd1:12;
2940         uint16_t wd30_class:4;
2941         uint16_t xri;
2942 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2943         uint16_t xri;
2944         uint16_t wd30_class:4;
2945         uint16_t rsvd1:12;
2946 #endif
2947     } f;
2948     uint32_t word;
2949 } REG_WD30;
2950 
2951 /* Structure for MB Command UNREG_LOGIN (20) */
2952 
2953 typedef struct {
2954 #ifdef __BIG_ENDIAN_BITFIELD
2955     uint16_t rsvd1;
2956     uint16_t rpi;
2957     uint32_t rsvd2;
2958     uint32_t rsvd3;
2959     uint32_t rsvd4;
2960     uint32_t rsvd5;
2961     uint16_t rsvd6;
2962     uint16_t vpi;
2963 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2964     uint16_t rpi;
2965     uint16_t rsvd1;
2966     uint32_t rsvd2;
2967     uint32_t rsvd3;
2968     uint32_t rsvd4;
2969     uint32_t rsvd5;
2970     uint16_t vpi;
2971     uint16_t rsvd6;
2972 #endif
2973 } UNREG_LOGIN_VAR;
2974 
2975 /* Structure for MB Command REG_VPI (0x96) */
2976 typedef struct {
2977 #ifdef __BIG_ENDIAN_BITFIELD
2978     uint32_t rsvd1;
2979     uint32_t rsvd2:7;
2980     uint32_t upd:1;
2981     uint32_t sid:24;
2982     uint32_t wwn[2];
2983     uint32_t rsvd5;
2984     uint16_t vfi;
2985     uint16_t vpi;
2986 #else   /*  __LITTLE_ENDIAN */
2987     uint32_t rsvd1;
2988     uint32_t sid:24;
2989     uint32_t upd:1;
2990     uint32_t rsvd2:7;
2991     uint32_t wwn[2];
2992     uint32_t rsvd5;
2993     uint16_t vpi;
2994     uint16_t vfi;
2995 #endif
2996 } REG_VPI_VAR;
2997 
2998 /* Structure for MB Command UNREG_VPI (0x97) */
2999 typedef struct {
3000     uint32_t rsvd1;
3001 #ifdef __BIG_ENDIAN_BITFIELD
3002     uint16_t rsvd2;
3003     uint16_t sli4_vpi;
3004 #else   /*  __LITTLE_ENDIAN */
3005     uint16_t sli4_vpi;
3006     uint16_t rsvd2;
3007 #endif
3008     uint32_t rsvd3;
3009     uint32_t rsvd4;
3010     uint32_t rsvd5;
3011 #ifdef __BIG_ENDIAN_BITFIELD
3012     uint16_t rsvd6;
3013     uint16_t vpi;
3014 #else   /*  __LITTLE_ENDIAN */
3015     uint16_t vpi;
3016     uint16_t rsvd6;
3017 #endif
3018 } UNREG_VPI_VAR;
3019 
3020 /* Structure for MB Command UNREG_D_ID (0x23) */
3021 
3022 typedef struct {
3023     uint32_t did;
3024     uint32_t rsvd2;
3025     uint32_t rsvd3;
3026     uint32_t rsvd4;
3027     uint32_t rsvd5;
3028 #ifdef __BIG_ENDIAN_BITFIELD
3029     uint16_t rsvd6;
3030     uint16_t vpi;
3031 #else
3032     uint16_t vpi;
3033     uint16_t rsvd6;
3034 #endif
3035 } UNREG_D_ID_VAR;
3036 
3037 /* Structure for MB Command READ_TOPOLOGY (0x95) */
3038 struct lpfc_mbx_read_top {
3039     uint32_t eventTag;  /* Event tag */
3040     uint32_t word2;
3041 #define lpfc_mbx_read_top_fa_SHIFT      12
3042 #define lpfc_mbx_read_top_fa_MASK       0x00000001
3043 #define lpfc_mbx_read_top_fa_WORD       word2
3044 #define lpfc_mbx_read_top_mm_SHIFT      11
3045 #define lpfc_mbx_read_top_mm_MASK       0x00000001
3046 #define lpfc_mbx_read_top_mm_WORD       word2
3047 #define lpfc_mbx_read_top_pb_SHIFT      9
3048 #define lpfc_mbx_read_top_pb_MASK       0X00000001
3049 #define lpfc_mbx_read_top_pb_WORD       word2
3050 #define lpfc_mbx_read_top_il_SHIFT      8
3051 #define lpfc_mbx_read_top_il_MASK       0x00000001
3052 #define lpfc_mbx_read_top_il_WORD       word2
3053 #define lpfc_mbx_read_top_att_type_SHIFT    0
3054 #define lpfc_mbx_read_top_att_type_MASK     0x000000FF
3055 #define lpfc_mbx_read_top_att_type_WORD     word2
3056 #define LPFC_ATT_RESERVED    0x00   /* Reserved - attType */
3057 #define LPFC_ATT_LINK_UP     0x01   /* Link is up */
3058 #define LPFC_ATT_LINK_DOWN   0x02   /* Link is down */
3059 #define LPFC_ATT_UNEXP_WWPN  0x06   /* Link is down Unexpected WWWPN */
3060     uint32_t word3;
3061 #define lpfc_mbx_read_top_alpa_granted_SHIFT    24
3062 #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF
3063 #define lpfc_mbx_read_top_alpa_granted_WORD word3
3064 #define lpfc_mbx_read_top_lip_alps_SHIFT    16
3065 #define lpfc_mbx_read_top_lip_alps_MASK     0x000000FF
3066 #define lpfc_mbx_read_top_lip_alps_WORD     word3
3067 #define lpfc_mbx_read_top_lip_type_SHIFT    8
3068 #define lpfc_mbx_read_top_lip_type_MASK     0x000000FF
3069 #define lpfc_mbx_read_top_lip_type_WORD     word3
3070 #define lpfc_mbx_read_top_topology_SHIFT    0
3071 #define lpfc_mbx_read_top_topology_MASK     0x000000FF
3072 #define lpfc_mbx_read_top_topology_WORD     word3
3073 #define LPFC_TOPOLOGY_PT_PT 0x01    /* Topology is pt-pt / pt-fabric */
3074 #define LPFC_TOPOLOGY_LOOP  0x02    /* Topology is FC-AL */
3075     /* store the LILP AL_PA position map into */
3076     struct ulp_bde64 lilpBde64;
3077 #define LPFC_ALPA_MAP_SIZE  128
3078     uint32_t word7;
3079 #define lpfc_mbx_read_top_ld_lu_SHIFT       31
3080 #define lpfc_mbx_read_top_ld_lu_MASK        0x00000001
3081 #define lpfc_mbx_read_top_ld_lu_WORD        word7
3082 #define lpfc_mbx_read_top_ld_tf_SHIFT       30
3083 #define lpfc_mbx_read_top_ld_tf_MASK        0x00000001
3084 #define lpfc_mbx_read_top_ld_tf_WORD        word7
3085 #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8
3086 #define lpfc_mbx_read_top_ld_link_spd_MASK  0x000000FF
3087 #define lpfc_mbx_read_top_ld_link_spd_WORD  word7
3088 #define lpfc_mbx_read_top_ld_nl_port_SHIFT  4
3089 #define lpfc_mbx_read_top_ld_nl_port_MASK   0x0000000F
3090 #define lpfc_mbx_read_top_ld_nl_port_WORD   word7
3091 #define lpfc_mbx_read_top_ld_tx_SHIFT       2
3092 #define lpfc_mbx_read_top_ld_tx_MASK        0x00000003
3093 #define lpfc_mbx_read_top_ld_tx_WORD        word7
3094 #define lpfc_mbx_read_top_ld_rx_SHIFT       0
3095 #define lpfc_mbx_read_top_ld_rx_MASK        0x00000003
3096 #define lpfc_mbx_read_top_ld_rx_WORD        word7
3097     uint32_t word8;
3098 #define lpfc_mbx_read_top_lu_SHIFT      31
3099 #define lpfc_mbx_read_top_lu_MASK       0x00000001
3100 #define lpfc_mbx_read_top_lu_WORD       word8
3101 #define lpfc_mbx_read_top_tf_SHIFT      30
3102 #define lpfc_mbx_read_top_tf_MASK       0x00000001
3103 #define lpfc_mbx_read_top_tf_WORD       word8
3104 #define lpfc_mbx_read_top_link_spd_SHIFT    8
3105 #define lpfc_mbx_read_top_link_spd_MASK     0x000000FF
3106 #define lpfc_mbx_read_top_link_spd_WORD     word8
3107 #define lpfc_mbx_read_top_nl_port_SHIFT     4
3108 #define lpfc_mbx_read_top_nl_port_MASK      0x0000000F
3109 #define lpfc_mbx_read_top_nl_port_WORD      word8
3110 #define lpfc_mbx_read_top_tx_SHIFT      2
3111 #define lpfc_mbx_read_top_tx_MASK       0x00000003
3112 #define lpfc_mbx_read_top_tx_WORD       word8
3113 #define lpfc_mbx_read_top_rx_SHIFT      0
3114 #define lpfc_mbx_read_top_rx_MASK       0x00000003
3115 #define lpfc_mbx_read_top_rx_WORD       word8
3116 #define LPFC_LINK_SPEED_UNKNOWN 0x0
3117 #define LPFC_LINK_SPEED_1GHZ    0x04
3118 #define LPFC_LINK_SPEED_2GHZ    0x08
3119 #define LPFC_LINK_SPEED_4GHZ    0x10
3120 #define LPFC_LINK_SPEED_8GHZ    0x20
3121 #define LPFC_LINK_SPEED_10GHZ   0x40
3122 #define LPFC_LINK_SPEED_16GHZ   0x80
3123 #define LPFC_LINK_SPEED_32GHZ   0x90
3124 #define LPFC_LINK_SPEED_64GHZ   0xA0
3125 #define LPFC_LINK_SPEED_128GHZ  0xB0
3126 #define LPFC_LINK_SPEED_256GHZ  0xC0
3127 };
3128 
3129 /* Structure for MB Command CLEAR_LA (22) */
3130 
3131 typedef struct {
3132     uint32_t eventTag;  /* Event tag */
3133     uint32_t rsvd1;
3134 } CLEAR_LA_VAR;
3135 
3136 /* Structure for MB Command DUMP */
3137 
3138 typedef struct {
3139 #ifdef __BIG_ENDIAN_BITFIELD
3140     uint32_t rsvd:25;
3141     uint32_t ra:1;
3142     uint32_t co:1;
3143     uint32_t cv:1;
3144     uint32_t type:4;
3145     uint32_t entry_index:16;
3146     uint32_t region_id:16;
3147 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3148     uint32_t type:4;
3149     uint32_t cv:1;
3150     uint32_t co:1;
3151     uint32_t ra:1;
3152     uint32_t rsvd:25;
3153     uint32_t region_id:16;
3154     uint32_t entry_index:16;
3155 #endif
3156 
3157     uint32_t sli4_length;
3158     uint32_t word_cnt;
3159     uint32_t resp_offset;
3160 } DUMP_VAR;
3161 
3162 #define  DMP_MEM_REG             0x1
3163 #define  DMP_NV_PARAMS           0x2
3164 #define  DMP_LMSD                0x3 /* Link Module Serial Data */
3165 #define  DMP_WELL_KNOWN          0x4
3166 
3167 #define  DMP_REGION_VPD          0xe
3168 #define  DMP_VPD_SIZE            0x400  /* maximum amount of VPD */
3169 #define  DMP_RSP_OFFSET          0x14   /* word 5 contains first word of rsp */
3170 #define  DMP_RSP_SIZE            0x6C   /* maximum of 27 words of rsp data */
3171 
3172 #define  DMP_REGION_VPORT    0x16   /* VPort info region */
3173 #define  DMP_VPORT_REGION_SIZE   0x200
3174 #define  DMP_MBOX_OFFSET_WORD    0x5
3175 
3176 #define  DMP_REGION_23       0x17   /* fcoe param  and port state region */
3177 #define  DMP_RGN23_SIZE      0x400
3178 
3179 #define  WAKE_UP_PARMS_REGION_ID    4
3180 #define  WAKE_UP_PARMS_WORD_SIZE   15
3181 
3182 struct vport_rec {
3183     uint8_t wwpn[8];
3184     uint8_t wwnn[8];
3185 };
3186 
3187 #define VPORT_INFO_SIG 0x32324752
3188 #define VPORT_INFO_REV_MASK 0xff
3189 #define VPORT_INFO_REV 0x1
3190 #define MAX_STATIC_VPORT_COUNT 16
3191 struct static_vport_info {
3192     uint32_t        signature;
3193     uint32_t        rev;
3194     struct vport_rec    vport_list[MAX_STATIC_VPORT_COUNT];
3195     uint32_t        resvd[66];
3196 };
3197 
3198 /* Option rom version structure */
3199 struct prog_id {
3200 #ifdef __BIG_ENDIAN_BITFIELD
3201     uint8_t  type;
3202     uint8_t  id;
3203     uint32_t ver:4;  /* Major Version */
3204     uint32_t rev:4;  /* Revision */
3205     uint32_t lev:2;  /* Level */
3206     uint32_t dist:2; /* Dist Type */
3207     uint32_t num:4;  /* number after dist type */
3208 #else /*  __LITTLE_ENDIAN_BITFIELD */
3209     uint32_t num:4;  /* number after dist type */
3210     uint32_t dist:2; /* Dist Type */
3211     uint32_t lev:2;  /* Level */
3212     uint32_t rev:4;  /* Revision */
3213     uint32_t ver:4;  /* Major Version */
3214     uint8_t  id;
3215     uint8_t  type;
3216 #endif
3217 };
3218 
3219 /* Structure for MB Command UPDATE_CFG (0x1B) */
3220 
3221 struct update_cfg_var {
3222 #ifdef __BIG_ENDIAN_BITFIELD
3223     uint32_t rsvd2:16;
3224     uint32_t type:8;
3225     uint32_t rsvd:1;
3226     uint32_t ra:1;
3227     uint32_t co:1;
3228     uint32_t cv:1;
3229     uint32_t req:4;
3230     uint32_t entry_length:16;
3231     uint32_t region_id:16;
3232 #else  /*  __LITTLE_ENDIAN_BITFIELD */
3233     uint32_t req:4;
3234     uint32_t cv:1;
3235     uint32_t co:1;
3236     uint32_t ra:1;
3237     uint32_t rsvd:1;
3238     uint32_t type:8;
3239     uint32_t rsvd2:16;
3240     uint32_t region_id:16;
3241     uint32_t entry_length:16;
3242 #endif
3243 
3244     uint32_t resp_info;
3245     uint32_t byte_cnt;
3246     uint32_t data_offset;
3247 };
3248 
3249 struct hbq_mask {
3250 #ifdef __BIG_ENDIAN_BITFIELD
3251     uint8_t tmatch;
3252     uint8_t tmask;
3253     uint8_t rctlmatch;
3254     uint8_t rctlmask;
3255 #else   /*  __LITTLE_ENDIAN */
3256     uint8_t rctlmask;
3257     uint8_t rctlmatch;
3258     uint8_t tmask;
3259     uint8_t tmatch;
3260 #endif
3261 };
3262 
3263 
3264 /* Structure for MB Command CONFIG_HBQ (7c) */
3265 
3266 struct config_hbq_var {
3267 #ifdef __BIG_ENDIAN_BITFIELD
3268     uint32_t rsvd1      :7;
3269     uint32_t recvNotify :1;     /* Receive Notification */
3270     uint32_t numMask    :8;     /* # Mask Entries       */
3271     uint32_t profile    :8;     /* Selection Profile    */
3272     uint32_t rsvd2      :8;
3273 #else   /*  __LITTLE_ENDIAN */
3274     uint32_t rsvd2      :8;
3275     uint32_t profile    :8;     /* Selection Profile    */
3276     uint32_t numMask    :8;     /* # Mask Entries       */
3277     uint32_t recvNotify :1;     /* Receive Notification */
3278     uint32_t rsvd1      :7;
3279 #endif
3280 
3281 #ifdef __BIG_ENDIAN_BITFIELD
3282     uint32_t hbqId      :16;
3283     uint32_t rsvd3      :12;
3284     uint32_t ringMask   :4;
3285 #else   /*  __LITTLE_ENDIAN */
3286     uint32_t ringMask   :4;
3287     uint32_t rsvd3      :12;
3288     uint32_t hbqId      :16;
3289 #endif
3290 
3291 #ifdef __BIG_ENDIAN_BITFIELD
3292     uint32_t entry_count :16;
3293     uint32_t rsvd4        :8;
3294     uint32_t headerLen    :8;
3295 #else   /*  __LITTLE_ENDIAN */
3296     uint32_t headerLen    :8;
3297     uint32_t rsvd4        :8;
3298     uint32_t entry_count :16;
3299 #endif
3300 
3301     uint32_t hbqaddrLow;
3302     uint32_t hbqaddrHigh;
3303 
3304 #ifdef __BIG_ENDIAN_BITFIELD
3305     uint32_t rsvd5      :31;
3306     uint32_t logEntry   :1;
3307 #else   /*  __LITTLE_ENDIAN */
3308     uint32_t logEntry   :1;
3309     uint32_t rsvd5      :31;
3310 #endif
3311 
3312     uint32_t rsvd6;    /* w7 */
3313     uint32_t rsvd7;    /* w8 */
3314     uint32_t rsvd8;    /* w9 */
3315 
3316     struct hbq_mask hbqMasks[6];
3317 
3318 
3319     union {
3320         uint32_t allprofiles[12];
3321 
3322         struct {
3323             #ifdef __BIG_ENDIAN_BITFIELD
3324                 uint32_t    seqlenoff   :16;
3325                 uint32_t    maxlen      :16;
3326             #else   /*  __LITTLE_ENDIAN */
3327                 uint32_t    maxlen      :16;
3328                 uint32_t    seqlenoff   :16;
3329             #endif
3330             #ifdef __BIG_ENDIAN_BITFIELD
3331                 uint32_t    rsvd1       :28;
3332                 uint32_t    seqlenbcnt  :4;
3333             #else   /*  __LITTLE_ENDIAN */
3334                 uint32_t    seqlenbcnt  :4;
3335                 uint32_t    rsvd1       :28;
3336             #endif
3337             uint32_t rsvd[10];
3338         } profile2;
3339 
3340         struct {
3341             #ifdef __BIG_ENDIAN_BITFIELD
3342                 uint32_t    seqlenoff   :16;
3343                 uint32_t    maxlen      :16;
3344             #else   /*  __LITTLE_ENDIAN */
3345                 uint32_t    maxlen      :16;
3346                 uint32_t    seqlenoff   :16;
3347             #endif
3348             #ifdef __BIG_ENDIAN_BITFIELD
3349                 uint32_t    cmdcodeoff  :28;
3350                 uint32_t    rsvd1       :12;
3351                 uint32_t    seqlenbcnt  :4;
3352             #else   /*  __LITTLE_ENDIAN */
3353                 uint32_t    seqlenbcnt  :4;
3354                 uint32_t    rsvd1       :12;
3355                 uint32_t    cmdcodeoff  :28;
3356             #endif
3357             uint32_t cmdmatch[8];
3358 
3359             uint32_t rsvd[2];
3360         } profile3;
3361 
3362         struct {
3363             #ifdef __BIG_ENDIAN_BITFIELD
3364                 uint32_t    seqlenoff   :16;
3365                 uint32_t    maxlen      :16;
3366             #else   /*  __LITTLE_ENDIAN */
3367                 uint32_t    maxlen      :16;
3368                 uint32_t    seqlenoff   :16;
3369             #endif
3370             #ifdef __BIG_ENDIAN_BITFIELD
3371                 uint32_t    cmdcodeoff  :28;
3372                 uint32_t    rsvd1       :12;
3373                 uint32_t    seqlenbcnt  :4;
3374             #else   /*  __LITTLE_ENDIAN */
3375                 uint32_t    seqlenbcnt  :4;
3376                 uint32_t    rsvd1       :12;
3377                 uint32_t    cmdcodeoff  :28;
3378             #endif
3379             uint32_t cmdmatch[8];
3380 
3381             uint32_t rsvd[2];
3382         } profile5;
3383 
3384     } profiles;
3385 
3386 };
3387 
3388 
3389 
3390 /* Structure for MB Command CONFIG_PORT (0x88) */
3391 typedef struct {
3392 #ifdef __BIG_ENDIAN_BITFIELD
3393     uint32_t cBE       :  1;
3394     uint32_t cET       :  1;
3395     uint32_t cHpcb     :  1;
3396     uint32_t cMA       :  1;
3397     uint32_t sli_mode  :  4;
3398     uint32_t pcbLen    : 24;       /* bit 23:0  of memory based port
3399                     * config block */
3400 #else   /*  __LITTLE_ENDIAN */
3401     uint32_t pcbLen    : 24;       /* bit 23:0  of memory based port
3402                     * config block */
3403     uint32_t sli_mode  :  4;
3404     uint32_t cMA       :  1;
3405     uint32_t cHpcb     :  1;
3406     uint32_t cET       :  1;
3407     uint32_t cBE       :  1;
3408 #endif
3409 
3410     uint32_t pcbLow;       /* bit 31:0  of memory based port config block */
3411     uint32_t pcbHigh;      /* bit 63:32 of memory based port config block */
3412     uint32_t hbainit[5];
3413 #ifdef __BIG_ENDIAN_BITFIELD
3414     uint32_t hps       :  1; /* bit 31 word9 Host Pointer in slim */
3415     uint32_t rsvd      : 31; /* least significant 31 bits of word 9 */
3416 #else   /*  __LITTLE_ENDIAN */
3417     uint32_t rsvd      : 31; /* least significant 31 bits of word 9 */
3418     uint32_t hps       :  1; /* bit 31 word9 Host Pointer in slim */
3419 #endif
3420 
3421 #ifdef __BIG_ENDIAN_BITFIELD
3422     uint32_t rsvd1     : 20;  /* Reserved                             */
3423     uint32_t casabt    :  1;  /* Configure async abts status notice   */
3424     uint32_t rsvd2     :  2;  /* Reserved                             */
3425     uint32_t cbg       :  1;  /* Configure BlockGuard                 */
3426     uint32_t cmv       :  1;  /* Configure Max VPIs                   */
3427     uint32_t ccrp      :  1;  /* Config Command Ring Polling          */
3428     uint32_t csah      :  1;  /* Configure Synchronous Abort Handling */
3429     uint32_t chbs      :  1;  /* Cofigure Host Backing store          */
3430     uint32_t cinb      :  1;  /* Enable Interrupt Notification Block  */
3431     uint32_t cerbm     :  1;  /* Configure Enhanced Receive Buf Mgmt  */
3432     uint32_t cmx       :  1;  /* Configure Max XRIs                   */
3433     uint32_t cmr       :  1;  /* Configure Max RPIs                   */
3434 #else   /*  __LITTLE_ENDIAN */
3435     uint32_t cmr       :  1;  /* Configure Max RPIs                   */
3436     uint32_t cmx       :  1;  /* Configure Max XRIs                   */
3437     uint32_t cerbm     :  1;  /* Configure Enhanced Receive Buf Mgmt  */
3438     uint32_t cinb      :  1;  /* Enable Interrupt Notification Block  */
3439     uint32_t chbs      :  1;  /* Cofigure Host Backing store          */
3440     uint32_t csah      :  1;  /* Configure Synchronous Abort Handling */
3441     uint32_t ccrp      :  1;  /* Config Command Ring Polling          */
3442     uint32_t cmv       :  1;  /* Configure Max VPIs                   */
3443     uint32_t cbg       :  1;  /* Configure BlockGuard                 */
3444     uint32_t rsvd2     :  2;  /* Reserved                             */
3445     uint32_t casabt    :  1;  /* Configure async abts status notice   */
3446     uint32_t rsvd1     : 20;  /* Reserved                             */
3447 #endif
3448 #ifdef __BIG_ENDIAN_BITFIELD
3449     uint32_t rsvd3     : 20;  /* Reserved                             */
3450     uint32_t gasabt    :  1;  /* Grant async abts status notice       */
3451     uint32_t rsvd4     :  2;  /* Reserved                             */
3452     uint32_t gbg       :  1;  /* Grant BlockGuard                     */
3453     uint32_t gmv       :  1;  /* Grant Max VPIs                       */
3454     uint32_t gcrp      :  1;  /* Grant Command Ring Polling           */
3455     uint32_t gsah      :  1;  /* Grant Synchronous Abort Handling     */
3456     uint32_t ghbs      :  1;  /* Grant Host Backing Store             */
3457     uint32_t ginb      :  1;  /* Grant Interrupt Notification Block   */
3458     uint32_t gerbm     :  1;  /* Grant ERBM Request                   */
3459     uint32_t gmx       :  1;  /* Grant Max XRIs                       */
3460     uint32_t gmr       :  1;  /* Grant Max RPIs                       */
3461 #else   /*  __LITTLE_ENDIAN */
3462     uint32_t gmr       :  1;  /* Grant Max RPIs                       */
3463     uint32_t gmx       :  1;  /* Grant Max XRIs                       */
3464     uint32_t gerbm     :  1;  /* Grant ERBM Request                   */
3465     uint32_t ginb      :  1;  /* Grant Interrupt Notification Block   */
3466     uint32_t ghbs      :  1;  /* Grant Host Backing Store             */
3467     uint32_t gsah      :  1;  /* Grant Synchronous Abort Handling     */
3468     uint32_t gcrp      :  1;  /* Grant Command Ring Polling           */
3469     uint32_t gmv       :  1;  /* Grant Max VPIs                       */
3470     uint32_t gbg       :  1;  /* Grant BlockGuard                     */
3471     uint32_t rsvd4     :  2;  /* Reserved                             */
3472     uint32_t gasabt    :  1;  /* Grant async abts status notice       */
3473     uint32_t rsvd3     : 20;  /* Reserved                             */
3474 #endif
3475 
3476 #ifdef __BIG_ENDIAN_BITFIELD
3477     uint32_t max_rpi   : 16;  /* Max RPIs Port should configure       */
3478     uint32_t max_xri   : 16;  /* Max XRIs Port should configure       */
3479 #else   /*  __LITTLE_ENDIAN */
3480     uint32_t max_xri   : 16;  /* Max XRIs Port should configure       */
3481     uint32_t max_rpi   : 16;  /* Max RPIs Port should configure       */
3482 #endif
3483 
3484 #ifdef __BIG_ENDIAN_BITFIELD
3485     uint32_t max_hbq   : 16;  /* Max HBQs Host expect to configure    */
3486     uint32_t rsvd5     : 16;  /* Max HBQs Host expect to configure    */
3487 #else   /*  __LITTLE_ENDIAN */
3488     uint32_t rsvd5     : 16;  /* Max HBQs Host expect to configure    */
3489     uint32_t max_hbq   : 16;  /* Max HBQs Host expect to configure    */
3490 #endif
3491 
3492     uint32_t rsvd6;           /* Reserved                             */
3493 
3494 #ifdef __BIG_ENDIAN_BITFIELD
3495     uint32_t rsvd7      : 16;
3496     uint32_t max_vpi    : 16;  /* Max number of virt N-Ports           */
3497 #else   /*  __LITTLE_ENDIAN */
3498     uint32_t max_vpi    : 16;  /* Max number of virt N-Ports           */
3499     uint32_t rsvd7      : 16;
3500 #endif
3501 
3502 } CONFIG_PORT_VAR;
3503 
3504 /* Structure for MB Command CONFIG_MSI (0x30) */
3505 struct config_msi_var {
3506 #ifdef __BIG_ENDIAN_BITFIELD
3507     uint32_t dfltMsgNum:8;  /* Default message number            */
3508     uint32_t rsvd1:11;  /* Reserved                          */
3509     uint32_t NID:5;     /* Number of secondary attention IDs */
3510     uint32_t rsvd2:5;   /* Reserved                          */
3511     uint32_t dfltPresent:1; /* Default message number present    */
3512     uint32_t addFlag:1; /* Add association flag              */
3513     uint32_t reportFlag:1;  /* Report association flag           */
3514 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3515     uint32_t reportFlag:1;  /* Report association flag           */
3516     uint32_t addFlag:1; /* Add association flag              */
3517     uint32_t dfltPresent:1; /* Default message number present    */
3518     uint32_t rsvd2:5;   /* Reserved                          */
3519     uint32_t NID:5;     /* Number of secondary attention IDs */
3520     uint32_t rsvd1:11;  /* Reserved                          */
3521     uint32_t dfltMsgNum:8;  /* Default message number            */
3522 #endif
3523     uint32_t attentionConditions[2];
3524     uint8_t  attentionId[16];
3525     uint8_t  messageNumberByHA[64];
3526     uint8_t  messageNumberByID[16];
3527     uint32_t autoClearHA[2];
3528 #ifdef __BIG_ENDIAN_BITFIELD
3529     uint32_t rsvd3:16;
3530     uint32_t autoClearID:16;
3531 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3532     uint32_t autoClearID:16;
3533     uint32_t rsvd3:16;
3534 #endif
3535     uint32_t rsvd4;
3536 };
3537 
3538 /* SLI-2 Port Control Block */
3539 
3540 /* SLIM POINTER */
3541 #define SLIMOFF 0x30        /* WORD */
3542 
3543 typedef struct _SLI2_RDSC {
3544     uint32_t cmdEntries;
3545     uint32_t cmdAddrLow;
3546     uint32_t cmdAddrHigh;
3547 
3548     uint32_t rspEntries;
3549     uint32_t rspAddrLow;
3550     uint32_t rspAddrHigh;
3551 } SLI2_RDSC;
3552 
3553 typedef struct _PCB {
3554 #ifdef __BIG_ENDIAN_BITFIELD
3555     uint32_t type:8;
3556 #define TYPE_NATIVE_SLI2       0x01
3557     uint32_t feature:8;
3558 #define FEATURE_INITIAL_SLI2   0x01
3559     uint32_t rsvd:12;
3560     uint32_t maxRing:4;
3561 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3562     uint32_t maxRing:4;
3563     uint32_t rsvd:12;
3564     uint32_t feature:8;
3565 #define FEATURE_INITIAL_SLI2   0x01
3566     uint32_t type:8;
3567 #define TYPE_NATIVE_SLI2       0x01
3568 #endif
3569 
3570     uint32_t mailBoxSize;
3571     uint32_t mbAddrLow;
3572     uint32_t mbAddrHigh;
3573 
3574     uint32_t hgpAddrLow;
3575     uint32_t hgpAddrHigh;
3576 
3577     uint32_t pgpAddrLow;
3578     uint32_t pgpAddrHigh;
3579     SLI2_RDSC rdsc[MAX_SLI3_RINGS];
3580 } PCB_t;
3581 
3582 /* NEW_FEATURE */
3583 typedef struct {
3584 #ifdef __BIG_ENDIAN_BITFIELD
3585     uint32_t rsvd0:27;
3586     uint32_t discardFarp:1;
3587     uint32_t IPEnable:1;
3588     uint32_t nodeName:1;
3589     uint32_t portName:1;
3590     uint32_t filterEnable:1;
3591 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3592     uint32_t filterEnable:1;
3593     uint32_t portName:1;
3594     uint32_t nodeName:1;
3595     uint32_t IPEnable:1;
3596     uint32_t discardFarp:1;
3597     uint32_t rsvd:27;
3598 #endif
3599 
3600     uint8_t portname[8];    /* Used to be struct lpfc_name */
3601     uint8_t nodename[8];
3602     uint32_t rsvd1;
3603     uint32_t rsvd2;
3604     uint32_t rsvd3;
3605     uint32_t IPAddress;
3606 } CONFIG_FARP_VAR;
3607 
3608 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
3609 
3610 typedef struct {
3611 #ifdef __BIG_ENDIAN_BITFIELD
3612     uint32_t rsvd:30;
3613     uint32_t ring:2;    /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3614 #else /*  __LITTLE_ENDIAN */
3615     uint32_t ring:2;    /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3616     uint32_t rsvd:30;
3617 #endif
3618 } ASYNCEVT_ENABLE_VAR;
3619 
3620 /* Union of all Mailbox Command types */
3621 #define MAILBOX_CMD_WSIZE   32
3622 #define MAILBOX_CMD_SIZE    (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
3623 /* ext_wsize times 4 bytes should not be greater than max xmit size */
3624 #define MAILBOX_EXT_WSIZE   512
3625 #define MAILBOX_EXT_SIZE    (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3626 #define MAILBOX_HBA_EXT_OFFSET  0x100
3627 /* max mbox xmit size is a page size for sysfs IO operations */
3628 #define MAILBOX_SYSFS_MAX   4096
3629 
3630 typedef union {
3631     uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
3632                             * feature/max ring number
3633                             */
3634     LOAD_SM_VAR varLdSM;        /* cmd =  1 (LOAD_SM)        */
3635     READ_NV_VAR varRDnvp;       /* cmd =  2 (READ_NVPARMS)   */
3636     WRITE_NV_VAR varWTnvp;      /* cmd =  3 (WRITE_NVPARMS)  */
3637     BIU_DIAG_VAR varBIUdiag;    /* cmd =  4 (RUN_BIU_DIAG)   */
3638     INIT_LINK_VAR varInitLnk;   /* cmd =  5 (INIT_LINK)      */
3639     DOWN_LINK_VAR varDwnLnk;    /* cmd =  6 (DOWN_LINK)      */
3640     CONFIG_LINK varCfgLnk;      /* cmd =  7 (CONFIG_LINK)    */
3641     PART_SLIM_VAR varSlim;      /* cmd =  8 (PART_SLIM)      */
3642     CONFIG_RING_VAR varCfgRing; /* cmd =  9 (CONFIG_RING)    */
3643     RESET_RING_VAR varRstRing;  /* cmd = 10 (RESET_RING)     */
3644     READ_CONFIG_VAR varRdConfig;    /* cmd = 11 (READ_CONFIG)    */
3645     READ_RCONF_VAR varRdRConfig;    /* cmd = 12 (READ_RCONFIG)   */
3646     READ_SPARM_VAR varRdSparm;  /* cmd = 13 (READ_SPARM(64)) */
3647     READ_STATUS_VAR varRdStatus;    /* cmd = 14 (READ_STATUS)    */
3648     READ_RPI_VAR varRdRPI;      /* cmd = 15 (READ_RPI(64))   */
3649     READ_XRI_VAR varRdXRI;      /* cmd = 16 (READ_XRI)       */
3650     READ_REV_VAR varRdRev;      /* cmd = 17 (READ_REV)       */
3651     READ_LNK_VAR varRdLnk;      /* cmd = 18 (READ_LNK_STAT)  */
3652     REG_LOGIN_VAR varRegLogin;  /* cmd = 19 (REG_LOGIN(64))  */
3653     UNREG_LOGIN_VAR varUnregLogin;  /* cmd = 20 (UNREG_LOGIN)    */
3654     CLEAR_LA_VAR varClearLA;    /* cmd = 22 (CLEAR_LA)       */
3655     DUMP_VAR varDmp;        /* Warm Start DUMP mbx cmd   */
3656     UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID)   */
3657     CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
3658                      * NEW_FEATURE
3659                      */
3660     struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ)  */
3661     struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
3662     CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT)  */
3663     struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
3664     REG_VPI_VAR varRegVpi;      /* cmd = 0x96 (REG_VPI) */
3665     UNREG_VPI_VAR varUnregVpi;  /* cmd = 0x97 (UNREG_VPI) */
3666     ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
3667     struct READ_EVENT_LOG_VAR varRdEventLog;    /* cmd = 0x38
3668                              * (READ_EVENT_LOG)
3669                              */
3670     struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI)     */
3671 } MAILVARIANTS;
3672 
3673 /*
3674  * SLI-2 specific structures
3675  */
3676 
3677 struct lpfc_hgp {
3678     __le32 cmdPutInx;
3679     __le32 rspGetInx;
3680 };
3681 
3682 struct lpfc_pgp {
3683     __le32 cmdGetInx;
3684     __le32 rspPutInx;
3685 };
3686 
3687 struct sli2_desc {
3688     uint32_t unused1[16];
3689     struct lpfc_hgp host[MAX_SLI3_RINGS];
3690     struct lpfc_pgp port[MAX_SLI3_RINGS];
3691 };
3692 
3693 struct sli3_desc {
3694     struct lpfc_hgp host[MAX_SLI3_RINGS];
3695     uint32_t reserved[8];
3696     uint32_t hbq_put[16];
3697 };
3698 
3699 struct sli3_pgp {
3700     struct lpfc_pgp port[MAX_SLI3_RINGS];
3701     uint32_t hbq_get[16];
3702 };
3703 
3704 union sli_var {
3705     struct sli2_desc    s2;
3706     struct sli3_desc    s3;
3707     struct sli3_pgp     s3_pgp;
3708 };
3709 
3710 typedef struct {
3711     struct_group_tagged(MAILBOX_word0, bits,
3712         union {
3713             struct {
3714 #ifdef __BIG_ENDIAN_BITFIELD
3715                 uint16_t mbxStatus;
3716                 uint8_t mbxCommand;
3717                 uint8_t mbxReserved:6;
3718                 uint8_t mbxHc:1;
3719                 uint8_t mbxOwner:1; /* Low order bit first word */
3720 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3721                 uint8_t mbxOwner:1; /* Low order bit first word */
3722                 uint8_t mbxHc:1;
3723                 uint8_t mbxReserved:6;
3724                 uint8_t mbxCommand;
3725                 uint16_t mbxStatus;
3726 #endif
3727             };
3728             u32 word0;
3729         };
3730     );
3731 
3732     MAILVARIANTS un;
3733     union sli_var us;
3734 } MAILBOX_t;
3735 
3736 /*
3737  *    Begin Structure Definitions for IOCB Commands
3738  */
3739 
3740 typedef struct {
3741 #ifdef __BIG_ENDIAN_BITFIELD
3742     uint8_t statAction;
3743     uint8_t statRsn;
3744     uint8_t statBaExp;
3745     uint8_t statLocalError;
3746 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3747     uint8_t statLocalError;
3748     uint8_t statBaExp;
3749     uint8_t statRsn;
3750     uint8_t statAction;
3751 #endif
3752     /* statRsn  P/F_RJT reason codes */
3753 #define RJT_BAD_D_ID       0x01 /* Invalid D_ID field */
3754 #define RJT_BAD_S_ID       0x02 /* Invalid S_ID field */
3755 #define RJT_UNAVAIL_TEMP   0x03 /* N_Port unavailable temp. */
3756 #define RJT_UNAVAIL_PERM   0x04 /* N_Port unavailable perm. */
3757 #define RJT_UNSUP_CLASS    0x05 /* Class not supported */
3758 #define RJT_DELIM_ERR      0x06 /* Delimiter usage error */
3759 #define RJT_UNSUP_TYPE     0x07 /* Type not supported */
3760 #define RJT_BAD_CONTROL    0x08 /* Invalid link conrtol */
3761 #define RJT_BAD_RCTL       0x09 /* R_CTL invalid */
3762 #define RJT_BAD_FCTL       0x0A /* F_CTL invalid */
3763 #define RJT_BAD_OXID       0x0B /* OX_ID invalid */
3764 #define RJT_BAD_RXID       0x0C /* RX_ID invalid */
3765 #define RJT_BAD_SEQID      0x0D /* SEQ_ID invalid */
3766 #define RJT_BAD_DFCTL      0x0E /* DF_CTL invalid */
3767 #define RJT_BAD_SEQCNT     0x0F /* SEQ_CNT invalid */
3768 #define RJT_BAD_PARM       0x10 /* Param. field invalid */
3769 #define RJT_XCHG_ERR       0x11 /* Exchange error */
3770 #define RJT_PROT_ERR       0x12 /* Protocol error */
3771 #define RJT_BAD_LENGTH     0x13 /* Invalid Length */
3772 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3773 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3774 #define RJT_TOO_MANY_SEQ   0x17 /* Excessive sequences */
3775 #define RJT_XCHG_NOT_STRT  0x18 /* Exchange not started */
3776 #define RJT_UNSUP_SEC_HDR  0x19 /* Security hdr not supported */
3777 #define RJT_UNAVAIL_PATH   0x1A /* Fabric Path not available */
3778 #define RJT_VENDOR_UNIQUE  0xFF /* Vendor unique error */
3779 
3780 #define IOERR_SUCCESS                 0x00  /* statLocalError */
3781 #define IOERR_MISSING_CONTINUE        0x01
3782 #define IOERR_SEQUENCE_TIMEOUT        0x02
3783 #define IOERR_INTERNAL_ERROR          0x03
3784 #define IOERR_INVALID_RPI             0x04
3785 #define IOERR_NO_XRI                  0x05
3786 #define IOERR_ILLEGAL_COMMAND         0x06
3787 #define IOERR_XCHG_DROPPED            0x07
3788 #define IOERR_ILLEGAL_FIELD           0x08
3789 #define IOERR_RPI_SUSPENDED           0x09
3790 #define IOERR_TOO_MANY_BUFFERS        0x0A
3791 #define IOERR_RCV_BUFFER_WAITING      0x0B
3792 #define IOERR_NO_CONNECTION           0x0C
3793 #define IOERR_TX_DMA_FAILED           0x0D
3794 #define IOERR_RX_DMA_FAILED           0x0E
3795 #define IOERR_ILLEGAL_FRAME           0x0F
3796 #define IOERR_EXTRA_DATA              0x10
3797 #define IOERR_NO_RESOURCES            0x11
3798 #define IOERR_RESERVED                0x12
3799 #define IOERR_ILLEGAL_LENGTH          0x13
3800 #define IOERR_UNSUPPORTED_FEATURE     0x14
3801 #define IOERR_ABORT_IN_PROGRESS       0x15
3802 #define IOERR_ABORT_REQUESTED         0x16
3803 #define IOERR_RECEIVE_BUFFER_TIMEOUT  0x17
3804 #define IOERR_LOOP_OPEN_FAILURE       0x18
3805 #define IOERR_RING_RESET              0x19
3806 #define IOERR_LINK_DOWN               0x1A
3807 #define IOERR_CORRUPTED_DATA          0x1B
3808 #define IOERR_CORRUPTED_RPI           0x1C
3809 #define IOERR_OUT_OF_ORDER_DATA       0x1D
3810 #define IOERR_OUT_OF_ORDER_ACK        0x1E
3811 #define IOERR_DUP_FRAME               0x1F
3812 #define IOERR_LINK_CONTROL_FRAME      0x20  /* ACK_N received */
3813 #define IOERR_BAD_HOST_ADDRESS        0x21
3814 #define IOERR_RCV_HDRBUF_WAITING      0x22
3815 #define IOERR_MISSING_HDR_BUFFER      0x23
3816 #define IOERR_MSEQ_CHAIN_CORRUPTED    0x24
3817 #define IOERR_ABORTMULT_REQUESTED     0x25
3818 #define IOERR_BUFFER_SHORTAGE         0x28
3819 #define IOERR_DEFAULT                 0x29
3820 #define IOERR_CNT                     0x2A
3821 #define IOERR_SLER_FAILURE            0x46
3822 #define IOERR_SLER_CMD_RCV_FAILURE    0x47
3823 #define IOERR_SLER_REC_RJT_ERR        0x48
3824 #define IOERR_SLER_REC_SRR_RETRY_ERR  0x49
3825 #define IOERR_SLER_SRR_RJT_ERR        0x4A
3826 #define IOERR_SLER_RRQ_RJT_ERR        0x4C
3827 #define IOERR_SLER_RRQ_RETRY_ERR      0x4D
3828 #define IOERR_SLER_ABTS_ERR           0x4E
3829 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR       0xF0
3830 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR   0xF1
3831 #define IOERR_ELXSEC_CRYPTO_ERROR       0xF2
3832 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR   0xF3
3833 #define IOERR_DRVR_MASK               0x100
3834 #define IOERR_SLI_DOWN                0x101  /* ulpStatus  - Driver defined */
3835 #define IOERR_SLI_BRESET              0x102
3836 #define IOERR_SLI_ABORTED             0x103
3837 #define IOERR_PARAM_MASK              0x1ff
3838 } PARM_ERR;
3839 
3840 typedef union {
3841     struct {
3842 #ifdef __BIG_ENDIAN_BITFIELD
3843         uint8_t Rctl;   /* R_CTL field */
3844         uint8_t Type;   /* TYPE field */
3845         uint8_t Dfctl;  /* DF_CTL field */
3846         uint8_t Fctl;   /* Bits 0-7 of IOCB word 5 */
3847 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3848         uint8_t Fctl;   /* Bits 0-7 of IOCB word 5 */
3849         uint8_t Dfctl;  /* DF_CTL field */
3850         uint8_t Type;   /* TYPE field */
3851         uint8_t Rctl;   /* R_CTL field */
3852 #endif
3853 
3854 #define BC      0x02        /* Broadcast Received  - Fctl */
3855 #define SI      0x04        /* Sequence Initiative */
3856 #define LA      0x08        /* Ignore Link Attention state */
3857 #define LS      0x80        /* Last Sequence */
3858     } hcsw;
3859     uint32_t reserved;
3860 } WORD5;
3861 
3862 /* IOCB Command template for a generic response */
3863 typedef struct {
3864     uint32_t reserved[4];
3865     PARM_ERR perr;
3866 } GENERIC_RSP;
3867 
3868 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3869 typedef struct {
3870     struct ulp_bde xrsqbde[2];
3871     uint32_t xrsqRo;    /* Starting Relative Offset */
3872     WORD5 w5;       /* Header control/status word */
3873 } XR_SEQ_FIELDS;
3874 
3875 /* IOCB Command template for ELS_REQUEST */
3876 typedef struct {
3877     struct ulp_bde elsReq;
3878     struct ulp_bde elsRsp;
3879 
3880 #ifdef __BIG_ENDIAN_BITFIELD
3881     uint32_t word4Rsvd:7;
3882     uint32_t fl:1;
3883     uint32_t myID:24;
3884     uint32_t word5Rsvd:8;
3885     uint32_t remoteID:24;
3886 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3887     uint32_t myID:24;
3888     uint32_t fl:1;
3889     uint32_t word4Rsvd:7;
3890     uint32_t remoteID:24;
3891     uint32_t word5Rsvd:8;
3892 #endif
3893 } ELS_REQUEST;
3894 
3895 /* IOCB Command template for RCV_ELS_REQ */
3896 typedef struct {
3897     struct ulp_bde elsReq[2];
3898     uint32_t parmRo;
3899 
3900 #ifdef __BIG_ENDIAN_BITFIELD
3901     uint32_t word5Rsvd:8;
3902     uint32_t remoteID:24;
3903 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3904     uint32_t remoteID:24;
3905     uint32_t word5Rsvd:8;
3906 #endif
3907 } RCV_ELS_REQ;
3908 
3909 /* IOCB Command template for ABORT / CLOSE_XRI */
3910 typedef struct {
3911     uint32_t rsvd[3];
3912     uint32_t abortType;
3913 #define ABORT_TYPE_ABTX  0x00000000
3914 #define ABORT_TYPE_ABTS  0x00000001
3915     uint32_t parm;
3916 #ifdef __BIG_ENDIAN_BITFIELD
3917     uint16_t abortContextTag; /* ulpContext from command to abort/close */
3918     uint16_t abortIoTag;    /* ulpIoTag from command to abort/close */
3919 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3920     uint16_t abortIoTag;    /* ulpIoTag from command to abort/close */
3921     uint16_t abortContextTag; /* ulpContext from command to abort/close */
3922 #endif
3923 } AC_XRI;
3924 
3925 /* IOCB Command template for ABORT_MXRI64 */
3926 typedef struct {
3927     uint32_t rsvd[3];
3928     uint32_t abortType;
3929     uint32_t parm;
3930     uint32_t iotag32;
3931 } A_MXRI64;
3932 
3933 /* IOCB Command template for GET_RPI */
3934 typedef struct {
3935     uint32_t rsvd[4];
3936     uint32_t parmRo;
3937 #ifdef __BIG_ENDIAN_BITFIELD
3938     uint32_t word5Rsvd:8;
3939     uint32_t remoteID:24;
3940 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3941     uint32_t remoteID:24;
3942     uint32_t word5Rsvd:8;
3943 #endif
3944 } GET_RPI;
3945 
3946 /* IOCB Command template for all FCP Initiator commands */
3947 typedef struct {
3948     struct ulp_bde fcpi_cmnd;   /* FCP_CMND payload descriptor */
3949     struct ulp_bde fcpi_rsp;    /* Rcv buffer */
3950     uint32_t fcpi_parm;
3951     uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3952 } FCPI_FIELDS;
3953 
3954 /* IOCB Command template for all FCP Target commands */
3955 typedef struct {
3956     struct ulp_bde fcpt_Buffer[2];  /* FCP_CMND payload descriptor */
3957     uint32_t fcpt_Offset;
3958     uint32_t fcpt_Length;   /* transfer ready for IWRITE */
3959 } FCPT_FIELDS;
3960 
3961 /* SLI-2 IOCB structure definitions */
3962 
3963 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3964 typedef struct {
3965     ULP_BDL bdl;
3966     uint32_t xrsqRo;    /* Starting Relative Offset */
3967     WORD5 w5;       /* Header control/status word */
3968 } XMT_SEQ_FIELDS64;
3969 
3970 /* This word is remote ports D_ID for XMIT_ELS_RSP64 */
3971 #define xmit_els_remoteID xrsqRo
3972 
3973 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3974 typedef struct {
3975     struct ulp_bde64 rcvBde;
3976     uint32_t rsvd1;
3977     uint32_t xrsqRo;    /* Starting Relative Offset */
3978     WORD5 w5;       /* Header control/status word */
3979 } RCV_SEQ_FIELDS64;
3980 
3981 /* IOCB Command template for ELS_REQUEST64 */
3982 typedef struct {
3983     ULP_BDL bdl;
3984 #ifdef __BIG_ENDIAN_BITFIELD
3985     uint32_t word4Rsvd:7;
3986     uint32_t fl:1;
3987     uint32_t myID:24;
3988     uint32_t word5Rsvd:8;
3989     uint32_t remoteID:24;
3990 #else   /*  __LITTLE_ENDIAN_BITFIELD */
3991     uint32_t myID:24;
3992     uint32_t fl:1;
3993     uint32_t word4Rsvd:7;
3994     uint32_t remoteID:24;
3995     uint32_t word5Rsvd:8;
3996 #endif
3997 } ELS_REQUEST64;
3998 
3999 /* IOCB Command template for GEN_REQUEST64 */
4000 typedef struct {
4001     ULP_BDL bdl;
4002     uint32_t xrsqRo;    /* Starting Relative Offset */
4003     WORD5 w5;       /* Header control/status word */
4004 } GEN_REQUEST64;
4005 
4006 /* IOCB Command template for RCV_ELS_REQ64 */
4007 typedef struct {
4008     struct ulp_bde64 elsReq;
4009     uint32_t rcvd1;
4010     uint32_t parmRo;
4011 
4012 #ifdef __BIG_ENDIAN_BITFIELD
4013     uint32_t word5Rsvd:8;
4014     uint32_t remoteID:24;
4015 #else   /*  __LITTLE_ENDIAN_BITFIELD */
4016     uint32_t remoteID:24;
4017     uint32_t word5Rsvd:8;
4018 #endif
4019 } RCV_ELS_REQ64;
4020 
4021 /* IOCB Command template for RCV_SEQ64 */
4022 struct rcv_seq64 {
4023     struct ulp_bde64 elsReq;
4024     uint32_t hbq_1;
4025     uint32_t parmRo;
4026 #ifdef __BIG_ENDIAN_BITFIELD
4027     uint32_t rctl:8;
4028     uint32_t type:8;
4029     uint32_t dfctl:8;
4030     uint32_t ls:1;
4031     uint32_t fs:1;
4032     uint32_t rsvd2:3;
4033     uint32_t si:1;
4034     uint32_t bc:1;
4035     uint32_t rsvd3:1;
4036 #else   /*  __LITTLE_ENDIAN_BITFIELD */
4037     uint32_t rsvd3:1;
4038     uint32_t bc:1;
4039     uint32_t si:1;
4040     uint32_t rsvd2:3;
4041     uint32_t fs:1;
4042     uint32_t ls:1;
4043     uint32_t dfctl:8;
4044     uint32_t type:8;
4045     uint32_t rctl:8;
4046 #endif
4047 };
4048 
4049 /* IOCB Command template for all 64 bit FCP Initiator commands */
4050 typedef struct {
4051     ULP_BDL bdl;
4052     uint32_t fcpi_parm;
4053     uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
4054 } FCPI_FIELDS64;
4055 
4056 /* IOCB Command template for all 64 bit FCP Target commands */
4057 typedef struct {
4058     ULP_BDL bdl;
4059     uint32_t fcpt_Offset;
4060     uint32_t fcpt_Length;   /* transfer ready for IWRITE */
4061 } FCPT_FIELDS64;
4062 
4063 /* IOCB Command template for Async Status iocb commands */
4064 typedef struct {
4065     uint32_t rsvd[4];
4066     uint32_t param;
4067 #ifdef __BIG_ENDIAN_BITFIELD
4068     uint16_t evt_code;      /* High order bits word 5 */
4069     uint16_t sub_ctxt_tag;      /* Low  order bits word 5 */
4070 #else   /*  __LITTLE_ENDIAN_BITFIELD */
4071     uint16_t sub_ctxt_tag;      /* High order bits word 5 */
4072     uint16_t evt_code;      /* Low  order bits word 5 */
4073 #endif
4074 } ASYNCSTAT_FIELDS;
4075 #define ASYNC_TEMP_WARN     0x100
4076 #define ASYNC_TEMP_SAFE     0x101
4077 #define ASYNC_STATUS_CN     0x102
4078 
4079 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
4080    or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
4081 
4082 struct rcv_sli3 {
4083 #ifdef __BIG_ENDIAN_BITFIELD
4084     uint16_t ox_id;
4085     uint16_t seq_cnt;
4086 
4087     uint16_t vpi;
4088     uint16_t word9Rsvd;
4089 #else  /*  __LITTLE_ENDIAN */
4090     uint16_t seq_cnt;
4091     uint16_t ox_id;
4092 
4093     uint16_t word9Rsvd;
4094     uint16_t vpi;
4095 #endif
4096     uint32_t word10Rsvd;
4097     uint32_t acc_len;      /* accumulated length */
4098     struct ulp_bde64 bde2;
4099 };
4100 
4101 /* Structure used for a single HBQ entry */
4102 struct lpfc_hbq_entry {
4103     struct ulp_bde64 bde;
4104     uint32_t buffer_tag;
4105 };
4106 
4107 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */
4108 typedef struct {
4109     struct lpfc_hbq_entry   buff;
4110     uint32_t                rsvd;
4111     uint32_t        rsvd1;
4112 } QUE_XRI64_CX_FIELDS;
4113 
4114 struct que_xri64cx_ext_fields {
4115     uint32_t    iotag64_low;
4116     uint32_t    iotag64_high;
4117     uint32_t    ebde_count;
4118     uint32_t    rsvd;
4119     struct lpfc_hbq_entry   buff[5];
4120 };
4121 
4122 struct sli3_bg_fields {
4123     uint32_t filler[6]; /* word 8-13 in IOCB */
4124     uint32_t bghm;      /* word 14 - BlockGuard High Water Mark */
4125 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
4126 #define BGS_BIDIR_BG_PROF_MASK      0xff000000
4127 #define BGS_BIDIR_BG_PROF_SHIFT     24
4128 #define BGS_BIDIR_ERR_COND_FLAGS_MASK   0x003f0000
4129 #define BGS_BIDIR_ERR_COND_SHIFT    16
4130 #define BGS_BG_PROFILE_MASK     0x0000ff00
4131 #define BGS_BG_PROFILE_SHIFT        8
4132 #define BGS_INVALID_PROF_MASK       0x00000020
4133 #define BGS_INVALID_PROF_SHIFT      5
4134 #define BGS_UNINIT_DIF_BLOCK_MASK   0x00000010
4135 #define BGS_UNINIT_DIF_BLOCK_SHIFT  4
4136 #define BGS_HI_WATER_MARK_PRESENT_MASK  0x00000008
4137 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
4138 #define BGS_REFTAG_ERR_MASK     0x00000004
4139 #define BGS_REFTAG_ERR_SHIFT        2
4140 #define BGS_APPTAG_ERR_MASK     0x00000002
4141 #define BGS_APPTAG_ERR_SHIFT        1
4142 #define BGS_GUARD_ERR_MASK      0x00000001
4143 #define BGS_GUARD_ERR_SHIFT     0
4144     uint32_t bgstat;    /* word 15 - BlockGuard Status */
4145 };
4146 
4147 static inline uint32_t
4148 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
4149 {
4150     return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
4151                 BGS_BIDIR_BG_PROF_SHIFT;
4152 }
4153 
4154 static inline uint32_t
4155 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
4156 {
4157     return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
4158                 BGS_BIDIR_ERR_COND_SHIFT;
4159 }
4160 
4161 static inline uint32_t
4162 lpfc_bgs_get_bg_prof(uint32_t bgstat)
4163 {
4164     return (bgstat & BGS_BG_PROFILE_MASK) >>
4165                 BGS_BG_PROFILE_SHIFT;
4166 }
4167 
4168 static inline uint32_t
4169 lpfc_bgs_get_invalid_prof(uint32_t bgstat)
4170 {
4171     return (bgstat & BGS_INVALID_PROF_MASK) >>
4172                 BGS_INVALID_PROF_SHIFT;
4173 }
4174 
4175 static inline uint32_t
4176 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
4177 {
4178     return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
4179                 BGS_UNINIT_DIF_BLOCK_SHIFT;
4180 }
4181 
4182 static inline uint32_t
4183 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
4184 {
4185     return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
4186                 BGS_HI_WATER_MARK_PRESENT_SHIFT;
4187 }
4188 
4189 static inline uint32_t
4190 lpfc_bgs_get_reftag_err(uint32_t bgstat)
4191 {
4192     return (bgstat & BGS_REFTAG_ERR_MASK) >>
4193                 BGS_REFTAG_ERR_SHIFT;
4194 }
4195 
4196 static inline uint32_t
4197 lpfc_bgs_get_apptag_err(uint32_t bgstat)
4198 {
4199     return (bgstat & BGS_APPTAG_ERR_MASK) >>
4200                 BGS_APPTAG_ERR_SHIFT;
4201 }
4202 
4203 static inline uint32_t
4204 lpfc_bgs_get_guard_err(uint32_t bgstat)
4205 {
4206     return (bgstat & BGS_GUARD_ERR_MASK) >>
4207                 BGS_GUARD_ERR_SHIFT;
4208 }
4209 
4210 #define LPFC_EXT_DATA_BDE_COUNT 3
4211 struct fcp_irw_ext {
4212     uint32_t    io_tag64_low;
4213     uint32_t    io_tag64_high;
4214 #ifdef __BIG_ENDIAN_BITFIELD
4215     uint8_t     reserved1;
4216     uint8_t     reserved2;
4217     uint8_t     reserved3;
4218     uint8_t     ebde_count;
4219 #else  /* __LITTLE_ENDIAN */
4220     uint8_t     ebde_count;
4221     uint8_t     reserved3;
4222     uint8_t     reserved2;
4223     uint8_t     reserved1;
4224 #endif
4225     uint32_t    reserved4;
4226     struct ulp_bde64 rbde;      /* response bde */
4227     struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
4228     uint8_t icd[32];        /* immediate command data (32 bytes) */
4229 };
4230 
4231 typedef struct _IOCB {  /* IOCB structure */
4232     union {
4233         GENERIC_RSP grsp;   /* Generic response */
4234         XR_SEQ_FIELDS xrseq;    /* XMIT / BCAST / RCV_SEQUENCE cmd */
4235         struct ulp_bde cont[3]; /* up to 3 continuation bdes */
4236         RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
4237         AC_XRI acxri;   /* ABORT / CLOSE_XRI template */
4238         A_MXRI64 amxri; /* abort multiple xri command overlay */
4239         GET_RPI getrpi; /* GET_RPI template */
4240         FCPI_FIELDS fcpi;   /* FCP Initiator template */
4241         FCPT_FIELDS fcpt;   /* FCP target template */
4242 
4243         /* SLI-2 structures */
4244 
4245         struct ulp_bde64 cont64[2];  /* up to 2 64 bit continuation
4246                           * bde_64s */
4247         ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
4248         GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
4249         RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
4250         XMT_SEQ_FIELDS64 xseq64;    /* XMIT / BCAST cmd */
4251         FCPI_FIELDS64 fcpi64;   /* FCP 64 bit Initiator template */
4252         FCPT_FIELDS64 fcpt64;   /* FCP 64 bit target template */
4253         ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
4254         QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
4255         struct rcv_seq64 rcvseq64;  /* RCV_SEQ64 and RCV_CONT64 */
4256         struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */
4257         uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
4258     } un;
4259     union {
4260         struct {
4261 #ifdef __BIG_ENDIAN_BITFIELD
4262             uint16_t ulpContext;    /* High order bits word 6 */
4263             uint16_t ulpIoTag;  /* Low  order bits word 6 */
4264 #else   /*  __LITTLE_ENDIAN_BITFIELD */
4265             uint16_t ulpIoTag;  /* Low  order bits word 6 */
4266             uint16_t ulpContext;    /* High order bits word 6 */
4267 #endif
4268         } t1;
4269         struct {
4270 #ifdef __BIG_ENDIAN_BITFIELD
4271             uint16_t ulpContext;    /* High order bits word 6 */
4272             uint16_t ulpIoTag1:2;   /* Low  order bits word 6 */
4273             uint16_t ulpIoTag0:14;  /* Low  order bits word 6 */
4274 #else   /*  __LITTLE_ENDIAN_BITFIELD */
4275             uint16_t ulpIoTag0:14;  /* Low  order bits word 6 */
4276             uint16_t ulpIoTag1:2;   /* Low  order bits word 6 */
4277             uint16_t ulpContext;    /* High order bits word 6 */
4278 #endif
4279         } t2;
4280     } un1;
4281 #define ulpContext un1.t1.ulpContext
4282 #define ulpIoTag   un1.t1.ulpIoTag
4283 #define ulpIoTag0  un1.t2.ulpIoTag0
4284 
4285 #ifdef __BIG_ENDIAN_BITFIELD
4286     uint32_t ulpTimeout:8;
4287     uint32_t ulpXS:1;
4288     uint32_t ulpFCP2Rcvy:1;
4289     uint32_t ulpPU:2;
4290     uint32_t ulpIr:1;
4291     uint32_t ulpClass:3;
4292     uint32_t ulpCommand:8;
4293     uint32_t ulpStatus:4;
4294     uint32_t ulpBdeCount:2;
4295     uint32_t ulpLe:1;
4296     uint32_t ulpOwner:1;    /* Low order bit word 7 */
4297 #else   /*  __LITTLE_ENDIAN_BITFIELD */
4298     uint32_t ulpOwner:1;    /* Low order bit word 7 */
4299     uint32_t ulpLe:1;
4300     uint32_t ulpBdeCount:2;
4301     uint32_t ulpStatus:4;
4302     uint32_t ulpCommand:8;
4303     uint32_t ulpClass:3;
4304     uint32_t ulpIr:1;
4305     uint32_t ulpPU:2;
4306     uint32_t ulpFCP2Rcvy:1;
4307     uint32_t ulpXS:1;
4308     uint32_t ulpTimeout:8;
4309 #endif
4310 
4311     union {
4312         struct rcv_sli3 rcvsli3; /* words 8 - 15 */
4313 
4314         /* words 8-31 used for que_xri_cx iocb */
4315         struct que_xri64cx_ext_fields que_xri64cx_ext_words;
4316         struct fcp_irw_ext fcp_ext;
4317         uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
4318 
4319         /* words 8-15 for BlockGuard */
4320         struct sli3_bg_fields sli3_bg;
4321     } unsli3;
4322 
4323 #define ulpCt_h ulpXS
4324 #define ulpCt_l ulpFCP2Rcvy
4325 
4326 #define IOCB_FCP       1    /* IOCB is used for FCP ELS cmds-ulpRsvByte */
4327 #define IOCB_IP        2    /* IOCB is used for IP ELS cmds */
4328 #define PARM_UNUSED        0    /* PU field (Word 4) not used */
4329 #define PARM_REL_OFF       1    /* PU field (Word 4) = R. O. */
4330 #define PARM_READ_CHECK    2    /* PU field (Word 4) = Data Transfer Length */
4331 #define PARM_NPIV_DID      3
4332 #define CLASS1             0    /* Class 1 */
4333 #define CLASS2             1    /* Class 2 */
4334 #define CLASS3             2    /* Class 3 */
4335 #define CLASS_FCP_INTERMIX 7    /* FCP Data->Cls 1, all else->Cls 2 */
4336 
4337 #define IOSTAT_SUCCESS         0x0  /* ulpStatus  - HBA defined */
4338 #define IOSTAT_FCP_RSP_ERROR   0x1
4339 #define IOSTAT_REMOTE_STOP     0x2
4340 #define IOSTAT_LOCAL_REJECT    0x3
4341 #define IOSTAT_NPORT_RJT       0x4
4342 #define IOSTAT_FABRIC_RJT      0x5
4343 #define IOSTAT_NPORT_BSY       0x6
4344 #define IOSTAT_FABRIC_BSY      0x7
4345 #define IOSTAT_INTERMED_RSP    0x8
4346 #define IOSTAT_LS_RJT          0x9
4347 #define IOSTAT_BA_RJT          0xA
4348 #define IOSTAT_RSVD1           0xB
4349 #define IOSTAT_RSVD2           0xC
4350 #define IOSTAT_RSVD3           0xD
4351 #define IOSTAT_RSVD4           0xE
4352 #define IOSTAT_NEED_BUFFER     0xF
4353 #define IOSTAT_DRIVER_REJECT   0x10   /* ulpStatus  - Driver defined */
4354 #define IOSTAT_DEFAULT         0xF    /* Same as rsvd5 for now */
4355 #define IOSTAT_CNT             0x11
4356 
4357 } IOCB_t;
4358 
4359 
4360 #define SLI1_SLIM_SIZE   (4 * 1024)
4361 
4362 /* Up to 498 IOCBs will fit into 16k
4363  * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
4364  */
4365 #define SLI2_SLIM_SIZE   (64 * 1024)
4366 
4367 /* Maximum IOCBs that will fit in SLI2 slim */
4368 #define MAX_SLI2_IOCB    498
4369 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
4370                 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
4371                 sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
4372 
4373 /* HBQ entries are 4 words each = 4k */
4374 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) *  \
4375                  lpfc_sli_hbq_count())
4376 
4377 struct lpfc_sli2_slim {
4378     MAILBOX_t mbx;
4379     uint32_t  mbx_ext_words[MAILBOX_EXT_WSIZE];
4380     PCB_t pcb;
4381     IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
4382 };
4383 
4384 /*
4385  * This function checks PCI device to allow special handling for LC HBAs.
4386  *
4387  * Parameters:
4388  * device : struct pci_dev 's device field
4389  *
4390  * return 1 => TRUE
4391  *        0 => FALSE
4392  */
4393 static inline int
4394 lpfc_is_LC_HBA(unsigned short device)
4395 {
4396     if ((device == PCI_DEVICE_ID_TFLY) ||
4397         (device == PCI_DEVICE_ID_PFLY) ||
4398         (device == PCI_DEVICE_ID_LP101) ||
4399         (device == PCI_DEVICE_ID_BMID) ||
4400         (device == PCI_DEVICE_ID_BSMB) ||
4401         (device == PCI_DEVICE_ID_ZMID) ||
4402         (device == PCI_DEVICE_ID_ZSMB) ||
4403         (device == PCI_DEVICE_ID_SAT_MID) ||
4404         (device == PCI_DEVICE_ID_SAT_SMB) ||
4405         (device == PCI_DEVICE_ID_RFLY))
4406         return 1;
4407     else
4408         return 0;
4409 }
4410 
4411 /*
4412  * Determine if failed because of a link event or firmware reset.
4413  */
4414 static inline int
4415 lpfc_error_lost_link(u32 ulp_status, u32 ulp_word4)
4416 {
4417     return (ulp_status == IOSTAT_LOCAL_REJECT &&
4418         (ulp_word4 == IOERR_SLI_ABORTED ||
4419          ulp_word4 == IOERR_LINK_DOWN ||
4420          ulp_word4 == IOERR_SLI_DOWN));
4421 }
4422 
4423 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */
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