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0023 #ifndef _H_LPFC_DEBUG_FS
0024 #define _H_LPFC_DEBUG_FS
0025
0026 #ifdef CONFIG_SCSI_LPFC_DEBUG_FS
0027
0028
0029 #define LPFC_DEBUG_TRC_ENTRY_SIZE 100
0030
0031
0032 #define LPFC_NODELIST_SIZE 8192
0033 #define LPFC_NODELIST_ENTRY_SIZE 120
0034
0035
0036 #define LPFC_DUMPHBASLIM_SIZE 4096
0037
0038
0039 #define LPFC_DUMPHOSTSLIM_SIZE 4096
0040
0041
0042 #define LPFC_DUMPSLIQINFO_SIZE 4096
0043
0044
0045 #define LPFC_HBQINFO_SIZE 8192
0046
0047
0048 #define LPFC_NVMESTAT_SIZE 8192
0049 #define LPFC_IOKTIME_SIZE 8192
0050 #define LPFC_NVMEIO_TRC_SIZE 8192
0051
0052
0053 #define LPFC_SCSISTAT_SIZE 8192
0054
0055
0056 #define LPFC_CGN_BUF_SIZE 8192
0057
0058 #define LPFC_DEBUG_OUT_LINE_SZ 80
0059
0060
0061
0062
0063
0064
0065 #define LPFC_PCI_CFG_BROWSE 0xffff
0066 #define LPFC_PCI_CFG_RD_CMD_ARG 2
0067 #define LPFC_PCI_CFG_WR_CMD_ARG 3
0068 #define LPFC_PCI_CFG_SIZE 4096
0069 #define LPFC_PCI_CFG_RD_SIZE (LPFC_PCI_CFG_SIZE/4)
0070
0071 #define IDIAG_PCICFG_WHERE_INDX 0
0072 #define IDIAG_PCICFG_COUNT_INDX 1
0073 #define IDIAG_PCICFG_VALUE_INDX 2
0074
0075
0076 #define LPFC_PCI_BAR_BROWSE 0xffff
0077 #define LPFC_PCI_BAR_RD_CMD_ARG 3
0078 #define LPFC_PCI_BAR_WR_CMD_ARG 3
0079
0080 #define LPFC_PCI_IF0_BAR0_SIZE (1024 * 16)
0081 #define LPFC_PCI_IF0_BAR1_SIZE (1024 * 128)
0082 #define LPFC_PCI_IF0_BAR2_SIZE (1024 * 128)
0083 #define LPFC_PCI_IF2_BAR0_SIZE (1024 * 32)
0084
0085 #define LPFC_PCI_BAR_RD_BUF_SIZE 4096
0086 #define LPFC_PCI_BAR_RD_SIZE (LPFC_PCI_BAR_RD_BUF_SIZE/4)
0087
0088 #define LPFC_PCI_IF0_BAR0_RD_SIZE (LPFC_PCI_IF0_BAR0_SIZE/4)
0089 #define LPFC_PCI_IF0_BAR1_RD_SIZE (LPFC_PCI_IF0_BAR1_SIZE/4)
0090 #define LPFC_PCI_IF0_BAR2_RD_SIZE (LPFC_PCI_IF0_BAR2_SIZE/4)
0091 #define LPFC_PCI_IF2_BAR0_RD_SIZE (LPFC_PCI_IF2_BAR0_SIZE/4)
0092
0093 #define IDIAG_BARACC_BAR_NUM_INDX 0
0094 #define IDIAG_BARACC_OFF_SET_INDX 1
0095 #define IDIAG_BARACC_ACC_MOD_INDX 2
0096 #define IDIAG_BARACC_REG_VAL_INDX 2
0097 #define IDIAG_BARACC_BAR_SZE_INDX 3
0098
0099 #define IDIAG_BARACC_BAR_0 0
0100 #define IDIAG_BARACC_BAR_1 1
0101 #define IDIAG_BARACC_BAR_2 2
0102
0103 #define SINGLE_WORD 1
0104
0105
0106 #define LPFC_QUE_INFO_GET_BUF_SIZE 4096
0107
0108
0109 #define LPFC_QUE_ACC_BROWSE 0xffff
0110 #define LPFC_QUE_ACC_RD_CMD_ARG 4
0111 #define LPFC_QUE_ACC_WR_CMD_ARG 6
0112 #define LPFC_QUE_ACC_BUF_SIZE 4096
0113 #define LPFC_QUE_ACC_SIZE (LPFC_QUE_ACC_BUF_SIZE/2)
0114
0115 #define LPFC_IDIAG_EQ 1
0116 #define LPFC_IDIAG_CQ 2
0117 #define LPFC_IDIAG_MQ 3
0118 #define LPFC_IDIAG_WQ 4
0119 #define LPFC_IDIAG_RQ 5
0120
0121 #define IDIAG_QUEACC_QUETP_INDX 0
0122 #define IDIAG_QUEACC_QUEID_INDX 1
0123 #define IDIAG_QUEACC_INDEX_INDX 2
0124 #define IDIAG_QUEACC_COUNT_INDX 3
0125 #define IDIAG_QUEACC_OFFST_INDX 4
0126 #define IDIAG_QUEACC_VALUE_INDX 5
0127
0128
0129 #define LPFC_DRB_ACC_ALL 0xffff
0130 #define LPFC_DRB_ACC_RD_CMD_ARG 1
0131 #define LPFC_DRB_ACC_WR_CMD_ARG 2
0132 #define LPFC_DRB_ACC_BUF_SIZE 256
0133
0134 #define LPFC_DRB_EQ 1
0135 #define LPFC_DRB_CQ 2
0136 #define LPFC_DRB_MQ 3
0137 #define LPFC_DRB_WQ 4
0138 #define LPFC_DRB_RQ 5
0139
0140 #define LPFC_DRB_MAX 5
0141
0142 #define IDIAG_DRBACC_REGID_INDX 0
0143 #define IDIAG_DRBACC_VALUE_INDX 1
0144
0145
0146 #define LPFC_CTL_ACC_ALL 0xffff
0147 #define LPFC_CTL_ACC_RD_CMD_ARG 1
0148 #define LPFC_CTL_ACC_WR_CMD_ARG 2
0149 #define LPFC_CTL_ACC_BUF_SIZE 256
0150
0151 #define LPFC_CTL_PORT_SEM 1
0152 #define LPFC_CTL_PORT_STA 2
0153 #define LPFC_CTL_PORT_CTL 3
0154 #define LPFC_CTL_PORT_ER1 4
0155 #define LPFC_CTL_PORT_ER2 5
0156 #define LPFC_CTL_PDEV_CTL 6
0157
0158 #define LPFC_CTL_MAX 6
0159
0160 #define IDIAG_CTLACC_REGID_INDX 0
0161 #define IDIAG_CTLACC_VALUE_INDX 1
0162
0163
0164 #define LPFC_MBX_DMP_ARG 4
0165
0166 #define LPFC_MBX_ACC_BUF_SIZE 512
0167 #define LPFC_MBX_ACC_LBUF_SZ 128
0168
0169 #define LPFC_MBX_DMP_MBX_WORD 0x00000001
0170 #define LPFC_MBX_DMP_MBX_BYTE 0x00000002
0171 #define LPFC_MBX_DMP_MBX_ALL (LPFC_MBX_DMP_MBX_WORD | LPFC_MBX_DMP_MBX_BYTE)
0172
0173 #define LPFC_BSG_DMP_MBX_RD_MBX 0x00000001
0174 #define LPFC_BSG_DMP_MBX_RD_BUF 0x00000002
0175 #define LPFC_BSG_DMP_MBX_WR_MBX 0x00000004
0176 #define LPFC_BSG_DMP_MBX_WR_BUF 0x00000008
0177 #define LPFC_BSG_DMP_MBX_ALL (LPFC_BSG_DMP_MBX_RD_MBX | \
0178 LPFC_BSG_DMP_MBX_RD_BUF | \
0179 LPFC_BSG_DMP_MBX_WR_MBX | \
0180 LPFC_BSG_DMP_MBX_WR_BUF)
0181
0182 #define LPFC_MBX_DMP_ALL 0xffff
0183 #define LPFC_MBX_ALL_CMD 0xff
0184
0185 #define IDIAG_MBXACC_MBCMD_INDX 0
0186 #define IDIAG_MBXACC_DPMAP_INDX 1
0187 #define IDIAG_MBXACC_DPCNT_INDX 2
0188 #define IDIAG_MBXACC_WDCNT_INDX 3
0189
0190
0191 #define LPFC_EXT_ACC_CMD_ARG 1
0192 #define LPFC_EXT_ACC_BUF_SIZE 4096
0193
0194 #define LPFC_EXT_ACC_AVAIL 0x1
0195 #define LPFC_EXT_ACC_ALLOC 0x2
0196 #define LPFC_EXT_ACC_DRIVR 0x4
0197 #define LPFC_EXT_ACC_ALL (LPFC_EXT_ACC_DRIVR | \
0198 LPFC_EXT_ACC_AVAIL | \
0199 LPFC_EXT_ACC_ALLOC)
0200
0201 #define IDIAG_EXTACC_EXMAP_INDX 0
0202
0203 #define SIZE_U8 sizeof(uint8_t)
0204 #define SIZE_U16 sizeof(uint16_t)
0205 #define SIZE_U32 sizeof(uint32_t)
0206
0207 #define lpfc_nvmeio_data(phba, fmt, arg...) \
0208 { \
0209 if (phba->nvmeio_trc_on) \
0210 lpfc_debugfs_nvme_trc(phba, fmt, ##arg); \
0211 }
0212
0213 struct lpfc_debug {
0214 char *i_private;
0215 char op;
0216 #define LPFC_IDIAG_OP_RD 1
0217 #define LPFC_IDIAG_OP_WR 2
0218 char *buffer;
0219 int len;
0220 };
0221
0222 struct lpfc_debugfs_trc {
0223 char *fmt;
0224 uint32_t data1;
0225 uint32_t data2;
0226 uint32_t data3;
0227 uint32_t seq_cnt;
0228 unsigned long jif;
0229 };
0230
0231 struct lpfc_debugfs_nvmeio_trc {
0232 char *fmt;
0233 uint16_t data1;
0234 uint16_t data2;
0235 uint32_t data3;
0236 };
0237
0238 struct lpfc_idiag_offset {
0239 uint32_t last_rd;
0240 };
0241
0242 #define LPFC_IDIAG_CMD_DATA_SIZE 8
0243 struct lpfc_idiag_cmd {
0244 uint32_t opcode;
0245 #define LPFC_IDIAG_CMD_PCICFG_RD 0x00000001
0246 #define LPFC_IDIAG_CMD_PCICFG_WR 0x00000002
0247 #define LPFC_IDIAG_CMD_PCICFG_ST 0x00000003
0248 #define LPFC_IDIAG_CMD_PCICFG_CL 0x00000004
0249
0250 #define LPFC_IDIAG_CMD_BARACC_RD 0x00000008
0251 #define LPFC_IDIAG_CMD_BARACC_WR 0x00000009
0252 #define LPFC_IDIAG_CMD_BARACC_ST 0x0000000a
0253 #define LPFC_IDIAG_CMD_BARACC_CL 0x0000000b
0254
0255 #define LPFC_IDIAG_CMD_QUEACC_RD 0x00000011
0256 #define LPFC_IDIAG_CMD_QUEACC_WR 0x00000012
0257 #define LPFC_IDIAG_CMD_QUEACC_ST 0x00000013
0258 #define LPFC_IDIAG_CMD_QUEACC_CL 0x00000014
0259
0260 #define LPFC_IDIAG_CMD_DRBACC_RD 0x00000021
0261 #define LPFC_IDIAG_CMD_DRBACC_WR 0x00000022
0262 #define LPFC_IDIAG_CMD_DRBACC_ST 0x00000023
0263 #define LPFC_IDIAG_CMD_DRBACC_CL 0x00000024
0264
0265 #define LPFC_IDIAG_CMD_CTLACC_RD 0x00000031
0266 #define LPFC_IDIAG_CMD_CTLACC_WR 0x00000032
0267 #define LPFC_IDIAG_CMD_CTLACC_ST 0x00000033
0268 #define LPFC_IDIAG_CMD_CTLACC_CL 0x00000034
0269
0270 #define LPFC_IDIAG_CMD_MBXACC_DP 0x00000041
0271 #define LPFC_IDIAG_BSG_MBXACC_DP 0x00000042
0272
0273 #define LPFC_IDIAG_CMD_EXTACC_RD 0x00000051
0274
0275 uint32_t data[LPFC_IDIAG_CMD_DATA_SIZE];
0276 };
0277
0278 struct lpfc_idiag {
0279 uint32_t active;
0280 struct lpfc_idiag_cmd cmd;
0281 struct lpfc_idiag_offset offset;
0282 void *ptr_private;
0283 };
0284
0285 #define MAX_DEBUGFS_RX_TABLE_SIZE (128 * LPFC_MAX_RXMONITOR_ENTRY)
0286 struct lpfc_rx_monitor_debug {
0287 char *i_private;
0288 char *buffer;
0289 };
0290
0291 #else
0292
0293 #define lpfc_nvmeio_data(phba, fmt, arg...) \
0294 no_printk(fmt, ##arg)
0295
0296 #endif
0297
0298
0299 #define LPFC_DUMP_MULTIXRIPOOL_SIZE 8192
0300
0301 enum {
0302 DUMP_IO,
0303 DUMP_MBX,
0304 DUMP_ELS,
0305 DUMP_NVMELS,
0306 };
0307
0308
0309 #define LPFC_DISC_TRC_ELS_CMD 0x1
0310 #define LPFC_DISC_TRC_ELS_RSP 0x2
0311 #define LPFC_DISC_TRC_ELS_UNSOL 0x4
0312 #define LPFC_DISC_TRC_ELS_ALL 0x7
0313 #define LPFC_DISC_TRC_MBOX_VPORT 0x8
0314 #define LPFC_DISC_TRC_MBOX 0x10
0315 #define LPFC_DISC_TRC_MBOX_ALL 0x18
0316 #define LPFC_DISC_TRC_CT 0x20
0317 #define LPFC_DISC_TRC_DSM 0x40
0318 #define LPFC_DISC_TRC_RPORT 0x80
0319 #define LPFC_DISC_TRC_NODE 0x100
0320
0321 #define LPFC_DISC_TRC_DISCOVERY 0xef
0322
0323 #endif
0324
0325
0326
0327
0328
0329
0330
0331
0332
0333
0334
0335
0336
0337
0338
0339
0340 static void
0341 lpfc_debug_dump_qe(struct lpfc_queue *q, uint32_t idx)
0342 {
0343 char line_buf[LPFC_LBUF_SZ];
0344 int i, esize, qe_word_cnt, len;
0345 uint32_t *pword;
0346
0347
0348 if (!q)
0349 return;
0350 if (idx >= q->entry_count)
0351 return;
0352
0353 esize = q->entry_size;
0354 qe_word_cnt = esize / sizeof(uint32_t);
0355 pword = lpfc_sli4_qe(q, idx);
0356
0357 len = 0;
0358 len += scnprintf(line_buf+len, LPFC_LBUF_SZ-len, "QE[%04d]: ", idx);
0359 if (qe_word_cnt > 8)
0360 printk(KERN_ERR "%s\n", line_buf);
0361
0362 for (i = 0; i < qe_word_cnt; i++) {
0363 if (!(i % 8)) {
0364 if (i != 0)
0365 printk(KERN_ERR "%s\n", line_buf);
0366 if (qe_word_cnt > 8) {
0367 len = 0;
0368 memset(line_buf, 0, LPFC_LBUF_SZ);
0369 len += scnprintf(line_buf+len, LPFC_LBUF_SZ-len,
0370 "%03d: ", i);
0371 }
0372 }
0373 len += scnprintf(line_buf+len, LPFC_LBUF_SZ-len, "%08x ",
0374 ((uint32_t)*pword) & 0xffffffff);
0375 pword++;
0376 }
0377 if (qe_word_cnt <= 8 || (i - 1) % 8)
0378 printk(KERN_ERR "%s\n", line_buf);
0379 }
0380
0381
0382
0383
0384
0385
0386
0387
0388 static inline void
0389 lpfc_debug_dump_q(struct lpfc_queue *q)
0390 {
0391 int idx, entry_count;
0392
0393
0394 if (!q)
0395 return;
0396
0397 dev_printk(KERN_ERR, &(((q->phba))->pcidev)->dev,
0398 "%d: [qid:%d, type:%d, subtype:%d, "
0399 "qe_size:%d, qe_count:%d, "
0400 "host_index:%d, port_index:%d]\n",
0401 (q->phba)->brd_no,
0402 q->queue_id, q->type, q->subtype,
0403 q->entry_size, q->entry_count,
0404 q->host_index, q->hba_index);
0405 entry_count = q->entry_count;
0406 for (idx = 0; idx < entry_count; idx++)
0407 lpfc_debug_dump_qe(q, idx);
0408 printk(KERN_ERR "\n");
0409 }
0410
0411
0412
0413
0414
0415
0416
0417
0418
0419 static inline void
0420 lpfc_debug_dump_wq(struct lpfc_hba *phba, int qtype, int wqidx)
0421 {
0422 struct lpfc_queue *wq;
0423 char *qtypestr;
0424
0425 if (qtype == DUMP_IO) {
0426 wq = phba->sli4_hba.hdwq[wqidx].io_wq;
0427 qtypestr = "IO";
0428 } else if (qtype == DUMP_MBX) {
0429 wq = phba->sli4_hba.mbx_wq;
0430 qtypestr = "MBX";
0431 } else if (qtype == DUMP_ELS) {
0432 wq = phba->sli4_hba.els_wq;
0433 qtypestr = "ELS";
0434 } else if (qtype == DUMP_NVMELS) {
0435 wq = phba->sli4_hba.nvmels_wq;
0436 qtypestr = "NVMELS";
0437 } else
0438 return;
0439
0440 if (qtype == DUMP_IO)
0441 pr_err("%s WQ: WQ[Idx:%d|Qid:%d]\n",
0442 qtypestr, wqidx, wq->queue_id);
0443 else
0444 pr_err("%s WQ: WQ[Qid:%d]\n",
0445 qtypestr, wq->queue_id);
0446
0447 lpfc_debug_dump_q(wq);
0448 }
0449
0450
0451
0452
0453
0454
0455
0456
0457
0458
0459 static inline void
0460 lpfc_debug_dump_cq(struct lpfc_hba *phba, int qtype, int wqidx)
0461 {
0462 struct lpfc_queue *wq, *cq, *eq;
0463 char *qtypestr;
0464 int eqidx;
0465
0466
0467 eq = NULL;
0468
0469 if (qtype == DUMP_IO) {
0470 wq = phba->sli4_hba.hdwq[wqidx].io_wq;
0471 cq = phba->sli4_hba.hdwq[wqidx].io_cq;
0472 qtypestr = "IO";
0473 } else if (qtype == DUMP_MBX) {
0474 wq = phba->sli4_hba.mbx_wq;
0475 cq = phba->sli4_hba.mbx_cq;
0476 qtypestr = "MBX";
0477 } else if (qtype == DUMP_ELS) {
0478 wq = phba->sli4_hba.els_wq;
0479 cq = phba->sli4_hba.els_cq;
0480 qtypestr = "ELS";
0481 } else if (qtype == DUMP_NVMELS) {
0482 wq = phba->sli4_hba.nvmels_wq;
0483 cq = phba->sli4_hba.nvmels_cq;
0484 qtypestr = "NVMELS";
0485 } else
0486 return;
0487
0488 for (eqidx = 0; eqidx < phba->cfg_hdw_queue; eqidx++) {
0489 eq = phba->sli4_hba.hdwq[eqidx].hba_eq;
0490 if (cq->assoc_qid == eq->queue_id)
0491 break;
0492 }
0493 if (eqidx == phba->cfg_hdw_queue) {
0494 pr_err("Couldn't find EQ for CQ. Using EQ[0]\n");
0495 eqidx = 0;
0496 eq = phba->sli4_hba.hdwq[0].hba_eq;
0497 }
0498
0499 if (qtype == DUMP_IO)
0500 pr_err("%s CQ: WQ[Idx:%d|Qid%d]->CQ[Idx%d|Qid%d]"
0501 "->EQ[Idx:%d|Qid:%d]:\n",
0502 qtypestr, wqidx, wq->queue_id, wqidx, cq->queue_id,
0503 eqidx, eq->queue_id);
0504 else
0505 pr_err("%s CQ: WQ[Qid:%d]->CQ[Qid:%d]"
0506 "->EQ[Idx:%d|Qid:%d]:\n",
0507 qtypestr, wq->queue_id, cq->queue_id,
0508 eqidx, eq->queue_id);
0509
0510 lpfc_debug_dump_q(cq);
0511 }
0512
0513
0514
0515
0516
0517
0518
0519
0520
0521 static inline void
0522 lpfc_debug_dump_hba_eq(struct lpfc_hba *phba, int qidx)
0523 {
0524 struct lpfc_queue *qp;
0525
0526 qp = phba->sli4_hba.hdwq[qidx].hba_eq;
0527
0528 pr_err("EQ[Idx:%d|Qid:%d]\n", qidx, qp->queue_id);
0529
0530 lpfc_debug_dump_q(qp);
0531 }
0532
0533
0534
0535
0536
0537
0538
0539 static inline void
0540 lpfc_debug_dump_dat_rq(struct lpfc_hba *phba)
0541 {
0542 printk(KERN_ERR "DAT RQ: RQ[Qid:%d]\n",
0543 phba->sli4_hba.dat_rq->queue_id);
0544 lpfc_debug_dump_q(phba->sli4_hba.dat_rq);
0545 }
0546
0547
0548
0549
0550
0551
0552
0553 static inline void
0554 lpfc_debug_dump_hdr_rq(struct lpfc_hba *phba)
0555 {
0556 printk(KERN_ERR "HDR RQ: RQ[Qid:%d]\n",
0557 phba->sli4_hba.hdr_rq->queue_id);
0558 lpfc_debug_dump_q(phba->sli4_hba.hdr_rq);
0559 }
0560
0561
0562
0563
0564
0565
0566
0567
0568
0569 static inline void
0570 lpfc_debug_dump_wq_by_id(struct lpfc_hba *phba, int qid)
0571 {
0572 int wq_idx;
0573
0574 for (wq_idx = 0; wq_idx < phba->cfg_hdw_queue; wq_idx++)
0575 if (phba->sli4_hba.hdwq[wq_idx].io_wq->queue_id == qid)
0576 break;
0577 if (wq_idx < phba->cfg_hdw_queue) {
0578 pr_err("IO WQ[Idx:%d|Qid:%d]\n", wq_idx, qid);
0579 lpfc_debug_dump_q(phba->sli4_hba.hdwq[wq_idx].io_wq);
0580 return;
0581 }
0582
0583 if (phba->sli4_hba.els_wq->queue_id == qid) {
0584 pr_err("ELS WQ[Qid:%d]\n", qid);
0585 lpfc_debug_dump_q(phba->sli4_hba.els_wq);
0586 return;
0587 }
0588
0589 if (phba->sli4_hba.nvmels_wq->queue_id == qid) {
0590 pr_err("NVME LS WQ[Qid:%d]\n", qid);
0591 lpfc_debug_dump_q(phba->sli4_hba.nvmels_wq);
0592 }
0593 }
0594
0595
0596
0597
0598
0599
0600
0601
0602
0603 static inline void
0604 lpfc_debug_dump_mq_by_id(struct lpfc_hba *phba, int qid)
0605 {
0606 if (phba->sli4_hba.mbx_wq->queue_id == qid) {
0607 printk(KERN_ERR "MBX WQ[Qid:%d]\n", qid);
0608 lpfc_debug_dump_q(phba->sli4_hba.mbx_wq);
0609 }
0610 }
0611
0612
0613
0614
0615
0616
0617
0618
0619
0620 static inline void
0621 lpfc_debug_dump_rq_by_id(struct lpfc_hba *phba, int qid)
0622 {
0623 if (phba->sli4_hba.hdr_rq->queue_id == qid) {
0624 printk(KERN_ERR "HDR RQ[Qid:%d]\n", qid);
0625 lpfc_debug_dump_q(phba->sli4_hba.hdr_rq);
0626 return;
0627 }
0628 if (phba->sli4_hba.dat_rq->queue_id == qid) {
0629 printk(KERN_ERR "DAT RQ[Qid:%d]\n", qid);
0630 lpfc_debug_dump_q(phba->sli4_hba.dat_rq);
0631 }
0632 }
0633
0634
0635
0636
0637
0638
0639
0640
0641
0642 static inline void
0643 lpfc_debug_dump_cq_by_id(struct lpfc_hba *phba, int qid)
0644 {
0645 int cq_idx;
0646
0647 for (cq_idx = 0; cq_idx < phba->cfg_hdw_queue; cq_idx++)
0648 if (phba->sli4_hba.hdwq[cq_idx].io_cq->queue_id == qid)
0649 break;
0650
0651 if (cq_idx < phba->cfg_hdw_queue) {
0652 pr_err("IO CQ[Idx:%d|Qid:%d]\n", cq_idx, qid);
0653 lpfc_debug_dump_q(phba->sli4_hba.hdwq[cq_idx].io_cq);
0654 return;
0655 }
0656
0657 if (phba->sli4_hba.els_cq->queue_id == qid) {
0658 pr_err("ELS CQ[Qid:%d]\n", qid);
0659 lpfc_debug_dump_q(phba->sli4_hba.els_cq);
0660 return;
0661 }
0662
0663 if (phba->sli4_hba.nvmels_cq->queue_id == qid) {
0664 pr_err("NVME LS CQ[Qid:%d]\n", qid);
0665 lpfc_debug_dump_q(phba->sli4_hba.nvmels_cq);
0666 return;
0667 }
0668
0669 if (phba->sli4_hba.mbx_cq->queue_id == qid) {
0670 pr_err("MBX CQ[Qid:%d]\n", qid);
0671 lpfc_debug_dump_q(phba->sli4_hba.mbx_cq);
0672 }
0673 }
0674
0675
0676
0677
0678
0679
0680
0681
0682
0683 static inline void
0684 lpfc_debug_dump_eq_by_id(struct lpfc_hba *phba, int qid)
0685 {
0686 int eq_idx;
0687
0688 for (eq_idx = 0; eq_idx < phba->cfg_hdw_queue; eq_idx++)
0689 if (phba->sli4_hba.hdwq[eq_idx].hba_eq->queue_id == qid)
0690 break;
0691
0692 if (eq_idx < phba->cfg_hdw_queue) {
0693 printk(KERN_ERR "FCP EQ[Idx:%d|Qid:%d]\n", eq_idx, qid);
0694 lpfc_debug_dump_q(phba->sli4_hba.hdwq[eq_idx].hba_eq);
0695 return;
0696 }
0697 }
0698
0699 void lpfc_debug_dump_all_queues(struct lpfc_hba *);