scsi/isci/probe_roms.h

0001 /*
0002  * This file is provided under a dual BSD/GPLv2 license.  When using or
0003  * redistributing this file, you may do so under either license.
0004  *
0005  * GPL LICENSE SUMMARY
0006  *
0007  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
0008  *
0009  * This program is free software; you can redistribute it and/or modify
0010  * it under the terms of version 2 of the GNU General Public License as
0011  * published by the Free Software Foundation.
0012  *
0013  * This program is distributed in the hope that it will be useful, but
0014  * WITHOUT ANY WARRANTY; without even the implied warranty of
0015  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
0016  * General Public License for more details.
0017  *
0018  * You should have received a copy of the GNU General Public License
0019  * along with this program; if not, write to the Free Software
0020  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
0021  * The full GNU General Public License is included in this distribution
0022  * in the file called LICENSE.GPL.
0023  *
0024  * BSD LICENSE
0025  *
0026  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
0027  * All rights reserved.
0028  *
0029  * Redistribution and use in source and binary forms, with or without
0030  * modification, are permitted provided that the following conditions
0031  * are met:
0032  *
0033  *   * Redistributions of source code must retain the above copyright
0034  *     notice, this list of conditions and the following disclaimer.
0035  *   * Redistributions in binary form must reproduce the above copyright
0036  *     notice, this list of conditions and the following disclaimer in
0037  *     the documentation and/or other materials provided with the
0038  *     distribution.
0039  *   * Neither the name of Intel Corporation nor the names of its
0040  *     contributors may be used to endorse or promote products derived
0041  *     from this software without specific prior written permission.
0042  *
0043  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0044  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0045  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0046  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0047  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0048  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0049  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0050  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0051  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0052  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0053  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0054  */
0055 #ifndef _ISCI_PROBE_ROMS_H_
0056 #define _ISCI_PROBE_ROMS_H_
0057
0058 #ifdef __KERNEL__
0059 #include <linux/firmware.h>
0060 #include <linux/pci.h>
0061 #include <linux/efi.h>
0062 #include "isci.h"
0063
0064 #define SCIC_SDS_PARM_NO_SPEED   0
0065
0066 /* generation 1 (i.e. 1.5 Gb/s) */
0067 #define SCIC_SDS_PARM_GEN1_SPEED 1
0068
0069 /* generation 2 (i.e. 3.0 Gb/s) */
0070 #define SCIC_SDS_PARM_GEN2_SPEED 2
0071
0072 /* generation 3 (i.e. 6.0 Gb/s) */
0073 #define SCIC_SDS_PARM_GEN3_SPEED 3
0074 #define SCIC_SDS_PARM_MAX_SPEED SCIC_SDS_PARM_GEN3_SPEED
0075
0076 /* parameters that can be set by module parameters */
0077 struct sci_user_parameters {
0078     struct sci_phy_user_params {
0079         /**
0080          * This field specifies the NOTIFY (ENABLE SPIN UP) primitive
0081          * insertion frequency for this phy index.
0082          */
0083         u32 notify_enable_spin_up_insertion_frequency;
0084
0085         /**
0086          * This method specifies the number of transmitted DWORDs within which
0087          * to transmit a single ALIGN primitive.  This value applies regardless
0088          * of what type of device is attached or connection state.  A value of
0089          * 0 indicates that no ALIGN primitives will be inserted.
0090          */
0091         u16 align_insertion_frequency;
0092
0093         /**
0094          * This method specifies the number of transmitted DWORDs within which
0095          * to transmit 2 ALIGN primitives.  This applies for SAS connections
0096          * only.  A minimum value of 3 is required for this field.
0097          */
0098         u16 in_connection_align_insertion_frequency;
0099
0100         /**
0101          * This field indicates the maximum speed generation to be utilized
0102          * by phys in the supplied port.
0103          * - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s).
0104          * - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s).
0105          * - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s).
0106          */
0107         u8 max_speed_generation;
0108
0109     } phys[SCI_MAX_PHYS];
0110
0111     /**
0112      * This field specifies the maximum number of direct attached devices
0113      * that can have power supplied to them simultaneously.
0114      */
0115     u8 max_concurr_spinup;
0116
0117     /**
0118      * This field specifies the number of seconds to allow a phy to consume
0119      * power before yielding to another phy.
0120      *
0121      */
0122     u8 phy_spin_up_delay_interval;
0123
0124     /**
0125      * These timer values specifies how long a link will remain open with no
0126      * activity in increments of a microsecond, it can be in increments of
0127      * 100 microseconds if the upper most bit is set.
0128      *
0129      */
0130     u16 stp_inactivity_timeout;
0131     u16 ssp_inactivity_timeout;
0132
0133     /**
0134      * These timer values specifies how long a link will remain open in increments
0135      * of 100 microseconds.
0136      *
0137      */
0138     u16 stp_max_occupancy_timeout;
0139     u16 ssp_max_occupancy_timeout;
0140
0141     /**
0142      * This timer value specifies how long a link will remain open with no
0143      * outbound traffic in increments of a microsecond.
0144      *
0145      */
0146     u8 no_outbound_task_timeout;
0147
0148 };
0149
0150 #define SCIC_SDS_PARM_PHY_MASK_MIN 0x0
0151 #define SCIC_SDS_PARM_PHY_MASK_MAX 0xF
0152 #define MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT 4
0153
0154 struct sci_oem_params;
0155 int sci_oem_parameters_validate(struct sci_oem_params *oem, u8 version);
0156
0157 struct isci_orom;
0158 struct isci_orom *isci_request_oprom(struct pci_dev *pdev);
0159 struct isci_orom *isci_request_firmware(struct pci_dev *pdev, const struct firmware *fw);
0160 struct isci_orom *isci_get_efi_var(struct pci_dev *pdev);
0161
0162 struct isci_oem_hdr {
0163     u8 sig[4];
0164     u8 rev_major;
0165     u8 rev_minor;
0166     u16 len;
0167     u8 checksum;
0168     u8 reserved1;
0169     u16 reserved2;
0170 } __attribute__ ((packed));
0171
0172 #else
0173 #define SCI_MAX_PORTS 4
0174 #define SCI_MAX_PHYS 4
0175 #define SCI_MAX_CONTROLLERS 2
0176 #endif
0177
0178 #define ISCI_FW_NAME        "isci/isci_firmware.bin"
0179
0180 #define ROMSIGNATURE        0xaa55
0181
0182 #define ISCI_OEM_SIG        "$OEM"
0183 #define ISCI_OEM_SIG_SIZE   4
0184 #define ISCI_ROM_SIG        "ISCUOEMB"
0185 #define ISCI_ROM_SIG_SIZE   8
0186
0187 #define ISCI_EFI_VENDOR_GUID    \
0188     EFI_GUID(0x193dfefa, 0xa445, 0x4302, 0x99, 0xd8, 0xef, 0x3a, 0xad, \
0189             0x1a, 0x04, 0xc6)
0190 #define ISCI_EFI_VAR_NAME   "RstScuO"
0191
0192 #define ISCI_ROM_VER_1_0    0x10
0193 #define ISCI_ROM_VER_1_1    0x11
0194 #define ISCI_ROM_VER_1_3    0x13
0195 #define ISCI_ROM_VER_LATEST ISCI_ROM_VER_1_3
0196
0197 /* Allowed PORT configuration modes APC Automatic PORT configuration mode is
0198  * defined by the OEM configuration parameters providing no PHY_MASK parameters
0199  * for any PORT. i.e. There are no phys assigned to any of the ports at start.
0200  * MPC Manual PORT configuration mode is defined by the OEM configuration
0201  * parameters providing a PHY_MASK value for any PORT.  It is assumed that any
0202  * PORT with no PHY_MASK is an invalid port and not all PHYs must be assigned.
0203  * A PORT_PHY mask that assigns just a single PHY to a port and no other PHYs
0204  * being assigned is sufficient to declare manual PORT configuration.
0205  */
0206 enum sci_port_configuration_mode {
0207     SCIC_PORT_MANUAL_CONFIGURATION_MODE = 0,
0208     SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE = 1
0209 };
0210
0211 struct sci_bios_oem_param_block_hdr {
0212     uint8_t signature[ISCI_ROM_SIG_SIZE];
0213     uint16_t total_block_length;
0214     uint8_t hdr_length;
0215     uint8_t version;
0216     uint8_t preboot_source;
0217     uint8_t num_elements;
0218     uint16_t element_length;
0219     uint8_t reserved[8];
0220 } __attribute__ ((packed));
0221
0222 struct sci_oem_params {
0223     struct {
0224         uint8_t mode_type;
0225         uint8_t max_concurr_spin_up;
0226         /*
0227          * This bitfield indicates the OEM's desired default Tx
0228          * Spread Spectrum Clocking (SSC) settings for SATA and SAS.
0229          * NOTE: Default SSC Modulation Frequency is 31.5KHz.
0230          */
0231         union {
0232             struct {
0233             /*
0234              * NOTE: Max spread for SATA is +0 / -5000 PPM.
0235              * Down-spreading SSC (only method allowed for SATA):
0236              *  SATA SSC Tx Disabled                    = 0x0
0237              *  SATA SSC Tx at +0 / -1419 PPM Spread    = 0x2
0238              *  SATA SSC Tx at +0 / -2129 PPM Spread    = 0x3
0239              *  SATA SSC Tx at +0 / -4257 PPM Spread    = 0x6
0240              *  SATA SSC Tx at +0 / -4967 PPM Spread    = 0x7
0241              */
0242                 uint8_t ssc_sata_tx_spread_level:4;
0243             /*
0244              * SAS SSC Tx Disabled                     = 0x0
0245              *
0246              * NOTE: Max spread for SAS down-spreading +0 /
0247              *   -2300 PPM
0248              * Down-spreading SSC:
0249              *  SAS SSC Tx at +0 / -1419 PPM Spread     = 0x2
0250              *  SAS SSC Tx at +0 / -2129 PPM Spread     = 0x3
0251              *
0252              * NOTE: Max spread for SAS center-spreading +2300 /
0253              *   -2300 PPM
0254              * Center-spreading SSC:
0255              *  SAS SSC Tx at +1064 / -1064 PPM Spread  = 0x3
0256              *  SAS SSC Tx at +2129 / -2129 PPM Spread  = 0x6
0257              */
0258                 uint8_t ssc_sas_tx_spread_level:3;
0259             /*
0260              * NOTE: Refer to the SSC section of the SAS 2.x
0261              * Specification for proper setting of this field.
0262              * For standard SAS Initiator SAS PHY operation it
0263              * should be 0 for Down-spreading.
0264              * SAS SSC Tx spread type:
0265              *  Down-spreading SSC      = 0
0266              *  Center-spreading SSC    = 1
0267              */
0268                 uint8_t ssc_sas_tx_type:1;
0269             };
0270             uint8_t do_enable_ssc;
0271         };
0272         /*
0273          * This field indicates length of the SAS/SATA cable between
0274          * host and device.
0275          * This field is used make relationship between analog
0276          * parameters of the phy in the silicon and length of the cable.
0277          * Supported cable attenuation levels:
0278          * "short"- up to 3m, "medium"-3m to 6m, and "long"- more than
0279          * 6m.
0280          *
0281          * This is bit mask field:
0282          *
0283          * BIT:      (MSB) 7     6     5     4
0284          * ASSIGNMENT:   <phy3><phy2><phy1><phy0>  - Medium cable
0285          *                                           length assignment
0286          * BIT:            3     2     1     0  (LSB)
0287          * ASSIGNMENT:   <phy3><phy2><phy1><phy0>  - Long cable length
0288          *                                           assignment
0289          *
0290          * BITS 7-4 are set when the cable length is assigned to medium
0291          * BITS 3-0 are set when the cable length is assigned to long
0292          *
0293          * The BIT positions are clear when the cable length is
0294          * assigned to short.
0295          *
0296          * Setting the bits for both long and medium cable length is
0297          * undefined.
0298          *
0299          * A value of 0x84 would assign
0300          *    phy3 - medium
0301          *    phy2 - long
0302          *    phy1 - short
0303          *    phy0 - short
0304          */
0305         uint8_t cable_selection_mask;
0306     } controller;
0307
0308     struct {
0309         uint8_t phy_mask;
0310     } ports[SCI_MAX_PORTS];
0311
0312     struct sci_phy_oem_params {
0313         struct {
0314             uint32_t high;
0315             uint32_t low;
0316         } sas_address;
0317
0318         uint32_t afe_tx_amp_control0;
0319         uint32_t afe_tx_amp_control1;
0320         uint32_t afe_tx_amp_control2;
0321         uint32_t afe_tx_amp_control3;
0322     } phys[SCI_MAX_PHYS];
0323 } __attribute__ ((packed));
0324
0325 struct isci_orom {
0326     struct sci_bios_oem_param_block_hdr hdr;
0327     struct sci_oem_params ctrl[SCI_MAX_CONTROLLERS];
0328 } __attribute__ ((packed));
0329
0330 #endif