scsi/isci/phy.c

0001 /*
0002  * This file is provided under a dual BSD/GPLv2 license.  When using or
0003  * redistributing this file, you may do so under either license.
0004  *
0005  * GPL LICENSE SUMMARY
0006  *
0007  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
0008  *
0009  * This program is free software; you can redistribute it and/or modify
0010  * it under the terms of version 2 of the GNU General Public License as
0011  * published by the Free Software Foundation.
0012  *
0013  * This program is distributed in the hope that it will be useful, but
0014  * WITHOUT ANY WARRANTY; without even the implied warranty of
0015  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
0016  * General Public License for more details.
0017  *
0018  * You should have received a copy of the GNU General Public License
0019  * along with this program; if not, write to the Free Software
0020  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
0021  * The full GNU General Public License is included in this distribution
0022  * in the file called LICENSE.GPL.
0023  *
0024  * BSD LICENSE
0025  *
0026  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
0027  * All rights reserved.
0028  *
0029  * Redistribution and use in source and binary forms, with or without
0030  * modification, are permitted provided that the following conditions
0031  * are met:
0032  *
0033  *   * Redistributions of source code must retain the above copyright
0034  *     notice, this list of conditions and the following disclaimer.
0035  *   * Redistributions in binary form must reproduce the above copyright
0036  *     notice, this list of conditions and the following disclaimer in
0037  *     the documentation and/or other materials provided with the
0038  *     distribution.
0039  *   * Neither the name of Intel Corporation nor the names of its
0040  *     contributors may be used to endorse or promote products derived
0041  *     from this software without specific prior written permission.
0042  *
0043  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0044  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0045  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0046  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0047  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0048  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0049  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0050  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0051  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0052  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0053  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0054  */
0055
0056 #include "isci.h"
0057 #include "host.h"
0058 #include "phy.h"
0059 #include "scu_event_codes.h"
0060 #include "probe_roms.h"
0061
0062 #undef C
0063 #define C(a) (#a)
0064 static const char *phy_state_name(enum sci_phy_states state)
0065 {
0066     static const char * const strings[] = PHY_STATES;
0067
0068     return strings[state];
0069 }
0070 #undef C
0071
0072 /* Maximum arbitration wait time in micro-seconds */
0073 #define SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME  (700)
0074
0075 enum sas_linkrate sci_phy_linkrate(struct isci_phy *iphy)
0076 {
0077     return iphy->max_negotiated_speed;
0078 }
0079
0080 static struct isci_host *phy_to_host(struct isci_phy *iphy)
0081 {
0082     struct isci_phy *table = iphy - iphy->phy_index;
0083     struct isci_host *ihost = container_of(table, typeof(*ihost), phys[0]);
0084
0085     return ihost;
0086 }
0087
0088 static struct device *sciphy_to_dev(struct isci_phy *iphy)
0089 {
0090     return &phy_to_host(iphy)->pdev->dev;
0091 }
0092
0093 static enum sci_status
0094 sci_phy_transport_layer_initialization(struct isci_phy *iphy,
0095                        struct scu_transport_layer_registers __iomem *reg)
0096 {
0097     u32 tl_control;
0098
0099     iphy->transport_layer_registers = reg;
0100
0101     writel(SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX,
0102         &iphy->transport_layer_registers->stp_rni);
0103
0104     /*
0105      * Hardware team recommends that we enable the STP prefetch for all
0106      * transports
0107      */
0108     tl_control = readl(&iphy->transport_layer_registers->control);
0109     tl_control |= SCU_TLCR_GEN_BIT(STP_WRITE_DATA_PREFETCH);
0110     writel(tl_control, &iphy->transport_layer_registers->control);
0111
0112     return SCI_SUCCESS;
0113 }
0114
0115 static enum sci_status
0116 sci_phy_link_layer_initialization(struct isci_phy *iphy,
0117                   struct scu_link_layer_registers __iomem *llr)
0118 {
0119     struct isci_host *ihost = iphy->owning_port->owning_controller;
0120     struct sci_phy_user_params *phy_user;
0121     struct sci_phy_oem_params *phy_oem;
0122     int phy_idx = iphy->phy_index;
0123     struct sci_phy_cap phy_cap;
0124     u32 phy_configuration;
0125     u32 parity_check = 0;
0126     u32 parity_count = 0;
0127     u32 llctl, link_rate;
0128     u32 clksm_value = 0;
0129     u32 sp_timeouts = 0;
0130
0131     phy_user = &ihost->user_parameters.phys[phy_idx];
0132     phy_oem = &ihost->oem_parameters.phys[phy_idx];
0133     iphy->link_layer_registers = llr;
0134
0135     /* Set our IDENTIFY frame data */
0136     #define SCI_END_DEVICE 0x01
0137
0138     writel(SCU_SAS_TIID_GEN_BIT(SMP_INITIATOR) |
0139            SCU_SAS_TIID_GEN_BIT(SSP_INITIATOR) |
0140            SCU_SAS_TIID_GEN_BIT(STP_INITIATOR) |
0141            SCU_SAS_TIID_GEN_BIT(DA_SATA_HOST) |
0142            SCU_SAS_TIID_GEN_VAL(DEVICE_TYPE, SCI_END_DEVICE),
0143            &llr->transmit_identification);
0144
0145     /* Write the device SAS Address */
0146     writel(0xFEDCBA98, &llr->sas_device_name_high);
0147     writel(phy_idx, &llr->sas_device_name_low);
0148
0149     /* Write the source SAS Address */
0150     writel(phy_oem->sas_address.high, &llr->source_sas_address_high);
0151     writel(phy_oem->sas_address.low, &llr->source_sas_address_low);
0152
0153     /* Clear and Set the PHY Identifier */
0154     writel(0, &llr->identify_frame_phy_id);
0155     writel(SCU_SAS_TIPID_GEN_VALUE(ID, phy_idx), &llr->identify_frame_phy_id);
0156
0157     /* Change the initial state of the phy configuration register */
0158     phy_configuration = readl(&llr->phy_configuration);
0159
0160     /* Hold OOB state machine in reset */
0161     phy_configuration |=  SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
0162     writel(phy_configuration, &llr->phy_configuration);
0163
0164     /* Configure the SNW capabilities */
0165     phy_cap.all = 0;
0166     phy_cap.start = 1;
0167     phy_cap.gen3_no_ssc = 1;
0168     phy_cap.gen2_no_ssc = 1;
0169     phy_cap.gen1_no_ssc = 1;
0170     if (ihost->oem_parameters.controller.do_enable_ssc) {
0171         struct scu_afe_registers __iomem *afe = &ihost->scu_registers->afe;
0172         struct scu_afe_transceiver __iomem *xcvr = &afe->scu_afe_xcvr[phy_idx];
0173         struct isci_pci_info *pci_info = to_pci_info(ihost->pdev);
0174         bool en_sas = false;
0175         bool en_sata = false;
0176         u32 sas_type = 0;
0177         u32 sata_spread = 0x2;
0178         u32 sas_spread = 0x2;
0179
0180         phy_cap.gen3_ssc = 1;
0181         phy_cap.gen2_ssc = 1;
0182         phy_cap.gen1_ssc = 1;
0183
0184         if (pci_info->orom->hdr.version < ISCI_ROM_VER_1_1)
0185             en_sas = en_sata = true;
0186         else {
0187             sata_spread = ihost->oem_parameters.controller.ssc_sata_tx_spread_level;
0188             sas_spread = ihost->oem_parameters.controller.ssc_sas_tx_spread_level;
0189
0190             if (sata_spread)
0191                 en_sata = true;
0192
0193             if (sas_spread) {
0194                 en_sas = true;
0195                 sas_type = ihost->oem_parameters.controller.ssc_sas_tx_type;
0196             }
0197
0198         }
0199
0200         if (en_sas) {
0201             u32 reg;
0202
0203             reg = readl(&xcvr->afe_xcvr_control0);
0204             reg |= (0x00100000 | (sas_type << 19));
0205             writel(reg, &xcvr->afe_xcvr_control0);
0206
0207             reg = readl(&xcvr->afe_tx_ssc_control);
0208             reg |= sas_spread << 8;
0209             writel(reg, &xcvr->afe_tx_ssc_control);
0210         }
0211
0212         if (en_sata) {
0213             u32 reg;
0214
0215             reg = readl(&xcvr->afe_tx_ssc_control);
0216             reg |= sata_spread;
0217             writel(reg, &xcvr->afe_tx_ssc_control);
0218
0219             reg = readl(&llr->stp_control);
0220             reg |= 1 << 12;
0221             writel(reg, &llr->stp_control);
0222         }
0223     }
0224
0225     /* The SAS specification indicates that the phy_capabilities that
0226      * are transmitted shall have an even parity.  Calculate the parity.
0227      */
0228     parity_check = phy_cap.all;
0229     while (parity_check != 0) {
0230         if (parity_check & 0x1)
0231             parity_count++;
0232         parity_check >>= 1;
0233     }
0234
0235     /* If parity indicates there are an odd number of bits set, then
0236      * set the parity bit to 1 in the phy capabilities.
0237      */
0238     if ((parity_count % 2) != 0)
0239         phy_cap.parity = 1;
0240
0241     writel(phy_cap.all, &llr->phy_capabilities);
0242
0243     /* Set the enable spinup period but disable the ability to send
0244      * notify enable spinup
0245      */
0246     writel(SCU_ENSPINUP_GEN_VAL(COUNT,
0247             phy_user->notify_enable_spin_up_insertion_frequency),
0248         &llr->notify_enable_spinup_control);
0249
0250     /* Write the ALIGN Insertion Ferequency for connected phy and
0251      * inpendent of connected state
0252      */
0253     clksm_value = SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(CONNECTED,
0254             phy_user->in_connection_align_insertion_frequency);
0255
0256     clksm_value |= SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(GENERAL,
0257             phy_user->align_insertion_frequency);
0258
0259     writel(clksm_value, &llr->clock_skew_management);
0260
0261     if (is_c0(ihost->pdev) || is_c1(ihost->pdev)) {
0262         writel(0x04210400, &llr->afe_lookup_table_control);
0263         writel(0x020A7C05, &llr->sas_primitive_timeout);
0264     } else
0265         writel(0x02108421, &llr->afe_lookup_table_control);
0266
0267     llctl = SCU_SAS_LLCTL_GEN_VAL(NO_OUTBOUND_TASK_TIMEOUT,
0268         (u8)ihost->user_parameters.no_outbound_task_timeout);
0269
0270     switch (phy_user->max_speed_generation) {
0271     case SCIC_SDS_PARM_GEN3_SPEED:
0272         link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN3;
0273         break;
0274     case SCIC_SDS_PARM_GEN2_SPEED:
0275         link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN2;
0276         break;
0277     default:
0278         link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1;
0279         break;
0280     }
0281     llctl |= SCU_SAS_LLCTL_GEN_VAL(MAX_LINK_RATE, link_rate);
0282     writel(llctl, &llr->link_layer_control);
0283
0284     sp_timeouts = readl(&llr->sas_phy_timeouts);
0285
0286     /* Clear the default 0x36 (54us) RATE_CHANGE timeout value. */
0287     sp_timeouts &= ~SCU_SAS_PHYTOV_GEN_VAL(RATE_CHANGE, 0xFF);
0288
0289     /* Set RATE_CHANGE timeout value to 0x3B (59us).  This ensures SCU can
0290      * lock with 3Gb drive when SCU max rate is set to 1.5Gb.
0291      */
0292     sp_timeouts |= SCU_SAS_PHYTOV_GEN_VAL(RATE_CHANGE, 0x3B);
0293
0294     writel(sp_timeouts, &llr->sas_phy_timeouts);
0295
0296     if (is_a2(ihost->pdev)) {
0297         /* Program the max ARB time for the PHY to 700us so we
0298          * inter-operate with the PMC expander which shuts down
0299          * PHYs if the expander PHY generates too many breaks.
0300          * This time value will guarantee that the initiator PHY
0301          * will generate the break.
0302          */
0303         writel(SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME,
0304                &llr->maximum_arbitration_wait_timer_timeout);
0305     }
0306
0307     /* Disable link layer hang detection, rely on the OS timeout for
0308      * I/O timeouts.
0309      */
0310     writel(0, &llr->link_layer_hang_detection_timeout);
0311
0312     /* We can exit the initial state to the stopped state */
0313     sci_change_state(&iphy->sm, SCI_PHY_STOPPED);
0314
0315     return SCI_SUCCESS;
0316 }
0317
0318 static void phy_sata_timeout(struct timer_list *t)
0319 {
0320     struct sci_timer *tmr = from_timer(tmr, t, timer);
0321     struct isci_phy *iphy = container_of(tmr, typeof(*iphy), sata_timer);
0322     struct isci_host *ihost = iphy->owning_port->owning_controller;
0323     unsigned long flags;
0324
0325     spin_lock_irqsave(&ihost->scic_lock, flags);
0326
0327     if (tmr->cancel)
0328         goto done;
0329
0330     dev_dbg(sciphy_to_dev(iphy),
0331          "%s: SCIC SDS Phy 0x%p did not receive signature fis before "
0332          "timeout.\n",
0333          __func__,
0334          iphy);
0335
0336     sci_change_state(&iphy->sm, SCI_PHY_STARTING);
0337 done:
0338     spin_unlock_irqrestore(&ihost->scic_lock, flags);
0339 }
0340
0341 /**
0342  * phy_get_non_dummy_port() - This method returns the port currently containing
0343  * this phy. If the phy is currently contained by the dummy port, then the phy
0344  * is considered to not be part of a port.
0345  *
0346  * @iphy: This parameter specifies the phy for which to retrieve the
0347  *    containing port.
0348  *
0349  * This method returns a handle to a port that contains the supplied phy.
0350  * NULL This value is returned if the phy is not part of a real
0351  * port (i.e. it's contained in the dummy port). !NULL All other
0352  * values indicate a handle/pointer to the port containing the phy.
0353  */
0354 struct isci_port *phy_get_non_dummy_port(struct isci_phy *iphy)
0355 {
0356     struct isci_port *iport = iphy->owning_port;
0357
0358     if (iport->physical_port_index == SCIC_SDS_DUMMY_PORT)
0359         return NULL;
0360
0361     return iphy->owning_port;
0362 }
0363
0364 /*
0365  * sci_phy_set_port() - This method will assign a port to the phy object.
0366  */
0367 void sci_phy_set_port(
0368     struct isci_phy *iphy,
0369     struct isci_port *iport)
0370 {
0371     iphy->owning_port = iport;
0372
0373     if (iphy->bcn_received_while_port_unassigned) {
0374         iphy->bcn_received_while_port_unassigned = false;
0375         sci_port_broadcast_change_received(iphy->owning_port, iphy);
0376     }
0377 }
0378
0379 enum sci_status sci_phy_initialize(struct isci_phy *iphy,
0380                    struct scu_transport_layer_registers __iomem *tl,
0381                    struct scu_link_layer_registers __iomem *ll)
0382 {
0383     /* Perfrom the initialization of the TL hardware */
0384     sci_phy_transport_layer_initialization(iphy, tl);
0385
0386     /* Perofrm the initialization of the PE hardware */
0387     sci_phy_link_layer_initialization(iphy, ll);
0388
0389     /* There is nothing that needs to be done in this state just
0390      * transition to the stopped state
0391      */
0392     sci_change_state(&iphy->sm, SCI_PHY_STOPPED);
0393
0394     return SCI_SUCCESS;
0395 }
0396
0397 /**
0398  * sci_phy_setup_transport() - This method assigns the direct attached device ID for this phy.
0399  *
0400  * @iphy: The phy for which the direct attached device id is to
0401  *       be assigned.
0402  * @device_id: The direct attached device ID to assign to the phy.
0403  *       This will either be the RNi for the device or an invalid RNi if there
0404  *       is no current device assigned to the phy.
0405  */
0406 void sci_phy_setup_transport(struct isci_phy *iphy, u32 device_id)
0407 {
0408     u32 tl_control;
0409
0410     writel(device_id, &iphy->transport_layer_registers->stp_rni);
0411
0412     /*
0413      * The read should guarantee that the first write gets posted
0414      * before the next write
0415      */
0416     tl_control = readl(&iphy->transport_layer_registers->control);
0417     tl_control |= SCU_TLCR_GEN_BIT(CLEAR_TCI_NCQ_MAPPING_TABLE);
0418     writel(tl_control, &iphy->transport_layer_registers->control);
0419 }
0420
0421 static void sci_phy_suspend(struct isci_phy *iphy)
0422 {
0423     u32 scu_sas_pcfg_value;
0424
0425     scu_sas_pcfg_value =
0426         readl(&iphy->link_layer_registers->phy_configuration);
0427     scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE);
0428     writel(scu_sas_pcfg_value,
0429         &iphy->link_layer_registers->phy_configuration);
0430
0431     sci_phy_setup_transport(iphy, SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX);
0432 }
0433
0434 void sci_phy_resume(struct isci_phy *iphy)
0435 {
0436     u32 scu_sas_pcfg_value;
0437
0438     scu_sas_pcfg_value =
0439         readl(&iphy->link_layer_registers->phy_configuration);
0440     scu_sas_pcfg_value &= ~SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE);
0441     writel(scu_sas_pcfg_value,
0442         &iphy->link_layer_registers->phy_configuration);
0443 }
0444
0445 void sci_phy_get_sas_address(struct isci_phy *iphy, struct sci_sas_address *sas)
0446 {
0447     sas->high = readl(&iphy->link_layer_registers->source_sas_address_high);
0448     sas->low = readl(&iphy->link_layer_registers->source_sas_address_low);
0449 }
0450
0451 void sci_phy_get_attached_sas_address(struct isci_phy *iphy, struct sci_sas_address *sas)
0452 {
0453     struct sas_identify_frame *iaf;
0454
0455     iaf = &iphy->frame_rcvd.iaf;
0456     memcpy(sas, iaf->sas_addr, SAS_ADDR_SIZE);
0457 }
0458
0459 void sci_phy_get_protocols(struct isci_phy *iphy, struct sci_phy_proto *proto)
0460 {
0461     proto->all = readl(&iphy->link_layer_registers->transmit_identification);
0462 }
0463
0464 enum sci_status sci_phy_start(struct isci_phy *iphy)
0465 {
0466     enum sci_phy_states state = iphy->sm.current_state_id;
0467
0468     if (state != SCI_PHY_STOPPED) {
0469         dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n",
0470             __func__, phy_state_name(state));
0471         return SCI_FAILURE_INVALID_STATE;
0472     }
0473
0474     sci_change_state(&iphy->sm, SCI_PHY_STARTING);
0475     return SCI_SUCCESS;
0476 }
0477
0478 enum sci_status sci_phy_stop(struct isci_phy *iphy)
0479 {
0480     enum sci_phy_states state = iphy->sm.current_state_id;
0481
0482     switch (state) {
0483     case SCI_PHY_SUB_INITIAL:
0484     case SCI_PHY_SUB_AWAIT_OSSP_EN:
0485     case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
0486     case SCI_PHY_SUB_AWAIT_SAS_POWER:
0487     case SCI_PHY_SUB_AWAIT_SATA_POWER:
0488     case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
0489     case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
0490     case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
0491     case SCI_PHY_SUB_FINAL:
0492     case SCI_PHY_READY:
0493         break;
0494     default:
0495         dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n",
0496             __func__, phy_state_name(state));
0497         return SCI_FAILURE_INVALID_STATE;
0498     }
0499
0500     sci_change_state(&iphy->sm, SCI_PHY_STOPPED);
0501     return SCI_SUCCESS;
0502 }
0503
0504 enum sci_status sci_phy_reset(struct isci_phy *iphy)
0505 {
0506     enum sci_phy_states state = iphy->sm.current_state_id;
0507
0508     if (state != SCI_PHY_READY) {
0509         dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n",
0510             __func__, phy_state_name(state));
0511         return SCI_FAILURE_INVALID_STATE;
0512     }
0513
0514     sci_change_state(&iphy->sm, SCI_PHY_RESETTING);
0515     return SCI_SUCCESS;
0516 }
0517
0518 enum sci_status sci_phy_consume_power_handler(struct isci_phy *iphy)
0519 {
0520     enum sci_phy_states state = iphy->sm.current_state_id;
0521
0522     switch (state) {
0523     case SCI_PHY_SUB_AWAIT_SAS_POWER: {
0524         u32 enable_spinup;
0525
0526         enable_spinup = readl(&iphy->link_layer_registers->notify_enable_spinup_control);
0527         enable_spinup |= SCU_ENSPINUP_GEN_BIT(ENABLE);
0528         writel(enable_spinup, &iphy->link_layer_registers->notify_enable_spinup_control);
0529
0530         /* Change state to the final state this substate machine has run to completion */
0531         sci_change_state(&iphy->sm, SCI_PHY_SUB_FINAL);
0532
0533         return SCI_SUCCESS;
0534     }
0535     case SCI_PHY_SUB_AWAIT_SATA_POWER: {
0536         u32 scu_sas_pcfg_value;
0537
0538         /* Release the spinup hold state and reset the OOB state machine */
0539         scu_sas_pcfg_value =
0540             readl(&iphy->link_layer_registers->phy_configuration);
0541         scu_sas_pcfg_value &=
0542             ~(SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD) | SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE));
0543         scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
0544         writel(scu_sas_pcfg_value,
0545             &iphy->link_layer_registers->phy_configuration);
0546
0547         /* Now restart the OOB operation */
0548         scu_sas_pcfg_value &= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
0549         scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
0550         writel(scu_sas_pcfg_value,
0551             &iphy->link_layer_registers->phy_configuration);
0552
0553         /* Change state to the final state this substate machine has run to completion */
0554         sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_PHY_EN);
0555
0556         return SCI_SUCCESS;
0557     }
0558     default:
0559         dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n",
0560             __func__, phy_state_name(state));
0561         return SCI_FAILURE_INVALID_STATE;
0562     }
0563 }
0564
0565 static void sci_phy_start_sas_link_training(struct isci_phy *iphy)
0566 {
0567     /* continue the link training for the phy as if it were a SAS PHY
0568      * instead of a SATA PHY. This is done because the completion queue had a SAS
0569      * PHY DETECTED event when the state machine was expecting a SATA PHY event.
0570      */
0571     u32 phy_control;
0572
0573     phy_control = readl(&iphy->link_layer_registers->phy_configuration);
0574     phy_control |= SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD);
0575     writel(phy_control,
0576            &iphy->link_layer_registers->phy_configuration);
0577
0578     sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SAS_SPEED_EN);
0579
0580     iphy->protocol = SAS_PROTOCOL_SSP;
0581 }
0582
0583 static void sci_phy_start_sata_link_training(struct isci_phy *iphy)
0584 {
0585     /* This method continues the link training for the phy as if it were a SATA PHY
0586      * instead of a SAS PHY.  This is done because the completion queue had a SATA
0587      * SPINUP HOLD event when the state machine was expecting a SAS PHY event. none
0588      */
0589     sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_POWER);
0590
0591     iphy->protocol = SAS_PROTOCOL_SATA;
0592 }
0593
0594 /**
0595  * sci_phy_complete_link_training - perform processing common to
0596  *    all protocols upon completion of link training.
0597  * @iphy: This parameter specifies the phy object for which link training
0598  *    has completed.
0599  * @max_link_rate: This parameter specifies the maximum link rate to be
0600  *    associated with this phy.
0601  * @next_state: This parameter specifies the next state for the phy's starting
0602  *    sub-state machine.
0603  *
0604  */
0605 static void sci_phy_complete_link_training(struct isci_phy *iphy,
0606                        enum sas_linkrate max_link_rate,
0607                        u32 next_state)
0608 {
0609     iphy->max_negotiated_speed = max_link_rate;
0610
0611     sci_change_state(&iphy->sm, next_state);
0612 }
0613
0614 static const char *phy_event_name(u32 event_code)
0615 {
0616     switch (scu_get_event_code(event_code)) {
0617     case SCU_EVENT_PORT_SELECTOR_DETECTED:
0618         return "port selector";
0619     case SCU_EVENT_SENT_PORT_SELECTION:
0620         return "port selection";
0621     case SCU_EVENT_HARD_RESET_TRANSMITTED:
0622         return "tx hard reset";
0623     case SCU_EVENT_HARD_RESET_RECEIVED:
0624         return "rx hard reset";
0625     case SCU_EVENT_RECEIVED_IDENTIFY_TIMEOUT:
0626         return "identify timeout";
0627     case SCU_EVENT_LINK_FAILURE:
0628         return "link fail";
0629     case SCU_EVENT_SATA_SPINUP_HOLD:
0630         return "sata spinup hold";
0631     case SCU_EVENT_SAS_15_SSC:
0632     case SCU_EVENT_SAS_15:
0633         return "sas 1.5";
0634     case SCU_EVENT_SAS_30_SSC:
0635     case SCU_EVENT_SAS_30:
0636         return "sas 3.0";
0637     case SCU_EVENT_SAS_60_SSC:
0638     case SCU_EVENT_SAS_60:
0639         return "sas 6.0";
0640     case SCU_EVENT_SATA_15_SSC:
0641     case SCU_EVENT_SATA_15:
0642         return "sata 1.5";
0643     case SCU_EVENT_SATA_30_SSC:
0644     case SCU_EVENT_SATA_30:
0645         return "sata 3.0";
0646     case SCU_EVENT_SATA_60_SSC:
0647     case SCU_EVENT_SATA_60:
0648         return "sata 6.0";
0649     case SCU_EVENT_SAS_PHY_DETECTED:
0650         return "sas detect";
0651     case SCU_EVENT_SATA_PHY_DETECTED:
0652         return "sata detect";
0653     default:
0654         return "unknown";
0655     }
0656 }
0657
0658 #define phy_event_dbg(iphy, state, code) \
0659     dev_dbg(sciphy_to_dev(iphy), "phy-%d:%d: %s event: %s (%x)\n", \
0660         phy_to_host(iphy)->id, iphy->phy_index, \
0661         phy_state_name(state), phy_event_name(code), code)
0662
0663 #define phy_event_warn(iphy, state, code) \
0664     dev_warn(sciphy_to_dev(iphy), "phy-%d:%d: %s event: %s (%x)\n", \
0665         phy_to_host(iphy)->id, iphy->phy_index, \
0666         phy_state_name(state), phy_event_name(code), code)
0667
0668
0669 static void scu_link_layer_set_txcomsas_timeout(struct isci_phy *iphy, u32 timeout)
0670 {
0671     u32 val;
0672
0673     /* Extend timeout */
0674     val = readl(&iphy->link_layer_registers->transmit_comsas_signal);
0675     val &= ~SCU_SAS_LLTXCOMSAS_GEN_VAL(NEGTIME, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_MASK);
0676     val |= SCU_SAS_LLTXCOMSAS_GEN_VAL(NEGTIME, timeout);
0677
0678     writel(val, &iphy->link_layer_registers->transmit_comsas_signal);
0679 }
0680
0681 enum sci_status sci_phy_event_handler(struct isci_phy *iphy, u32 event_code)
0682 {
0683     enum sci_phy_states state = iphy->sm.current_state_id;
0684
0685     switch (state) {
0686     case SCI_PHY_SUB_AWAIT_OSSP_EN:
0687         switch (scu_get_event_code(event_code)) {
0688         case SCU_EVENT_SAS_PHY_DETECTED:
0689             sci_phy_start_sas_link_training(iphy);
0690             iphy->is_in_link_training = true;
0691             break;
0692         case SCU_EVENT_SATA_SPINUP_HOLD:
0693             sci_phy_start_sata_link_training(iphy);
0694             iphy->is_in_link_training = true;
0695             break;
0696         case SCU_EVENT_RECEIVED_IDENTIFY_TIMEOUT:
0697                /* Extend timeout value */
0698                scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_EXTENDED);
0699
0700                /* Start the oob/sn state machine over again */
0701                sci_change_state(&iphy->sm, SCI_PHY_STARTING);
0702                break;
0703         default:
0704             phy_event_dbg(iphy, state, event_code);
0705             return SCI_FAILURE;
0706         }
0707         return SCI_SUCCESS;
0708     case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
0709         switch (scu_get_event_code(event_code)) {
0710         case SCU_EVENT_SAS_PHY_DETECTED:
0711             /*
0712              * Why is this being reported again by the controller?
0713              * We would re-enter this state so just stay here */
0714             break;
0715         case SCU_EVENT_SAS_15:
0716         case SCU_EVENT_SAS_15_SSC:
0717             sci_phy_complete_link_training(iphy, SAS_LINK_RATE_1_5_GBPS,
0718                                SCI_PHY_SUB_AWAIT_IAF_UF);
0719             break;
0720         case SCU_EVENT_SAS_30:
0721         case SCU_EVENT_SAS_30_SSC:
0722             sci_phy_complete_link_training(iphy, SAS_LINK_RATE_3_0_GBPS,
0723                                SCI_PHY_SUB_AWAIT_IAF_UF);
0724             break;
0725         case SCU_EVENT_SAS_60:
0726         case SCU_EVENT_SAS_60_SSC:
0727             sci_phy_complete_link_training(iphy, SAS_LINK_RATE_6_0_GBPS,
0728                                SCI_PHY_SUB_AWAIT_IAF_UF);
0729             break;
0730         case SCU_EVENT_SATA_SPINUP_HOLD:
0731             /*
0732              * We were doing SAS PHY link training and received a SATA PHY event
0733              * continue OOB/SN as if this were a SATA PHY */
0734             sci_phy_start_sata_link_training(iphy);
0735             break;
0736         case SCU_EVENT_LINK_FAILURE:
0737             /* Change the timeout value to default */
0738             scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT);
0739
0740             /* Link failure change state back to the starting state */
0741             sci_change_state(&iphy->sm, SCI_PHY_STARTING);
0742             break;
0743         case SCU_EVENT_RECEIVED_IDENTIFY_TIMEOUT:
0744                /* Extend the timeout value */
0745                scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_EXTENDED);
0746
0747                /* Start the oob/sn state machine over again */
0748                sci_change_state(&iphy->sm, SCI_PHY_STARTING);
0749                break;
0750         default:
0751             phy_event_warn(iphy, state, event_code);
0752             return SCI_FAILURE;
0753         }
0754         return SCI_SUCCESS;
0755     case SCI_PHY_SUB_AWAIT_IAF_UF:
0756         switch (scu_get_event_code(event_code)) {
0757         case SCU_EVENT_SAS_PHY_DETECTED:
0758             /* Backup the state machine */
0759             sci_phy_start_sas_link_training(iphy);
0760             break;
0761         case SCU_EVENT_SATA_SPINUP_HOLD:
0762             /* We were doing SAS PHY link training and received a
0763              * SATA PHY event continue OOB/SN as if this were a
0764              * SATA PHY
0765              */
0766             sci_phy_start_sata_link_training(iphy);
0767             break;
0768         case SCU_EVENT_RECEIVED_IDENTIFY_TIMEOUT:
0769             /* Extend the timeout value */
0770             scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_EXTENDED);
0771
0772             /* Start the oob/sn state machine over again */
0773             sci_change_state(&iphy->sm, SCI_PHY_STARTING);
0774             break;
0775         case SCU_EVENT_LINK_FAILURE:
0776             scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT);
0777             fallthrough;
0778         case SCU_EVENT_HARD_RESET_RECEIVED:
0779             /* Start the oob/sn state machine over again */
0780             sci_change_state(&iphy->sm, SCI_PHY_STARTING);
0781             break;
0782         default:
0783             phy_event_warn(iphy, state, event_code);
0784             return SCI_FAILURE;
0785         }
0786         return SCI_SUCCESS;
0787     case SCI_PHY_SUB_AWAIT_SAS_POWER:
0788         switch (scu_get_event_code(event_code)) {
0789         case SCU_EVENT_LINK_FAILURE:
0790             /* Change the timeout value to default */
0791             scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT);
0792
0793             /* Link failure change state back to the starting state */
0794             sci_change_state(&iphy->sm, SCI_PHY_STARTING);
0795             break;
0796         default:
0797             phy_event_warn(iphy, state, event_code);
0798             return SCI_FAILURE;
0799         }
0800         return SCI_SUCCESS;
0801     case SCI_PHY_SUB_AWAIT_SATA_POWER:
0802         switch (scu_get_event_code(event_code)) {
0803         case SCU_EVENT_LINK_FAILURE:
0804             /* Change the timeout value to default */
0805             scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT);
0806
0807             /* Link failure change state back to the starting state */
0808             sci_change_state(&iphy->sm, SCI_PHY_STARTING);
0809             break;
0810         case SCU_EVENT_SATA_SPINUP_HOLD:
0811             /* These events are received every 10ms and are
0812              * expected while in this state
0813              */
0814             break;
0815
0816         case SCU_EVENT_SAS_PHY_DETECTED:
0817             /* There has been a change in the phy type before OOB/SN for the
0818              * SATA finished start down the SAS link traning path.
0819              */
0820             sci_phy_start_sas_link_training(iphy);
0821             break;
0822
0823         default:
0824             phy_event_warn(iphy, state, event_code);
0825             return SCI_FAILURE;
0826         }
0827         return SCI_SUCCESS;
0828     case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
0829         switch (scu_get_event_code(event_code)) {
0830         case SCU_EVENT_LINK_FAILURE:
0831             /* Change the timeout value to default */
0832             scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT);
0833
0834             /* Link failure change state back to the starting state */
0835             sci_change_state(&iphy->sm, SCI_PHY_STARTING);
0836             break;
0837         case SCU_EVENT_SATA_SPINUP_HOLD:
0838             /* These events might be received since we dont know how many may be in
0839              * the completion queue while waiting for power
0840              */
0841             break;
0842         case SCU_EVENT_SATA_PHY_DETECTED:
0843             iphy->protocol = SAS_PROTOCOL_SATA;
0844
0845             /* We have received the SATA PHY notification change state */
0846             sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_SPEED_EN);
0847             break;
0848         case SCU_EVENT_SAS_PHY_DETECTED:
0849             /* There has been a change in the phy type before OOB/SN for the
0850              * SATA finished start down the SAS link traning path.
0851              */
0852             sci_phy_start_sas_link_training(iphy);
0853             break;
0854         default:
0855             phy_event_warn(iphy, state, event_code);
0856             return SCI_FAILURE;
0857         }
0858         return SCI_SUCCESS;
0859     case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
0860         switch (scu_get_event_code(event_code)) {
0861         case SCU_EVENT_SATA_PHY_DETECTED:
0862             /*
0863              * The hardware reports multiple SATA PHY detected events
0864              * ignore the extras */
0865             break;
0866         case SCU_EVENT_SATA_15:
0867         case SCU_EVENT_SATA_15_SSC:
0868             sci_phy_complete_link_training(iphy, SAS_LINK_RATE_1_5_GBPS,
0869                                SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
0870             break;
0871         case SCU_EVENT_SATA_30:
0872         case SCU_EVENT_SATA_30_SSC:
0873             sci_phy_complete_link_training(iphy, SAS_LINK_RATE_3_0_GBPS,
0874                                SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
0875             break;
0876         case SCU_EVENT_SATA_60:
0877         case SCU_EVENT_SATA_60_SSC:
0878             sci_phy_complete_link_training(iphy, SAS_LINK_RATE_6_0_GBPS,
0879                                SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
0880             break;
0881         case SCU_EVENT_LINK_FAILURE:
0882             /* Change the timeout value to default */
0883             scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT);
0884
0885             /* Link failure change state back to the starting state */
0886             sci_change_state(&iphy->sm, SCI_PHY_STARTING);
0887             break;
0888         case SCU_EVENT_SAS_PHY_DETECTED:
0889             /*
0890              * There has been a change in the phy type before OOB/SN for the
0891              * SATA finished start down the SAS link traning path. */
0892             sci_phy_start_sas_link_training(iphy);
0893             break;
0894         default:
0895             phy_event_warn(iphy, state, event_code);
0896             return SCI_FAILURE;
0897         }
0898
0899         return SCI_SUCCESS;
0900     case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
0901         switch (scu_get_event_code(event_code)) {
0902         case SCU_EVENT_SATA_PHY_DETECTED:
0903             /* Backup the state machine */
0904             sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_SPEED_EN);
0905             break;
0906
0907         case SCU_EVENT_LINK_FAILURE:
0908             /* Change the timeout value to default */
0909             scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT);
0910
0911             /* Link failure change state back to the starting state */
0912             sci_change_state(&iphy->sm, SCI_PHY_STARTING);
0913             break;
0914
0915         default:
0916             phy_event_warn(iphy, state, event_code);
0917             return SCI_FAILURE;
0918         }
0919         return SCI_SUCCESS;
0920     case SCI_PHY_READY:
0921         switch (scu_get_event_code(event_code)) {
0922         case SCU_EVENT_LINK_FAILURE:
0923             /* Set default timeout */
0924             scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT);
0925
0926             /* Link failure change state back to the starting state */
0927             sci_change_state(&iphy->sm, SCI_PHY_STARTING);
0928             break;
0929         case SCU_EVENT_BROADCAST_CHANGE:
0930         case SCU_EVENT_BROADCAST_SES:
0931         case SCU_EVENT_BROADCAST_RESERVED0:
0932         case SCU_EVENT_BROADCAST_RESERVED1:
0933         case SCU_EVENT_BROADCAST_EXPANDER:
0934         case SCU_EVENT_BROADCAST_AEN:
0935             /* Broadcast change received. Notify the port. */
0936             if (phy_get_non_dummy_port(iphy) != NULL)
0937                 sci_port_broadcast_change_received(iphy->owning_port, iphy);
0938             else
0939                 iphy->bcn_received_while_port_unassigned = true;
0940             break;
0941         case SCU_EVENT_BROADCAST_RESERVED3:
0942         case SCU_EVENT_BROADCAST_RESERVED4:
0943         default:
0944             phy_event_warn(iphy, state, event_code);
0945             return SCI_FAILURE_INVALID_STATE;
0946         }
0947         return SCI_SUCCESS;
0948     case SCI_PHY_RESETTING:
0949         switch (scu_get_event_code(event_code)) {
0950         case SCU_EVENT_HARD_RESET_TRANSMITTED:
0951             /* Link failure change state back to the starting state */
0952             sci_change_state(&iphy->sm, SCI_PHY_STARTING);
0953             break;
0954         default:
0955             phy_event_warn(iphy, state, event_code);
0956             return SCI_FAILURE_INVALID_STATE;
0957         }
0958         return SCI_SUCCESS;
0959     default:
0960         dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n",
0961             __func__, phy_state_name(state));
0962         return SCI_FAILURE_INVALID_STATE;
0963     }
0964 }
0965
0966 enum sci_status sci_phy_frame_handler(struct isci_phy *iphy, u32 frame_index)
0967 {
0968     enum sci_phy_states state = iphy->sm.current_state_id;
0969     struct isci_host *ihost = iphy->owning_port->owning_controller;
0970     enum sci_status result;
0971     unsigned long flags;
0972
0973     switch (state) {
0974     case SCI_PHY_SUB_AWAIT_IAF_UF: {
0975         u32 *frame_words;
0976         struct sas_identify_frame iaf;
0977
0978         result = sci_unsolicited_frame_control_get_header(&ihost->uf_control,
0979                                   frame_index,
0980                                   (void **)&frame_words);
0981
0982         if (result != SCI_SUCCESS)
0983             return result;
0984
0985         sci_swab32_cpy(&iaf, frame_words, sizeof(iaf) / sizeof(u32));
0986         if (iaf.frame_type == 0) {
0987             u32 state;
0988
0989             spin_lock_irqsave(&iphy->sas_phy.frame_rcvd_lock, flags);
0990             memcpy(&iphy->frame_rcvd.iaf, &iaf, sizeof(iaf));
0991             spin_unlock_irqrestore(&iphy->sas_phy.frame_rcvd_lock, flags);
0992             if (iaf.smp_tport) {
0993                 /* We got the IAF for an expander PHY go to the final
0994                  * state since there are no power requirements for
0995                  * expander phys.
0996                  */
0997                 state = SCI_PHY_SUB_FINAL;
0998             } else {
0999                 /* We got the IAF we can now go to the await spinup
1000                  * semaphore state
1001                  */
1002                 state = SCI_PHY_SUB_AWAIT_SAS_POWER;
1003             }
1004             sci_change_state(&iphy->sm, state);
1005             result = SCI_SUCCESS;
1006         } else
1007             dev_warn(sciphy_to_dev(iphy),
1008                 "%s: PHY starting substate machine received "
1009                 "unexpected frame id %x\n",
1010                 __func__, frame_index);
1011
1012         sci_controller_release_frame(ihost, frame_index);
1013         return result;
1014     }
1015     case SCI_PHY_SUB_AWAIT_SIG_FIS_UF: {
1016         struct dev_to_host_fis *frame_header;
1017         u32 *fis_frame_data;
1018
1019         result = sci_unsolicited_frame_control_get_header(&ihost->uf_control,
1020                                   frame_index,
1021                                   (void **)&frame_header);
1022
1023         if (result != SCI_SUCCESS)
1024             return result;
1025
1026         if ((frame_header->fis_type == FIS_REGD2H) &&
1027             !(frame_header->status & ATA_BUSY)) {
1028             sci_unsolicited_frame_control_get_buffer(&ihost->uf_control,
1029                                  frame_index,
1030                                  (void **)&fis_frame_data);
1031
1032             spin_lock_irqsave(&iphy->sas_phy.frame_rcvd_lock, flags);
1033             sci_controller_copy_sata_response(&iphy->frame_rcvd.fis,
1034                               frame_header,
1035                               fis_frame_data);
1036             spin_unlock_irqrestore(&iphy->sas_phy.frame_rcvd_lock, flags);
1037
1038             /* got IAF we can now go to the await spinup semaphore state */
1039             sci_change_state(&iphy->sm, SCI_PHY_SUB_FINAL);
1040
1041             result = SCI_SUCCESS;
1042         } else
1043             dev_warn(sciphy_to_dev(iphy),
1044                  "%s: PHY starting substate machine received "
1045                  "unexpected frame id %x\n",
1046                  __func__, frame_index);
1047
1048         /* Regardless of the result we are done with this frame with it */
1049         sci_controller_release_frame(ihost, frame_index);
1050
1051         return result;
1052     }
1053     default:
1054         dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n",
1055             __func__, phy_state_name(state));
1056         return SCI_FAILURE_INVALID_STATE;
1057     }
1058
1059 }
1060
1061 static void sci_phy_starting_initial_substate_enter(struct sci_base_state_machine *sm)
1062 {
1063     struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1064
1065     /* This is just an temporary state go off to the starting state */
1066     sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_OSSP_EN);
1067 }
1068
1069 static void sci_phy_starting_await_sas_power_substate_enter(struct sci_base_state_machine *sm)
1070 {
1071     struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1072     struct isci_host *ihost = iphy->owning_port->owning_controller;
1073
1074     sci_controller_power_control_queue_insert(ihost, iphy);
1075 }
1076
1077 static void sci_phy_starting_await_sas_power_substate_exit(struct sci_base_state_machine *sm)
1078 {
1079     struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1080     struct isci_host *ihost = iphy->owning_port->owning_controller;
1081
1082     sci_controller_power_control_queue_remove(ihost, iphy);
1083 }
1084
1085 static void sci_phy_starting_await_sata_power_substate_enter(struct sci_base_state_machine *sm)
1086 {
1087     struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1088     struct isci_host *ihost = iphy->owning_port->owning_controller;
1089
1090     sci_controller_power_control_queue_insert(ihost, iphy);
1091 }
1092
1093 static void sci_phy_starting_await_sata_power_substate_exit(struct sci_base_state_machine *sm)
1094 {
1095     struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1096     struct isci_host *ihost = iphy->owning_port->owning_controller;
1097
1098     sci_controller_power_control_queue_remove(ihost, iphy);
1099 }
1100
1101 static void sci_phy_starting_await_sata_phy_substate_enter(struct sci_base_state_machine *sm)
1102 {
1103     struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1104
1105     sci_mod_timer(&iphy->sata_timer, SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT);
1106 }
1107
1108 static void sci_phy_starting_await_sata_phy_substate_exit(struct sci_base_state_machine *sm)
1109 {
1110     struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1111
1112     sci_del_timer(&iphy->sata_timer);
1113 }
1114
1115 static void sci_phy_starting_await_sata_speed_substate_enter(struct sci_base_state_machine *sm)
1116 {
1117     struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1118
1119     sci_mod_timer(&iphy->sata_timer, SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT);
1120 }
1121
1122 static void sci_phy_starting_await_sata_speed_substate_exit(struct sci_base_state_machine *sm)
1123 {
1124     struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1125
1126     sci_del_timer(&iphy->sata_timer);
1127 }
1128
1129 static void sci_phy_starting_await_sig_fis_uf_substate_enter(struct sci_base_state_machine *sm)
1130 {
1131     struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1132
1133     if (sci_port_link_detected(iphy->owning_port, iphy)) {
1134
1135         /*
1136          * Clear the PE suspend condition so we can actually
1137          * receive SIG FIS
1138          * The hardware will not respond to the XRDY until the PE
1139          * suspend condition is cleared.
1140          */
1141         sci_phy_resume(iphy);
1142
1143         sci_mod_timer(&iphy->sata_timer,
1144                   SCIC_SDS_SIGNATURE_FIS_TIMEOUT);
1145     } else
1146         iphy->is_in_link_training = false;
1147 }
1148
1149 static void sci_phy_starting_await_sig_fis_uf_substate_exit(struct sci_base_state_machine *sm)
1150 {
1151     struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1152
1153     sci_del_timer(&iphy->sata_timer);
1154 }
1155
1156 static void sci_phy_starting_final_substate_enter(struct sci_base_state_machine *sm)
1157 {
1158     struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1159
1160     /* State machine has run to completion so exit out and change
1161      * the base state machine to the ready state
1162      */
1163     sci_change_state(&iphy->sm, SCI_PHY_READY);
1164 }
1165
1166 /**
1167  * scu_link_layer_stop_protocol_engine()
1168  * @iphy: This is the struct isci_phy object to stop.
1169  *
1170  * This method will stop the struct isci_phy object. This does not reset the
1171  * protocol engine it just suspends it and places it in a state where it will
1172  * not cause the end device to power up. none
1173  */
1174 static void scu_link_layer_stop_protocol_engine(
1175     struct isci_phy *iphy)
1176 {
1177     u32 scu_sas_pcfg_value;
1178     u32 enable_spinup_value;
1179
1180     /* Suspend the protocol engine and place it in a sata spinup hold state */
1181     scu_sas_pcfg_value =
1182         readl(&iphy->link_layer_registers->phy_configuration);
1183     scu_sas_pcfg_value |=
1184         (SCU_SAS_PCFG_GEN_BIT(OOB_RESET) |
1185          SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE) |
1186          SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD));
1187     writel(scu_sas_pcfg_value,
1188            &iphy->link_layer_registers->phy_configuration);
1189
1190     /* Disable the notify enable spinup primitives */
1191     enable_spinup_value = readl(&iphy->link_layer_registers->notify_enable_spinup_control);
1192     enable_spinup_value &= ~SCU_ENSPINUP_GEN_BIT(ENABLE);
1193     writel(enable_spinup_value, &iphy->link_layer_registers->notify_enable_spinup_control);
1194 }
1195
1196 static void scu_link_layer_start_oob(struct isci_phy *iphy)
1197 {
1198     struct scu_link_layer_registers __iomem *ll = iphy->link_layer_registers;
1199     u32 val;
1200
1201     /** Reset OOB sequence - start */
1202     val = readl(&ll->phy_configuration);
1203     val &= ~(SCU_SAS_PCFG_GEN_BIT(OOB_RESET) |
1204          SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE) |
1205          SCU_SAS_PCFG_GEN_BIT(HARD_RESET));
1206     writel(val, &ll->phy_configuration);
1207     readl(&ll->phy_configuration); /* flush */
1208     /** Reset OOB sequence - end */
1209
1210     /** Start OOB sequence - start */
1211     val = readl(&ll->phy_configuration);
1212     val |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
1213     writel(val, &ll->phy_configuration);
1214     readl(&ll->phy_configuration); /* flush */
1215     /** Start OOB sequence - end */
1216 }
1217
1218 /**
1219  * scu_link_layer_tx_hard_reset()
1220  * @iphy: This is the struct isci_phy object to stop.
1221  *
1222  * This method will transmit a hard reset request on the specified phy. The SCU
1223  * hardware requires that we reset the OOB state machine and set the hard reset
1224  * bit in the phy configuration register. We then must start OOB over with the
1225  * hard reset bit set.
1226  */
1227 static void scu_link_layer_tx_hard_reset(
1228     struct isci_phy *iphy)
1229 {
1230     u32 phy_configuration_value;
1231
1232     /*
1233      * SAS Phys must wait for the HARD_RESET_TX event notification to transition
1234      * to the starting state. */
1235     phy_configuration_value =
1236         readl(&iphy->link_layer_registers->phy_configuration);
1237     phy_configuration_value &= ~(SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE));
1238     phy_configuration_value |=
1239         (SCU_SAS_PCFG_GEN_BIT(HARD_RESET) |
1240          SCU_SAS_PCFG_GEN_BIT(OOB_RESET));
1241     writel(phy_configuration_value,
1242            &iphy->link_layer_registers->phy_configuration);
1243
1244     /* Now take the OOB state machine out of reset */
1245     phy_configuration_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
1246     phy_configuration_value &= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
1247     writel(phy_configuration_value,
1248            &iphy->link_layer_registers->phy_configuration);
1249 }
1250
1251 static void sci_phy_stopped_state_enter(struct sci_base_state_machine *sm)
1252 {
1253     struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1254     struct isci_port *iport = iphy->owning_port;
1255     struct isci_host *ihost = iport->owning_controller;
1256
1257     /*
1258      * @todo We need to get to the controller to place this PE in a
1259      * reset state
1260      */
1261     sci_del_timer(&iphy->sata_timer);
1262
1263     scu_link_layer_stop_protocol_engine(iphy);
1264
1265     if (iphy->sm.previous_state_id != SCI_PHY_INITIAL)
1266         sci_controller_link_down(ihost, phy_get_non_dummy_port(iphy), iphy);
1267 }
1268
1269 static void sci_phy_starting_state_enter(struct sci_base_state_machine *sm)
1270 {
1271     struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1272     struct isci_port *iport = iphy->owning_port;
1273     struct isci_host *ihost = iport->owning_controller;
1274
1275     scu_link_layer_stop_protocol_engine(iphy);
1276     scu_link_layer_start_oob(iphy);
1277
1278     /* We don't know what kind of phy we are going to be just yet */
1279     iphy->protocol = SAS_PROTOCOL_NONE;
1280     iphy->bcn_received_while_port_unassigned = false;
1281
1282     if (iphy->sm.previous_state_id == SCI_PHY_READY)
1283         sci_controller_link_down(ihost, phy_get_non_dummy_port(iphy), iphy);
1284
1285     sci_change_state(&iphy->sm, SCI_PHY_SUB_INITIAL);
1286 }
1287
1288 static void sci_phy_ready_state_enter(struct sci_base_state_machine *sm)
1289 {
1290     struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1291     struct isci_port *iport = iphy->owning_port;
1292     struct isci_host *ihost = iport->owning_controller;
1293
1294     sci_controller_link_up(ihost, phy_get_non_dummy_port(iphy), iphy);
1295 }
1296
1297 static void sci_phy_ready_state_exit(struct sci_base_state_machine *sm)
1298 {
1299     struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1300
1301     sci_phy_suspend(iphy);
1302 }
1303
1304 static void sci_phy_resetting_state_enter(struct sci_base_state_machine *sm)
1305 {
1306     struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1307
1308     /* The phy is being reset, therefore deactivate it from the port.  In
1309      * the resetting state we don't notify the user regarding link up and
1310      * link down notifications
1311      */
1312     sci_port_deactivate_phy(iphy->owning_port, iphy, false);
1313
1314     if (iphy->protocol == SAS_PROTOCOL_SSP) {
1315         scu_link_layer_tx_hard_reset(iphy);
1316     } else {
1317         /* The SCU does not need to have a discrete reset state so
1318          * just go back to the starting state.
1319          */
1320         sci_change_state(&iphy->sm, SCI_PHY_STARTING);
1321     }
1322 }
1323
1324 static const struct sci_base_state sci_phy_state_table[] = {
1325     [SCI_PHY_INITIAL] = { },
1326     [SCI_PHY_STOPPED] = {
1327         .enter_state = sci_phy_stopped_state_enter,
1328     },
1329     [SCI_PHY_STARTING] = {
1330         .enter_state = sci_phy_starting_state_enter,
1331     },
1332     [SCI_PHY_SUB_INITIAL] = {
1333         .enter_state = sci_phy_starting_initial_substate_enter,
1334     },
1335     [SCI_PHY_SUB_AWAIT_OSSP_EN] = { },
1336     [SCI_PHY_SUB_AWAIT_SAS_SPEED_EN] = { },
1337     [SCI_PHY_SUB_AWAIT_IAF_UF] = { },
1338     [SCI_PHY_SUB_AWAIT_SAS_POWER] = {
1339         .enter_state = sci_phy_starting_await_sas_power_substate_enter,
1340         .exit_state  = sci_phy_starting_await_sas_power_substate_exit,
1341     },
1342     [SCI_PHY_SUB_AWAIT_SATA_POWER] = {
1343         .enter_state = sci_phy_starting_await_sata_power_substate_enter,
1344         .exit_state  = sci_phy_starting_await_sata_power_substate_exit
1345     },
1346     [SCI_PHY_SUB_AWAIT_SATA_PHY_EN] = {
1347         .enter_state = sci_phy_starting_await_sata_phy_substate_enter,
1348         .exit_state  = sci_phy_starting_await_sata_phy_substate_exit
1349     },
1350     [SCI_PHY_SUB_AWAIT_SATA_SPEED_EN] = {
1351         .enter_state = sci_phy_starting_await_sata_speed_substate_enter,
1352         .exit_state  = sci_phy_starting_await_sata_speed_substate_exit
1353     },
1354     [SCI_PHY_SUB_AWAIT_SIG_FIS_UF] = {
1355         .enter_state = sci_phy_starting_await_sig_fis_uf_substate_enter,
1356         .exit_state  = sci_phy_starting_await_sig_fis_uf_substate_exit
1357     },
1358     [SCI_PHY_SUB_FINAL] = {
1359         .enter_state = sci_phy_starting_final_substate_enter,
1360     },
1361     [SCI_PHY_READY] = {
1362         .enter_state = sci_phy_ready_state_enter,
1363         .exit_state = sci_phy_ready_state_exit,
1364     },
1365     [SCI_PHY_RESETTING] = {
1366         .enter_state = sci_phy_resetting_state_enter,
1367     },
1368     [SCI_PHY_FINAL] = { },
1369 };
1370
1371 void sci_phy_construct(struct isci_phy *iphy,
1372                 struct isci_port *iport, u8 phy_index)
1373 {
1374     sci_init_sm(&iphy->sm, sci_phy_state_table, SCI_PHY_INITIAL);
1375
1376     /* Copy the rest of the input data to our locals */
1377     iphy->owning_port = iport;
1378     iphy->phy_index = phy_index;
1379     iphy->bcn_received_while_port_unassigned = false;
1380     iphy->protocol = SAS_PROTOCOL_NONE;
1381     iphy->link_layer_registers = NULL;
1382     iphy->max_negotiated_speed = SAS_LINK_RATE_UNKNOWN;
1383
1384     /* Create the SIGNATURE FIS Timeout timer for this phy */
1385     sci_init_timer(&iphy->sata_timer, phy_sata_timeout);
1386 }
1387
1388 void isci_phy_init(struct isci_phy *iphy, struct isci_host *ihost, int index)
1389 {
1390     struct sci_oem_params *oem = &ihost->oem_parameters;
1391     u64 sci_sas_addr;
1392     __be64 sas_addr;
1393
1394     sci_sas_addr = oem->phys[index].sas_address.high;
1395     sci_sas_addr <<= 32;
1396     sci_sas_addr |= oem->phys[index].sas_address.low;
1397     sas_addr = cpu_to_be64(sci_sas_addr);
1398     memcpy(iphy->sas_addr, &sas_addr, sizeof(sas_addr));
1399
1400     iphy->sas_phy.enabled = 0;
1401     iphy->sas_phy.id = index;
1402     iphy->sas_phy.sas_addr = &iphy->sas_addr[0];
1403     iphy->sas_phy.frame_rcvd = (u8 *)&iphy->frame_rcvd;
1404     iphy->sas_phy.ha = &ihost->sas_ha;
1405     iphy->sas_phy.lldd_phy = iphy;
1406     iphy->sas_phy.enabled = 1;
1407     iphy->sas_phy.class = SAS;
1408     iphy->sas_phy.iproto = SAS_PROTOCOL_ALL;
1409     iphy->sas_phy.tproto = 0;
1410     iphy->sas_phy.type = PHY_TYPE_PHYSICAL;
1411     iphy->sas_phy.role = PHY_ROLE_INITIATOR;
1412     iphy->sas_phy.oob_mode = OOB_NOT_CONNECTED;
1413     iphy->sas_phy.linkrate = SAS_LINK_RATE_UNKNOWN;
1414     memset(&iphy->frame_rcvd, 0, sizeof(iphy->frame_rcvd));
1415 }
1416
1417
1418 /**
1419  * isci_phy_control() - This function is one of the SAS Domain Template
1420  *    functions. This is a phy management function.
1421  * @sas_phy: This parameter specifies the sphy being controlled.
1422  * @func: This parameter specifies the phy control function being invoked.
1423  * @buf: This parameter is specific to the phy function being invoked.
1424  *
1425  * status, zero indicates success.
1426  */
1427 int isci_phy_control(struct asd_sas_phy *sas_phy,
1428              enum phy_func func,
1429              void *buf)
1430 {
1431     int ret = 0;
1432     struct isci_phy *iphy = sas_phy->lldd_phy;
1433     struct asd_sas_port *port = sas_phy->port;
1434     struct isci_host *ihost = sas_phy->ha->lldd_ha;
1435     unsigned long flags;
1436
1437     dev_dbg(&ihost->pdev->dev,
1438         "%s: phy %p; func %d; buf %p; isci phy %p, port %p\n",
1439         __func__, sas_phy, func, buf, iphy, port);
1440
1441     switch (func) {
1442     case PHY_FUNC_DISABLE:
1443         spin_lock_irqsave(&ihost->scic_lock, flags);
1444         scu_link_layer_start_oob(iphy);
1445         sci_phy_stop(iphy);
1446         spin_unlock_irqrestore(&ihost->scic_lock, flags);
1447         break;
1448
1449     case PHY_FUNC_LINK_RESET:
1450         spin_lock_irqsave(&ihost->scic_lock, flags);
1451         scu_link_layer_start_oob(iphy);
1452         sci_phy_stop(iphy);
1453         sci_phy_start(iphy);
1454         spin_unlock_irqrestore(&ihost->scic_lock, flags);
1455         break;
1456
1457     case PHY_FUNC_HARD_RESET:
1458         if (!port)
1459             return -ENODEV;
1460
1461         ret = isci_port_perform_hard_reset(ihost, port->lldd_port, iphy);
1462
1463         break;
1464     case PHY_FUNC_GET_EVENTS: {
1465         struct scu_link_layer_registers __iomem *r;
1466         struct sas_phy *phy = sas_phy->phy;
1467
1468         r = iphy->link_layer_registers;
1469         phy->running_disparity_error_count = readl(&r->running_disparity_error_count);
1470         phy->loss_of_dword_sync_count = readl(&r->loss_of_sync_error_count);
1471         phy->phy_reset_problem_count = readl(&r->phy_reset_problem_count);
1472         phy->invalid_dword_count = readl(&r->invalid_dword_counter);
1473         break;
1474     }
1475
1476     default:
1477         dev_dbg(&ihost->pdev->dev,
1478                "%s: phy %p; func %d NOT IMPLEMENTED!\n",
1479                __func__, sas_phy, func);
1480         ret = -ENOSYS;
1481         break;
1482     }
1483     return ret;
1484 }