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0001 /*****************************************************************************/
0002 /* ips.h -- driver for the Adaptec / IBM ServeRAID controller                */
0003 /*                                                                           */
0004 /* Written By: Keith Mitchell, IBM Corporation                               */
0005 /*             Jack Hammer, Adaptec, Inc.                                    */
0006 /*             David Jeffery, Adaptec, Inc.                                  */
0007 /*                                                                           */
0008 /* Copyright (C) 1999 IBM Corporation                                        */
0009 /* Copyright (C) 2003 Adaptec, Inc.                                          */
0010 /*                                                                           */
0011 /* This program is free software; you can redistribute it and/or modify      */
0012 /* it under the terms of the GNU General Public License as published by      */
0013 /* the Free Software Foundation; either version 2 of the License, or         */
0014 /* (at your option) any later version.                                       */
0015 /*                                                                           */
0016 /* This program is distributed in the hope that it will be useful,           */
0017 /* but WITHOUT ANY WARRANTY; without even the implied warranty of            */
0018 /* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the             */
0019 /* GNU General Public License for more details.                              */
0020 /*                                                                           */
0021 /* NO WARRANTY                                                               */
0022 /* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR        */
0023 /* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT      */
0024 /* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,      */
0025 /* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is    */
0026 /* solely responsible for determining the appropriateness of using and       */
0027 /* distributing the Program and assumes all risks associated with its        */
0028 /* exercise of rights under this Agreement, including but not limited to     */
0029 /* the risks and costs of program errors, damage to or loss of data,         */
0030 /* programs or equipment, and unavailability or interruption of operations.  */
0031 /*                                                                           */
0032 /* DISCLAIMER OF LIABILITY                                                   */
0033 /* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY   */
0034 /* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL        */
0035 /* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND   */
0036 /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR     */
0037 /* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE    */
0038 /* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED  */
0039 /* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES             */
0040 /*                                                                           */
0041 /* You should have received a copy of the GNU General Public License         */
0042 /* along with this program; if not, write to the Free Software               */
0043 /* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA */
0044 /*                                                                           */
0045 /* Bugs/Comments/Suggestions should be mailed to:                            */
0046 /*      ipslinux@adaptec.com                                                 */
0047 /*                                                                           */
0048 /*****************************************************************************/
0049 
0050 #ifndef _IPS_H_
0051    #define _IPS_H_
0052 
0053 #include <linux/nmi.h>
0054 #include <linux/uaccess.h>
0055    #include <asm/io.h>
0056 
0057    /*
0058     * Some handy macros
0059     */
0060    #define IPS_HA(x)                   ((ips_ha_t *) x->hostdata)
0061    #define IPS_COMMAND_ID(ha, scb)     (int) (scb - ha->scbs)
0062    #define IPS_IS_TROMBONE(ha)         (((ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) && \
0063                                          (ha->pcidev->revision >= IPS_REVID_TROMBONE32) && \
0064                                          (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) ? 1 : 0)
0065    #define IPS_IS_CLARINET(ha)         (((ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) && \
0066                                          (ha->pcidev->revision >= IPS_REVID_CLARINETP1) && \
0067                                          (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) ? 1 : 0)
0068    #define IPS_IS_MORPHEUS(ha)         (ha->pcidev->device == IPS_DEVICEID_MORPHEUS)
0069    #define IPS_IS_MARCO(ha)            (ha->pcidev->device == IPS_DEVICEID_MARCO)
0070    #define IPS_USE_I2O_DELIVER(ha)     ((IPS_IS_MORPHEUS(ha) || \
0071                                          (IPS_IS_TROMBONE(ha) && \
0072                                           (ips_force_i2o))) ? 1 : 0)
0073    #define IPS_USE_MEMIO(ha)           ((IPS_IS_MORPHEUS(ha) || \
0074                                          ((IPS_IS_TROMBONE(ha) || IPS_IS_CLARINET(ha)) && \
0075                                           (ips_force_memio))) ? 1 : 0)
0076 
0077     #define IPS_HAS_ENH_SGLIST(ha)    (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha))
0078     #define IPS_USE_ENH_SGLIST(ha)    ((ha)->flags & IPS_HA_ENH_SG)
0079     #define IPS_SGLIST_SIZE(ha)       (IPS_USE_ENH_SGLIST(ha) ? \
0080                                          sizeof(IPS_ENH_SG_LIST) : sizeof(IPS_STD_SG_LIST))
0081 
0082   #define IPS_PRINTK(level, pcidev, format, arg...)                 \
0083             dev_printk(level , &((pcidev)->dev) , format , ## arg)
0084 
0085    #define MDELAY(n)            \
0086     do {                \
0087         mdelay(n);      \
0088         touch_nmi_watchdog();   \
0089     } while (0)
0090 
0091    #ifndef min
0092       #define min(x,y) ((x) < (y) ? x : y)
0093    #endif
0094 
0095    #ifndef __iomem       /* For clean compiles in earlier kernels without __iomem annotations */
0096       #define __iomem
0097    #endif
0098 
0099    /*
0100     * Adapter address map equates
0101     */
0102    #define IPS_REG_HISR                 0x08    /* Host Interrupt Status Reg   */
0103    #define IPS_REG_CCSAR                0x10    /* Cmd Channel System Addr Reg */
0104    #define IPS_REG_CCCR                 0x14    /* Cmd Channel Control Reg     */
0105    #define IPS_REG_SQHR                 0x20    /* Status Q Head Reg           */
0106    #define IPS_REG_SQTR                 0x24    /* Status Q Tail Reg           */
0107    #define IPS_REG_SQER                 0x28    /* Status Q End Reg            */
0108    #define IPS_REG_SQSR                 0x2C    /* Status Q Start Reg          */
0109    #define IPS_REG_SCPR                 0x05    /* Subsystem control port reg  */
0110    #define IPS_REG_ISPR                 0x06    /* interrupt status port reg   */
0111    #define IPS_REG_CBSP                 0x07    /* CBSP register               */
0112    #define IPS_REG_FLAP                 0x18    /* Flash address port          */
0113    #define IPS_REG_FLDP                 0x1C    /* Flash data port             */
0114    #define IPS_REG_NDAE                 0x38    /* Anaconda 64 NDAE Register   */
0115    #define IPS_REG_I2O_INMSGQ           0x40    /* I2O Inbound Message Queue   */
0116    #define IPS_REG_I2O_OUTMSGQ          0x44    /* I2O Outbound Message Queue  */
0117    #define IPS_REG_I2O_HIR              0x30    /* I2O Interrupt Status        */
0118    #define IPS_REG_I960_IDR             0x20    /* i960 Inbound Doorbell       */
0119    #define IPS_REG_I960_MSG0            0x18    /* i960 Outbound Reg 0         */
0120    #define IPS_REG_I960_MSG1            0x1C    /* i960 Outbound Reg 1         */
0121    #define IPS_REG_I960_OIMR            0x34    /* i960 Oubound Int Mask Reg   */
0122 
0123    /*
0124     * Adapter register bit equates
0125     */
0126    #define IPS_BIT_GHI                  0x04    /* HISR General Host Interrupt */
0127    #define IPS_BIT_SQO                  0x02    /* HISR Status Q Overflow      */
0128    #define IPS_BIT_SCE                  0x01    /* HISR Status Channel Enqueue */
0129    #define IPS_BIT_SEM                  0x08    /* CCCR Semaphore Bit          */
0130    #define IPS_BIT_ILE                  0x10    /* CCCR ILE Bit                */
0131    #define IPS_BIT_START_CMD            0x101A  /* CCCR Start Command Channel  */
0132    #define IPS_BIT_START_STOP           0x0002  /* CCCR Start/Stop Bit         */
0133    #define IPS_BIT_RST                  0x80    /* SCPR Reset Bit              */
0134    #define IPS_BIT_EBM                  0x02    /* SCPR Enable Bus Master      */
0135    #define IPS_BIT_EI                   0x80    /* HISR Enable Interrupts      */
0136    #define IPS_BIT_OP                   0x01    /* OP bit in CBSP              */
0137    #define IPS_BIT_I2O_OPQI             0x08    /* General Host Interrupt      */
0138    #define IPS_BIT_I960_MSG0I           0x01    /* Message Register 0 Interrupt*/
0139    #define IPS_BIT_I960_MSG1I           0x02    /* Message Register 1 Interrupt*/
0140 
0141    /*
0142     * Adapter Command ID Equates
0143     */
0144    #define IPS_CMD_GET_LD_INFO          0x19
0145    #define IPS_CMD_GET_SUBSYS           0x40
0146    #define IPS_CMD_READ_CONF            0x38
0147    #define IPS_CMD_RW_NVRAM_PAGE        0xBC
0148    #define IPS_CMD_READ                 0x02
0149    #define IPS_CMD_WRITE                0x03
0150    #define IPS_CMD_FFDC                 0xD7
0151    #define IPS_CMD_ENQUIRY              0x05
0152    #define IPS_CMD_FLUSH                0x0A
0153    #define IPS_CMD_READ_SG              0x82
0154    #define IPS_CMD_WRITE_SG             0x83
0155    #define IPS_CMD_DCDB                 0x04
0156    #define IPS_CMD_DCDB_SG              0x84
0157    #define IPS_CMD_EXTENDED_DCDB        0x95
0158    #define IPS_CMD_EXTENDED_DCDB_SG     0x96
0159    #define IPS_CMD_CONFIG_SYNC          0x58
0160    #define IPS_CMD_ERROR_TABLE          0x17
0161    #define IPS_CMD_DOWNLOAD             0x20
0162    #define IPS_CMD_RW_BIOSFW            0x22
0163    #define IPS_CMD_GET_VERSION_INFO     0xC6
0164    #define IPS_CMD_RESET_CHANNEL        0x1A
0165 
0166    /*
0167     * Adapter Equates
0168     */
0169    #define IPS_CSL                      0xFF
0170    #define IPS_POCL                     0x30
0171    #define IPS_NORM_STATE               0x00
0172    #define IPS_MAX_ADAPTER_TYPES        3
0173    #define IPS_MAX_ADAPTERS             16
0174    #define IPS_MAX_IOCTL                1
0175    #define IPS_MAX_IOCTL_QUEUE          8
0176    #define IPS_MAX_QUEUE                128
0177    #define IPS_BLKSIZE                  512
0178    #define IPS_MAX_SG                   17
0179    #define IPS_MAX_LD                   8
0180    #define IPS_MAX_CHANNELS             4
0181    #define IPS_MAX_TARGETS              15
0182    #define IPS_MAX_CHUNKS               16
0183    #define IPS_MAX_CMDS                 128
0184    #define IPS_MAX_XFER                 0x10000
0185    #define IPS_NVRAM_P5_SIG             0xFFDDBB99
0186    #define IPS_MAX_POST_BYTES           0x02
0187    #define IPS_MAX_CONFIG_BYTES         0x02
0188    #define IPS_GOOD_POST_STATUS         0x80
0189    #define IPS_SEM_TIMEOUT              2000
0190    #define IPS_IOCTL_COMMAND            0x0D
0191    #define IPS_INTR_ON                  0
0192    #define IPS_INTR_IORL                1
0193    #define IPS_FFDC                     99
0194    #define IPS_ADAPTER_ID               0xF
0195    #define IPS_VENDORID_IBM             0x1014
0196    #define IPS_VENDORID_ADAPTEC         0x9005
0197    #define IPS_DEVICEID_COPPERHEAD      0x002E
0198    #define IPS_DEVICEID_MORPHEUS        0x01BD
0199    #define IPS_DEVICEID_MARCO           0x0250
0200    #define IPS_SUBDEVICEID_4M           0x01BE
0201    #define IPS_SUBDEVICEID_4L           0x01BF
0202    #define IPS_SUBDEVICEID_4MX          0x0208
0203    #define IPS_SUBDEVICEID_4LX          0x020E
0204    #define IPS_SUBDEVICEID_5I2          0x0259
0205    #define IPS_SUBDEVICEID_5I1          0x0258
0206    #define IPS_SUBDEVICEID_6M           0x0279
0207    #define IPS_SUBDEVICEID_6I           0x028C
0208    #define IPS_SUBDEVICEID_7k           0x028E
0209    #define IPS_SUBDEVICEID_7M           0x028F
0210    #define IPS_IOCTL_SIZE               8192
0211    #define IPS_STATUS_SIZE              4
0212    #define IPS_STATUS_Q_SIZE            (IPS_MAX_CMDS+1) * IPS_STATUS_SIZE
0213    #define IPS_IMAGE_SIZE               500 * 1024
0214    #define IPS_MEMMAP_SIZE              128
0215    #define IPS_ONE_MSEC                 1
0216    #define IPS_ONE_SEC                  1000
0217 
0218    /*
0219     * Geometry Settings
0220     */
0221    #define IPS_COMP_HEADS               128
0222    #define IPS_COMP_SECTORS             32
0223    #define IPS_NORM_HEADS               254
0224    #define IPS_NORM_SECTORS             63
0225 
0226    /*
0227     * Adapter Basic Status Codes
0228     */
0229    #define IPS_BASIC_STATUS_MASK        0xFF
0230    #define IPS_GSC_STATUS_MASK          0x0F
0231    #define IPS_CMD_SUCCESS              0x00
0232    #define IPS_CMD_RECOVERED_ERROR      0x01
0233    #define IPS_INVAL_OPCO               0x03
0234    #define IPS_INVAL_CMD_BLK            0x04
0235    #define IPS_INVAL_PARM_BLK           0x05
0236    #define IPS_BUSY                     0x08
0237    #define IPS_CMD_CMPLT_WERROR         0x0C
0238    #define IPS_LD_ERROR                 0x0D
0239    #define IPS_CMD_TIMEOUT              0x0E
0240    #define IPS_PHYS_DRV_ERROR           0x0F
0241 
0242    /*
0243     * Adapter Extended Status Equates
0244     */
0245    #define IPS_ERR_SEL_TO               0xF0
0246    #define IPS_ERR_OU_RUN               0xF2
0247    #define IPS_ERR_HOST_RESET           0xF7
0248    #define IPS_ERR_DEV_RESET            0xF8
0249    #define IPS_ERR_RECOVERY             0xFC
0250    #define IPS_ERR_CKCOND               0xFF
0251 
0252    /*
0253     * Operating System Defines
0254     */
0255    #define IPS_OS_WINDOWS_NT            0x01
0256    #define IPS_OS_NETWARE               0x02
0257    #define IPS_OS_OPENSERVER            0x03
0258    #define IPS_OS_UNIXWARE              0x04
0259    #define IPS_OS_SOLARIS               0x05
0260    #define IPS_OS_OS2                   0x06
0261    #define IPS_OS_LINUX                 0x07
0262    #define IPS_OS_FREEBSD               0x08
0263 
0264    /*
0265     * Adapter Revision ID's
0266     */
0267    #define IPS_REVID_SERVERAID          0x02
0268    #define IPS_REVID_NAVAJO             0x03
0269    #define IPS_REVID_SERVERAID2         0x04
0270    #define IPS_REVID_CLARINETP1         0x05
0271    #define IPS_REVID_CLARINETP2         0x07
0272    #define IPS_REVID_CLARINETP3         0x0D
0273    #define IPS_REVID_TROMBONE32         0x0F
0274    #define IPS_REVID_TROMBONE64         0x10
0275 
0276    /*
0277     * NVRAM Page 5 Adapter Defines
0278     */
0279    #define IPS_ADTYPE_SERVERAID         0x01
0280    #define IPS_ADTYPE_SERVERAID2        0x02
0281    #define IPS_ADTYPE_NAVAJO            0x03
0282    #define IPS_ADTYPE_KIOWA             0x04
0283    #define IPS_ADTYPE_SERVERAID3        0x05
0284    #define IPS_ADTYPE_SERVERAID3L       0x06
0285    #define IPS_ADTYPE_SERVERAID4H       0x07
0286    #define IPS_ADTYPE_SERVERAID4M       0x08
0287    #define IPS_ADTYPE_SERVERAID4L       0x09
0288    #define IPS_ADTYPE_SERVERAID4MX      0x0A
0289    #define IPS_ADTYPE_SERVERAID4LX      0x0B
0290    #define IPS_ADTYPE_SERVERAID5I2      0x0C
0291    #define IPS_ADTYPE_SERVERAID5I1      0x0D
0292    #define IPS_ADTYPE_SERVERAID6M       0x0E
0293    #define IPS_ADTYPE_SERVERAID6I       0x0F
0294    #define IPS_ADTYPE_SERVERAID7t       0x10
0295    #define IPS_ADTYPE_SERVERAID7k       0x11
0296    #define IPS_ADTYPE_SERVERAID7M       0x12
0297 
0298    /*
0299     * Adapter Command/Status Packet Definitions
0300     */
0301    #define IPS_SUCCESS                  0x01 /* Successfully completed       */
0302    #define IPS_SUCCESS_IMM              0x02 /* Success - Immediately        */
0303    #define IPS_FAILURE                  0x04 /* Completed with Error         */
0304 
0305    /*
0306     * Logical Drive Equates
0307     */
0308    #define IPS_LD_OFFLINE               0x02
0309    #define IPS_LD_OKAY                  0x03
0310    #define IPS_LD_FREE                  0x00
0311    #define IPS_LD_SYS                   0x06
0312    #define IPS_LD_CRS                   0x24
0313 
0314    /*
0315     * DCDB Table Equates
0316     */
0317    #define IPS_NO_DISCONNECT            0x00
0318    #define IPS_DISCONNECT_ALLOWED       0x80
0319    #define IPS_NO_AUTO_REQSEN           0x40
0320    #define IPS_DATA_NONE                0x00
0321    #define IPS_DATA_UNK                 0x00
0322    #define IPS_DATA_IN                  0x01
0323    #define IPS_DATA_OUT                 0x02
0324    #define IPS_TRANSFER64K              0x08
0325    #define IPS_NOTIMEOUT                0x00
0326    #define IPS_TIMEOUT10                0x10
0327    #define IPS_TIMEOUT60                0x20
0328    #define IPS_TIMEOUT20M               0x30
0329 
0330    /*
0331     * SCSI Inquiry Data Flags
0332     */
0333    #define IPS_SCSI_INQ_TYPE_DASD       0x00
0334    #define IPS_SCSI_INQ_TYPE_PROCESSOR  0x03
0335    #define IPS_SCSI_INQ_LU_CONNECTED    0x00
0336    #define IPS_SCSI_INQ_RD_REV2         0x02
0337    #define IPS_SCSI_INQ_REV2            0x02
0338    #define IPS_SCSI_INQ_REV3            0x03
0339    #define IPS_SCSI_INQ_Address16       0x01
0340    #define IPS_SCSI_INQ_Address32       0x02
0341    #define IPS_SCSI_INQ_MedChanger      0x08
0342    #define IPS_SCSI_INQ_MultiPort       0x10
0343    #define IPS_SCSI_INQ_EncServ         0x40
0344    #define IPS_SCSI_INQ_SoftReset       0x01
0345    #define IPS_SCSI_INQ_CmdQue          0x02
0346    #define IPS_SCSI_INQ_Linked          0x08
0347    #define IPS_SCSI_INQ_Sync            0x10
0348    #define IPS_SCSI_INQ_WBus16          0x20
0349    #define IPS_SCSI_INQ_WBus32          0x40
0350    #define IPS_SCSI_INQ_RelAdr          0x80
0351 
0352    /*
0353     * SCSI Request Sense Data Flags
0354     */
0355    #define IPS_SCSI_REQSEN_VALID        0x80
0356    #define IPS_SCSI_REQSEN_CURRENT_ERR  0x70
0357    #define IPS_SCSI_REQSEN_NO_SENSE     0x00
0358 
0359    /*
0360     * SCSI Mode Page Equates
0361     */
0362    #define IPS_SCSI_MP3_SoftSector      0x01
0363    #define IPS_SCSI_MP3_HardSector      0x02
0364    #define IPS_SCSI_MP3_Removeable      0x04
0365    #define IPS_SCSI_MP3_AllocateSurface 0x08
0366 
0367    /*
0368     * HA Flags
0369     */
0370 
0371    #define IPS_HA_ENH_SG                0x1
0372 
0373    /*
0374     * SCB Flags
0375     */
0376    #define IPS_SCB_MAP_SG               0x00008
0377    #define IPS_SCB_MAP_SINGLE           0X00010
0378 
0379    /*
0380     * Passthru stuff
0381     */
0382    #define IPS_COPPUSRCMD              (('C'<<8) | 65)
0383    #define IPS_COPPIOCCMD              (('C'<<8) | 66)
0384    #define IPS_NUMCTRLS                (('C'<<8) | 68)
0385    #define IPS_CTRLINFO                (('C'<<8) | 69)
0386 
0387    /* flashing defines */
0388    #define IPS_FW_IMAGE                0x00
0389    #define IPS_BIOS_IMAGE              0x01
0390    #define IPS_WRITE_FW                0x01
0391    #define IPS_WRITE_BIOS              0x02
0392    #define IPS_ERASE_BIOS              0x03
0393    #define IPS_BIOS_HEADER             0xC0
0394 
0395    /* time oriented stuff */
0396    #define IPS_SECS_8HOURS              28800
0397 
0398    /*
0399     * Scsi_Host Template
0400     */
0401    static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
0402         sector_t capacity, int geom[]);
0403    static int ips_slave_configure(struct scsi_device *SDptr);
0404 
0405 /*
0406  * Raid Command Formats
0407  */
0408 typedef struct {
0409    uint8_t  op_code;
0410    uint8_t  command_id;
0411    uint8_t  log_drv;
0412    uint8_t  sg_count;
0413    uint32_t lba;
0414    uint32_t sg_addr;
0415    uint16_t sector_count;
0416    uint8_t  segment_4G;
0417    uint8_t  enhanced_sg;
0418    uint32_t ccsar;
0419    uint32_t cccr;
0420 } IPS_IO_CMD, *PIPS_IO_CMD;
0421 
0422 typedef struct {
0423    uint8_t  op_code;
0424    uint8_t  command_id;
0425    uint16_t reserved;
0426    uint32_t reserved2;
0427    uint32_t buffer_addr;
0428    uint32_t reserved3;
0429    uint32_t ccsar;
0430    uint32_t cccr;
0431 } IPS_LD_CMD, *PIPS_LD_CMD;
0432 
0433 typedef struct {
0434    uint8_t  op_code;
0435    uint8_t  command_id;
0436    uint8_t  reserved;
0437    uint8_t  reserved2;
0438    uint32_t reserved3;
0439    uint32_t buffer_addr;
0440    uint32_t reserved4;
0441 } IPS_IOCTL_CMD, *PIPS_IOCTL_CMD;
0442 
0443 typedef struct {
0444    uint8_t  op_code;
0445    uint8_t  command_id;
0446    uint8_t  channel;
0447    uint8_t  reserved3;
0448    uint8_t  reserved4;
0449    uint8_t  reserved5;
0450    uint8_t  reserved6;
0451    uint8_t  reserved7;
0452    uint8_t  reserved8;
0453    uint8_t  reserved9;
0454    uint8_t  reserved10;
0455    uint8_t  reserved11;
0456    uint8_t  reserved12;
0457    uint8_t  reserved13;
0458    uint8_t  reserved14;
0459    uint8_t  adapter_flag;
0460 } IPS_RESET_CMD, *PIPS_RESET_CMD;
0461 
0462 typedef struct {
0463    uint8_t  op_code;
0464    uint8_t  command_id;
0465    uint16_t reserved;
0466    uint32_t reserved2;
0467    uint32_t dcdb_address;
0468    uint16_t reserved3;
0469    uint8_t  segment_4G;
0470    uint8_t  enhanced_sg;
0471    uint32_t ccsar;
0472    uint32_t cccr;
0473 } IPS_DCDB_CMD, *PIPS_DCDB_CMD;
0474 
0475 typedef struct {
0476    uint8_t  op_code;
0477    uint8_t  command_id;
0478    uint8_t  channel;
0479    uint8_t  source_target;
0480    uint32_t reserved;
0481    uint32_t reserved2;
0482    uint32_t reserved3;
0483    uint32_t ccsar;
0484    uint32_t cccr;
0485 } IPS_CS_CMD, *PIPS_CS_CMD;
0486 
0487 typedef struct {
0488    uint8_t  op_code;
0489    uint8_t  command_id;
0490    uint8_t  log_drv;
0491    uint8_t  control;
0492    uint32_t reserved;
0493    uint32_t reserved2;
0494    uint32_t reserved3;
0495    uint32_t ccsar;
0496    uint32_t cccr;
0497 } IPS_US_CMD, *PIPS_US_CMD;
0498 
0499 typedef struct {
0500    uint8_t  op_code;
0501    uint8_t  command_id;
0502    uint8_t  reserved;
0503    uint8_t  state;
0504    uint32_t reserved2;
0505    uint32_t reserved3;
0506    uint32_t reserved4;
0507    uint32_t ccsar;
0508    uint32_t cccr;
0509 } IPS_FC_CMD, *PIPS_FC_CMD;
0510 
0511 typedef struct {
0512    uint8_t  op_code;
0513    uint8_t  command_id;
0514    uint8_t  reserved;
0515    uint8_t  desc;
0516    uint32_t reserved2;
0517    uint32_t buffer_addr;
0518    uint32_t reserved3;
0519    uint32_t ccsar;
0520    uint32_t cccr;
0521 } IPS_STATUS_CMD, *PIPS_STATUS_CMD;
0522 
0523 typedef struct {
0524    uint8_t  op_code;
0525    uint8_t  command_id;
0526    uint8_t  page;
0527    uint8_t  write;
0528    uint32_t reserved;
0529    uint32_t buffer_addr;
0530    uint32_t reserved2;
0531    uint32_t ccsar;
0532    uint32_t cccr;
0533 } IPS_NVRAM_CMD, *PIPS_NVRAM_CMD;
0534 
0535 typedef struct
0536 {
0537     uint8_t  op_code;
0538     uint8_t  command_id;
0539     uint16_t reserved;
0540     uint32_t count;
0541     uint32_t buffer_addr;
0542     uint32_t reserved2;
0543 } IPS_VERSION_INFO, *PIPS_VERSION_INFO;
0544 
0545 typedef struct {
0546    uint8_t  op_code;
0547    uint8_t  command_id;
0548    uint8_t  reset_count;
0549    uint8_t  reset_type;
0550    uint8_t  second;
0551    uint8_t  minute;
0552    uint8_t  hour;
0553    uint8_t  day;
0554    uint8_t  reserved1[4];
0555    uint8_t  month;
0556    uint8_t  yearH;
0557    uint8_t  yearL;
0558    uint8_t  reserved2;
0559 } IPS_FFDC_CMD, *PIPS_FFDC_CMD;
0560 
0561 typedef struct {
0562    uint8_t  op_code;
0563    uint8_t  command_id;
0564    uint8_t  type;
0565    uint8_t  direction;
0566    uint32_t count;
0567    uint32_t buffer_addr;
0568    uint8_t  total_packets;
0569    uint8_t  packet_num;
0570    uint16_t reserved;
0571 } IPS_FLASHFW_CMD, *PIPS_FLASHFW_CMD;
0572 
0573 typedef struct {
0574    uint8_t  op_code;
0575    uint8_t  command_id;
0576    uint8_t  type;
0577    uint8_t  direction;
0578    uint32_t count;
0579    uint32_t buffer_addr;
0580    uint32_t offset;
0581 } IPS_FLASHBIOS_CMD, *PIPS_FLASHBIOS_CMD;
0582 
0583 typedef union {
0584    IPS_IO_CMD         basic_io;
0585    IPS_LD_CMD         logical_info;
0586    IPS_IOCTL_CMD      ioctl_info;
0587    IPS_DCDB_CMD       dcdb;
0588    IPS_CS_CMD         config_sync;
0589    IPS_US_CMD         unlock_stripe;
0590    IPS_FC_CMD         flush_cache;
0591    IPS_STATUS_CMD     status;
0592    IPS_NVRAM_CMD      nvram;
0593    IPS_FFDC_CMD       ffdc;
0594    IPS_FLASHFW_CMD    flashfw;
0595    IPS_FLASHBIOS_CMD  flashbios;
0596    IPS_VERSION_INFO   version_info;
0597    IPS_RESET_CMD      reset;
0598 } IPS_HOST_COMMAND, *PIPS_HOST_COMMAND;
0599 
0600 typedef struct {
0601    uint8_t  logical_id;
0602    uint8_t  reserved;
0603    uint8_t  raid_level;
0604    uint8_t  state;
0605    uint32_t sector_count;
0606 } IPS_DRIVE_INFO, *PIPS_DRIVE_INFO;
0607 
0608 typedef struct {
0609    uint8_t       no_of_log_drive;
0610    uint8_t       reserved[3];
0611    IPS_DRIVE_INFO drive_info[IPS_MAX_LD];
0612 } IPS_LD_INFO, *PIPS_LD_INFO;
0613 
0614 typedef struct {
0615    uint8_t   device_address;
0616    uint8_t   cmd_attribute;
0617    uint16_t  transfer_length;
0618    uint32_t  buffer_pointer;
0619    uint8_t   cdb_length;
0620    uint8_t   sense_length;
0621    uint8_t   sg_count;
0622    uint8_t   reserved;
0623    uint8_t   scsi_cdb[12];
0624    uint8_t   sense_info[64];
0625    uint8_t   scsi_status;
0626    uint8_t   reserved2[3];
0627 } IPS_DCDB_TABLE, *PIPS_DCDB_TABLE;
0628 
0629 typedef struct {
0630    uint8_t   device_address;
0631    uint8_t   cmd_attribute;
0632    uint8_t   cdb_length;
0633    uint8_t   reserved_for_LUN;
0634    uint32_t  transfer_length;
0635    uint32_t  buffer_pointer;
0636    uint16_t  sg_count;
0637    uint8_t   sense_length;
0638    uint8_t   scsi_status;
0639    uint32_t  reserved;
0640    uint8_t   scsi_cdb[16];
0641    uint8_t   sense_info[56];
0642 } IPS_DCDB_TABLE_TAPE, *PIPS_DCDB_TABLE_TAPE;
0643 
0644 typedef union {
0645    struct {
0646       volatile uint8_t  reserved;
0647       volatile uint8_t  command_id;
0648       volatile uint8_t  basic_status;
0649       volatile uint8_t  extended_status;
0650    } fields;
0651 
0652    volatile uint32_t    value;
0653 } IPS_STATUS, *PIPS_STATUS;
0654 
0655 typedef struct {
0656    IPS_STATUS           status[IPS_MAX_CMDS + 1];
0657    volatile PIPS_STATUS p_status_start;
0658    volatile PIPS_STATUS p_status_end;
0659    volatile PIPS_STATUS p_status_tail;
0660    volatile uint32_t    hw_status_start;
0661    volatile uint32_t    hw_status_tail;
0662 } IPS_ADAPTER, *PIPS_ADAPTER;
0663 
0664 typedef struct {
0665    uint8_t  ucLogDriveCount;
0666    uint8_t  ucMiscFlag;
0667    uint8_t  ucSLTFlag;
0668    uint8_t  ucBSTFlag;
0669    uint8_t  ucPwrChgCnt;
0670    uint8_t  ucWrongAdrCnt;
0671    uint8_t  ucUnidentCnt;
0672    uint8_t  ucNVramDevChgCnt;
0673    uint8_t  CodeBlkVersion[8];
0674    uint8_t  BootBlkVersion[8];
0675    uint32_t ulDriveSize[IPS_MAX_LD];
0676    uint8_t  ucConcurrentCmdCount;
0677    uint8_t  ucMaxPhysicalDevices;
0678    uint16_t usFlashRepgmCount;
0679    uint8_t  ucDefunctDiskCount;
0680    uint8_t  ucRebuildFlag;
0681    uint8_t  ucOfflineLogDrvCount;
0682    uint8_t  ucCriticalDrvCount;
0683    uint16_t usConfigUpdateCount;
0684    uint8_t  ucBlkFlag;
0685    uint8_t  reserved;
0686    uint16_t usAddrDeadDisk[IPS_MAX_CHANNELS * (IPS_MAX_TARGETS + 1)];
0687 } IPS_ENQ, *PIPS_ENQ;
0688 
0689 typedef struct {
0690    uint8_t  ucInitiator;
0691    uint8_t  ucParameters;
0692    uint8_t  ucMiscFlag;
0693    uint8_t  ucState;
0694    uint32_t ulBlockCount;
0695    uint8_t  ucDeviceId[28];
0696 } IPS_DEVSTATE, *PIPS_DEVSTATE;
0697 
0698 typedef struct {
0699    uint8_t  ucChn;
0700    uint8_t  ucTgt;
0701    uint16_t ucReserved;
0702    uint32_t ulStartSect;
0703    uint32_t ulNoOfSects;
0704 } IPS_CHUNK, *PIPS_CHUNK;
0705 
0706 typedef struct {
0707    uint16_t ucUserField;
0708    uint8_t  ucState;
0709    uint8_t  ucRaidCacheParam;
0710    uint8_t  ucNoOfChunkUnits;
0711    uint8_t  ucStripeSize;
0712    uint8_t  ucParams;
0713    uint8_t  ucReserved;
0714    uint32_t ulLogDrvSize;
0715    IPS_CHUNK chunk[IPS_MAX_CHUNKS];
0716 } IPS_LD, *PIPS_LD;
0717 
0718 typedef struct {
0719    uint8_t  board_disc[8];
0720    uint8_t  processor[8];
0721    uint8_t  ucNoChanType;
0722    uint8_t  ucNoHostIntType;
0723    uint8_t  ucCompression;
0724    uint8_t  ucNvramType;
0725    uint32_t ulNvramSize;
0726 } IPS_HARDWARE, *PIPS_HARDWARE;
0727 
0728 typedef struct {
0729    uint8_t        ucLogDriveCount;
0730    uint8_t        ucDateD;
0731    uint8_t        ucDateM;
0732    uint8_t        ucDateY;
0733    uint8_t        init_id[4];
0734    uint8_t        host_id[12];
0735    uint8_t        time_sign[8];
0736    uint32_t       UserOpt;
0737    uint16_t       user_field;
0738    uint8_t        ucRebuildRate;
0739    uint8_t        ucReserve;
0740    IPS_HARDWARE   hardware_disc;
0741    IPS_LD         logical_drive[IPS_MAX_LD];
0742    IPS_DEVSTATE   dev[IPS_MAX_CHANNELS][IPS_MAX_TARGETS+1];
0743    uint8_t        reserved[512];
0744 } IPS_CONF, *PIPS_CONF;
0745 
0746 typedef struct {
0747    uint32_t  signature;
0748    uint8_t   reserved1;
0749    uint8_t   adapter_slot;
0750    uint16_t  adapter_type;
0751    uint8_t   ctrl_bios[8];
0752    uint8_t   versioning;                   /* 1 = Versioning Supported, else 0 */
0753    uint8_t   version_mismatch;             /* 1 = Versioning MisMatch,  else 0 */
0754    uint8_t   reserved2;
0755    uint8_t   operating_system;
0756    uint8_t   driver_high[4];
0757    uint8_t   driver_low[4];
0758    uint8_t   BiosCompatibilityID[8];
0759    uint8_t   ReservedForOS2[8];
0760    uint8_t   bios_high[4];                 /* Adapter's Flashed BIOS Version   */
0761    uint8_t   bios_low[4];
0762    uint8_t   adapter_order[16];            /* BIOS Telling us the Sort Order   */
0763    uint8_t   Filler[60];
0764 } IPS_NVRAM_P5, *PIPS_NVRAM_P5;
0765 
0766 /*--------------------------------------------------------------------------*/
0767 /* Data returned from a GetVersion Command                                  */
0768 /*--------------------------------------------------------------------------*/
0769 
0770                                              /* SubSystem Parameter[4]      */
0771 #define  IPS_GET_VERSION_SUPPORT 0x00018000  /* Mask for Versioning Support */
0772 
0773 typedef struct
0774 {
0775    uint32_t  revision;
0776    uint8_t   bootBlkVersion[32];
0777    uint8_t   bootBlkAttributes[4];
0778    uint8_t   codeBlkVersion[32];
0779    uint8_t   biosVersion[32];
0780    uint8_t   biosAttributes[4];
0781    uint8_t   compatibilityId[32];
0782    uint8_t   reserved[4];
0783 } IPS_VERSION_DATA;
0784 
0785 
0786 typedef struct _IPS_SUBSYS {
0787    uint32_t  param[128];
0788 } IPS_SUBSYS, *PIPS_SUBSYS;
0789 
0790 /**
0791  ** SCSI Structures
0792  **/
0793 
0794 /*
0795  * Inquiry Data Format
0796  */
0797 typedef struct {
0798    uint8_t   DeviceType;
0799    uint8_t   DeviceTypeQualifier;
0800    uint8_t   Version;
0801    uint8_t   ResponseDataFormat;
0802    uint8_t   AdditionalLength;
0803    uint8_t   Reserved;
0804    uint8_t   Flags[2];
0805    uint8_t   VendorId[8];
0806    uint8_t   ProductId[16];
0807    uint8_t   ProductRevisionLevel[4];
0808    uint8_t   Reserved2;                                  /* Provides NULL terminator to name */
0809 } IPS_SCSI_INQ_DATA, *PIPS_SCSI_INQ_DATA;
0810 
0811 /*
0812  * Read Capacity Data Format
0813  */
0814 typedef struct {
0815    uint32_t lba;
0816    uint32_t len;
0817 } IPS_SCSI_CAPACITY;
0818 
0819 /*
0820  * Request Sense Data Format
0821  */
0822 typedef struct {
0823    uint8_t  ResponseCode;
0824    uint8_t  SegmentNumber;
0825    uint8_t  Flags;
0826    uint8_t  Information[4];
0827    uint8_t  AdditionalLength;
0828    uint8_t  CommandSpecific[4];
0829    uint8_t  AdditionalSenseCode;
0830    uint8_t  AdditionalSenseCodeQual;
0831    uint8_t  FRUCode;
0832    uint8_t  SenseKeySpecific[3];
0833 } IPS_SCSI_REQSEN;
0834 
0835 /*
0836  * Sense Data Format - Page 3
0837  */
0838 typedef struct {
0839    uint8_t  PageCode;
0840    uint8_t  PageLength;
0841    uint16_t TracksPerZone;
0842    uint16_t AltSectorsPerZone;
0843    uint16_t AltTracksPerZone;
0844    uint16_t AltTracksPerVolume;
0845    uint16_t SectorsPerTrack;
0846    uint16_t BytesPerSector;
0847    uint16_t Interleave;
0848    uint16_t TrackSkew;
0849    uint16_t CylinderSkew;
0850    uint8_t  flags;
0851    uint8_t  reserved[3];
0852 } IPS_SCSI_MODE_PAGE3;
0853 
0854 /*
0855  * Sense Data Format - Page 4
0856  */
0857 typedef struct {
0858    uint8_t  PageCode;
0859    uint8_t  PageLength;
0860    uint16_t CylindersHigh;
0861    uint8_t  CylindersLow;
0862    uint8_t  Heads;
0863    uint16_t WritePrecompHigh;
0864    uint8_t  WritePrecompLow;
0865    uint16_t ReducedWriteCurrentHigh;
0866    uint8_t  ReducedWriteCurrentLow;
0867    uint16_t StepRate;
0868    uint16_t LandingZoneHigh;
0869    uint8_t  LandingZoneLow;
0870    uint8_t  flags;
0871    uint8_t  RotationalOffset;
0872    uint8_t  Reserved;
0873    uint16_t MediumRotationRate;
0874    uint8_t  Reserved2[2];
0875 } IPS_SCSI_MODE_PAGE4;
0876 
0877 /*
0878  * Sense Data Format - Page 8
0879  */
0880 typedef struct {
0881    uint8_t  PageCode;
0882    uint8_t  PageLength;
0883    uint8_t  flags;
0884    uint8_t  RetentPrio;
0885    uint16_t DisPrefetchLen;
0886    uint16_t MinPrefetchLen;
0887    uint16_t MaxPrefetchLen;
0888    uint16_t MaxPrefetchCeiling;
0889 } IPS_SCSI_MODE_PAGE8;
0890 
0891 /*
0892  * Sense Data Format - Block Descriptor (DASD)
0893  */
0894 typedef struct {
0895    uint32_t NumberOfBlocks;
0896    uint8_t  DensityCode;
0897    uint16_t BlockLengthHigh;
0898    uint8_t  BlockLengthLow;
0899 } IPS_SCSI_MODE_PAGE_BLKDESC;
0900 
0901 /*
0902  * Sense Data Format - Mode Page Header
0903  */
0904 typedef struct {
0905    uint8_t  DataLength;
0906    uint8_t  MediumType;
0907    uint8_t  Reserved;
0908    uint8_t  BlockDescLength;
0909 } IPS_SCSI_MODE_PAGE_HEADER;
0910 
0911 typedef struct {
0912    IPS_SCSI_MODE_PAGE_HEADER  hdr;
0913    IPS_SCSI_MODE_PAGE_BLKDESC blkdesc;
0914 
0915    union {
0916       IPS_SCSI_MODE_PAGE3 pg3;
0917       IPS_SCSI_MODE_PAGE4 pg4;
0918       IPS_SCSI_MODE_PAGE8 pg8;
0919    } pdata;
0920 } IPS_SCSI_MODE_PAGE_DATA;
0921 
0922 /*
0923  * Scatter Gather list format
0924  */
0925 typedef struct ips_sglist {
0926    uint32_t address;
0927    uint32_t length;
0928 } IPS_STD_SG_LIST;
0929 
0930 typedef struct ips_enh_sglist {
0931    uint32_t address_lo;
0932    uint32_t address_hi;
0933    uint32_t length;
0934    uint32_t reserved;
0935 } IPS_ENH_SG_LIST;
0936 
0937 typedef union {
0938    void             *list;
0939    IPS_STD_SG_LIST  *std_list;
0940    IPS_ENH_SG_LIST  *enh_list;
0941 } IPS_SG_LIST;
0942 
0943 typedef struct {
0944    char *option_name;
0945    int  *option_flag;
0946    int   option_value;
0947 } IPS_OPTION;
0948 
0949 /*
0950  * Status Info
0951  */
0952 typedef struct ips_stat {
0953    uint32_t residue_len;
0954    void     *scb_addr;
0955    uint8_t  padding[12 - sizeof(void *)];
0956 } ips_stat_t;
0957 
0958 /*
0959  * SCB Queue Format
0960  */
0961 typedef struct ips_scb_queue {
0962    struct ips_scb *head;
0963    struct ips_scb *tail;
0964    int             count;
0965 } ips_scb_queue_t;
0966 
0967 /*
0968  * Wait queue_format
0969  */
0970 typedef struct ips_wait_queue {
0971     struct scsi_cmnd *head;
0972     struct scsi_cmnd *tail;
0973     int count;
0974 } ips_wait_queue_entry_t;
0975 
0976 typedef struct ips_copp_wait_item {
0977     struct scsi_cmnd *scsi_cmd;
0978     struct ips_copp_wait_item *next;
0979 } ips_copp_wait_item_t;
0980 
0981 typedef struct ips_copp_queue {
0982    struct ips_copp_wait_item *head;
0983    struct ips_copp_wait_item *tail;
0984    int                        count;
0985 } ips_copp_queue_t;
0986 
0987 /* forward decl for host structure */
0988 struct ips_ha;
0989 
0990 typedef struct {
0991    int       (*reset)(struct ips_ha *);
0992    int       (*issue)(struct ips_ha *, struct ips_scb *);
0993    int       (*isinit)(struct ips_ha *);
0994    int       (*isintr)(struct ips_ha *);
0995    int       (*init)(struct ips_ha *);
0996    int       (*erasebios)(struct ips_ha *);
0997    int       (*programbios)(struct ips_ha *, char *, uint32_t, uint32_t);
0998    int       (*verifybios)(struct ips_ha *, char *, uint32_t, uint32_t);
0999    void      (*statinit)(struct ips_ha *);
1000    int       (*intr)(struct ips_ha *);
1001    void      (*enableint)(struct ips_ha *);
1002    uint32_t (*statupd)(struct ips_ha *);
1003 } ips_hw_func_t;
1004 
1005 typedef struct ips_ha {
1006    uint8_t            ha_id[IPS_MAX_CHANNELS+1];
1007    uint32_t           dcdb_active[IPS_MAX_CHANNELS];
1008    uint32_t           io_addr;            /* Base I/O address           */
1009    uint8_t            ntargets;           /* Number of targets          */
1010    uint8_t            nbus;               /* Number of buses            */
1011    uint8_t            nlun;               /* Number of Luns             */
1012    uint16_t           ad_type;            /* Adapter type               */
1013    uint16_t           host_num;           /* Adapter number             */
1014    uint32_t           max_xfer;           /* Maximum Xfer size          */
1015    uint32_t           max_cmds;           /* Max concurrent commands    */
1016    uint32_t           num_ioctl;          /* Number of Ioctls           */
1017    ips_stat_t         sp;                 /* Status packer pointer      */
1018    struct ips_scb    *scbs;               /* Array of all CCBS          */
1019    struct ips_scb    *scb_freelist;       /* SCB free list              */
1020    ips_wait_queue_entry_t   scb_waitlist;       /* Pending SCB list           */
1021    ips_copp_queue_t   copp_waitlist;      /* Pending PT list            */
1022    ips_scb_queue_t    scb_activelist;     /* Active SCB list            */
1023    IPS_IO_CMD        *dummy;              /* dummy command              */
1024    IPS_ADAPTER       *adapt;              /* Adapter status area        */
1025    IPS_LD_INFO       *logical_drive_info; /* Adapter Logical Drive Info */
1026    dma_addr_t         logical_drive_info_dma_addr; /* Logical Drive Info DMA Address */
1027    IPS_ENQ           *enq;                /* Adapter Enquiry data       */
1028    IPS_CONF          *conf;               /* Adapter config data        */
1029    IPS_NVRAM_P5      *nvram;              /* NVRAM page 5 data          */
1030    IPS_SUBSYS        *subsys;             /* Subsystem parameters       */
1031    char              *ioctl_data;         /* IOCTL data area            */
1032    uint32_t           ioctl_datasize;     /* IOCTL data size            */
1033    uint32_t           cmd_in_progress;    /* Current command in progress*/
1034    int                flags;              /*                            */
1035    uint8_t            waitflag;           /* are we waiting for cmd     */
1036    uint8_t            active;
1037    int                ioctl_reset;        /* IOCTL Requested Reset Flag */
1038    uint16_t           reset_count;        /* number of resets           */
1039    time64_t           last_ffdc;          /* last time we sent ffdc info*/
1040    uint8_t            slot_num;           /* PCI Slot Number            */
1041    int                ioctl_len;          /* size of ioctl buffer       */
1042    dma_addr_t         ioctl_busaddr;      /* dma address of ioctl buffer*/
1043    uint8_t            bios_version[8];    /* BIOS Revision              */
1044    uint32_t           mem_addr;           /* Memory mapped address      */
1045    uint32_t           io_len;             /* Size of IO Address         */
1046    uint32_t           mem_len;            /* Size of memory address     */
1047    char              __iomem *mem_ptr;    /* Memory mapped Ptr          */
1048    char              __iomem *ioremap_ptr;/* ioremapped memory pointer  */
1049    ips_hw_func_t      func;               /* hw function pointers       */
1050    struct pci_dev    *pcidev;             /* PCI device handle          */
1051    char              *flash_data;         /* Save Area for flash data   */
1052    int                flash_len;          /* length of flash buffer     */
1053    u32                flash_datasize;     /* Save Area for flash data size */
1054    dma_addr_t         flash_busaddr;      /* dma address of flash buffer*/
1055    dma_addr_t         enq_busaddr;        /* dma address of enq struct  */
1056    uint8_t            requires_esl;       /* Requires an EraseStripeLock */
1057 } ips_ha_t;
1058 
1059 typedef void (*ips_scb_callback) (ips_ha_t *, struct ips_scb *);
1060 
1061 /*
1062  * SCB Format
1063  */
1064 typedef struct ips_scb {
1065    IPS_HOST_COMMAND  cmd;
1066    IPS_DCDB_TABLE    dcdb;
1067    uint8_t           target_id;
1068    uint8_t           bus;
1069    uint8_t           lun;
1070    uint8_t           cdb[12];
1071    uint32_t          scb_busaddr;
1072    uint32_t          old_data_busaddr;  // Obsolete, but kept for old utility compatibility
1073    uint32_t          timeout;
1074    uint8_t           basic_status;
1075    uint8_t           extended_status;
1076    uint8_t           breakup;
1077    uint8_t           sg_break;
1078    uint32_t          data_len;
1079    uint32_t          sg_len;
1080    uint32_t          flags;
1081    uint32_t          op_code;
1082    IPS_SG_LIST       sg_list;
1083    struct scsi_cmnd *scsi_cmd;
1084    struct ips_scb   *q_next;
1085    ips_scb_callback  callback;
1086    uint32_t          sg_busaddr;
1087    int               sg_count;
1088    dma_addr_t        data_busaddr;
1089 } ips_scb_t;
1090 
1091 typedef struct ips_scb_pt {
1092    IPS_HOST_COMMAND  cmd;
1093    IPS_DCDB_TABLE    dcdb;
1094    uint8_t           target_id;
1095    uint8_t           bus;
1096    uint8_t           lun;
1097    uint8_t           cdb[12];
1098    uint32_t          scb_busaddr;
1099    uint32_t          data_busaddr;
1100    uint32_t          timeout;
1101    uint8_t           basic_status;
1102    uint8_t           extended_status;
1103    uint16_t          breakup;
1104    uint32_t          data_len;
1105    uint32_t          sg_len;
1106    uint32_t          flags;
1107    uint32_t          op_code;
1108    IPS_SG_LIST      *sg_list;
1109    struct scsi_cmnd *scsi_cmd;
1110    struct ips_scb   *q_next;
1111    ips_scb_callback  callback;
1112 } ips_scb_pt_t;
1113 
1114 /*
1115  * Passthru Command Format
1116  */
1117 typedef struct {
1118    uint8_t       CoppID[4];
1119    uint32_t      CoppCmd;
1120    uint32_t      PtBuffer;
1121    uint8_t      *CmdBuffer;
1122    uint32_t      CmdBSize;
1123    ips_scb_pt_t  CoppCP;
1124    uint32_t      TimeOut;
1125    uint8_t       BasicStatus;
1126    uint8_t       ExtendedStatus;
1127    uint8_t       AdapterType;
1128    uint8_t       reserved;
1129 } ips_passthru_t;
1130 
1131 #endif
1132 
1133 /* The Version Information below gets created by SED during the build process. */
1134 /* Do not modify the next line; it's what SED is looking for to do the insert. */
1135 /* Version Info                                                                */
1136 /*************************************************************************
1137 *
1138 * VERSION.H -- version numbers and copyright notices in various formats
1139 *
1140 *************************************************************************/
1141 
1142 #define IPS_VER_MAJOR 7
1143 #define IPS_VER_MAJOR_STRING __stringify(IPS_VER_MAJOR)
1144 #define IPS_VER_MINOR 12
1145 #define IPS_VER_MINOR_STRING __stringify(IPS_VER_MINOR)
1146 #define IPS_VER_BUILD 05
1147 #define IPS_VER_BUILD_STRING __stringify(IPS_VER_BUILD)
1148 #define IPS_VER_STRING IPS_VER_MAJOR_STRING "." \
1149         IPS_VER_MINOR_STRING "." IPS_VER_BUILD_STRING
1150 #define IPS_RELEASE_ID 0x00020000
1151 #define IPS_BUILD_IDENT 761
1152 #define IPS_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002. All Rights Reserved."
1153 #define IPS_ADAPTECCOPYRIGHT_STRING "(c) Copyright Adaptec, Inc. 2002 to 2004. All Rights Reserved."
1154 #define IPS_DELLCOPYRIGHT_STRING "(c) Copyright Dell 2004. All Rights Reserved."
1155 #define IPS_NT_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002."
1156 
1157 /* Version numbers for various adapters */
1158 #define IPS_VER_SERVERAID1 "2.25.01"
1159 #define IPS_VER_SERVERAID2 "2.88.13"
1160 #define IPS_VER_NAVAJO "2.88.13"
1161 #define IPS_VER_SERVERAID3 "6.10.24"
1162 #define IPS_VER_SERVERAID4H "7.12.02"
1163 #define IPS_VER_SERVERAID4MLx "7.12.02"
1164 #define IPS_VER_SARASOTA "7.12.02"
1165 #define IPS_VER_MARCO "7.12.02"
1166 #define IPS_VER_SEBRING "7.12.02"
1167 #define IPS_VER_KEYWEST "7.12.02"
1168 
1169 /* Compatibility IDs for various adapters */
1170 #define IPS_COMPAT_UNKNOWN ""
1171 #define IPS_COMPAT_CURRENT "KW710"
1172 #define IPS_COMPAT_SERVERAID1 "2.25.01"
1173 #define IPS_COMPAT_SERVERAID2 "2.88.13"
1174 #define IPS_COMPAT_NAVAJO  "2.88.13"
1175 #define IPS_COMPAT_KIOWA "2.88.13"
1176 #define IPS_COMPAT_SERVERAID3H  "SB610"
1177 #define IPS_COMPAT_SERVERAID3L  "SB610"
1178 #define IPS_COMPAT_SERVERAID4H  "KW710"
1179 #define IPS_COMPAT_SERVERAID4M  "KW710"
1180 #define IPS_COMPAT_SERVERAID4L  "KW710"
1181 #define IPS_COMPAT_SERVERAID4Mx "KW710"
1182 #define IPS_COMPAT_SERVERAID4Lx "KW710"
1183 #define IPS_COMPAT_SARASOTA     "KW710"
1184 #define IPS_COMPAT_MARCO        "KW710"
1185 #define IPS_COMPAT_SEBRING      "KW710"
1186 #define IPS_COMPAT_TAMPA        "KW710"
1187 #define IPS_COMPAT_KEYWEST      "KW710"
1188 #define IPS_COMPAT_BIOS "KW710"
1189 
1190 #define IPS_COMPAT_MAX_ADAPTER_TYPE 18
1191 #define IPS_COMPAT_ID_LENGTH 8
1192 
1193 #define IPS_DEFINE_COMPAT_TABLE(tablename) \
1194    char tablename[IPS_COMPAT_MAX_ADAPTER_TYPE] [IPS_COMPAT_ID_LENGTH] = { \
1195       IPS_COMPAT_UNKNOWN, \
1196       IPS_COMPAT_SERVERAID1, \
1197       IPS_COMPAT_SERVERAID2, \
1198       IPS_COMPAT_NAVAJO, \
1199       IPS_COMPAT_KIOWA, \
1200       IPS_COMPAT_SERVERAID3H, \
1201       IPS_COMPAT_SERVERAID3L, \
1202       IPS_COMPAT_SERVERAID4H, \
1203       IPS_COMPAT_SERVERAID4M, \
1204       IPS_COMPAT_SERVERAID4L, \
1205       IPS_COMPAT_SERVERAID4Mx, \
1206       IPS_COMPAT_SERVERAID4Lx, \
1207       IPS_COMPAT_SARASOTA,         /* one-channel variety of SARASOTA */  \
1208       IPS_COMPAT_SARASOTA,         /* two-channel variety of SARASOTA */  \
1209       IPS_COMPAT_MARCO, \
1210       IPS_COMPAT_SEBRING, \
1211       IPS_COMPAT_TAMPA, \
1212       IPS_COMPAT_KEYWEST \
1213    }
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