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0001 /************************************************************************** 0002 * Initio 9100 device driver for Linux. 0003 * 0004 * Copyright (c) 1994-1998 Initio Corporation 0005 * All rights reserved. 0006 * 0007 * Cleanups (c) Copyright 2007 Red Hat <alan@lxorguk.ukuu.org.uk> 0008 * 0009 * This program is free software; you can redistribute it and/or modify 0010 * it under the terms of the GNU General Public License as published by 0011 * the Free Software Foundation; either version 2, or (at your option) 0012 * any later version. 0013 * 0014 * This program is distributed in the hope that it will be useful, 0015 * but WITHOUT ANY WARRANTY; without even the implied warranty of 0016 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 0017 * GNU General Public License for more details. 0018 * 0019 * You should have received a copy of the GNU General Public License 0020 * along with this program; see the file COPYING. If not, write to 0021 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 0022 * 0023 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 0024 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 0025 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 0026 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 0027 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 0028 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 0029 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 0030 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 0031 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 0032 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 0033 * SUCH DAMAGE. 0034 * 0035 **************************************************************************/ 0036 0037 0038 #include <linux/types.h> 0039 0040 #define TOTAL_SG_ENTRY 32 0041 #define MAX_SUPPORTED_ADAPTERS 8 0042 #define MAX_OFFSET 15 0043 #define MAX_TARGETS 16 0044 0045 typedef struct { 0046 unsigned short base; 0047 unsigned short vec; 0048 } i91u_config; 0049 0050 /***************************************/ 0051 /* Tulip Configuration Register Set */ 0052 /***************************************/ 0053 #define TUL_PVID 0x00 /* Vendor ID */ 0054 #define TUL_PDID 0x02 /* Device ID */ 0055 #define TUL_PCMD 0x04 /* Command */ 0056 #define TUL_PSTUS 0x06 /* Status */ 0057 #define TUL_PRID 0x08 /* Revision number */ 0058 #define TUL_PPI 0x09 /* Programming interface */ 0059 #define TUL_PSC 0x0A /* Sub Class */ 0060 #define TUL_PBC 0x0B /* Base Class */ 0061 #define TUL_PCLS 0x0C /* Cache line size */ 0062 #define TUL_PLTR 0x0D /* Latency timer */ 0063 #define TUL_PHDT 0x0E /* Header type */ 0064 #define TUL_PBIST 0x0F /* BIST */ 0065 #define TUL_PBAD 0x10 /* Base address */ 0066 #define TUL_PBAD1 0x14 /* Base address */ 0067 #define TUL_PBAD2 0x18 /* Base address */ 0068 #define TUL_PBAD3 0x1C /* Base address */ 0069 #define TUL_PBAD4 0x20 /* Base address */ 0070 #define TUL_PBAD5 0x24 /* Base address */ 0071 #define TUL_PRSVD 0x28 /* Reserved */ 0072 #define TUL_PRSVD1 0x2C /* Reserved */ 0073 #define TUL_PRAD 0x30 /* Expansion ROM base address */ 0074 #define TUL_PRSVD2 0x34 /* Reserved */ 0075 #define TUL_PRSVD3 0x38 /* Reserved */ 0076 #define TUL_PINTL 0x3C /* Interrupt line */ 0077 #define TUL_PINTP 0x3D /* Interrupt pin */ 0078 #define TUL_PIGNT 0x3E /* MIN_GNT */ 0079 #define TUL_PMGNT 0x3F /* MAX_GNT */ 0080 0081 /************************/ 0082 /* Jasmin Register Set */ 0083 /************************/ 0084 #define TUL_HACFG0 0x40 /* H/A Configuration Register 0 */ 0085 #define TUL_HACFG1 0x41 /* H/A Configuration Register 1 */ 0086 #define TUL_HACFG2 0x42 /* H/A Configuration Register 2 */ 0087 0088 #define TUL_SDCFG0 0x44 /* SCSI Device Configuration 0 */ 0089 #define TUL_SDCFG1 0x45 /* SCSI Device Configuration 1 */ 0090 #define TUL_SDCFG2 0x46 /* SCSI Device Configuration 2 */ 0091 #define TUL_SDCFG3 0x47 /* SCSI Device Configuration 3 */ 0092 0093 #define TUL_GINTS 0x50 /* Global Interrupt Status Register */ 0094 #define TUL_GIMSK 0x52 /* Global Interrupt MASK Register */ 0095 #define TUL_GCTRL 0x54 /* Global Control Register */ 0096 #define TUL_GCTRL_EEPROM_BIT 0x04 0097 #define TUL_GCTRL1 0x55 /* Global Control Register */ 0098 #define TUL_DMACFG 0x5B /* DMA configuration */ 0099 #define TUL_NVRAM 0x5D /* Non-volatile RAM port */ 0100 0101 #define TUL_SCnt0 0x80 /* 00 R/W Transfer Counter Low */ 0102 #define TUL_SCnt1 0x81 /* 01 R/W Transfer Counter Mid */ 0103 #define TUL_SCnt2 0x82 /* 02 R/W Transfer Count High */ 0104 #define TUL_SFifoCnt 0x83 /* 03 R FIFO counter */ 0105 #define TUL_SIntEnable 0x84 /* 03 W Interrupt enble */ 0106 #define TUL_SInt 0x84 /* 04 R Interrupt Register */ 0107 #define TUL_SCtrl0 0x85 /* 05 W Control 0 */ 0108 #define TUL_SStatus0 0x85 /* 05 R Status 0 */ 0109 #define TUL_SCtrl1 0x86 /* 06 W Control 1 */ 0110 #define TUL_SStatus1 0x86 /* 06 R Status 1 */ 0111 #define TUL_SConfig 0x87 /* 07 W Configuration */ 0112 #define TUL_SStatus2 0x87 /* 07 R Status 2 */ 0113 #define TUL_SPeriod 0x88 /* 08 W Sync. Transfer Period & Offset */ 0114 #define TUL_SOffset 0x88 /* 08 R Offset */ 0115 #define TUL_SScsiId 0x89 /* 09 W SCSI ID */ 0116 #define TUL_SBusId 0x89 /* 09 R SCSI BUS ID */ 0117 #define TUL_STimeOut 0x8A /* 0A W Sel/Resel Time Out Register */ 0118 #define TUL_SIdent 0x8A /* 0A R Identify Message Register */ 0119 #define TUL_SAvail 0x8A /* 0A R Available Counter Register */ 0120 #define TUL_SData 0x8B /* 0B R/W SCSI data in/out */ 0121 #define TUL_SFifo 0x8C /* 0C R/W FIFO */ 0122 #define TUL_SSignal 0x90 /* 10 R/W SCSI signal in/out */ 0123 #define TUL_SCmd 0x91 /* 11 R/W Command */ 0124 #define TUL_STest0 0x92 /* 12 R/W Test0 */ 0125 #define TUL_STest1 0x93 /* 13 R/W Test1 */ 0126 #define TUL_SCFG1 0x94 /* 14 R/W Configuration */ 0127 0128 #define TUL_XAddH 0xC0 /*DMA Transfer Physical Address */ 0129 #define TUL_XAddW 0xC8 /*DMA Current Transfer Physical Address */ 0130 #define TUL_XCntH 0xD0 /*DMA Transfer Counter */ 0131 #define TUL_XCntW 0xD4 /*DMA Current Transfer Counter */ 0132 #define TUL_XCmd 0xD8 /*DMA Command Register */ 0133 #define TUL_Int 0xDC /*Interrupt Register */ 0134 #define TUL_XStatus 0xDD /*DMA status Register */ 0135 #define TUL_Mask 0xE0 /*Interrupt Mask Register */ 0136 #define TUL_XCtrl 0xE4 /*DMA Control Register */ 0137 #define TUL_XCtrl1 0xE5 /*DMA Control Register 1 */ 0138 #define TUL_XFifo 0xE8 /*DMA FIFO */ 0139 0140 #define TUL_WCtrl 0xF7 /*Bus master wait state control */ 0141 #define TUL_DCtrl 0xFB /*DMA delay control */ 0142 0143 /*----------------------------------------------------------------------*/ 0144 /* bit definition for Command register of Configuration Space Header */ 0145 /*----------------------------------------------------------------------*/ 0146 #define BUSMS 0x04 /* BUS MASTER Enable */ 0147 #define IOSPA 0x01 /* IO Space Enable */ 0148 0149 /*----------------------------------------------------------------------*/ 0150 /* Command Codes of Tulip SCSI Command register */ 0151 /*----------------------------------------------------------------------*/ 0152 #define TSC_EN_RESEL 0x80 /* Enable Reselection */ 0153 #define TSC_CMD_COMP 0x84 /* Command Complete Sequence */ 0154 #define TSC_SEL 0x01 /* Select Without ATN Sequence */ 0155 #define TSC_SEL_ATN 0x11 /* Select With ATN Sequence */ 0156 #define TSC_SEL_ATN_DMA 0x51 /* Select With ATN Sequence with DMA */ 0157 #define TSC_SEL_ATN3 0x31 /* Select With ATN3 Sequence */ 0158 #define TSC_SEL_ATNSTOP 0x12 /* Select With ATN and Stop Sequence */ 0159 #define TSC_SELATNSTOP 0x1E /* Select With ATN and Stop Sequence */ 0160 0161 #define TSC_SEL_ATN_DIRECT_IN 0x95 /* Select With ATN Sequence */ 0162 #define TSC_SEL_ATN_DIRECT_OUT 0x15 /* Select With ATN Sequence */ 0163 #define TSC_SEL_ATN3_DIRECT_IN 0xB5 /* Select With ATN3 Sequence */ 0164 #define TSC_SEL_ATN3_DIRECT_OUT 0x35 /* Select With ATN3 Sequence */ 0165 #define TSC_XF_DMA_OUT_DIRECT 0x06 /* DMA Xfer Information out */ 0166 #define TSC_XF_DMA_IN_DIRECT 0x86 /* DMA Xfer Information in */ 0167 0168 #define TSC_XF_DMA_OUT 0x43 /* DMA Xfer Information out */ 0169 #define TSC_XF_DMA_IN 0xC3 /* DMA Xfer Information in */ 0170 #define TSC_XF_FIFO_OUT 0x03 /* FIFO Xfer Information out */ 0171 #define TSC_XF_FIFO_IN 0x83 /* FIFO Xfer Information in */ 0172 0173 #define TSC_MSG_ACCEPT 0x0F /* Message Accept */ 0174 0175 /*----------------------------------------------------------------------*/ 0176 /* bit definition for Tulip SCSI Control 0 Register */ 0177 /*----------------------------------------------------------------------*/ 0178 #define TSC_RST_SEQ 0x20 /* Reset sequence counter */ 0179 #define TSC_FLUSH_FIFO 0x10 /* Flush FIFO */ 0180 #define TSC_ABT_CMD 0x04 /* Abort command (sequence) */ 0181 #define TSC_RST_CHIP 0x02 /* Reset SCSI Chip */ 0182 #define TSC_RST_BUS 0x01 /* Reset SCSI Bus */ 0183 0184 /*----------------------------------------------------------------------*/ 0185 /* bit definition for Tulip SCSI Control 1 Register */ 0186 /*----------------------------------------------------------------------*/ 0187 #define TSC_EN_SCAM 0x80 /* Enable SCAM */ 0188 #define TSC_TIMER 0x40 /* Select timeout unit */ 0189 #define TSC_EN_SCSI2 0x20 /* SCSI-2 mode */ 0190 #define TSC_PWDN 0x10 /* Power down mode */ 0191 #define TSC_WIDE_CPU 0x08 /* Wide CPU */ 0192 #define TSC_HW_RESELECT 0x04 /* Enable HW reselect */ 0193 #define TSC_EN_BUS_OUT 0x02 /* Enable SCSI data bus out latch */ 0194 #define TSC_EN_BUS_IN 0x01 /* Enable SCSI data bus in latch */ 0195 0196 /*----------------------------------------------------------------------*/ 0197 /* bit definition for Tulip SCSI Configuration Register */ 0198 /*----------------------------------------------------------------------*/ 0199 #define TSC_EN_LATCH 0x80 /* Enable phase latch */ 0200 #define TSC_INITIATOR 0x40 /* Initiator mode */ 0201 #define TSC_EN_SCSI_PAR 0x20 /* Enable SCSI parity */ 0202 #define TSC_DMA_8BIT 0x10 /* Alternate dma 8-bits mode */ 0203 #define TSC_DMA_16BIT 0x08 /* Alternate dma 16-bits mode */ 0204 #define TSC_EN_WDACK 0x04 /* Enable DACK while wide SCSI xfer */ 0205 #define TSC_ALT_PERIOD 0x02 /* Alternate sync period mode */ 0206 #define TSC_DIS_SCSIRST 0x01 /* Disable SCSI bus reset us */ 0207 0208 #define TSC_INITDEFAULT (TSC_INITIATOR | TSC_EN_LATCH | TSC_ALT_PERIOD | TSC_DIS_SCSIRST) 0209 0210 #define TSC_WIDE_SCSI 0x80 /* Enable Wide SCSI */ 0211 0212 /*----------------------------------------------------------------------*/ 0213 /* bit definition for Tulip SCSI signal Register */ 0214 /*----------------------------------------------------------------------*/ 0215 #define TSC_RST_ACK 0x00 /* Release ACK signal */ 0216 #define TSC_RST_ATN 0x00 /* Release ATN signal */ 0217 #define TSC_RST_BSY 0x00 /* Release BSY signal */ 0218 0219 #define TSC_SET_ACK 0x40 /* ACK signal */ 0220 #define TSC_SET_ATN 0x08 /* ATN signal */ 0221 0222 #define TSC_REQI 0x80 /* REQ signal */ 0223 #define TSC_ACKI 0x40 /* ACK signal */ 0224 #define TSC_BSYI 0x20 /* BSY signal */ 0225 #define TSC_SELI 0x10 /* SEL signal */ 0226 #define TSC_ATNI 0x08 /* ATN signal */ 0227 #define TSC_MSGI 0x04 /* MSG signal */ 0228 #define TSC_CDI 0x02 /* C/D signal */ 0229 #define TSC_IOI 0x01 /* I/O signal */ 0230 0231 0232 /*----------------------------------------------------------------------*/ 0233 /* bit definition for Tulip SCSI Status 0 Register */ 0234 /*----------------------------------------------------------------------*/ 0235 #define TSS_INT_PENDING 0x80 /* Interrupt pending */ 0236 #define TSS_SEQ_ACTIVE 0x40 /* Sequencer active */ 0237 #define TSS_XFER_CNT 0x20 /* Transfer counter zero */ 0238 #define TSS_FIFO_EMPTY 0x10 /* FIFO empty */ 0239 #define TSS_PAR_ERROR 0x08 /* SCSI parity error */ 0240 #define TSS_PH_MASK 0x07 /* SCSI phase mask */ 0241 0242 /*----------------------------------------------------------------------*/ 0243 /* bit definition for Tulip SCSI Status 1 Register */ 0244 /*----------------------------------------------------------------------*/ 0245 #define TSS_STATUS_RCV 0x08 /* Status received */ 0246 #define TSS_MSG_SEND 0x40 /* Message sent */ 0247 #define TSS_CMD_PH_CMP 0x20 /* command phase done */ 0248 #define TSS_DATA_PH_CMP 0x10 /* Data phase done */ 0249 #define TSS_STATUS_SEND 0x08 /* Status sent */ 0250 #define TSS_XFER_CMP 0x04 /* Transfer completed */ 0251 #define TSS_SEL_CMP 0x02 /* Selection completed */ 0252 #define TSS_ARB_CMP 0x01 /* Arbitration completed */ 0253 0254 /*----------------------------------------------------------------------*/ 0255 /* bit definition for Tulip SCSI Status 2 Register */ 0256 /*----------------------------------------------------------------------*/ 0257 #define TSS_CMD_ABTED 0x80 /* Command aborted */ 0258 #define TSS_OFFSET_0 0x40 /* Offset counter zero */ 0259 #define TSS_FIFO_FULL 0x20 /* FIFO full */ 0260 #define TSS_TIMEOUT_0 0x10 /* Timeout counter zero */ 0261 #define TSS_BUSY_RLS 0x08 /* Busy release */ 0262 #define TSS_PH_MISMATCH 0x04 /* Phase mismatch */ 0263 #define TSS_SCSI_BUS_EN 0x02 /* SCSI data bus enable */ 0264 #define TSS_SCSIRST 0x01 /* SCSI bus reset in progress */ 0265 0266 /*----------------------------------------------------------------------*/ 0267 /* bit definition for Tulip SCSI Interrupt Register */ 0268 /*----------------------------------------------------------------------*/ 0269 #define TSS_RESEL_INT 0x80 /* Reselected interrupt */ 0270 #define TSS_SEL_TIMEOUT 0x40 /* Selected/reselected timeout */ 0271 #define TSS_BUS_SERV 0x20 0272 #define TSS_SCSIRST_INT 0x10 /* SCSI bus reset detected */ 0273 #define TSS_DISC_INT 0x08 /* Disconnected interrupt */ 0274 #define TSS_SEL_INT 0x04 /* Select interrupt */ 0275 #define TSS_SCAM_SEL 0x02 /* SCAM selected */ 0276 #define TSS_FUNC_COMP 0x01 0277 0278 /*----------------------------------------------------------------------*/ 0279 /* SCSI Phase Codes. */ 0280 /*----------------------------------------------------------------------*/ 0281 #define DATA_OUT 0 0282 #define DATA_IN 1 /* 4 */ 0283 #define CMD_OUT 2 0284 #define STATUS_IN 3 /* 6 */ 0285 #define MSG_OUT 6 /* 3 */ 0286 #define MSG_IN 7 0287 0288 0289 0290 /*----------------------------------------------------------------------*/ 0291 /* Command Codes of Tulip xfer Command register */ 0292 /*----------------------------------------------------------------------*/ 0293 #define TAX_X_FORC 0x02 0294 #define TAX_X_ABT 0x04 0295 #define TAX_X_CLR_FIFO 0x08 0296 0297 #define TAX_X_IN 0x21 0298 #define TAX_X_OUT 0x01 0299 #define TAX_SG_IN 0xA1 0300 #define TAX_SG_OUT 0x81 0301 0302 /*----------------------------------------------------------------------*/ 0303 /* Tulip Interrupt Register */ 0304 /*----------------------------------------------------------------------*/ 0305 #define XCMP 0x01 0306 #define FCMP 0x02 0307 #define XABT 0x04 0308 #define XERR 0x08 0309 #define SCMP 0x10 0310 #define IPEND 0x80 0311 0312 /*----------------------------------------------------------------------*/ 0313 /* Tulip DMA Status Register */ 0314 /*----------------------------------------------------------------------*/ 0315 #define XPEND 0x01 /* Transfer pending */ 0316 #define FEMPTY 0x02 /* FIFO empty */ 0317 0318 0319 0320 /*----------------------------------------------------------------------*/ 0321 /* bit definition for TUL_GCTRL */ 0322 /*----------------------------------------------------------------------*/ 0323 #define EXTSG 0x80 0324 #define EXTAD 0x60 0325 #define SEG4K 0x08 0326 #define EEPRG 0x04 0327 #define MRMUL 0x02 0328 0329 /*----------------------------------------------------------------------*/ 0330 /* bit definition for TUL_NVRAM */ 0331 /*----------------------------------------------------------------------*/ 0332 #define SE2CS 0x08 0333 #define SE2CLK 0x04 0334 #define SE2DO 0x02 0335 #define SE2DI 0x01 0336 0337 0338 /************************************************************************/ 0339 /* Scatter-Gather Element Structure */ 0340 /************************************************************************/ 0341 struct sg_entry { 0342 u32 data; /* Data Pointer */ 0343 u32 len; /* Data Length */ 0344 }; 0345 0346 /*********************************************************************** 0347 SCSI Control Block 0348 ************************************************************************/ 0349 struct scsi_ctrl_blk { 0350 struct scsi_ctrl_blk *next; 0351 u8 status; /*4 */ 0352 u8 next_state; /*5 */ 0353 u8 mode; /*6 */ 0354 u8 msgin; /*7 SCB_Res0 */ 0355 u16 sgidx; /*8 */ 0356 u16 sgmax; /*A */ 0357 #ifdef ALPHA 0358 u32 reserved[2]; /*C */ 0359 #else 0360 u32 reserved[3]; /*C */ 0361 #endif 0362 0363 u32 xferlen; /*18 Current xfer len */ 0364 u32 totxlen; /*1C Total xfer len */ 0365 u32 paddr; /*20 SCB phy. Addr. */ 0366 0367 u8 opcode; /*24 SCB command code */ 0368 u8 flags; /*25 SCB Flags */ 0369 u8 target; /*26 Target Id */ 0370 u8 lun; /*27 Lun */ 0371 u32 bufptr; /*28 Data Buffer Pointer */ 0372 u32 buflen; /*2C Data Allocation Length */ 0373 u8 sglen; /*30 SG list # */ 0374 u8 senselen; /*31 Sense Allocation Length */ 0375 u8 hastat; /*32 */ 0376 u8 tastat; /*33 */ 0377 u8 cdblen; /*34 CDB Length */ 0378 u8 ident; /*35 Identify */ 0379 u8 tagmsg; /*36 Tag Message */ 0380 u8 tagid; /*37 Queue Tag */ 0381 u8 cdb[12]; /*38 */ 0382 u32 sgpaddr; /*44 SG List/Sense Buf phy. Addr. */ 0383 u32 senseptr; /*48 Sense data pointer */ 0384 void (*post) (u8 *, u8 *); /*4C POST routine */ 0385 struct scsi_cmnd *srb; /*50 SRB Pointer */ 0386 struct sg_entry sglist[TOTAL_SG_ENTRY]; /*54 Start of SG list */ 0387 }; 0388 0389 /* Bit Definition for status */ 0390 #define SCB_RENT 0x01 0391 #define SCB_PEND 0x02 0392 #define SCB_CONTIG 0x04 /* Contingent Allegiance */ 0393 #define SCB_SELECT 0x08 0394 #define SCB_BUSY 0x10 0395 #define SCB_DONE 0x20 0396 0397 0398 /* Opcodes for opcode */ 0399 #define ExecSCSI 0x1 0400 #define BusDevRst 0x2 0401 #define AbortCmd 0x3 0402 0403 0404 /* Bit Definition for mode */ 0405 #define SCM_RSENS 0x01 /* request sense mode */ 0406 0407 0408 /* Bit Definition for flags */ 0409 #define SCF_DONE 0x01 0410 #define SCF_POST 0x02 0411 #define SCF_SENSE 0x04 0412 #define SCF_DIR 0x18 0413 #define SCF_NO_DCHK 0x00 0414 #define SCF_DIN 0x08 0415 #define SCF_DOUT 0x10 0416 #define SCF_NO_XF 0x18 0417 #define SCF_WR_VF 0x20 /* Write verify turn on */ 0418 #define SCF_POLL 0x40 0419 #define SCF_SG 0x80 0420 0421 /* Error Codes for SCB_HaStat */ 0422 #define HOST_SEL_TOUT 0x11 0423 #define HOST_DO_DU 0x12 0424 #define HOST_BUS_FREE 0x13 0425 #define HOST_BAD_PHAS 0x14 0426 #define HOST_INV_CMD 0x16 0427 #define HOST_ABORTED 0x1A /* 07/21/98 */ 0428 #define HOST_SCSI_RST 0x1B 0429 #define HOST_DEV_RST 0x1C 0430 0431 /* Error Codes for SCB_TaStat */ 0432 #define TARGET_CHKCOND 0x02 0433 #define TARGET_BUSY 0x08 0434 #define INI_QUEUE_FULL 0x28 0435 0436 /*********************************************************************** 0437 Target Device Control Structure 0438 **********************************************************************/ 0439 0440 struct target_control { 0441 u16 flags; 0442 u8 js_period; 0443 u8 sconfig0; 0444 u16 drv_flags; 0445 u8 heads; 0446 u8 sectors; 0447 }; 0448 0449 /*********************************************************************** 0450 Target Device Control Structure 0451 **********************************************************************/ 0452 0453 /* Bit Definition for TCF_Flags */ 0454 #define TCF_SCSI_RATE 0x0007 0455 #define TCF_EN_DISC 0x0008 0456 #define TCF_NO_SYNC_NEGO 0x0010 0457 #define TCF_NO_WDTR 0x0020 0458 #define TCF_EN_255 0x0040 0459 #define TCF_EN_START 0x0080 0460 #define TCF_WDTR_DONE 0x0100 0461 #define TCF_SYNC_DONE 0x0200 0462 #define TCF_BUSY 0x0400 0463 0464 0465 /* Bit Definition for TCF_DrvFlags */ 0466 #define TCF_DRV_BUSY 0x01 /* Indicate target busy(driver) */ 0467 #define TCF_DRV_EN_TAG 0x0800 0468 #define TCF_DRV_255_63 0x0400 0469 0470 /*********************************************************************** 0471 Host Adapter Control Structure 0472 ************************************************************************/ 0473 struct initio_host { 0474 u16 addr; /* 00 */ 0475 u16 bios_addr; /* 02 */ 0476 u8 irq; /* 04 */ 0477 u8 scsi_id; /* 05 */ 0478 u8 max_tar; /* 06 */ 0479 u8 num_scbs; /* 07 */ 0480 0481 u8 flags; /* 08 */ 0482 u8 index; /* 09 */ 0483 u8 ha_id; /* 0A */ 0484 u8 config; /* 0B */ 0485 u16 idmask; /* 0C */ 0486 u8 semaph; /* 0E */ 0487 u8 phase; /* 0F */ 0488 u8 jsstatus0; /* 10 */ 0489 u8 jsint; /* 11 */ 0490 u8 jsstatus1; /* 12 */ 0491 u8 sconf1; /* 13 */ 0492 0493 u8 msg[8]; /* 14 */ 0494 struct scsi_ctrl_blk *next_avail; /* 1C */ 0495 struct scsi_ctrl_blk *scb; /* 20 */ 0496 struct scsi_ctrl_blk *scb_end; /* 24 */ /*UNUSED*/ 0497 struct scsi_ctrl_blk *next_pending; /* 28 */ 0498 struct scsi_ctrl_blk *next_contig; /* 2C */ /*UNUSED*/ 0499 struct scsi_ctrl_blk *active; /* 30 */ 0500 struct target_control *active_tc; /* 34 */ 0501 0502 struct scsi_ctrl_blk *first_avail; /* 38 */ 0503 struct scsi_ctrl_blk *last_avail; /* 3C */ 0504 struct scsi_ctrl_blk *first_pending; /* 40 */ 0505 struct scsi_ctrl_blk *last_pending; /* 44 */ 0506 struct scsi_ctrl_blk *first_busy; /* 48 */ 0507 struct scsi_ctrl_blk *last_busy; /* 4C */ 0508 struct scsi_ctrl_blk *first_done; /* 50 */ 0509 struct scsi_ctrl_blk *last_done; /* 54 */ 0510 u8 max_tags[16]; /* 58 */ 0511 u8 act_tags[16]; /* 68 */ 0512 struct target_control targets[MAX_TARGETS]; /* 78 */ 0513 spinlock_t avail_lock; 0514 spinlock_t semaph_lock; 0515 struct pci_dev *pci_dev; 0516 }; 0517 0518 /* Bit Definition for HCB_Config */ 0519 #define HCC_SCSI_RESET 0x01 0520 #define HCC_EN_PAR 0x02 0521 #define HCC_ACT_TERM1 0x04 0522 #define HCC_ACT_TERM2 0x08 0523 #define HCC_AUTO_TERM 0x10 0524 #define HCC_EN_PWR 0x80 0525 0526 /* Bit Definition for HCB_Flags */ 0527 #define HCF_EXPECT_DISC 0x01 0528 #define HCF_EXPECT_SELECT 0x02 0529 #define HCF_EXPECT_RESET 0x10 0530 #define HCF_EXPECT_DONE_DISC 0x20 0531 0532 /****************************************************************** 0533 Serial EEProm 0534 *******************************************************************/ 0535 0536 typedef struct _NVRAM_SCSI { /* SCSI channel configuration */ 0537 u8 NVM_ChSCSIID; /* 0Ch -> Channel SCSI ID */ 0538 u8 NVM_ChConfig1; /* 0Dh -> Channel config 1 */ 0539 u8 NVM_ChConfig2; /* 0Eh -> Channel config 2 */ 0540 u8 NVM_NumOfTarg; /* 0Fh -> Number of SCSI target */ 0541 /* SCSI target configuration */ 0542 u8 NVM_Targ0Config; /* 10h -> Target 0 configuration */ 0543 u8 NVM_Targ1Config; /* 11h -> Target 1 configuration */ 0544 u8 NVM_Targ2Config; /* 12h -> Target 2 configuration */ 0545 u8 NVM_Targ3Config; /* 13h -> Target 3 configuration */ 0546 u8 NVM_Targ4Config; /* 14h -> Target 4 configuration */ 0547 u8 NVM_Targ5Config; /* 15h -> Target 5 configuration */ 0548 u8 NVM_Targ6Config; /* 16h -> Target 6 configuration */ 0549 u8 NVM_Targ7Config; /* 17h -> Target 7 configuration */ 0550 u8 NVM_Targ8Config; /* 18h -> Target 8 configuration */ 0551 u8 NVM_Targ9Config; /* 19h -> Target 9 configuration */ 0552 u8 NVM_TargAConfig; /* 1Ah -> Target A configuration */ 0553 u8 NVM_TargBConfig; /* 1Bh -> Target B configuration */ 0554 u8 NVM_TargCConfig; /* 1Ch -> Target C configuration */ 0555 u8 NVM_TargDConfig; /* 1Dh -> Target D configuration */ 0556 u8 NVM_TargEConfig; /* 1Eh -> Target E configuration */ 0557 u8 NVM_TargFConfig; /* 1Fh -> Target F configuration */ 0558 } NVRAM_SCSI; 0559 0560 typedef struct _NVRAM { 0561 /*----------header ---------------*/ 0562 u16 NVM_Signature; /* 0,1: Signature */ 0563 u8 NVM_Size; /* 2: Size of data structure */ 0564 u8 NVM_Revision; /* 3: Revision of data structure */ 0565 /* ----Host Adapter Structure ---- */ 0566 u8 NVM_ModelByte0; /* 4: Model number (byte 0) */ 0567 u8 NVM_ModelByte1; /* 5: Model number (byte 1) */ 0568 u8 NVM_ModelInfo; /* 6: Model information */ 0569 u8 NVM_NumOfCh; /* 7: Number of SCSI channel */ 0570 u8 NVM_BIOSConfig1; /* 8: BIOS configuration 1 */ 0571 u8 NVM_BIOSConfig2; /* 9: BIOS configuration 2 */ 0572 u8 NVM_HAConfig1; /* A: Hoat adapter configuration 1 */ 0573 u8 NVM_HAConfig2; /* B: Hoat adapter configuration 2 */ 0574 NVRAM_SCSI NVM_SCSIInfo[2]; 0575 u8 NVM_reserved[10]; 0576 /* ---------- CheckSum ---------- */ 0577 u16 NVM_CheckSum; /* 0x3E, 0x3F: Checksum of NVRam */ 0578 } NVRAM, *PNVRAM; 0579 0580 /* Bios Configuration for nvram->BIOSConfig1 */ 0581 #define NBC1_ENABLE 0x01 /* BIOS enable */ 0582 #define NBC1_8DRIVE 0x02 /* Support more than 2 drives */ 0583 #define NBC1_REMOVABLE 0x04 /* Support removable drive */ 0584 #define NBC1_INT19 0x08 /* Intercept int 19h */ 0585 #define NBC1_BIOSSCAN 0x10 /* Dynamic BIOS scan */ 0586 #define NBC1_LUNSUPPORT 0x40 /* Support LUN */ 0587 0588 /* HA Configuration Byte 1 */ 0589 #define NHC1_BOOTIDMASK 0x0F /* Boot ID number */ 0590 #define NHC1_LUNMASK 0x70 /* Boot LUN number */ 0591 #define NHC1_CHANMASK 0x80 /* Boot Channel number */ 0592 0593 /* Bit definition for nvram->SCSIconfig1 */ 0594 #define NCC1_BUSRESET 0x01 /* Reset SCSI bus at power up */ 0595 #define NCC1_PARITYCHK 0x02 /* SCSI parity enable */ 0596 #define NCC1_ACTTERM1 0x04 /* Enable active terminator 1 */ 0597 #define NCC1_ACTTERM2 0x08 /* Enable active terminator 2 */ 0598 #define NCC1_AUTOTERM 0x10 /* Enable auto terminator */ 0599 #define NCC1_PWRMGR 0x80 /* Enable power management */ 0600 0601 /* Bit definition for SCSI Target configuration byte */ 0602 #define NTC_DISCONNECT 0x08 /* Enable SCSI disconnect */ 0603 #define NTC_SYNC 0x10 /* SYNC_NEGO */ 0604 #define NTC_NO_WDTR 0x20 /* SYNC_NEGO */ 0605 #define NTC_1GIGA 0x40 /* 255 head / 63 sectors (64/32) */ 0606 #define NTC_SPINUP 0x80 /* Start disk drive */ 0607 0608 /* Default NVRam values */ 0609 #define INI_SIGNATURE 0xC925 0610 #define NBC1_DEFAULT (NBC1_ENABLE) 0611 #define NCC1_DEFAULT (NCC1_BUSRESET | NCC1_AUTOTERM | NCC1_PARITYCHK) 0612 #define NTC_DEFAULT (NTC_NO_WDTR | NTC_1GIGA | NTC_DISCONNECT) 0613 0614 /* SCSI related definition */ 0615 #define DISC_NOT_ALLOW 0x80 /* Disconnect is not allowed */ 0616 #define DISC_ALLOW 0xC0 /* Disconnect is allowed */ 0617 #define SCSICMD_RequestSense 0x03 0618 0619 #define SCSI_ABORT_SNOOZE 0 0620 #define SCSI_ABORT_SUCCESS 1 0621 #define SCSI_ABORT_PENDING 2 0622 #define SCSI_ABORT_BUSY 3 0623 #define SCSI_ABORT_NOT_RUNNING 4 0624 #define SCSI_ABORT_ERROR 5 0625 0626 #define SCSI_RESET_SNOOZE 0 0627 #define SCSI_RESET_PUNT 1 0628 #define SCSI_RESET_SUCCESS 2 0629 #define SCSI_RESET_PENDING 3 0630 #define SCSI_RESET_WAKEUP 4 0631 #define SCSI_RESET_NOT_RUNNING 5 0632 #define SCSI_RESET_ERROR 6 0633 0634 #define SCSI_RESET_SYNCHRONOUS 0x01 0635 #define SCSI_RESET_ASYNCHRONOUS 0x02 0636 #define SCSI_RESET_SUGGEST_BUS_RESET 0x04 0637 #define SCSI_RESET_SUGGEST_HOST_RESET 0x08 0638 0639 #define SCSI_RESET_BUS_RESET 0x100 0640 #define SCSI_RESET_HOST_RESET 0x200 0641 #define SCSI_RESET_ACTION 0xff 0642 0643 struct initio_cmd_priv { 0644 dma_addr_t sense_dma_addr; 0645 dma_addr_t sglist_dma_addr; 0646 }; 0647 0648 static inline struct initio_cmd_priv *initio_priv(struct scsi_cmnd *cmd) 0649 { 0650 return scsi_cmd_priv(cmd); 0651 }
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