drivers/scsi/hptiop.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * HighPoint RR3xxx/4xxx controller driver for Linux
0004  * Copyright (C) 2006-2015 HighPoint Technologies, Inc. All Rights Reserved.
0005  *
0006  * Please report bugs/comments/suggestions to linux@highpoint-tech.com
0007  *
0008  * For more information, visit http://www.highpoint-tech.com
0009  */
0010 #ifndef _HPTIOP_H_
0011 #define _HPTIOP_H_
0012
0013 struct hpt_iopmu_itl {
0014     __le32 resrved0[4];
0015     __le32 inbound_msgaddr0;
0016     __le32 inbound_msgaddr1;
0017     __le32 outbound_msgaddr0;
0018     __le32 outbound_msgaddr1;
0019     __le32 inbound_doorbell;
0020     __le32 inbound_intstatus;
0021     __le32 inbound_intmask;
0022     __le32 outbound_doorbell;
0023     __le32 outbound_intstatus;
0024     __le32 outbound_intmask;
0025     __le32 reserved1[2];
0026     __le32 inbound_queue;
0027     __le32 outbound_queue;
0028 };
0029
0030 #define IOPMU_QUEUE_EMPTY            0xffffffff
0031 #define IOPMU_QUEUE_MASK_HOST_BITS   0xf0000000
0032 #define IOPMU_QUEUE_ADDR_HOST_BIT    0x80000000
0033 #define IOPMU_QUEUE_REQUEST_SIZE_BIT    0x40000000
0034 #define IOPMU_QUEUE_REQUEST_RESULT_BIT   0x40000000
0035
0036 #define IOPMU_OUTBOUND_INT_MSG0      1
0037 #define IOPMU_OUTBOUND_INT_MSG1      2
0038 #define IOPMU_OUTBOUND_INT_DOORBELL  4
0039 #define IOPMU_OUTBOUND_INT_POSTQUEUE 8
0040 #define IOPMU_OUTBOUND_INT_PCI       0x10
0041
0042 #define IOPMU_INBOUND_INT_MSG0       1
0043 #define IOPMU_INBOUND_INT_MSG1       2
0044 #define IOPMU_INBOUND_INT_DOORBELL   4
0045 #define IOPMU_INBOUND_INT_ERROR      8
0046 #define IOPMU_INBOUND_INT_POSTQUEUE  0x10
0047
0048 #define MVIOP_QUEUE_LEN  512
0049
0050 struct hpt_iopmu_mv {
0051     __le32 inbound_head;
0052     __le32 inbound_tail;
0053     __le32 outbound_head;
0054     __le32 outbound_tail;
0055     __le32 inbound_msg;
0056     __le32 outbound_msg;
0057     __le32 reserve[10];
0058     __le64 inbound_q[MVIOP_QUEUE_LEN];
0059     __le64 outbound_q[MVIOP_QUEUE_LEN];
0060 };
0061
0062 struct hpt_iopmv_regs {
0063     __le32 reserved[0x20400 / 4];
0064     __le32 inbound_doorbell;
0065     __le32 inbound_intmask;
0066     __le32 outbound_doorbell;
0067     __le32 outbound_intmask;
0068 };
0069
0070 #pragma pack(1)
0071 struct hpt_iopmu_mvfrey {
0072     __le32 reserved0[(0x4000 - 0) / 4];
0073     __le32 inbound_base;
0074     __le32 inbound_base_high;
0075     __le32 reserved1[(0x4018 - 0x4008) / 4];
0076     __le32 inbound_write_ptr;
0077     __le32 reserved2[(0x402c - 0x401c) / 4];
0078     __le32 inbound_conf_ctl;
0079     __le32 reserved3[(0x4050 - 0x4030) / 4];
0080     __le32 outbound_base;
0081     __le32 outbound_base_high;
0082     __le32 outbound_shadow_base;
0083     __le32 outbound_shadow_base_high;
0084     __le32 reserved4[(0x4088 - 0x4060) / 4];
0085     __le32 isr_cause;
0086     __le32 isr_enable;
0087     __le32 reserved5[(0x1020c - 0x4090) / 4];
0088     __le32 pcie_f0_int_enable;
0089     __le32 reserved6[(0x10400 - 0x10210) / 4];
0090     __le32 f0_to_cpu_msg_a;
0091     __le32 reserved7[(0x10420 - 0x10404) / 4];
0092     __le32 cpu_to_f0_msg_a;
0093     __le32 reserved8[(0x10480 - 0x10424) / 4];
0094     __le32 f0_doorbell;
0095     __le32 f0_doorbell_enable;
0096 };
0097
0098 struct mvfrey_inlist_entry {
0099     dma_addr_t addr;
0100     __le32 intrfc_len;
0101     __le32 reserved;
0102 };
0103
0104 struct mvfrey_outlist_entry {
0105     __le32 val;
0106 };
0107 #pragma pack()
0108
0109 #define MVIOP_MU_QUEUE_ADDR_HOST_MASK   (~(0x1full))
0110 #define MVIOP_MU_QUEUE_ADDR_HOST_BIT    4
0111
0112 #define MVIOP_MU_QUEUE_ADDR_IOP_HIGH32  0xffffffff
0113 #define MVIOP_MU_QUEUE_REQUEST_RESULT_BIT   1
0114 #define MVIOP_MU_QUEUE_REQUEST_RETURN_CONTEXT 2
0115
0116 #define MVIOP_MU_INBOUND_INT_MSG        1
0117 #define MVIOP_MU_INBOUND_INT_POSTQUEUE  2
0118 #define MVIOP_MU_OUTBOUND_INT_MSG       1
0119 #define MVIOP_MU_OUTBOUND_INT_POSTQUEUE 2
0120
0121 #define CL_POINTER_TOGGLE        0x00004000
0122 #define CPU_TO_F0_DRBL_MSG_BIT   0x02000000
0123
0124 enum hpt_iopmu_message {
0125     /* host-to-iop messages */
0126     IOPMU_INBOUND_MSG0_NOP = 0,
0127     IOPMU_INBOUND_MSG0_RESET,
0128     IOPMU_INBOUND_MSG0_FLUSH,
0129     IOPMU_INBOUND_MSG0_SHUTDOWN,
0130     IOPMU_INBOUND_MSG0_STOP_BACKGROUND_TASK,
0131     IOPMU_INBOUND_MSG0_START_BACKGROUND_TASK,
0132     IOPMU_INBOUND_MSG0_RESET_COMM,
0133     IOPMU_INBOUND_MSG0_MAX = 0xff,
0134     /* iop-to-host messages */
0135     IOPMU_OUTBOUND_MSG0_REGISTER_DEVICE_0 = 0x100,
0136     IOPMU_OUTBOUND_MSG0_REGISTER_DEVICE_MAX = 0x1ff,
0137     IOPMU_OUTBOUND_MSG0_UNREGISTER_DEVICE_0 = 0x200,
0138     IOPMU_OUTBOUND_MSG0_UNREGISTER_DEVICE_MAX = 0x2ff,
0139     IOPMU_OUTBOUND_MSG0_REVALIDATE_DEVICE_0 = 0x300,
0140     IOPMU_OUTBOUND_MSG0_REVALIDATE_DEVICE_MAX = 0x3ff,
0141 };
0142
0143 struct hpt_iop_request_header {
0144     __le32 size;
0145     __le32 type;
0146     __le32 flags;
0147     __le32 result;
0148     __le32 context; /* host context */
0149     __le32 context_hi32;
0150 };
0151
0152 #define IOP_REQUEST_FLAG_SYNC_REQUEST 1
0153 #define IOP_REQUEST_FLAG_BIST_REQUEST 2
0154 #define IOP_REQUEST_FLAG_REMAPPED     4
0155 #define IOP_REQUEST_FLAG_OUTPUT_CONTEXT 8
0156 #define IOP_REQUEST_FLAG_ADDR_BITS 0x40 /* flags[31:16] is phy_addr[47:32] */
0157
0158 enum hpt_iop_request_type {
0159     IOP_REQUEST_TYPE_GET_CONFIG = 0,
0160     IOP_REQUEST_TYPE_SET_CONFIG,
0161     IOP_REQUEST_TYPE_BLOCK_COMMAND,
0162     IOP_REQUEST_TYPE_SCSI_COMMAND,
0163     IOP_REQUEST_TYPE_IOCTL_COMMAND,
0164     IOP_REQUEST_TYPE_MAX
0165 };
0166
0167 enum hpt_iop_result_type {
0168     IOP_RESULT_PENDING = 0,
0169     IOP_RESULT_SUCCESS,
0170     IOP_RESULT_FAIL,
0171     IOP_RESULT_BUSY,
0172     IOP_RESULT_RESET,
0173     IOP_RESULT_INVALID_REQUEST,
0174     IOP_RESULT_BAD_TARGET,
0175     IOP_RESULT_CHECK_CONDITION,
0176 };
0177
0178 struct hpt_iop_request_get_config {
0179     struct hpt_iop_request_header header;
0180     __le32 interface_version;
0181     __le32 firmware_version;
0182     __le32 max_requests;
0183     __le32 request_size;
0184     __le32 max_sg_count;
0185     __le32 data_transfer_length;
0186     __le32 alignment_mask;
0187     __le32 max_devices;
0188     __le32 sdram_size;
0189 };
0190
0191 struct hpt_iop_request_set_config {
0192     struct hpt_iop_request_header header;
0193     __le32 iop_id;
0194     __le16 vbus_id;
0195     __le16 max_host_request_size;
0196     __le32 reserve[6];
0197 };
0198
0199 struct hpt_iopsg {
0200     __le32 size;
0201     __le32 eot; /* non-zero: end of table */
0202     __le64 pci_address;
0203 };
0204
0205 struct hpt_iop_request_block_command {
0206     struct hpt_iop_request_header header;
0207     u8     channel;
0208     u8     target;
0209     u8     lun;
0210     u8     pad1;
0211     __le16 command; /* IOP_BLOCK_COMMAND_{READ,WRITE} */
0212     __le16 sectors;
0213     __le64 lba;
0214     struct hpt_iopsg sg_list[1];
0215 };
0216
0217 #define IOP_BLOCK_COMMAND_READ     1
0218 #define IOP_BLOCK_COMMAND_WRITE    2
0219 #define IOP_BLOCK_COMMAND_VERIFY   3
0220 #define IOP_BLOCK_COMMAND_FLUSH    4
0221 #define IOP_BLOCK_COMMAND_SHUTDOWN 5
0222
0223 struct hpt_iop_request_scsi_command {
0224     struct hpt_iop_request_header header;
0225     u8     channel;
0226     u8     target;
0227     u8     lun;
0228     u8     pad1;
0229     u8     cdb[16];
0230     __le32 dataxfer_length;
0231     struct hpt_iopsg sg_list[1];
0232 };
0233
0234 struct hpt_iop_request_ioctl_command {
0235     struct hpt_iop_request_header header;
0236     __le32 ioctl_code;
0237     __le32 inbuf_size;
0238     __le32 outbuf_size;
0239     __le32 bytes_returned;
0240     u8     buf[1];
0241     /* out data should be put at buf[(inbuf_size+3)&~3] */
0242 };
0243
0244 #define HPTIOP_MAX_REQUESTS  256u
0245
0246 struct hptiop_request {
0247     struct hptiop_request *next;
0248     void                  *req_virt;
0249     u32                   req_shifted_phy;
0250     struct scsi_cmnd      *scp;
0251     int                   index;
0252 };
0253
0254 struct hpt_cmd_priv {
0255     int mapped;
0256     int sgcnt;
0257     dma_addr_t dma_handle;
0258 };
0259
0260 #define HPT_SCP(scp) ((struct hpt_cmd_priv *)scsi_cmd_priv(scp))
0261
0262 enum hptiop_family {
0263     UNKNOWN_BASED_IOP,
0264     INTEL_BASED_IOP,
0265     MV_BASED_IOP,
0266     MVFREY_BASED_IOP
0267 } ;
0268
0269 struct hptiop_hba {
0270     struct hptiop_adapter_ops *ops;
0271     union {
0272         struct {
0273             struct hpt_iopmu_itl __iomem *iop;
0274             void __iomem *plx;
0275         } itl;
0276         struct {
0277             struct hpt_iopmv_regs *regs;
0278             struct hpt_iopmu_mv __iomem *mu;
0279             void *internal_req;
0280             dma_addr_t internal_req_phy;
0281         } mv;
0282         struct {
0283             struct hpt_iop_request_get_config __iomem *config;
0284             struct hpt_iopmu_mvfrey __iomem *mu;
0285
0286             int internal_mem_size;
0287             struct hptiop_request internal_req;
0288             int list_count;
0289             struct mvfrey_inlist_entry *inlist;
0290             dma_addr_t inlist_phy;
0291             __le32 inlist_wptr;
0292             struct mvfrey_outlist_entry *outlist;
0293             dma_addr_t outlist_phy;
0294             __le32 *outlist_cptr; /* copy pointer shadow */
0295             dma_addr_t outlist_cptr_phy;
0296             __le32 outlist_rptr;
0297         } mvfrey;
0298     } u;
0299
0300     struct Scsi_Host *host;
0301     struct pci_dev *pcidev;
0302
0303     /* IOP config info */
0304     u32     interface_version;
0305     u32     firmware_version;
0306     u32     sdram_size;
0307     u32     max_devices;
0308     u32     max_requests;
0309     u32     max_request_size;
0310     u32     max_sg_descriptors;
0311
0312     u32     req_size; /* host-allocated request buffer size */
0313
0314     u32     iopintf_v2: 1;
0315     u32     initialized: 1;
0316     u32     msg_done: 1;
0317
0318     struct hptiop_request * req_list;
0319     struct hptiop_request reqs[HPTIOP_MAX_REQUESTS];
0320
0321     /* used to free allocated dma area */
0322     void        *dma_coherent[HPTIOP_MAX_REQUESTS];
0323     dma_addr_t  dma_coherent_handle[HPTIOP_MAX_REQUESTS];
0324
0325     atomic_t    reset_count;
0326     atomic_t    resetting;
0327
0328     wait_queue_head_t reset_wq;
0329     wait_queue_head_t ioctl_wq;
0330 };
0331
0332 struct hpt_ioctl_k {
0333     struct hptiop_hba * hba;
0334     u32    ioctl_code;
0335     u32    inbuf_size;
0336     u32    outbuf_size;
0337     void   *inbuf;
0338     void   *outbuf;
0339     u32    *bytes_returned;
0340     void (*done)(struct hpt_ioctl_k *);
0341     int    result; /* HPT_IOCTL_RESULT_ */
0342 };
0343
0344 struct hptiop_adapter_ops {
0345     enum hptiop_family family;
0346     int  (*iop_wait_ready)(struct hptiop_hba *hba, u32 millisec);
0347     int  (*internal_memalloc)(struct hptiop_hba *hba);
0348     int  (*internal_memfree)(struct hptiop_hba *hba);
0349     int  (*map_pci_bar)(struct hptiop_hba *hba);
0350     void (*unmap_pci_bar)(struct hptiop_hba *hba);
0351     void (*enable_intr)(struct hptiop_hba *hba);
0352     void (*disable_intr)(struct hptiop_hba *hba);
0353     int  (*get_config)(struct hptiop_hba *hba,
0354                 struct hpt_iop_request_get_config *config);
0355     int  (*set_config)(struct hptiop_hba *hba,
0356                 struct hpt_iop_request_set_config *config);
0357     int  (*iop_intr)(struct hptiop_hba *hba);
0358     void (*post_msg)(struct hptiop_hba *hba, u32 msg);
0359     void (*post_req)(struct hptiop_hba *hba, struct hptiop_request *_req);
0360     int  hw_dma_bit_mask;
0361     int  (*reset_comm)(struct hptiop_hba *hba);
0362     __le64  host_phy_flag;
0363 };
0364
0365 #define HPT_IOCTL_RESULT_OK         0
0366 #define HPT_IOCTL_RESULT_FAILED     (-1)
0367
0368 #if 0
0369 #define dprintk(fmt, args...) do { printk(fmt, ##args); } while(0)
0370 #else
0371 #define dprintk(fmt, args...)
0372 #endif
0373
0374 #endif