drivers/scsi/hpsa_cmd.h

0001 /*
0002  *    Disk Array driver for HP Smart Array SAS controllers
0003  *    Copyright (c) 2019-2020 Microchip Technology Inc. and its subsidiaries
0004  *    Copyright 2016 Microsemi Corporation
0005  *    Copyright 2014-2015 PMC-Sierra, Inc.
0006  *    Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
0007  *
0008  *    This program is free software; you can redistribute it and/or modify
0009  *    it under the terms of the GNU General Public License as published by
0010  *    the Free Software Foundation; version 2 of the License.
0011  *
0012  *    This program is distributed in the hope that it will be useful,
0013  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
0014  *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
0015  *    NON INFRINGEMENT.  See the GNU General Public License for more details.
0016  *
0017  *    Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
0018  *
0019  */
0020 #ifndef HPSA_CMD_H
0021 #define HPSA_CMD_H
0022
0023 #include <linux/compiler.h>
0024
0025 #include <linux/build_bug.h> /* static_assert */
0026 #include <linux/stddef.h> /* offsetof */
0027
0028 /* general boundary defintions */
0029 #define SENSEINFOBYTES          32 /* may vary between hbas */
0030 #define SG_ENTRIES_IN_CMD   32 /* Max SG entries excluding chain blocks */
0031 #define HPSA_SG_CHAIN       0x80000000
0032 #define HPSA_SG_LAST        0x40000000
0033 #define MAXREPLYQS              256
0034
0035 /* Command Status value */
0036 #define CMD_SUCCESS             0x0000
0037 #define CMD_TARGET_STATUS       0x0001
0038 #define CMD_DATA_UNDERRUN       0x0002
0039 #define CMD_DATA_OVERRUN        0x0003
0040 #define CMD_INVALID             0x0004
0041 #define CMD_PROTOCOL_ERR        0x0005
0042 #define CMD_HARDWARE_ERR        0x0006
0043 #define CMD_CONNECTION_LOST     0x0007
0044 #define CMD_ABORTED             0x0008
0045 #define CMD_ABORT_FAILED        0x0009
0046 #define CMD_UNSOLICITED_ABORT   0x000A
0047 #define CMD_TIMEOUT             0x000B
0048 #define CMD_UNABORTABLE     0x000C
0049 #define CMD_TMF_STATUS      0x000D
0050 #define CMD_IOACCEL_DISABLED    0x000E
0051 #define CMD_CTLR_LOCKUP     0xffff
0052 /* Note: CMD_CTLR_LOCKUP is not a value defined by the CISS spec
0053  * it is a value defined by the driver that commands can be marked
0054  * with when a controller lockup has been detected by the driver
0055  */
0056
0057 /* TMF function status values */
0058 #define CISS_TMF_COMPLETE   0x00
0059 #define CISS_TMF_INVALID_FRAME  0x02
0060 #define CISS_TMF_NOT_SUPPORTED  0x04
0061 #define CISS_TMF_FAILED     0x05
0062 #define CISS_TMF_SUCCESS    0x08
0063 #define CISS_TMF_WRONG_LUN  0x09
0064 #define CISS_TMF_OVERLAPPED_TAG 0x0a
0065
0066 /* Unit Attentions ASC's as defined for the MSA2012sa */
0067 #define POWER_OR_RESET          0x29
0068 #define STATE_CHANGED           0x2a
0069 #define UNIT_ATTENTION_CLEARED      0x2f
0070 #define LUN_FAILED          0x3e
0071 #define REPORT_LUNS_CHANGED     0x3f
0072
0073 /* Unit Attentions ASCQ's as defined for the MSA2012sa */
0074
0075     /* These ASCQ's defined for ASC = POWER_OR_RESET */
0076 #define POWER_ON_RESET          0x00
0077 #define POWER_ON_REBOOT         0x01
0078 #define SCSI_BUS_RESET          0x02
0079 #define MSA_TARGET_RESET        0x03
0080 #define CONTROLLER_FAILOVER     0x04
0081 #define TRANSCEIVER_SE          0x05
0082 #define TRANSCEIVER_LVD         0x06
0083
0084     /* These ASCQ's defined for ASC = STATE_CHANGED */
0085 #define RESERVATION_PREEMPTED       0x03
0086 #define ASYM_ACCESS_CHANGED     0x06
0087 #define LUN_CAPACITY_CHANGED        0x09
0088
0089 /* transfer direction */
0090 #define XFER_NONE               0x00
0091 #define XFER_WRITE              0x01
0092 #define XFER_READ               0x02
0093 #define XFER_RSVD               0x03
0094
0095 /* task attribute */
0096 #define ATTR_UNTAGGED           0x00
0097 #define ATTR_SIMPLE             0x04
0098 #define ATTR_HEADOFQUEUE        0x05
0099 #define ATTR_ORDERED            0x06
0100 #define ATTR_ACA                0x07
0101
0102 /* cdb type */
0103 #define TYPE_CMD        0x00
0104 #define TYPE_MSG        0x01
0105 #define TYPE_IOACCEL2_CMD   0x81 /* 0x81 is not used by hardware */
0106
0107 /* Message Types  */
0108 #define HPSA_TASK_MANAGEMENT    0x00
0109 #define HPSA_RESET              0x01
0110 #define HPSA_SCAN               0x02
0111 #define HPSA_NOOP               0x03
0112
0113 #define HPSA_CTLR_RESET_TYPE    0x00
0114 #define HPSA_BUS_RESET_TYPE     0x01
0115 #define HPSA_TARGET_RESET_TYPE  0x03
0116 #define HPSA_LUN_RESET_TYPE     0x04
0117 #define HPSA_NEXUS_RESET_TYPE   0x05
0118
0119 /* Task Management Functions */
0120 #define HPSA_TMF_ABORT_TASK     0x00
0121 #define HPSA_TMF_ABORT_TASK_SET 0x01
0122 #define HPSA_TMF_CLEAR_ACA      0x02
0123 #define HPSA_TMF_CLEAR_TASK_SET 0x03
0124 #define HPSA_TMF_QUERY_TASK     0x04
0125 #define HPSA_TMF_QUERY_TASK_SET 0x05
0126 #define HPSA_TMF_QUERY_ASYNCEVENT 0x06
0127
0128
0129
0130 /* config space register offsets */
0131 #define CFG_VENDORID            0x00
0132 #define CFG_DEVICEID            0x02
0133 #define CFG_I2OBAR              0x10
0134 #define CFG_MEM1BAR             0x14
0135
0136 /* i2o space register offsets */
0137 #define I2O_IBDB_SET            0x20
0138 #define I2O_IBDB_CLEAR          0x70
0139 #define I2O_INT_STATUS          0x30
0140 #define I2O_INT_MASK            0x34
0141 #define I2O_IBPOST_Q            0x40
0142 #define I2O_OBPOST_Q            0x44
0143 #define I2O_DMA1_CFG        0x214
0144
0145 /* Configuration Table */
0146 #define CFGTBL_ChangeReq        0x00000001l
0147 #define CFGTBL_AccCmds          0x00000001l
0148 #define DOORBELL_CTLR_RESET 0x00000004l
0149 #define DOORBELL_CTLR_RESET2    0x00000020l
0150 #define DOORBELL_CLEAR_EVENTS   0x00000040l
0151 #define DOORBELL_GENERATE_CHKPT 0x00000080l
0152
0153 #define CFGTBL_Trans_Simple     0x00000002l
0154 #define CFGTBL_Trans_Performant 0x00000004l
0155 #define CFGTBL_Trans_io_accel1  0x00000080l
0156 #define CFGTBL_Trans_io_accel2  0x00000100l
0157 #define CFGTBL_Trans_use_short_tags 0x20000000l
0158 #define CFGTBL_Trans_enable_directed_msix (1 << 30)
0159
0160 #define CFGTBL_BusType_Ultra2   0x00000001l
0161 #define CFGTBL_BusType_Ultra3   0x00000002l
0162 #define CFGTBL_BusType_Fibre1G  0x00000100l
0163 #define CFGTBL_BusType_Fibre2G  0x00000200l
0164
0165 /* VPD Inquiry types */
0166 #define HPSA_INQUIRY_FAILED     0x02
0167 #define HPSA_VPD_SUPPORTED_PAGES        0x00
0168 #define HPSA_VPD_LV_DEVICE_ID           0x83
0169 #define HPSA_VPD_LV_DEVICE_GEOMETRY     0xC1
0170 #define HPSA_VPD_LV_IOACCEL_STATUS      0xC2
0171 #define HPSA_VPD_LV_STATUS      0xC3
0172 #define HPSA_VPD_HEADER_SZ              4
0173
0174 /* Logical volume states */
0175 #define HPSA_VPD_LV_STATUS_UNSUPPORTED          0xff
0176 #define HPSA_LV_OK                                      0x0
0177 #define HPSA_LV_FAILED                  0x01
0178 #define HPSA_LV_NOT_AVAILABLE               0x0b
0179 #define HPSA_LV_UNDERGOING_ERASE            0x0F
0180 #define HPSA_LV_UNDERGOING_RPI              0x12
0181 #define HPSA_LV_PENDING_RPI             0x13
0182 #define HPSA_LV_ENCRYPTED_NO_KEY            0x14
0183 #define HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER    0x15
0184 #define HPSA_LV_UNDERGOING_ENCRYPTION           0x16
0185 #define HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING      0x17
0186 #define HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER   0x18
0187 #define HPSA_LV_PENDING_ENCRYPTION          0x19
0188 #define HPSA_LV_PENDING_ENCRYPTION_REKEYING     0x1A
0189
0190 struct vals32 {
0191     u32   lower;
0192     u32   upper;
0193 };
0194
0195 union u64bit {
0196     struct vals32 val32;
0197     u64 val;
0198 };
0199
0200 /* FIXME this is a per controller value (barf!) */
0201 #define HPSA_MAX_LUN 1024
0202 #define HPSA_MAX_PHYS_LUN 1024
0203 #define MAX_EXT_TARGETS 32
0204 #define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \
0205     MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */
0206
0207 /* SCSI-3 Commands */
0208 #define HPSA_INQUIRY 0x12
0209 struct InquiryData {
0210     u8 data_byte[36];
0211 } __packed;
0212
0213 #define HPSA_REPORT_LOG 0xc2    /* Report Logical LUNs */
0214 #define HPSA_REPORT_PHYS 0xc3   /* Report Physical LUNs */
0215 #define HPSA_REPORT_PHYS_EXTENDED 0x02
0216 #define HPSA_CISS_READ  0xc0    /* CISS Read */
0217 #define HPSA_GET_RAID_MAP 0xc8  /* CISS Get RAID Layout Map */
0218
0219 #define RAID_MAP_MAX_ENTRIES   256
0220
0221 struct raid_map_disk_data {
0222     u32   ioaccel_handle;         /**< Handle to access this disk via the
0223                     *  I/O accelerator */
0224     u8    xor_mult[2];            /**< XOR multipliers for this position,
0225                     *  valid for data disks only */
0226     u8    reserved[2];
0227 } __packed;
0228
0229 struct raid_map_data {
0230     __le32   structure_size;    /* Size of entire structure in bytes */
0231     __le32   volume_blk_size;   /* bytes / block in the volume */
0232     __le64   volume_blk_cnt;    /* logical blocks on the volume */
0233     u8    phys_blk_shift;       /* Shift factor to convert between
0234                      * units of logical blocks and physical
0235                      * disk blocks */
0236     u8    parity_rotation_shift;    /* Shift factor to convert between units
0237                      * of logical stripes and physical
0238                      * stripes */
0239     __le16   strip_size;        /* blocks used on each disk / stripe */
0240     __le64   disk_starting_blk; /* First disk block used in volume */
0241     __le64   disk_blk_cnt;      /* disk blocks used by volume / disk */
0242     __le16   data_disks_per_row;    /* data disk entries / row in the map */
0243     __le16   metadata_disks_per_row;/* mirror/parity disk entries / row
0244                      * in the map */
0245     __le16   row_cnt;       /* rows in each layout map */
0246     __le16   layout_map_count;  /* layout maps (1 map per mirror/parity
0247                      * group) */
0248     __le16   flags;         /* Bit 0 set if encryption enabled */
0249 #define RAID_MAP_FLAG_ENCRYPT_ON  0x01
0250     __le16   dekindex;      /* Data encryption key index. */
0251     u8    reserved[16];
0252     struct raid_map_disk_data data[RAID_MAP_MAX_ENTRIES];
0253 } __packed;
0254
0255 struct ReportLUNdata {
0256     u8 LUNListLength[4];
0257     u8 extended_response_flag;
0258     u8 reserved[3];
0259     u8 LUN[HPSA_MAX_LUN][8];
0260 } __packed;
0261
0262 struct ext_report_lun_entry {
0263     u8 lunid[8];
0264 #define MASKED_DEVICE(x) ((x)[3] & 0xC0)
0265 #define GET_BMIC_BUS(lunid) ((lunid)[7] & 0x3F)
0266 #define GET_BMIC_LEVEL_TWO_TARGET(lunid) ((lunid)[6])
0267 #define GET_BMIC_DRIVE_NUMBER(lunid) (((GET_BMIC_BUS((lunid)) - 1) << 8) + \
0268             GET_BMIC_LEVEL_TWO_TARGET((lunid)))
0269     u8 wwid[8];
0270     u8 device_type;
0271     u8 device_flags;
0272     u8 lun_count; /* multi-lun device, how many luns */
0273     u8 redundant_paths;
0274     u32 ioaccel_handle; /* ioaccel1 only uses lower 16 bits */
0275 } __packed;
0276
0277 struct ReportExtendedLUNdata {
0278     u8 LUNListLength[4];
0279     u8 extended_response_flag;
0280     u8 reserved[3];
0281     struct ext_report_lun_entry LUN[HPSA_MAX_PHYS_LUN];
0282 } __packed;
0283
0284 struct SenseSubsystem_info {
0285     u8 reserved[36];
0286     u8 portname[8];
0287     u8 reserved1[1108];
0288 } __packed;
0289
0290 /* BMIC commands */
0291 #define BMIC_READ 0x26
0292 #define BMIC_WRITE 0x27
0293 #define BMIC_CACHE_FLUSH 0xc2
0294 #define HPSA_CACHE_FLUSH 0x01   /* C2 was already being used by HPSA */
0295 #define BMIC_FLASH_FIRMWARE 0xF7
0296 #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64
0297 #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15
0298 #define BMIC_IDENTIFY_CONTROLLER 0x11
0299 #define BMIC_SET_DIAG_OPTIONS 0xF4
0300 #define BMIC_SENSE_DIAG_OPTIONS 0xF5
0301 #define HPSA_DIAG_OPTS_DISABLE_RLD_CACHING 0x80000000
0302 #define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66
0303 #define BMIC_SENSE_STORAGE_BOX_PARAMS 0x65
0304
0305 /* Command List Structure */
0306 union SCSI3Addr {
0307     struct {
0308         u8 Dev;
0309         u8 Bus:6;
0310         u8 Mode:2;        /* b00 */
0311     } PeripDev;
0312     struct {
0313         u8 DevLSB;
0314         u8 DevMSB:6;
0315         u8 Mode:2;        /* b01 */
0316     } LogDev;
0317     struct {
0318         u8 Dev:5;
0319         u8 Bus:3;
0320         u8 Targ:6;
0321         u8 Mode:2;        /* b10 */
0322     } LogUnit;
0323 } __packed;
0324
0325 struct PhysDevAddr {
0326     u32             TargetId:24;
0327     u32             Bus:6;
0328     u32             Mode:2;
0329     /* 2 level target device addr */
0330     union SCSI3Addr  Target[2];
0331 } __packed;
0332
0333 struct LogDevAddr {
0334     u32            VolId:30;
0335     u32            Mode:2;
0336     u8             reserved[4];
0337 } __packed;
0338
0339 union LUNAddr {
0340     u8               LunAddrBytes[8];
0341     union SCSI3Addr    SCSI3Lun[4];
0342     struct PhysDevAddr PhysDev;
0343     struct LogDevAddr  LogDev;
0344 } __packed;
0345
0346 struct CommandListHeader {
0347     u8              ReplyQueue;
0348     u8              SGList;
0349     __le16          SGTotal;
0350     __le64      tag;
0351     union LUNAddr     LUN;
0352 } __packed;
0353
0354 struct RequestBlock {
0355     u8   CDBLen;
0356     /*
0357      * type_attr_dir:
0358      * type: low 3 bits
0359      * attr: middle 3 bits
0360      * dir: high 2 bits
0361      */
0362     u8  type_attr_dir;
0363 #define TYPE_ATTR_DIR(t, a, d) ((((d) & 0x03) << 6) |\
0364                 (((a) & 0x07) << 3) |\
0365                 ((t) & 0x07))
0366 #define GET_TYPE(tad) ((tad) & 0x07)
0367 #define GET_ATTR(tad) (((tad) >> 3) & 0x07)
0368 #define GET_DIR(tad) (((tad) >> 6) & 0x03)
0369     u16  Timeout;
0370     u8   CDB[16];
0371 } __packed;
0372
0373 struct ErrDescriptor {
0374     __le64 Addr;
0375     __le32 Len;
0376 } __packed;
0377
0378 struct SGDescriptor {
0379     __le64 Addr;
0380     __le32 Len;
0381     __le32 Ext;
0382 } __packed;
0383
0384 union MoreErrInfo {
0385     struct {
0386         u8  Reserved[3];
0387         u8  Type;
0388         u32 ErrorInfo;
0389     } Common_Info;
0390     struct {
0391         u8  Reserved[2];
0392         u8  offense_size; /* size of offending entry */
0393         u8  offense_num;  /* byte # of offense 0-base */
0394         u32 offense_value;
0395     } Invalid_Cmd;
0396 } __packed;
0397
0398 struct ErrorInfo {
0399     u8               ScsiStatus;
0400     u8               SenseLen;
0401     u16              CommandStatus;
0402     u32              ResidualCnt;
0403     union MoreErrInfo  MoreErrInfo;
0404     u8               SenseInfo[SENSEINFOBYTES];
0405 } __packed;
0406 /* Command types */
0407 #define CMD_IOCTL_PEND  0x01
0408 #define CMD_SCSI    0x03
0409 #define CMD_IOACCEL1    0x04
0410 #define CMD_IOACCEL2    0x05
0411 #define IOACCEL2_TMF    0x06
0412
0413 #define DIRECT_LOOKUP_SHIFT 4
0414 #define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1))
0415
0416 #define HPSA_ERROR_BIT          0x02
0417 struct ctlr_info; /* defined in hpsa.h */
0418 /* The size of this structure needs to be divisible by 128
0419  * on all architectures.  The low 4 bits of the addresses
0420  * are used as follows:
0421  *
0422  * bit 0: to device, used to indicate "performant mode" command
0423  *        from device, indidcates error status.
0424  * bit 1-3: to device, indicates block fetch table entry for
0425  *          reducing DMA in fetching commands from host memory.
0426  */
0427
0428 #define COMMANDLIST_ALIGNMENT 128
0429 struct CommandList {
0430     struct CommandListHeader Header;
0431     struct RequestBlock      Request;
0432     struct ErrDescriptor     ErrDesc;
0433     struct SGDescriptor      SG[SG_ENTRIES_IN_CMD];
0434     /* information associated with the command */
0435     u32            busaddr; /* physical addr of this record */
0436     struct ErrorInfo *err_info; /* pointer to the allocated mem */
0437     struct ctlr_info       *h;
0438     int            cmd_type;
0439     long               cmdindex;
0440     struct completion *waiting;
0441     struct scsi_cmnd *scsi_cmd;
0442     struct work_struct work;
0443
0444     /*
0445      * For commands using either of the two "ioaccel" paths to
0446      * bypass the RAID stack and go directly to the physical disk
0447      * phys_disk is a pointer to the hpsa_scsi_dev_t to which the
0448      * i/o is destined.  We need to store that here because the command
0449      * may potentially encounter TASK SET FULL and need to be resubmitted
0450      * For "normal" i/o's not using the "ioaccel" paths, phys_disk is
0451      * not used.
0452      */
0453     struct hpsa_scsi_dev_t *phys_disk;
0454
0455     bool retry_pending;
0456     struct hpsa_scsi_dev_t *device;
0457     atomic_t refcount; /* Must be last to avoid memset in hpsa_cmd_init() */
0458 } __aligned(COMMANDLIST_ALIGNMENT);
0459
0460 /*
0461  * Make sure our embedded atomic variable is aligned. Otherwise we break atomic
0462  * operations on architectures that don't support unaligned atomics like IA64.
0463  *
0464  * The assert guards against reintroductin against unwanted __packed to
0465  * the struct CommandList.
0466  */
0467 static_assert(offsetof(struct CommandList, refcount) % __alignof__(atomic_t) == 0);
0468
0469 /* Max S/G elements in I/O accelerator command */
0470 #define IOACCEL1_MAXSGENTRIES           24
0471 #define IOACCEL2_MAXSGENTRIES       28
0472
0473 /*
0474  * Structure for I/O accelerator (mode 1) commands.
0475  * Note that this structure must be 128-byte aligned in size.
0476  */
0477 #define IOACCEL1_COMMANDLIST_ALIGNMENT 128
0478 struct io_accel1_cmd {
0479     __le16 dev_handle;      /* 0x00 - 0x01 */
0480     u8  reserved1;          /* 0x02 */
0481     u8  function;           /* 0x03 */
0482     u8  reserved2[8];       /* 0x04 - 0x0B */
0483     u32 err_info;           /* 0x0C - 0x0F */
0484     u8  reserved3[2];       /* 0x10 - 0x11 */
0485     u8  err_info_len;       /* 0x12 */
0486     u8  reserved4;          /* 0x13 */
0487     u8  sgl_offset;         /* 0x14 */
0488     u8  reserved5[7];       /* 0x15 - 0x1B */
0489     __le32 transfer_len;        /* 0x1C - 0x1F */
0490     u8  reserved6[4];       /* 0x20 - 0x23 */
0491     __le16 io_flags;        /* 0x24 - 0x25 */
0492     u8  reserved7[14];      /* 0x26 - 0x33 */
0493     u8  LUN[8];         /* 0x34 - 0x3B */
0494     __le32 control;         /* 0x3C - 0x3F */
0495     u8  CDB[16];            /* 0x40 - 0x4F */
0496     u8  reserved8[16];      /* 0x50 - 0x5F */
0497     __le16 host_context_flags;  /* 0x60 - 0x61 */
0498     __le16 timeout_sec;     /* 0x62 - 0x63 */
0499     u8  ReplyQueue;         /* 0x64 */
0500     u8  reserved9[3];       /* 0x65 - 0x67 */
0501     __le64 tag;         /* 0x68 - 0x6F */
0502     __le64 host_addr;       /* 0x70 - 0x77 */
0503     u8  CISS_LUN[8];        /* 0x78 - 0x7F */
0504     struct SGDescriptor SG[IOACCEL1_MAXSGENTRIES];
0505 } __packed __aligned(IOACCEL1_COMMANDLIST_ALIGNMENT);
0506
0507 #define IOACCEL1_FUNCTION_SCSIIO        0x00
0508 #define IOACCEL1_SGLOFFSET              32
0509
0510 #define IOACCEL1_IOFLAGS_IO_REQ         0x4000
0511 #define IOACCEL1_IOFLAGS_CDBLEN_MASK    0x001F
0512 #define IOACCEL1_IOFLAGS_CDBLEN_MAX     16
0513
0514 #define IOACCEL1_CONTROL_NODATAXFER     0x00000000
0515 #define IOACCEL1_CONTROL_DATA_OUT       0x01000000
0516 #define IOACCEL1_CONTROL_DATA_IN        0x02000000
0517 #define IOACCEL1_CONTROL_TASKPRIO_MASK  0x00007800
0518 #define IOACCEL1_CONTROL_TASKPRIO_SHIFT 11
0519 #define IOACCEL1_CONTROL_SIMPLEQUEUE    0x00000000
0520 #define IOACCEL1_CONTROL_HEADOFQUEUE    0x00000100
0521 #define IOACCEL1_CONTROL_ORDEREDQUEUE   0x00000200
0522 #define IOACCEL1_CONTROL_ACA            0x00000400
0523
0524 #define IOACCEL1_HCFLAGS_CISS_FORMAT    0x0013
0525
0526 #define IOACCEL1_BUSADDR_CMDTYPE        0x00000060
0527
0528 struct ioaccel2_sg_element {
0529     __le64 address;
0530     __le32 length;
0531     u8 reserved[3];
0532     u8 chain_indicator;
0533 #define IOACCEL2_CHAIN 0x80
0534 #define IOACCEL2_LAST_SG 0x40
0535 } __packed;
0536
0537 /*
0538  * SCSI Response Format structure for IO Accelerator Mode 2
0539  */
0540 struct io_accel2_scsi_response {
0541     u8 IU_type;
0542 #define IOACCEL2_IU_TYPE_SRF            0x60
0543     u8 reserved1[3];
0544     u8 req_id[4];       /* request identifier */
0545     u8 reserved2[4];
0546     u8 serv_response;       /* service response */
0547 #define IOACCEL2_SERV_RESPONSE_COMPLETE     0x000
0548 #define IOACCEL2_SERV_RESPONSE_FAILURE      0x001
0549 #define IOACCEL2_SERV_RESPONSE_TMF_COMPLETE 0x002
0550 #define IOACCEL2_SERV_RESPONSE_TMF_SUCCESS  0x003
0551 #define IOACCEL2_SERV_RESPONSE_TMF_REJECTED 0x004
0552 #define IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN    0x005
0553     u8 status;          /* status */
0554 #define IOACCEL2_STATUS_SR_TASK_COMP_GOOD   0x00
0555 #define IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND   0x02
0556 #define IOACCEL2_STATUS_SR_TASK_COMP_BUSY   0x08
0557 #define IOACCEL2_STATUS_SR_TASK_COMP_RES_CON    0x18
0558 #define IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL   0x28
0559 #define IOACCEL2_STATUS_SR_TASK_COMP_ABORTED    0x40
0560 #define IOACCEL2_STATUS_SR_IOACCEL_DISABLED 0x0E
0561 #define IOACCEL2_STATUS_SR_IO_ERROR     0x01
0562 #define IOACCEL2_STATUS_SR_IO_ABORTED       0x02
0563 #define IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE    0x03
0564 #define IOACCEL2_STATUS_SR_INVALID_DEVICE   0x04
0565 #define IOACCEL2_STATUS_SR_UNDERRUN     0x51
0566 #define IOACCEL2_STATUS_SR_OVERRUN      0x75
0567     u8 data_present;        /* low 2 bits */
0568 #define IOACCEL2_NO_DATAPRESENT     0x000
0569 #define IOACCEL2_RESPONSE_DATAPRESENT   0x001
0570 #define IOACCEL2_SENSE_DATA_PRESENT 0x002
0571 #define IOACCEL2_RESERVED       0x003
0572     u8 sense_data_len;      /* sense/response data length */
0573     u8 resid_cnt[4];        /* residual count */
0574     u8 sense_data_buff[32];     /* sense/response data buffer */
0575 } __packed;
0576
0577 /*
0578  * Structure for I/O accelerator (mode 2 or m2) commands.
0579  * Note that this structure must be 128-byte aligned in size.
0580  */
0581 #define IOACCEL2_COMMANDLIST_ALIGNMENT 128
0582 struct io_accel2_cmd {
0583     u8  IU_type;            /* IU Type */
0584     u8  direction;          /* direction, memtype, and encryption */
0585 #define IOACCEL2_DIRECTION_MASK     0x03 /* bits 0,1: direction  */
0586 #define IOACCEL2_DIRECTION_MEMTYPE_MASK 0x04 /* bit 2: memtype source/dest */
0587                          /*     0b=PCIe, 1b=DDR */
0588 #define IOACCEL2_DIRECTION_ENCRYPT_MASK 0x08 /* bit 3: encryption flag */
0589                          /*     0=off, 1=on */
0590     u8  reply_queue;        /* Reply Queue ID */
0591     u8  reserved1;          /* Reserved */
0592     __le32 scsi_nexus;      /* Device Handle */
0593     __le32 Tag;         /* cciss tag, lower 4 bytes only */
0594     __le32 tweak_lower;     /* Encryption tweak, lower 4 bytes */
0595     u8  cdb[16];            /* SCSI Command Descriptor Block */
0596     u8  cciss_lun[8];       /* 8 byte SCSI address */
0597     __le32 data_len;        /* Total bytes to transfer */
0598     u8  cmd_priority_task_attr; /* priority and task attrs */
0599 #define IOACCEL2_PRIORITY_MASK 0x78
0600 #define IOACCEL2_ATTR_MASK 0x07
0601     u8  sg_count;           /* Number of sg elements */
0602     __le16 dekindex;        /* Data encryption key index */
0603     __le64 err_ptr;         /* Error Pointer */
0604     __le32 err_len;         /* Error Length*/
0605     __le32 tweak_upper;     /* Encryption tweak, upper 4 bytes */
0606     struct ioaccel2_sg_element sg[IOACCEL2_MAXSGENTRIES];
0607     struct io_accel2_scsi_response error_data;
0608 } __packed __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT);
0609
0610 /*
0611  * defines for Mode 2 command struct
0612  * FIXME: this can't be all I need mfm
0613  */
0614 #define IOACCEL2_IU_TYPE    0x40
0615 #define IOACCEL2_IU_TMF_TYPE    0x41
0616 #define IOACCEL2_DIR_NO_DATA    0x00
0617 #define IOACCEL2_DIR_DATA_IN    0x01
0618 #define IOACCEL2_DIR_DATA_OUT   0x02
0619 #define IOACCEL2_TMF_ABORT  0x01
0620 /*
0621  * SCSI Task Management Request format for Accelerator Mode 2
0622  */
0623 struct hpsa_tmf_struct {
0624     u8 iu_type;     /* Information Unit Type */
0625     u8 reply_queue;     /* Reply Queue ID */
0626     u8 tmf;         /* Task Management Function */
0627     u8 reserved1;       /* byte 3 Reserved */
0628     __le32 it_nexus;    /* SCSI I-T Nexus */
0629     u8 lun_id[8];       /* LUN ID for TMF request */
0630     __le64 tag;     /* cciss tag associated w/ request */
0631     __le64 abort_tag;   /* cciss tag of SCSI cmd or TMF to abort */
0632     __le64 error_ptr;       /* Error Pointer */
0633     __le32 error_len;       /* Error Length */
0634 } __packed __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT);
0635
0636 /* Configuration Table Structure */
0637 struct HostWrite {
0638     __le32      TransportRequest;
0639     __le32      command_pool_addr_hi;
0640     __le32      CoalIntDelay;
0641     __le32      CoalIntCount;
0642 } __packed;
0643
0644 #define SIMPLE_MODE     0x02
0645 #define PERFORMANT_MODE 0x04
0646 #define MEMQ_MODE       0x08
0647 #define IOACCEL_MODE_1  0x80
0648
0649 #define DRIVER_SUPPORT_UA_ENABLE        0x00000001
0650
0651 struct CfgTable {
0652     u8      Signature[4];
0653     __le32      SpecValence;
0654     __le32      TransportSupport;
0655     __le32      TransportActive;
0656     struct HostWrite HostWrite;
0657     __le32      CmdsOutMax;
0658     __le32      BusTypes;
0659     __le32      TransMethodOffset;
0660     u8      ServerName[16];
0661     __le32      HeartBeat;
0662     __le32      driver_support;
0663 #define         ENABLE_SCSI_PREFETCH        0x100
0664 #define         ENABLE_UNIT_ATTN        0x01
0665     __le32      MaxScatterGatherElements;
0666     __le32      MaxLogicalUnits;
0667     __le32      MaxPhysicalDevices;
0668     __le32      MaxPhysicalDrivesPerLogicalUnit;
0669     __le32      MaxPerformantModeCommands;
0670     __le32      MaxBlockFetch;
0671     __le32      PowerConservationSupport;
0672     __le32      PowerConservationEnable;
0673     __le32      TMFSupportFlags;
0674     u8      TMFTagMask[8];
0675     u8      reserved[0x78 - 0x70];
0676     __le32      misc_fw_support;        /* offset 0x78 */
0677 #define         MISC_FW_DOORBELL_RESET      0x02
0678 #define         MISC_FW_DOORBELL_RESET2     0x010
0679 #define         MISC_FW_RAID_OFFLOAD_BASIC  0x020
0680 #define         MISC_FW_EVENT_NOTIFY        0x080
0681     u8      driver_version[32];
0682     __le32      max_cached_write_size;
0683     u8      driver_scratchpad[16];
0684     __le32      max_error_info_length;
0685     __le32      io_accel_max_embedded_sg_count;
0686     __le32      io_accel_request_size_offset;
0687     __le32      event_notify;
0688 #define     HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE (1 << 30)
0689 #define     HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE (1 << 31)
0690     __le32      clear_event_notify;
0691 } __packed;
0692
0693 #define NUM_BLOCKFETCH_ENTRIES 8
0694 struct TransTable_struct {
0695     __le32      BlockFetch[NUM_BLOCKFETCH_ENTRIES];
0696     __le32      RepQSize;
0697     __le32      RepQCount;
0698     __le32      RepQCtrAddrLow32;
0699     __le32      RepQCtrAddrHigh32;
0700 #define MAX_REPLY_QUEUES 64
0701     struct vals32  RepQAddr[MAX_REPLY_QUEUES];
0702 } __packed;
0703
0704 struct hpsa_pci_info {
0705     unsigned char   bus;
0706     unsigned char   dev_fn;
0707     unsigned short  domain;
0708     u32     board_id;
0709 } __packed;
0710
0711 struct bmic_identify_controller {
0712     u8  configured_logical_drive_count; /* offset 0 */
0713     u8  pad1[153];
0714     __le16  extended_logical_unit_count;    /* offset 154 */
0715     u8  pad2[136];
0716     u8  controller_mode;    /* offset 292 */
0717     u8  pad3[32];
0718 } __packed;
0719
0720
0721 struct bmic_identify_physical_device {
0722     u8    scsi_bus;          /* SCSI Bus number on controller */
0723     u8    scsi_id;           /* SCSI ID on this bus */
0724     __le16 block_size;       /* sector size in bytes */
0725     __le32 total_blocks;         /* number for sectors on drive */
0726     __le32 reserved_blocks;   /* controller reserved (RIS) */
0727     u8    model[40];         /* Physical Drive Model */
0728     u8    serial_number[40]; /* Drive Serial Number */
0729     u8    firmware_revision[8]; /* drive firmware revision */
0730     u8    scsi_inquiry_bits; /* inquiry byte 7 bits */
0731     u8    compaq_drive_stamp; /* 0 means drive not stamped */
0732     u8    last_failure_reason;
0733 #define BMIC_LAST_FAILURE_TOO_SMALL_IN_LOAD_CONFIG      0x01
0734 #define BMIC_LAST_FAILURE_ERROR_ERASING_RIS         0x02
0735 #define BMIC_LAST_FAILURE_ERROR_SAVING_RIS          0x03
0736 #define BMIC_LAST_FAILURE_FAIL_DRIVE_COMMAND            0x04
0737 #define BMIC_LAST_FAILURE_MARK_BAD_FAILED           0x05
0738 #define BMIC_LAST_FAILURE_MARK_BAD_FAILED_IN_FINISH_REMAP   0x06
0739 #define BMIC_LAST_FAILURE_TIMEOUT               0x07
0740 #define BMIC_LAST_FAILURE_AUTOSENSE_FAILED          0x08
0741 #define BMIC_LAST_FAILURE_MEDIUM_ERROR_1            0x09
0742 #define BMIC_LAST_FAILURE_MEDIUM_ERROR_2            0x0a
0743 #define BMIC_LAST_FAILURE_NOT_READY_BAD_SENSE           0x0b
0744 #define BMIC_LAST_FAILURE_NOT_READY             0x0c
0745 #define BMIC_LAST_FAILURE_HARDWARE_ERROR            0x0d
0746 #define BMIC_LAST_FAILURE_ABORTED_COMMAND           0x0e
0747 #define BMIC_LAST_FAILURE_WRITE_PROTECTED           0x0f
0748 #define BMIC_LAST_FAILURE_SPIN_UP_FAILURE_IN_RECOVER        0x10
0749 #define BMIC_LAST_FAILURE_REBUILD_WRITE_ERROR           0x11
0750 #define BMIC_LAST_FAILURE_TOO_SMALL_IN_HOT_PLUG         0x12
0751 #define BMIC_LAST_FAILURE_BUS_RESET_RECOVERY_ABORTED        0x13
0752 #define BMIC_LAST_FAILURE_REMOVED_IN_HOT_PLUG           0x14
0753 #define BMIC_LAST_FAILURE_INIT_REQUEST_SENSE_FAILED     0x15
0754 #define BMIC_LAST_FAILURE_INIT_START_UNIT_FAILED        0x16
0755 #define BMIC_LAST_FAILURE_INQUIRY_FAILED            0x17
0756 #define BMIC_LAST_FAILURE_NON_DISK_DEVICE           0x18
0757 #define BMIC_LAST_FAILURE_READ_CAPACITY_FAILED          0x19
0758 #define BMIC_LAST_FAILURE_INVALID_BLOCK_SIZE            0x1a
0759 #define BMIC_LAST_FAILURE_HOT_PLUG_REQUEST_SENSE_FAILED     0x1b
0760 #define BMIC_LAST_FAILURE_HOT_PLUG_START_UNIT_FAILED        0x1c
0761 #define BMIC_LAST_FAILURE_WRITE_ERROR_AFTER_REMAP       0x1d
0762 #define BMIC_LAST_FAILURE_INIT_RESET_RECOVERY_ABORTED       0x1e
0763 #define BMIC_LAST_FAILURE_DEFERRED_WRITE_ERROR          0x1f
0764 #define BMIC_LAST_FAILURE_MISSING_IN_SAVE_RIS           0x20
0765 #define BMIC_LAST_FAILURE_WRONG_REPLACE             0x21
0766 #define BMIC_LAST_FAILURE_GDP_VPD_INQUIRY_FAILED        0x22
0767 #define BMIC_LAST_FAILURE_GDP_MODE_SENSE_FAILED         0x23
0768 #define BMIC_LAST_FAILURE_DRIVE_NOT_IN_48BIT_MODE       0x24
0769 #define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_HOT_PLUG        0x25
0770 #define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_LOAD_CFG        0x26
0771 #define BMIC_LAST_FAILURE_PROTOCOL_ADAPTER_FAILED       0x27
0772 #define BMIC_LAST_FAILURE_FAULTY_ID_BAY_EMPTY           0x28
0773 #define BMIC_LAST_FAILURE_FAULTY_ID_BAY_OCCUPIED        0x29
0774 #define BMIC_LAST_FAILURE_FAULTY_ID_INVALID_BAY         0x2a
0775 #define BMIC_LAST_FAILURE_WRITE_RETRIES_FAILED          0x2b
0776
0777 #define BMIC_LAST_FAILURE_SMART_ERROR_REPORTED          0x37
0778 #define BMIC_LAST_FAILURE_PHY_RESET_FAILED          0x38
0779 #define BMIC_LAST_FAILURE_ONLY_ONE_CTLR_CAN_SEE_DRIVE       0x40
0780 #define BMIC_LAST_FAILURE_KC_VOLUME_FAILED          0x41
0781 #define BMIC_LAST_FAILURE_UNEXPECTED_REPLACEMENT        0x42
0782 #define BMIC_LAST_FAILURE_OFFLINE_ERASE             0x80
0783 #define BMIC_LAST_FAILURE_OFFLINE_TOO_SMALL         0x81
0784 #define BMIC_LAST_FAILURE_OFFLINE_DRIVE_TYPE_MIX        0x82
0785 #define BMIC_LAST_FAILURE_OFFLINE_ERASE_COMPLETE        0x83
0786
0787     u8     flags;
0788     u8     more_flags;
0789     u8     scsi_lun;          /* SCSI LUN for phys drive */
0790     u8     yet_more_flags;
0791     u8     even_more_flags;
0792     __le32 spi_speed_rules;/* SPI Speed data:Ultra disable diagnose */
0793     u8     phys_connector[2];         /* connector number on controller */
0794     u8     phys_box_on_bus;  /* phys enclosure this drive resides */
0795     u8     phys_bay_in_box;  /* phys drv bay this drive resides */
0796     __le32 rpm;              /* Drive rotational speed in rpm */
0797     u8     device_type;       /* type of drive */
0798 #define BMIC_DEVICE_TYPE_CONTROLLER 0x07
0799
0800     u8     sata_version;     /* only valid when drive_type is SATA */
0801     __le64 big_total_block_count;
0802     __le64 ris_starting_lba;
0803     __le32 ris_size;
0804     u8     wwid[20];
0805     u8     controller_phy_map[32];
0806     __le16 phy_count;
0807     u8     phy_connected_dev_type[256];
0808     u8     phy_to_drive_bay_num[256];
0809     __le16 phy_to_attached_dev_index[256];
0810     u8     box_index;
0811     u8     reserved;
0812     __le16 extra_physical_drive_flags;
0813 #define BMIC_PHYS_DRIVE_SUPPORTS_GAS_GAUGE(idphydrv) \
0814     (idphydrv->extra_physical_drive_flags & (1 << 10))
0815     u8     negotiated_link_rate[256];
0816     u8     phy_to_phy_map[256];
0817     u8     redundant_path_present_map;
0818     u8     redundant_path_failure_map;
0819     u8     active_path_number;
0820     __le16 alternate_paths_phys_connector[8];
0821     u8     alternate_paths_phys_box_on_port[8];
0822     u8     multi_lun_device_lun_count;
0823     u8     minimum_good_fw_revision[8];
0824     u8     unique_inquiry_bytes[20];
0825     u8     current_temperature_degreesC;
0826     u8     temperature_threshold_degreesC;
0827     u8     max_temperature_degreesC;
0828     u8     logical_blocks_per_phys_block_exp; /* phyblocksize = 512*2^exp */
0829     __le16 current_queue_depth_limit;
0830     u8     reserved_switch_stuff[60];
0831     __le16 power_on_hours; /* valid only if gas gauge supported */
0832     __le16 percent_endurance_used; /* valid only if gas gauge supported. */
0833 #define BMIC_PHYS_DRIVE_SSD_WEAROUT(idphydrv) \
0834     ((idphydrv->percent_endurance_used & 0x80) || \
0835      (idphydrv->percent_endurance_used > 10000))
0836     u8     drive_authentication;
0837 #define BMIC_PHYS_DRIVE_AUTHENTICATED(idphydrv) \
0838     (idphydrv->drive_authentication == 0x80)
0839     u8     smart_carrier_authentication;
0840 #define BMIC_SMART_CARRIER_AUTHENTICATION_SUPPORTED(idphydrv) \
0841     (idphydrv->smart_carrier_authentication != 0x0)
0842 #define BMIC_SMART_CARRIER_AUTHENTICATED(idphydrv) \
0843     (idphydrv->smart_carrier_authentication == 0x01)
0844     u8     smart_carrier_app_fw_version;
0845     u8     smart_carrier_bootloader_fw_version;
0846     u8     sanitize_support_flags;
0847     u8     drive_key_flags;
0848     u8     encryption_key_name[64];
0849     __le32 misc_drive_flags;
0850     __le16 dek_index;
0851     __le16 hba_drive_encryption_flags;
0852     __le16 max_overwrite_time;
0853     __le16 max_block_erase_time;
0854     __le16 max_crypto_erase_time;
0855     u8     device_connector_info[5];
0856     u8     connector_name[8][8];
0857     u8     page_83_id[16];
0858     u8     max_link_rate[256];
0859     u8     neg_phys_link_rate[256];
0860     u8     box_conn_name[8];
0861 } __packed __attribute((aligned(512)));
0862
0863 struct bmic_sense_subsystem_info {
0864     u8  primary_slot_number;
0865     u8  reserved[3];
0866     u8  chasis_serial_number[32];
0867     u8  primary_world_wide_id[8];
0868     u8  primary_array_serial_number[32]; /* NULL terminated */
0869     u8  primary_cache_serial_number[32]; /* NULL terminated */
0870     u8  reserved_2[8];
0871     u8  secondary_array_serial_number[32];
0872     u8  secondary_cache_serial_number[32];
0873     u8  pad[332];
0874 } __packed;
0875
0876 struct bmic_sense_storage_box_params {
0877     u8  reserved[36];
0878     u8  inquiry_valid;
0879     u8  reserved_1[68];
0880     u8  phys_box_on_port;
0881     u8  reserved_2[22];
0882     u16 connection_info;
0883     u8  reserver_3[84];
0884     u8  phys_connector[2];
0885     u8  reserved_4[296];
0886 } __packed;
0887
0888 #endif /* HPSA_CMD_H */