scsi/fnic/vnic_wq.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright 2008 Cisco Systems, Inc.  All rights reserved.
0004  * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
0005  */
0006 #ifndef _VNIC_WQ_H_
0007 #define _VNIC_WQ_H_
0008
0009 #include <linux/pci.h>
0010 #include "vnic_dev.h"
0011 #include "vnic_cq.h"
0012
0013 /*
0014  * These defines avoid symbol clash between fnic and enic (Cisco 10G Eth
0015  * Driver) when both are built with CONFIG options =y
0016  */
0017 #define vnic_wq_desc_avail fnic_wq_desc_avail
0018 #define vnic_wq_desc_used fnic_wq_desc_used
0019 #define vnic_wq_next_desc fni_cwq_next_desc
0020 #define vnic_wq_post fnic_wq_post
0021 #define vnic_wq_service fnic_wq_service
0022 #define vnic_wq_free fnic_wq_free
0023 #define vnic_wq_alloc fnic_wq_alloc
0024 #define vnic_wq_devcmd2_alloc fnic_wq_devcmd2_alloc
0025 #define vnic_wq_init_start fnic_wq_init_start
0026 #define vnic_wq_init fnic_wq_init
0027 #define vnic_wq_error_status fnic_wq_error_status
0028 #define vnic_wq_enable fnic_wq_enable
0029 #define vnic_wq_disable fnic_wq_disable
0030 #define vnic_wq_clean fnic_wq_clean
0031
0032 /* Work queue control */
0033 struct vnic_wq_ctrl {
0034     u64 ring_base;          /* 0x00 */
0035     u32 ring_size;          /* 0x08 */
0036     u32 pad0;
0037     u32 posted_index;       /* 0x10 */
0038     u32 pad1;
0039     u32 cq_index;           /* 0x18 */
0040     u32 pad2;
0041     u32 enable;         /* 0x20 */
0042     u32 pad3;
0043     u32 running;            /* 0x28 */
0044     u32 pad4;
0045     u32 fetch_index;        /* 0x30 */
0046     u32 pad5;
0047     u32 dca_value;          /* 0x38 */
0048     u32 pad6;
0049     u32 error_interrupt_enable; /* 0x40 */
0050     u32 pad7;
0051     u32 error_interrupt_offset; /* 0x48 */
0052     u32 pad8;
0053     u32 error_status;       /* 0x50 */
0054     u32 pad9;
0055 };
0056
0057 struct vnic_wq_buf {
0058     struct vnic_wq_buf *next;
0059     dma_addr_t dma_addr;
0060     void *os_buf;
0061     unsigned int len;
0062     unsigned int index;
0063     int sop;
0064     void *desc;
0065 };
0066
0067 /* Break the vnic_wq_buf allocations into blocks of 64 entries */
0068 #define VNIC_WQ_BUF_BLK_ENTRIES 64
0069 #define VNIC_WQ_BUF_BLK_SZ \
0070     (VNIC_WQ_BUF_BLK_ENTRIES * sizeof(struct vnic_wq_buf))
0071 #define VNIC_WQ_BUF_BLKS_NEEDED(entries) \
0072     DIV_ROUND_UP(entries, VNIC_WQ_BUF_BLK_ENTRIES)
0073 #define VNIC_WQ_BUF_BLKS_MAX VNIC_WQ_BUF_BLKS_NEEDED(4096)
0074
0075 struct vnic_wq {
0076     unsigned int index;
0077     struct vnic_dev *vdev;
0078     struct vnic_wq_ctrl __iomem *ctrl;  /* memory-mapped */
0079     struct vnic_dev_ring ring;
0080     struct vnic_wq_buf *bufs[VNIC_WQ_BUF_BLKS_MAX];
0081     struct vnic_wq_buf *to_use;
0082     struct vnic_wq_buf *to_clean;
0083     unsigned int pkts_outstanding;
0084 };
0085
0086 static inline unsigned int vnic_wq_desc_avail(struct vnic_wq *wq)
0087 {
0088     /* how many does SW own? */
0089     return wq->ring.desc_avail;
0090 }
0091
0092 static inline unsigned int vnic_wq_desc_used(struct vnic_wq *wq)
0093 {
0094     /* how many does HW own? */
0095     return wq->ring.desc_count - wq->ring.desc_avail - 1;
0096 }
0097
0098 static inline void *vnic_wq_next_desc(struct vnic_wq *wq)
0099 {
0100     return wq->to_use->desc;
0101 }
0102
0103 static inline void vnic_wq_post(struct vnic_wq *wq,
0104     void *os_buf, dma_addr_t dma_addr,
0105     unsigned int len, int sop, int eop)
0106 {
0107     struct vnic_wq_buf *buf = wq->to_use;
0108
0109     buf->sop = sop;
0110     buf->os_buf = eop ? os_buf : NULL;
0111     buf->dma_addr = dma_addr;
0112     buf->len = len;
0113
0114     buf = buf->next;
0115     if (eop) {
0116         /* Adding write memory barrier prevents compiler and/or CPU
0117          * reordering, thus avoiding descriptor posting before
0118          * descriptor is initialized. Otherwise, hardware can read
0119          * stale descriptor fields.
0120          */
0121         wmb();
0122         iowrite32(buf->index, &wq->ctrl->posted_index);
0123     }
0124     wq->to_use = buf;
0125
0126     wq->ring.desc_avail--;
0127 }
0128
0129 static inline void vnic_wq_service(struct vnic_wq *wq,
0130     struct cq_desc *cq_desc, u16 completed_index,
0131     void (*buf_service)(struct vnic_wq *wq,
0132     struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque),
0133     void *opaque)
0134 {
0135     struct vnic_wq_buf *buf;
0136
0137     buf = wq->to_clean;
0138     while (1) {
0139
0140         (*buf_service)(wq, cq_desc, buf, opaque);
0141
0142         wq->ring.desc_avail++;
0143
0144         wq->to_clean = buf->next;
0145
0146         if (buf->index == completed_index)
0147             break;
0148
0149         buf = wq->to_clean;
0150     }
0151 }
0152
0153 void vnic_wq_free(struct vnic_wq *wq);
0154 int vnic_wq_alloc(struct vnic_dev *vdev, struct vnic_wq *wq, unsigned int index,
0155     unsigned int desc_count, unsigned int desc_size);
0156 int vnic_wq_devcmd2_alloc(struct vnic_dev *vdev, struct vnic_wq *wq,
0157         unsigned int desc_count, unsigned int desc_size);
0158 void vnic_wq_init_start(struct vnic_wq *wq, unsigned int cq_index,
0159         unsigned int fetch_index, unsigned int posted_index,
0160         unsigned int error_interrupt_enable,
0161         unsigned int error_interrupt_offset);
0162 void vnic_wq_init(struct vnic_wq *wq, unsigned int cq_index,
0163     unsigned int error_interrupt_enable,
0164     unsigned int error_interrupt_offset);
0165 unsigned int vnic_wq_error_status(struct vnic_wq *wq);
0166 void vnic_wq_enable(struct vnic_wq *wq);
0167 int vnic_wq_disable(struct vnic_wq *wq);
0168 void vnic_wq_clean(struct vnic_wq *wq,
0169     void (*buf_clean)(struct vnic_wq *wq, struct vnic_wq_buf *buf));
0170
0171 #endif /* _VNIC_WQ_H_ */