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0001 /*
0002  *  linux/drivers/scsi/esas2r/esas2r.h
0003  *      For use with ATTO ExpressSAS R6xx SAS/SATA RAID controllers
0004  *
0005  *  Copyright (c) 2001-2013 ATTO Technology, Inc.
0006  *  (mailto:linuxdrivers@attotech.com)
0007  *
0008  * This program is free software; you can redistribute it and/or
0009  * modify it under the terms of the GNU General Public License
0010  * as published by the Free Software Foundation; either version 2
0011  * of the License, or (at your option) any later version.
0012  *
0013  * This program is distributed in the hope that it will be useful,
0014  * but WITHOUT ANY WARRANTY; without even the implied warranty of
0015  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
0016  * GNU General Public License for more details.
0017  *
0018  * NO WARRANTY
0019  * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
0020  * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
0021  * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
0022  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
0023  * solely responsible for determining the appropriateness of using and
0024  * distributing the Program and assumes all risks associated with its
0025  * exercise of rights under this Agreement, including but not limited to
0026  * the risks and costs of program errors, damage to or loss of data,
0027  * programs or equipment, and unavailability or interruption of operations.
0028  *
0029  * DISCLAIMER OF LIABILITY
0030  * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
0031  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0032  * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
0033  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
0034  * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
0035  * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
0036  * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
0037  *
0038  * You should have received a copy of the GNU General Public License
0039  * along with this program; if not, write to the Free Software
0040  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301,
0041  * USA.
0042  */
0043 
0044 #include <linux/kernel.h>
0045 #include <linux/delay.h>
0046 #include <linux/pci.h>
0047 #include <linux/proc_fs.h>
0048 #include <linux/workqueue.h>
0049 #include <linux/interrupt.h>
0050 #include <linux/module.h>
0051 #include <linux/vmalloc.h>
0052 #include <scsi/scsi.h>
0053 #include <scsi/scsi_host.h>
0054 #include <scsi/scsi_cmnd.h>
0055 #include <scsi/scsi_device.h>
0056 #include <scsi/scsi_eh.h>
0057 #include <scsi/scsi_tcq.h>
0058 
0059 #include "esas2r_log.h"
0060 #include "atioctl.h"
0061 #include "atvda.h"
0062 
0063 #ifndef ESAS2R_H
0064 #define ESAS2R_H
0065 
0066 /* Global Variables */
0067 extern struct esas2r_adapter *esas2r_adapters[];
0068 extern u8 *esas2r_buffered_ioctl;
0069 extern dma_addr_t esas2r_buffered_ioctl_addr;
0070 extern u32 esas2r_buffered_ioctl_size;
0071 extern struct pci_dev *esas2r_buffered_ioctl_pcid;
0072 #define SGL_PG_SZ_MIN   64
0073 #define SGL_PG_SZ_MAX   1024
0074 extern int sgl_page_size;
0075 #define NUM_SGL_MIN     8
0076 #define NUM_SGL_MAX     2048
0077 extern int num_sg_lists;
0078 #define NUM_REQ_MIN     4
0079 #define NUM_REQ_MAX     256
0080 extern int num_requests;
0081 #define NUM_AE_MIN      2
0082 #define NUM_AE_MAX      8
0083 extern int num_ae_requests;
0084 extern int cmd_per_lun;
0085 extern int can_queue;
0086 extern int esas2r_max_sectors;
0087 extern int sg_tablesize;
0088 extern int interrupt_mode;
0089 extern int num_io_requests;
0090 
0091 /* Macro defintions */
0092 #define ESAS2R_MAX_ID        255
0093 #define MAX_ADAPTERS         32
0094 #define ESAS2R_DRVR_NAME     "esas2r"
0095 #define ESAS2R_LONGNAME      "ATTO ExpressSAS 6GB RAID Adapter"
0096 #define ESAS2R_MAX_DEVICES     32
0097 #define ATTONODE_NAME         "ATTONode"
0098 #define ESAS2R_MAJOR_REV       1
0099 #define ESAS2R_MINOR_REV       00
0100 #define ESAS2R_VERSION_STR     DEFINED_NUM_TO_STR(ESAS2R_MAJOR_REV) "." \
0101     DEFINED_NUM_TO_STR(ESAS2R_MINOR_REV)
0102 #define ESAS2R_COPYRIGHT_YEARS "2001-2013"
0103 #define ESAS2R_DEFAULT_SGL_PAGE_SIZE 384
0104 #define ESAS2R_DEFAULT_CMD_PER_LUN   64
0105 #define ESAS2R_DEFAULT_NUM_SG_LISTS 1024
0106 #define DEFINED_NUM_TO_STR(num) NUM_TO_STR(num)
0107 #define NUM_TO_STR(num) #num
0108 
0109 #define ESAS2R_SGL_ALIGN    16
0110 #define ESAS2R_LIST_ALIGN   16
0111 #define ESAS2R_LIST_EXTRA   ESAS2R_NUM_EXTRA
0112 #define ESAS2R_DATA_BUF_LEN         256
0113 #define ESAS2R_DEFAULT_TMO          5000
0114 #define ESAS2R_DISC_BUF_LEN         512
0115 #define ESAS2R_FWCOREDUMP_SZ        0x80000
0116 #define ESAS2R_NUM_PHYS             8
0117 #define ESAS2R_TARG_ID_INV          0xFFFF
0118 #define ESAS2R_INT_STS_MASK         MU_INTSTAT_MASK
0119 #define ESAS2R_INT_ENB_MASK         MU_INTSTAT_MASK
0120 #define ESAS2R_INT_DIS_MASK         0
0121 #define ESAS2R_MAX_TARGETS          256
0122 #define ESAS2R_KOBJ_NAME_LEN        20
0123 
0124 /* u16 (WORD) component macros */
0125 #define LOBYTE(w) ((u8)(u16)(w))
0126 #define HIBYTE(w) ((u8)(((u16)(w)) >> 8))
0127 #define MAKEWORD(lo, hi) ((u16)((u8)(lo) | ((u16)(u8)(hi) << 8)))
0128 
0129 /* u32 (DWORD) component macros */
0130 #define LOWORD(d) ((u16)(u32)(d))
0131 #define HIWORD(d) ((u16)(((u32)(d)) >> 16))
0132 #define MAKEDWORD(lo, hi) ((u32)((u16)(lo) | ((u32)(u16)(hi) << 16)))
0133 
0134 /* macro to get the lowest nonzero bit of a value */
0135 #define LOBIT(x) ((x) & (0 - (x)))
0136 
0137 /* These functions are provided to access the chip's control registers.
0138  * The register is specified by its byte offset from the register base
0139  * for the adapter.
0140  */
0141 #define esas2r_read_register_dword(a, reg)                             \
0142     readl((void __iomem *)a->regs + (reg) + MW_REG_OFFSET_HWREG)
0143 
0144 #define esas2r_write_register_dword(a, reg, data)                      \
0145     writel(data, (void __iomem *)(a->regs + (reg) + MW_REG_OFFSET_HWREG))
0146 
0147 #define esas2r_flush_register_dword(a, r) esas2r_read_register_dword(a, r)
0148 
0149 /* This function is provided to access the chip's data window.   The
0150  * register is specified by its byte offset from the window base
0151  * for the adapter.
0152  */
0153 #define esas2r_read_data_byte(a, reg)                                  \
0154     readb((void __iomem *)a->data_window + (reg))
0155 
0156 /* ATTO vendor and device Ids */
0157 #define ATTO_VENDOR_ID          0x117C
0158 #define ATTO_DID_INTEL_IOP348   0x002C
0159 #define ATTO_DID_MV_88RC9580    0x0049
0160 #define ATTO_DID_MV_88RC9580TS  0x0066
0161 #define ATTO_DID_MV_88RC9580TSE 0x0067
0162 #define ATTO_DID_MV_88RC9580TL  0x0068
0163 
0164 /* ATTO subsystem device Ids */
0165 #define ATTO_SSDID_TBT      0x4000
0166 #define ATTO_TSSC_3808      0x4066
0167 #define ATTO_TSSC_3808E     0x4067
0168 #define ATTO_TLSH_1068      0x4068
0169 #define ATTO_ESAS_R680      0x0049
0170 #define ATTO_ESAS_R608      0x004A
0171 #define ATTO_ESAS_R60F      0x004B
0172 #define ATTO_ESAS_R6F0      0x004C
0173 #define ATTO_ESAS_R644      0x004D
0174 #define ATTO_ESAS_R648      0x004E
0175 
0176 /*
0177  * flash definitions & structures
0178  * define the code types
0179  */
0180 #define FBT_CPYR        0xAA00
0181 #define FBT_SETUP       0xAA02
0182 #define FBT_FLASH_VER   0xAA04
0183 
0184 /* offsets to various locations in flash */
0185 #define FLS_OFFSET_BOOT (u32)(0x00700000)
0186 #define FLS_OFFSET_NVR  (u32)(0x007C0000)
0187 #define FLS_OFFSET_CPYR FLS_OFFSET_NVR
0188 #define FLS_LENGTH_BOOT (FLS_OFFSET_CPYR - FLS_OFFSET_BOOT)
0189 #define FLS_BLOCK_SIZE  (u32)(0x00020000)
0190 #define FI_NVR_2KB  0x0800
0191 #define FI_NVR_8KB  0x2000
0192 #define FM_BUF_SZ   0x800
0193 
0194 /*
0195  * marvell frey (88R9580) register definitions
0196  * chip revision identifiers
0197  */
0198 #define MVR_FREY_B2     0xB2
0199 
0200 /*
0201  * memory window definitions.  window 0 is the data window with definitions
0202  * of MW_DATA_XXX.  window 1 is the register window with definitions of
0203  * MW_REG_XXX.
0204  */
0205 #define MW_REG_WINDOW_SIZE      (u32)(0x00040000)
0206 #define MW_REG_OFFSET_HWREG     (u32)(0x00000000)
0207 #define MW_REG_OFFSET_PCI       (u32)(0x00008000)
0208 #define MW_REG_PCI_HWREG_DELTA  (MW_REG_OFFSET_PCI - MW_REG_OFFSET_HWREG)
0209 #define MW_DATA_WINDOW_SIZE     (u32)(0x00020000)
0210 #define MW_DATA_ADDR_SER_FLASH  (u32)(0xEC000000)
0211 #define MW_DATA_ADDR_SRAM       (u32)(0xF4000000)
0212 #define MW_DATA_ADDR_PAR_FLASH  (u32)(0xFC000000)
0213 
0214 /*
0215  * the following registers are for the communication
0216  * list interface (AKA message unit (MU))
0217  */
0218 #define MU_IN_LIST_ADDR_LO      (u32)(0x00004000)
0219 #define MU_IN_LIST_ADDR_HI      (u32)(0x00004004)
0220 
0221 #define MU_IN_LIST_WRITE        (u32)(0x00004018)
0222     #define MU_ILW_TOGGLE       (u32)(0x00004000)
0223 
0224 #define MU_IN_LIST_READ         (u32)(0x0000401C)
0225     #define MU_ILR_TOGGLE       (u32)(0x00004000)
0226     #define MU_ILIC_LIST        (u32)(0x0000000F)
0227     #define MU_ILIC_LIST_F0     (u32)(0x00000000)
0228     #define MU_ILIC_DEST        (u32)(0x00000F00)
0229     #define MU_ILIC_DEST_DDR    (u32)(0x00000200)
0230 #define MU_IN_LIST_IFC_CONFIG   (u32)(0x00004028)
0231 
0232 #define MU_IN_LIST_CONFIG       (u32)(0x0000402C)
0233     #define MU_ILC_ENABLE       (u32)(0x00000001)
0234     #define MU_ILC_ENTRY_MASK   (u32)(0x000000F0)
0235     #define MU_ILC_ENTRY_4_DW   (u32)(0x00000020)
0236     #define MU_ILC_DYNAMIC_SRC  (u32)(0x00008000)
0237     #define MU_ILC_NUMBER_MASK  (u32)(0x7FFF0000)
0238     #define MU_ILC_NUMBER_SHIFT            16
0239 
0240 #define MU_OUT_LIST_ADDR_LO     (u32)(0x00004050)
0241 #define MU_OUT_LIST_ADDR_HI     (u32)(0x00004054)
0242 
0243 #define MU_OUT_LIST_COPY_PTR_LO (u32)(0x00004058)
0244 #define MU_OUT_LIST_COPY_PTR_HI (u32)(0x0000405C)
0245 
0246 #define MU_OUT_LIST_WRITE       (u32)(0x00004068)
0247     #define MU_OLW_TOGGLE       (u32)(0x00004000)
0248 
0249 #define MU_OUT_LIST_COPY        (u32)(0x0000406C)
0250     #define MU_OLC_TOGGLE       (u32)(0x00004000)
0251     #define MU_OLC_WRT_PTR      (u32)(0x00003FFF)
0252 
0253 #define MU_OUT_LIST_IFC_CONFIG  (u32)(0x00004078)
0254     #define MU_OLIC_LIST        (u32)(0x0000000F)
0255     #define MU_OLIC_LIST_F0     (u32)(0x00000000)
0256     #define MU_OLIC_SOURCE      (u32)(0x00000F00)
0257     #define MU_OLIC_SOURCE_DDR  (u32)(0x00000200)
0258 
0259 #define MU_OUT_LIST_CONFIG      (u32)(0x0000407C)
0260     #define MU_OLC_ENABLE       (u32)(0x00000001)
0261     #define MU_OLC_ENTRY_MASK   (u32)(0x000000F0)
0262     #define MU_OLC_ENTRY_4_DW   (u32)(0x00000020)
0263     #define MU_OLC_NUMBER_MASK  (u32)(0x7FFF0000)
0264     #define MU_OLC_NUMBER_SHIFT            16
0265 
0266 #define MU_OUT_LIST_INT_STAT    (u32)(0x00004088)
0267     #define MU_OLIS_INT         (u32)(0x00000001)
0268 
0269 #define MU_OUT_LIST_INT_MASK    (u32)(0x0000408C)
0270     #define MU_OLIS_MASK        (u32)(0x00000001)
0271 
0272 /*
0273  * the maximum size of the communication lists is two greater than the
0274  * maximum amount of VDA requests.  the extra are to prevent queue overflow.
0275  */
0276 #define ESAS2R_MAX_NUM_REQS         256
0277 #define ESAS2R_NUM_EXTRA            2
0278 #define ESAS2R_MAX_COMM_LIST_SIZE   (ESAS2R_MAX_NUM_REQS + ESAS2R_NUM_EXTRA)
0279 
0280 /*
0281  * the following registers are for the CPU interface
0282  */
0283 #define MU_CTL_STATUS_IN        (u32)(0x00010108)
0284     #define MU_CTL_IN_FULL_RST  (u32)(0x00000020)
0285 #define MU_CTL_STATUS_IN_B2     (u32)(0x00010130)
0286     #define MU_CTL_IN_FULL_RST2 (u32)(0x80000000)
0287 #define MU_DOORBELL_IN          (u32)(0x00010460)
0288     #define DRBL_RESET_BUS      (u32)(0x00000002)
0289     #define DRBL_PAUSE_AE       (u32)(0x00000004)
0290     #define DRBL_RESUME_AE      (u32)(0x00000008)
0291     #define DRBL_MSG_IFC_DOWN   (u32)(0x00000010)
0292     #define DRBL_FLASH_REQ      (u32)(0x00000020)
0293     #define DRBL_FLASH_DONE     (u32)(0x00000040)
0294     #define DRBL_FORCE_INT      (u32)(0x00000080)
0295     #define DRBL_MSG_IFC_INIT   (u32)(0x00000100)
0296     #define DRBL_POWER_DOWN     (u32)(0x00000200)
0297     #define DRBL_DRV_VER_1      (u32)(0x00010000)
0298     #define DRBL_DRV_VER        DRBL_DRV_VER_1
0299 #define MU_DOORBELL_IN_ENB      (u32)(0x00010464)
0300 #define MU_DOORBELL_OUT         (u32)(0x00010480)
0301  #define DRBL_PANIC_REASON_MASK (u32)(0x00F00000)
0302     #define DRBL_UNUSED_HANDLER (u32)(0x00100000)
0303     #define DRBL_UNDEF_INSTR    (u32)(0x00200000)
0304     #define DRBL_PREFETCH_ABORT (u32)(0x00300000)
0305     #define DRBL_DATA_ABORT     (u32)(0x00400000)
0306     #define DRBL_JUMP_TO_ZERO   (u32)(0x00500000)
0307   #define DRBL_FW_RESET         (u32)(0x00080000)
0308   #define DRBL_FW_VER_MSK       (u32)(0x00070000)
0309   #define DRBL_FW_VER_0         (u32)(0x00000000)
0310   #define DRBL_FW_VER_1         (u32)(0x00010000)
0311   #define DRBL_FW_VER           DRBL_FW_VER_1
0312 #define MU_DOORBELL_OUT_ENB     (u32)(0x00010484)
0313     #define DRBL_ENB_MASK       (u32)(0x00F803FF)
0314 #define MU_INT_STATUS_OUT       (u32)(0x00010200)
0315     #define MU_INTSTAT_POST_OUT (u32)(0x00000010)
0316     #define MU_INTSTAT_DRBL_IN  (u32)(0x00000100)
0317     #define MU_INTSTAT_DRBL     (u32)(0x00001000)
0318     #define MU_INTSTAT_MASK     (u32)(0x00001010)
0319 #define MU_INT_MASK_OUT         (u32)(0x0001020C)
0320 
0321 /* PCI express registers accessed via window 1 */
0322 #define MVR_PCI_WIN1_REMAP      (u32)(0x00008438)
0323     #define MVRPW1R_ENABLE      (u32)(0x00000001)
0324 
0325 
0326 /* structures */
0327 
0328 /* inbound list dynamic source entry */
0329 struct esas2r_inbound_list_source_entry {
0330     u64 address;
0331     u32 length;
0332     #define HWILSE_INTERFACE_F0  0x00000000
0333     u32 reserved;
0334 };
0335 
0336 /* PCI data structure in expansion ROM images */
0337 struct __packed esas2r_boot_header {
0338     char signature[4];
0339     u16 vendor_id;
0340     u16 device_id;
0341     u16 VPD;
0342     u16 struct_length;
0343     u8 struct_revision;
0344     u8 class_code[3];
0345     u16 image_length;
0346     u16 code_revision;
0347     u8 code_type;
0348     #define CODE_TYPE_PC    0
0349     #define CODE_TYPE_OPEN  1
0350     #define CODE_TYPE_EFI   3
0351     u8 indicator;
0352     #define INDICATOR_LAST  0x80
0353     u8 reserved[2];
0354 };
0355 
0356 struct __packed esas2r_boot_image {
0357     u16 signature;
0358     u8 reserved[22];
0359     u16 header_offset;
0360     u16 pnp_offset;
0361 };
0362 
0363 struct __packed esas2r_pc_image {
0364     u16 signature;
0365     u8 length;
0366     u8 entry_point[3];
0367     u8 checksum;
0368     u16 image_end;
0369     u16 min_size;
0370     u8 rom_flags;
0371     u8 reserved[12];
0372     u16 header_offset;
0373     u16 pnp_offset;
0374     struct esas2r_boot_header boot_image;
0375 };
0376 
0377 struct __packed esas2r_efi_image {
0378     u16 signature;
0379     u16 length;
0380     u32 efi_signature;
0381     #define EFI_ROM_SIG     0x00000EF1
0382     u16 image_type;
0383     #define EFI_IMAGE_APP   10
0384     #define EFI_IMAGE_BSD   11
0385     #define EFI_IMAGE_RTD   12
0386     u16 machine_type;
0387     #define EFI_MACHINE_IA32 0x014c
0388     #define EFI_MACHINE_IA64 0x0200
0389     #define EFI_MACHINE_X64  0x8664
0390     #define EFI_MACHINE_EBC  0x0EBC
0391     u16 compression;
0392     #define EFI_UNCOMPRESSED 0x0000
0393     #define EFI_COMPRESSED   0x0001
0394     u8 reserved[8];
0395     u16 efi_offset;
0396     u16 header_offset;
0397     u16 reserved2;
0398     struct esas2r_boot_header boot_image;
0399 };
0400 
0401 struct esas2r_adapter;
0402 struct esas2r_sg_context;
0403 struct esas2r_request;
0404 
0405 typedef void (*RQCALLBK)     (struct esas2r_adapter *a,
0406                   struct esas2r_request *rq);
0407 typedef bool (*RQBUILDSGL)   (struct esas2r_adapter *a,
0408                   struct esas2r_sg_context *sgc);
0409 
0410 struct esas2r_component_header {
0411     u8 img_type;
0412     #define CH_IT_FW    0x00
0413     #define CH_IT_NVR   0x01
0414     #define CH_IT_BIOS  0x02
0415     #define CH_IT_MAC   0x03
0416     #define CH_IT_CFG   0x04
0417     #define CH_IT_EFI   0x05
0418     u8 status;
0419     #define CH_STAT_PENDING 0xff
0420     #define CH_STAT_FAILED  0x00
0421     #define CH_STAT_SUCCESS 0x01
0422     #define CH_STAT_RETRY   0x02
0423     #define CH_STAT_INVALID 0x03
0424     u8 pad[2];
0425     u32 version;
0426     u32 length;
0427     u32 image_offset;
0428 };
0429 
0430 #define FI_REL_VER_SZ   16
0431 
0432 struct esas2r_flash_img_v0 {
0433     u8 fi_version;
0434     #define FI_VERSION_0    00
0435     u8 status;
0436     u8 adap_typ;
0437     u8 action;
0438     u32 length;
0439     u16 checksum;
0440     u16 driver_error;
0441     u16 flags;
0442     u16 num_comps;
0443     #define FI_NUM_COMPS_V0 5
0444     u8 rel_version[FI_REL_VER_SZ];
0445     struct esas2r_component_header cmp_hdr[FI_NUM_COMPS_V0];
0446     u8 scratch_buf[FM_BUF_SZ];
0447 };
0448 
0449 struct esas2r_flash_img {
0450     u8 fi_version;
0451     #define FI_VERSION_1    01
0452     u8 status;
0453     #define FI_STAT_SUCCESS  0x00
0454     #define FI_STAT_FAILED   0x01
0455     #define FI_STAT_REBOOT   0x02
0456     #define FI_STAT_ADAPTYP  0x03
0457     #define FI_STAT_INVALID  0x04
0458     #define FI_STAT_CHKSUM   0x05
0459     #define FI_STAT_LENGTH   0x06
0460     #define FI_STAT_UNKNOWN  0x07
0461     #define FI_STAT_IMG_VER  0x08
0462     #define FI_STAT_BUSY     0x09
0463     #define FI_STAT_DUAL     0x0A
0464     #define FI_STAT_MISSING  0x0B
0465     #define FI_STAT_UNSUPP   0x0C
0466     #define FI_STAT_ERASE    0x0D
0467     #define FI_STAT_FLASH    0x0E
0468     #define FI_STAT_DEGRADED 0x0F
0469     u8 adap_typ;
0470     #define FI_AT_UNKNWN    0xFF
0471     #define FI_AT_SUN_LAKE  0x0B
0472     #define FI_AT_MV_9580   0x0F
0473     u8 action;
0474     #define FI_ACT_DOWN     0x00
0475     #define FI_ACT_UP       0x01
0476     #define FI_ACT_UPSZ     0x02
0477     #define FI_ACT_MAX      0x02
0478     #define FI_ACT_DOWN1    0x80
0479     u32 length;
0480     u16 checksum;
0481     u16 driver_error;
0482     u16 flags;
0483     #define FI_FLG_NVR_DEF  0x0001
0484     u16 num_comps;
0485     #define FI_NUM_COMPS_V1 6
0486     u8 rel_version[FI_REL_VER_SZ];
0487     struct esas2r_component_header cmp_hdr[FI_NUM_COMPS_V1];
0488     u8 scratch_buf[FM_BUF_SZ];
0489 };
0490 
0491 /* definitions for flash script (FS) commands */
0492 struct esas2r_ioctlfs_command {
0493     u8 command;
0494     #define ESAS2R_FS_CMD_ERASE    0
0495     #define ESAS2R_FS_CMD_READ     1
0496     #define ESAS2R_FS_CMD_BEGINW   2
0497     #define ESAS2R_FS_CMD_WRITE    3
0498     #define ESAS2R_FS_CMD_COMMIT   4
0499     #define ESAS2R_FS_CMD_CANCEL   5
0500     u8 checksum;
0501     u8 reserved[2];
0502     u32 flash_addr;
0503     u32 length;
0504     u32 image_offset;
0505 };
0506 
0507 struct esas2r_ioctl_fs {
0508     u8 version;
0509     #define ESAS2R_FS_VER      0
0510     u8 status;
0511     u8 driver_error;
0512     u8 adap_type;
0513     #define ESAS2R_FS_AT_ESASRAID2     3
0514     #define ESAS2R_FS_AT_TSSASRAID2    4
0515     #define ESAS2R_FS_AT_TSSASRAID2E   5
0516     #define ESAS2R_FS_AT_TLSASHBA      6
0517     u8 driver_ver;
0518     u8 reserved[11];
0519     struct esas2r_ioctlfs_command command;
0520     u8 data[1];
0521 };
0522 
0523 struct esas2r_sas_nvram {
0524     u8 signature[4];
0525     u8 version;
0526     #define SASNVR_VERSION_0    0x00
0527     #define SASNVR_VERSION      SASNVR_VERSION_0
0528     u8 checksum;
0529     #define SASNVR_CKSUM_SEED   0x5A
0530     u8 max_lun_for_target;
0531     u8 pci_latency;
0532     #define SASNVR_PCILAT_DIS   0x00
0533     #define SASNVR_PCILAT_MIN   0x10
0534     #define SASNVR_PCILAT_MAX   0xF8
0535     u8 options1;
0536     #define SASNVR1_BOOT_DRVR   0x01
0537     #define SASNVR1_BOOT_SCAN   0x02
0538     #define SASNVR1_DIS_PCI_MWI 0x04
0539     #define SASNVR1_FORCE_ORD_Q 0x08
0540     #define SASNVR1_CACHELINE_0 0x10
0541     #define SASNVR1_DIS_DEVSORT 0x20
0542     #define SASNVR1_PWR_MGT_EN  0x40
0543     #define SASNVR1_WIDEPORT    0x80
0544     u8 options2;
0545     #define SASNVR2_SINGLE_BUS  0x01
0546     #define SASNVR2_SLOT_BIND   0x02
0547     #define SASNVR2_EXP_PROG    0x04
0548     #define SASNVR2_CMDTHR_LUN  0x08
0549     #define SASNVR2_HEARTBEAT   0x10
0550     #define SASNVR2_INT_CONNECT 0x20
0551     #define SASNVR2_SW_MUX_CTRL 0x40
0552     #define SASNVR2_DISABLE_NCQ 0x80
0553     u8 int_coalescing;
0554     #define SASNVR_COAL_DIS     0x00
0555     #define SASNVR_COAL_LOW     0x01
0556     #define SASNVR_COAL_MED     0x02
0557     #define SASNVR_COAL_HI      0x03
0558     u8 cmd_throttle;
0559     #define SASNVR_CMDTHR_NONE  0x00
0560     u8 dev_wait_time;
0561     u8 dev_wait_count;
0562     u8 spin_up_delay;
0563     #define SASNVR_SPINUP_MAX   0x14
0564     u8 ssp_align_rate;
0565     u8 sas_addr[8];
0566     u8 phy_speed[16];
0567     #define SASNVR_SPEED_AUTO   0x00
0568     #define SASNVR_SPEED_1_5GB  0x01
0569     #define SASNVR_SPEED_3GB    0x02
0570     #define SASNVR_SPEED_6GB    0x03
0571     #define SASNVR_SPEED_12GB   0x04
0572     u8 phy_mux[16];
0573     #define SASNVR_MUX_DISABLED 0x00
0574     #define SASNVR_MUX_1_5GB    0x01
0575     #define SASNVR_MUX_3GB      0x02
0576     #define SASNVR_MUX_6GB      0x03
0577     u8 phy_flags[16];
0578     #define SASNVR_PHF_DISABLED 0x01
0579     #define SASNVR_PHF_RD_ONLY  0x02
0580     u8 sort_type;
0581     #define SASNVR_SORT_SAS_ADDR    0x00
0582     #define SASNVR_SORT_H308_CONN   0x01
0583     #define SASNVR_SORT_PHY_ID      0x02
0584     #define SASNVR_SORT_SLOT_ID     0x03
0585     u8 dpm_reqcmd_lmt;
0586     u8 dpm_stndby_time;
0587     u8 dpm_active_time;
0588     u8 phy_target_id[16];
0589     #define SASNVR_PTI_DISABLED     0xFF
0590     u8 virt_ses_mode;
0591     #define SASNVR_VSMH_DISABLED    0x00
0592     u8 read_write_mode;
0593     #define SASNVR_RWM_DEFAULT      0x00
0594     u8 link_down_to;
0595     u8 reserved[0xA1];
0596 };
0597 
0598 typedef u32 (*PGETPHYSADDR) (struct esas2r_sg_context *sgc, u64 *addr);
0599 
0600 struct esas2r_sg_context {
0601     struct esas2r_adapter *adapter;
0602     struct esas2r_request *first_req;
0603     u32 length;
0604     u8 *cur_offset;
0605     PGETPHYSADDR get_phys_addr;
0606     union {
0607         struct {
0608             struct atto_vda_sge *curr;
0609             struct atto_vda_sge *last;
0610             struct atto_vda_sge *limit;
0611             struct atto_vda_sge *chain;
0612         } a64;
0613         struct {
0614             struct atto_physical_region_description *curr;
0615             struct atto_physical_region_description *chain;
0616             u32 sgl_max_cnt;
0617             u32 sge_cnt;
0618         } prd;
0619     } sge;
0620     struct scatterlist *cur_sgel;
0621     u8 *exp_offset;
0622     int num_sgel;
0623     int sgel_count;
0624 };
0625 
0626 struct esas2r_target {
0627     u8 flags;
0628     #define TF_PASS_THRU    0x01
0629     #define TF_USED         0x02
0630     u8 new_target_state;
0631     u8 target_state;
0632     u8 buffered_target_state;
0633 #define TS_NOT_PRESENT      0x00
0634 #define TS_PRESENT          0x05
0635 #define TS_LUN_CHANGE       0x06
0636 #define TS_INVALID          0xFF
0637     u32 block_size;
0638     u32 inter_block;
0639     u32 inter_byte;
0640     u16 virt_targ_id;
0641     u16 phys_targ_id;
0642     u8 identifier_len;
0643     u64 sas_addr;
0644     u8 identifier[60];
0645     struct atto_vda_ae_lu lu_event;
0646 };
0647 
0648 struct esas2r_request {
0649     struct list_head comp_list;
0650     struct list_head req_list;
0651     union atto_vda_req *vrq;
0652     struct esas2r_mem_desc *vrq_md;
0653     union {
0654         void *data_buf;
0655         union atto_vda_rsp_data *vda_rsp_data;
0656     };
0657     u8 *sense_buf;
0658     struct list_head sg_table_head;
0659     struct esas2r_mem_desc *sg_table;
0660     u32 timeout;
0661     #define RQ_TIMEOUT_S1     0xFFFFFFFF
0662     #define RQ_TIMEOUT_S2     0xFFFFFFFE
0663     #define RQ_MAX_TIMEOUT    0xFFFFFFFD
0664     u16 target_id;
0665     u8 req_type;
0666     #define RT_INI_REQ          0x01
0667     #define RT_DISC_REQ         0x02
0668     u8 sense_len;
0669     union atto_vda_func_rsp func_rsp;
0670     RQCALLBK comp_cb;
0671     RQCALLBK interrupt_cb;
0672     void *interrupt_cx;
0673     u8 flags;
0674     #define RF_1ST_IBLK_BASE    0x04
0675     #define RF_FAILURE_OK       0x08
0676     u8 req_stat;
0677     u16 vda_req_sz;
0678     #define RQ_SIZE_DEFAULT   0
0679     u64 lba;
0680     RQCALLBK aux_req_cb;
0681     void *aux_req_cx;
0682     u32 blk_len;
0683     u32 max_blk_len;
0684     union {
0685         struct scsi_cmnd *cmd;
0686         u8 *task_management_status_ptr;
0687     };
0688 };
0689 
0690 struct esas2r_flash_context {
0691     struct esas2r_flash_img *fi;
0692     RQCALLBK interrupt_cb;
0693     u8 *sgc_offset;
0694     u8 *scratch;
0695     u32 fi_hdr_len;
0696     u8 task;
0697     #define     FMTSK_ERASE_BOOT    0
0698     #define     FMTSK_WRTBIOS       1
0699     #define     FMTSK_READBIOS      2
0700     #define     FMTSK_WRTMAC        3
0701     #define     FMTSK_READMAC       4
0702     #define     FMTSK_WRTEFI        5
0703     #define     FMTSK_READEFI       6
0704     #define     FMTSK_WRTCFG        7
0705     #define     FMTSK_READCFG       8
0706     u8 func;
0707     u16 num_comps;
0708     u32 cmp_len;
0709     u32 flsh_addr;
0710     u32 curr_len;
0711     u8 comp_typ;
0712     struct esas2r_sg_context sgc;
0713 };
0714 
0715 struct esas2r_disc_context {
0716     u8 disc_evt;
0717     #define DCDE_DEV_CHANGE     0x01
0718     #define DCDE_DEV_SCAN       0x02
0719     u8 state;
0720     #define DCS_DEV_RMV         0x00
0721     #define DCS_DEV_ADD         0x01
0722     #define DCS_BLOCK_DEV_SCAN  0x02
0723     #define DCS_RAID_GRP_INFO   0x03
0724     #define DCS_PART_INFO       0x04
0725     #define DCS_PT_DEV_INFO     0x05
0726     #define DCS_PT_DEV_ADDR     0x06
0727     #define DCS_DISC_DONE       0xFF
0728     u16 flags;
0729     #define DCF_DEV_CHANGE      0x0001
0730     #define DCF_DEV_SCAN        0x0002
0731     #define DCF_POLLED          0x8000
0732     u32 interleave;
0733     u32 block_size;
0734     u16 dev_ix;
0735     u8 part_num;
0736     u8 raid_grp_ix;
0737     char raid_grp_name[16];
0738     struct esas2r_target *curr_targ;
0739     u16 curr_virt_id;
0740     u16 curr_phys_id;
0741     u8 scan_gen;
0742     u8 dev_addr_type;
0743     u64 sas_addr;
0744 };
0745 
0746 struct esas2r_mem_desc {
0747     struct list_head next_desc;
0748     void *virt_addr;
0749     u64 phys_addr;
0750     void *pad;
0751     void *esas2r_data;
0752     u32 esas2r_param;
0753     u32 size;
0754 };
0755 
0756 enum fw_event_type {
0757     fw_event_null,
0758     fw_event_lun_change,
0759     fw_event_present,
0760     fw_event_not_present,
0761     fw_event_vda_ae
0762 };
0763 
0764 struct esas2r_vda_ae {
0765     u32 signature;
0766 #define ESAS2R_VDA_EVENT_SIG  0x4154544F
0767     u8 bus_number;
0768     u8 devfn;
0769     u8 pad[2];
0770     union atto_vda_ae vda_ae;
0771 };
0772 
0773 struct esas2r_fw_event_work {
0774     struct list_head list;
0775     struct delayed_work work;
0776     struct esas2r_adapter *a;
0777     enum fw_event_type type;
0778     u8 data[sizeof(struct esas2r_vda_ae)];
0779 };
0780 
0781 enum state {
0782     FW_INVALID_ST,
0783     FW_STATUS_ST,
0784     FW_COMMAND_ST
0785 };
0786 
0787 struct esas2r_firmware {
0788     enum state state;
0789     struct esas2r_flash_img header;
0790     u8 *data;
0791     u64 phys;
0792     int orig_len;
0793     void *header_buff;
0794     u64 header_buff_phys;
0795 };
0796 
0797 struct esas2r_adapter {
0798     struct esas2r_target targetdb[ESAS2R_MAX_TARGETS];
0799     struct esas2r_target *targetdb_end;
0800     unsigned char *regs;
0801     unsigned char *data_window;
0802     long flags;
0803     #define AF_PORT_CHANGE      0
0804     #define AF_CHPRST_NEEDED    1
0805     #define AF_CHPRST_PENDING   2
0806     #define AF_CHPRST_DETECTED  3
0807     #define AF_BUSRST_NEEDED    4
0808     #define AF_BUSRST_PENDING   5
0809     #define AF_BUSRST_DETECTED  6
0810     #define AF_DISABLED         7
0811     #define AF_FLASH_LOCK       8
0812     #define AF_OS_RESET         9
0813     #define AF_FLASHING         10
0814     #define AF_POWER_MGT        11
0815     #define AF_NVR_VALID        12
0816     #define AF_DEGRADED_MODE    13
0817     #define AF_DISC_PENDING     14
0818     #define AF_TASKLET_SCHEDULED    15
0819     #define AF_HEARTBEAT        16
0820     #define AF_HEARTBEAT_ENB    17
0821     #define AF_NOT_PRESENT      18
0822     #define AF_CHPRST_STARTED   19
0823     #define AF_FIRST_INIT       20
0824     #define AF_POWER_DOWN       21
0825     #define AF_DISC_IN_PROG     22
0826     #define AF_COMM_LIST_TOGGLE 23
0827     #define AF_LEGACY_SGE_MODE  24
0828     #define AF_DISC_POLLED      25
0829     long flags2;
0830     #define AF2_SERIAL_FLASH    0
0831     #define AF2_DEV_SCAN        1
0832     #define AF2_DEV_CNT_OK      2
0833     #define AF2_COREDUMP_AVAIL  3
0834     #define AF2_COREDUMP_SAVED  4
0835     #define AF2_VDA_POWER_DOWN  5
0836     #define AF2_THUNDERLINK     6
0837     #define AF2_THUNDERBOLT     7
0838     #define AF2_INIT_DONE       8
0839     #define AF2_INT_PENDING     9
0840     #define AF2_TIMER_TICK      10
0841     #define AF2_IRQ_CLAIMED     11
0842     #define AF2_MSI_ENABLED     12
0843     atomic_t disable_cnt;
0844     atomic_t dis_ints_cnt;
0845     u32 int_stat;
0846     u32 int_mask;
0847     u32 volatile *outbound_copy;
0848     struct list_head avail_request;
0849     spinlock_t request_lock;
0850     spinlock_t sg_list_lock;
0851     spinlock_t queue_lock;
0852     spinlock_t mem_lock;
0853     struct list_head free_sg_list_head;
0854     struct esas2r_mem_desc *sg_list_mds;
0855     struct list_head active_list;
0856     struct list_head defer_list;
0857     struct esas2r_request **req_table;
0858     union {
0859         u16 prev_dev_cnt;
0860         u32 heartbeat_time;
0861     #define ESAS2R_HEARTBEAT_TIME       (3000)
0862     };
0863     u32 chip_uptime;
0864     #define ESAS2R_CHP_UPTIME_MAX       (60000)
0865     #define ESAS2R_CHP_UPTIME_CNT       (20000)
0866     u64 uncached_phys;
0867     u8 *uncached;
0868     struct esas2r_sas_nvram *nvram;
0869     struct esas2r_request general_req;
0870     u8 init_msg;
0871     #define ESAS2R_INIT_MSG_START       1
0872     #define ESAS2R_INIT_MSG_INIT        2
0873     #define ESAS2R_INIT_MSG_GET_INIT    3
0874     #define ESAS2R_INIT_MSG_REINIT      4
0875     u16 cmd_ref_no;
0876     u32 fw_version;
0877     u32 fw_build;
0878     u32 chip_init_time;
0879     #define ESAS2R_CHPRST_TIME         (180000)
0880     #define ESAS2R_CHPRST_WAIT_TIME    (2000)
0881     u32 last_tick_time;
0882     u32 window_base;
0883     RQBUILDSGL build_sgl;
0884     struct esas2r_request *first_ae_req;
0885     u32 list_size;
0886     u32 last_write;
0887     u32 last_read;
0888     u16 max_vdareq_size;
0889     u16 disc_wait_cnt;
0890     struct esas2r_mem_desc inbound_list_md;
0891     struct esas2r_mem_desc outbound_list_md;
0892     struct esas2r_disc_context disc_ctx;
0893     u8 *disc_buffer;
0894     u32 disc_start_time;
0895     u32 disc_wait_time;
0896     u32 flash_ver;
0897     char flash_rev[16];
0898     char fw_rev[16];
0899     char image_type[16];
0900     struct esas2r_flash_context flash_context;
0901     u32 num_targets_backend;
0902     u32 ioctl_tunnel;
0903     struct tasklet_struct tasklet;
0904     struct pci_dev *pcid;
0905     struct Scsi_Host *host;
0906     unsigned int index;
0907     char name[32];
0908     struct timer_list timer;
0909     struct esas2r_firmware firmware;
0910     wait_queue_head_t nvram_waiter;
0911     int nvram_command_done;
0912     wait_queue_head_t fm_api_waiter;
0913     int fm_api_command_done;
0914     wait_queue_head_t vda_waiter;
0915     int vda_command_done;
0916     u8 *vda_buffer;
0917     u64 ppvda_buffer;
0918 #define VDA_BUFFER_HEADER_SZ (offsetof(struct atto_ioctl_vda, data))
0919 #define VDA_MAX_BUFFER_SIZE  (0x40000 + VDA_BUFFER_HEADER_SZ)
0920     wait_queue_head_t fs_api_waiter;
0921     int fs_api_command_done;
0922     u64 ppfs_api_buffer;
0923     u8 *fs_api_buffer;
0924     u32 fs_api_buffer_size;
0925     wait_queue_head_t buffered_ioctl_waiter;
0926     int buffered_ioctl_done;
0927     int uncached_size;
0928     struct workqueue_struct *fw_event_q;
0929     struct list_head fw_event_list;
0930     spinlock_t fw_event_lock;
0931     u8 fw_events_off;                       /* if '1', then ignore events */
0932     char fw_event_q_name[ESAS2R_KOBJ_NAME_LEN];
0933     /*
0934      * intr_mode stores the interrupt mode currently being used by this
0935      * adapter. it is based on the interrupt_mode module parameter, but
0936      * can be changed based on the ability (or not) to utilize the
0937      * mode requested by the parameter.
0938      */
0939     int intr_mode;
0940 #define INTR_MODE_LEGACY 0
0941 #define INTR_MODE_MSI    1
0942 #define INTR_MODE_MSIX   2
0943     struct esas2r_sg_context fm_api_sgc;
0944     u8 *save_offset;
0945     struct list_head vrq_mds_head;
0946     struct esas2r_mem_desc *vrq_mds;
0947     int num_vrqs;
0948     struct mutex fm_api_mutex;
0949     struct mutex fs_api_mutex;
0950     struct semaphore nvram_semaphore;
0951     struct atto_ioctl *local_atto_ioctl;
0952     u8 fw_coredump_buff[ESAS2R_FWCOREDUMP_SZ];
0953     unsigned int sysfs_fw_created:1;
0954     unsigned int sysfs_fs_created:1;
0955     unsigned int sysfs_vda_created:1;
0956     unsigned int sysfs_hw_created:1;
0957     unsigned int sysfs_live_nvram_created:1;
0958     unsigned int sysfs_default_nvram_created:1;
0959 };
0960 
0961 /*
0962  * Function Declarations
0963  * SCSI functions
0964  */
0965 const char *esas2r_info(struct Scsi_Host *);
0966 int esas2r_write_params(struct esas2r_adapter *a, struct esas2r_request *rq,
0967             struct esas2r_sas_nvram *data);
0968 int esas2r_ioctl_handler(void *hostdata, unsigned int cmd, void __user *arg);
0969 int esas2r_ioctl(struct scsi_device *dev, unsigned int cmd, void __user *arg);
0970 u8 handle_hba_ioctl(struct esas2r_adapter *a,
0971             struct atto_ioctl *ioctl_hba);
0972 int esas2r_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd);
0973 int esas2r_show_info(struct seq_file *m, struct Scsi_Host *sh);
0974 long esas2r_proc_ioctl(struct file *fp, unsigned int cmd, unsigned long arg);
0975 
0976 /* SCSI error handler (eh) functions */
0977 int esas2r_eh_abort(struct scsi_cmnd *cmd);
0978 int esas2r_device_reset(struct scsi_cmnd *cmd);
0979 int esas2r_host_reset(struct scsi_cmnd *cmd);
0980 int esas2r_bus_reset(struct scsi_cmnd *cmd);
0981 int esas2r_target_reset(struct scsi_cmnd *cmd);
0982 
0983 /* Internal functions */
0984 int esas2r_init_adapter(struct Scsi_Host *host, struct pci_dev *pcid,
0985             int index);
0986 int esas2r_read_fw(struct esas2r_adapter *a, char *buf, long off, int count);
0987 int esas2r_write_fw(struct esas2r_adapter *a, const char *buf, long off,
0988             int count);
0989 int esas2r_read_vda(struct esas2r_adapter *a, char *buf, long off, int count);
0990 int esas2r_write_vda(struct esas2r_adapter *a, const char *buf, long off,
0991              int count);
0992 int esas2r_read_fs(struct esas2r_adapter *a, char *buf, long off, int count);
0993 int esas2r_write_fs(struct esas2r_adapter *a, const char *buf, long off,
0994             int count);
0995 void esas2r_adapter_tasklet(unsigned long context);
0996 irqreturn_t esas2r_interrupt(int irq, void *dev_id);
0997 irqreturn_t esas2r_msi_interrupt(int irq, void *dev_id);
0998 void esas2r_kickoff_timer(struct esas2r_adapter *a);
0999 
1000 extern const struct dev_pm_ops esas2r_pm_ops;
1001 
1002 void esas2r_fw_event_off(struct esas2r_adapter *a);
1003 void esas2r_fw_event_on(struct esas2r_adapter *a);
1004 bool esas2r_nvram_write(struct esas2r_adapter *a, struct esas2r_request *rq,
1005             struct esas2r_sas_nvram *nvram);
1006 void esas2r_nvram_get_defaults(struct esas2r_adapter *a,
1007                    struct esas2r_sas_nvram *nvram);
1008 void esas2r_complete_request_cb(struct esas2r_adapter *a,
1009                 struct esas2r_request *rq);
1010 void esas2r_reset_detected(struct esas2r_adapter *a);
1011 void esas2r_target_state_changed(struct esas2r_adapter *ha, u16 targ_id,
1012                  u8 state);
1013 int esas2r_req_status_to_error(u8 req_stat);
1014 void esas2r_kill_adapter(int i);
1015 void esas2r_free_request(struct esas2r_adapter *a, struct esas2r_request *rq);
1016 struct esas2r_request *esas2r_alloc_request(struct esas2r_adapter *a);
1017 u32 esas2r_get_uncached_size(struct esas2r_adapter *a);
1018 bool esas2r_init_adapter_struct(struct esas2r_adapter *a,
1019                 void **uncached_area);
1020 bool esas2r_check_adapter(struct esas2r_adapter *a);
1021 bool esas2r_init_adapter_hw(struct esas2r_adapter *a, bool init_poll);
1022 void esas2r_start_request(struct esas2r_adapter *a, struct esas2r_request *rq);
1023 bool esas2r_send_task_mgmt(struct esas2r_adapter *a,
1024                struct esas2r_request *rqaux, u8 task_mgt_func);
1025 void esas2r_do_tasklet_tasks(struct esas2r_adapter *a);
1026 void esas2r_adapter_interrupt(struct esas2r_adapter *a);
1027 void esas2r_do_deferred_processes(struct esas2r_adapter *a);
1028 void esas2r_reset_bus(struct esas2r_adapter *a);
1029 void esas2r_reset_adapter(struct esas2r_adapter *a);
1030 void esas2r_timer_tick(struct esas2r_adapter *a);
1031 const char *esas2r_get_model_name(struct esas2r_adapter *a);
1032 const char *esas2r_get_model_name_short(struct esas2r_adapter *a);
1033 u32 esas2r_stall_execution(struct esas2r_adapter *a, u32 start_time,
1034                u32 *delay);
1035 void esas2r_build_flash_req(struct esas2r_adapter *a,
1036                 struct esas2r_request *rq,
1037                 u8 sub_func,
1038                 u8 cksum,
1039                 u32 addr,
1040                 u32 length);
1041 void esas2r_build_mgt_req(struct esas2r_adapter *a,
1042               struct esas2r_request *rq,
1043               u8 sub_func,
1044               u8 scan_gen,
1045               u16 dev_index,
1046               u32 length,
1047               void *data);
1048 void esas2r_build_ae_req(struct esas2r_adapter *a, struct esas2r_request *rq);
1049 void esas2r_build_cli_req(struct esas2r_adapter *a,
1050               struct esas2r_request *rq,
1051               u32 length,
1052               u32 cmd_rsp_len);
1053 void esas2r_build_ioctl_req(struct esas2r_adapter *a,
1054                 struct esas2r_request *rq,
1055                 u32 length,
1056                 u8 sub_func);
1057 void esas2r_build_cfg_req(struct esas2r_adapter *a,
1058               struct esas2r_request *rq,
1059               u8 sub_func,
1060               u32 length,
1061               void *data);
1062 void esas2r_power_down(struct esas2r_adapter *a);
1063 bool esas2r_power_up(struct esas2r_adapter *a, bool init_poll);
1064 void esas2r_wait_request(struct esas2r_adapter *a, struct esas2r_request *rq);
1065 u32 esas2r_map_data_window(struct esas2r_adapter *a, u32 addr_lo);
1066 bool esas2r_process_fs_ioctl(struct esas2r_adapter *a,
1067                  struct esas2r_ioctl_fs *fs,
1068                  struct esas2r_request *rq,
1069                  struct esas2r_sg_context *sgc);
1070 bool esas2r_read_flash_block(struct esas2r_adapter *a, void *to, u32 from,
1071                  u32 size);
1072 bool esas2r_read_mem_block(struct esas2r_adapter *a, void *to, u32 from,
1073                u32 size);
1074 bool esas2r_fm_api(struct esas2r_adapter *a, struct esas2r_flash_img *fi,
1075            struct esas2r_request *rq, struct esas2r_sg_context *sgc);
1076 void esas2r_force_interrupt(struct esas2r_adapter *a);
1077 void esas2r_local_start_request(struct esas2r_adapter *a,
1078                 struct esas2r_request *rq);
1079 void esas2r_process_adapter_reset(struct esas2r_adapter *a);
1080 void esas2r_complete_request(struct esas2r_adapter *a,
1081                  struct esas2r_request *rq);
1082 void esas2r_dummy_complete(struct esas2r_adapter *a,
1083                struct esas2r_request *rq);
1084 void esas2r_ae_complete(struct esas2r_adapter *a, struct esas2r_request *rq);
1085 void esas2r_start_vda_request(struct esas2r_adapter *a,
1086                   struct esas2r_request *rq);
1087 bool esas2r_read_flash_rev(struct esas2r_adapter *a);
1088 bool esas2r_read_image_type(struct esas2r_adapter *a);
1089 bool esas2r_nvram_read_direct(struct esas2r_adapter *a);
1090 bool esas2r_nvram_validate(struct esas2r_adapter *a);
1091 void esas2r_nvram_set_defaults(struct esas2r_adapter *a);
1092 bool esas2r_print_flash_rev(struct esas2r_adapter *a);
1093 void esas2r_send_reset_ae(struct esas2r_adapter *a, bool pwr_mgt);
1094 bool esas2r_init_msgs(struct esas2r_adapter *a);
1095 bool esas2r_is_adapter_present(struct esas2r_adapter *a);
1096 void esas2r_nuxi_mgt_data(u8 function, void *data);
1097 void esas2r_nuxi_cfg_data(u8 function, void *data);
1098 void esas2r_nuxi_ae_data(union atto_vda_ae *ae);
1099 void esas2r_reset_chip(struct esas2r_adapter *a);
1100 void esas2r_log_request_failure(struct esas2r_adapter *a,
1101                 struct esas2r_request *rq);
1102 void esas2r_polled_interrupt(struct esas2r_adapter *a);
1103 bool esas2r_ioreq_aborted(struct esas2r_adapter *a, struct esas2r_request *rq,
1104               u8 status);
1105 bool esas2r_build_sg_list_sge(struct esas2r_adapter *a,
1106                   struct esas2r_sg_context *sgc);
1107 bool esas2r_build_sg_list_prd(struct esas2r_adapter *a,
1108                   struct esas2r_sg_context *sgc);
1109 void esas2r_targ_db_initialize(struct esas2r_adapter *a);
1110 void esas2r_targ_db_remove_all(struct esas2r_adapter *a, bool notify);
1111 void esas2r_targ_db_report_changes(struct esas2r_adapter *a);
1112 struct esas2r_target *esas2r_targ_db_add_raid(struct esas2r_adapter *a,
1113                           struct esas2r_disc_context *dc);
1114 struct esas2r_target *esas2r_targ_db_add_pthru(struct esas2r_adapter *a,
1115                            struct esas2r_disc_context *dc,
1116                            u8 *ident,
1117                            u8 ident_len);
1118 void esas2r_targ_db_remove(struct esas2r_adapter *a, struct esas2r_target *t);
1119 struct esas2r_target *esas2r_targ_db_find_by_sas_addr(struct esas2r_adapter *a,
1120                               u64 *sas_addr);
1121 struct esas2r_target *esas2r_targ_db_find_by_ident(struct esas2r_adapter *a,
1122                            void *identifier,
1123                            u8 ident_len);
1124 u16 esas2r_targ_db_find_next_present(struct esas2r_adapter *a, u16 target_id);
1125 struct esas2r_target *esas2r_targ_db_find_by_virt_id(struct esas2r_adapter *a,
1126                              u16 virt_id);
1127 u16 esas2r_targ_db_get_tgt_cnt(struct esas2r_adapter *a);
1128 void esas2r_disc_initialize(struct esas2r_adapter *a);
1129 void esas2r_disc_start_waiting(struct esas2r_adapter *a);
1130 void esas2r_disc_check_for_work(struct esas2r_adapter *a);
1131 void esas2r_disc_check_complete(struct esas2r_adapter *a);
1132 void esas2r_disc_queue_event(struct esas2r_adapter *a, u8 disc_evt);
1133 bool esas2r_disc_start_port(struct esas2r_adapter *a);
1134 void esas2r_disc_local_start_request(struct esas2r_adapter *a,
1135                      struct esas2r_request *rq);
1136 bool esas2r_set_degraded_mode(struct esas2r_adapter *a, char *error_str);
1137 bool esas2r_process_vda_ioctl(struct esas2r_adapter *a,
1138                   struct atto_ioctl_vda *vi,
1139                   struct esas2r_request *rq,
1140                   struct esas2r_sg_context *sgc);
1141 void esas2r_queue_fw_event(struct esas2r_adapter *a,
1142                enum fw_event_type type,
1143                void *data,
1144                int data_sz);
1145 
1146 /* Inline functions */
1147 
1148 /* Allocate a chip scatter/gather list entry */
1149 static inline struct esas2r_mem_desc *esas2r_alloc_sgl(struct esas2r_adapter *a)
1150 {
1151     unsigned long flags;
1152     struct list_head *sgl;
1153     struct esas2r_mem_desc *result = NULL;
1154 
1155     spin_lock_irqsave(&a->sg_list_lock, flags);
1156     if (likely(!list_empty(&a->free_sg_list_head))) {
1157         sgl = a->free_sg_list_head.next;
1158         result = list_entry(sgl, struct esas2r_mem_desc, next_desc);
1159         list_del_init(sgl);
1160     }
1161     spin_unlock_irqrestore(&a->sg_list_lock, flags);
1162 
1163     return result;
1164 }
1165 
1166 /* Initialize a scatter/gather context */
1167 static inline void esas2r_sgc_init(struct esas2r_sg_context *sgc,
1168                    struct esas2r_adapter *a,
1169                    struct esas2r_request *rq,
1170                    struct atto_vda_sge *first)
1171 {
1172     sgc->adapter = a;
1173     sgc->first_req = rq;
1174 
1175     /*
1176      * set the limit pointer such that an SGE pointer above this value
1177      * would be the first one to overflow the SGL.
1178      */
1179     sgc->sge.a64.limit = (struct atto_vda_sge *)((u8 *)rq->vrq
1180                              + (sizeof(union
1181                                    atto_vda_req) /
1182                             8)
1183                              - sizeof(struct
1184                                   atto_vda_sge));
1185     if (first) {
1186         sgc->sge.a64.last =
1187             sgc->sge.a64.curr = first;
1188         rq->vrq->scsi.sg_list_offset = (u8)
1189                            ((u8 *)first -
1190                         (u8 *)rq->vrq);
1191     } else {
1192         sgc->sge.a64.last =
1193             sgc->sge.a64.curr = &rq->vrq->scsi.u.sge[0];
1194         rq->vrq->scsi.sg_list_offset =
1195             (u8)offsetof(struct atto_vda_scsi_req, u.sge);
1196     }
1197     sgc->sge.a64.chain = NULL;
1198 }
1199 
1200 static inline void esas2r_rq_init_request(struct esas2r_request *rq,
1201                       struct esas2r_adapter *a)
1202 {
1203     union atto_vda_req *vrq = rq->vrq;
1204 
1205     INIT_LIST_HEAD(&rq->sg_table_head);
1206     rq->data_buf = (void *)(vrq + 1);
1207     rq->interrupt_cb = NULL;
1208     rq->comp_cb = esas2r_complete_request_cb;
1209     rq->flags = 0;
1210     rq->timeout = 0;
1211     rq->req_stat = RS_PENDING;
1212     rq->req_type = RT_INI_REQ;
1213 
1214     /* clear the outbound response */
1215     rq->func_rsp.dwords[0] = 0;
1216     rq->func_rsp.dwords[1] = 0;
1217 
1218     /*
1219      * clear the size of the VDA request.  esas2r_build_sg_list() will
1220      * only allow the size of the request to grow.  there are some
1221      * management requests that go through there twice and the second
1222      * time through sets a smaller request size.  if this is not modified
1223      * at all we'll set it to the size of the entire VDA request.
1224      */
1225     rq->vda_req_sz = RQ_SIZE_DEFAULT;
1226 
1227     /* req_table entry should be NULL at this point - if not, halt */
1228 
1229     if (a->req_table[LOWORD(vrq->scsi.handle)]) {
1230         esas2r_bugon();
1231     }
1232 
1233     /* fill in the table for this handle so we can get back to the
1234      * request.
1235      */
1236     a->req_table[LOWORD(vrq->scsi.handle)] = rq;
1237 
1238     /*
1239      * add a reference number to the handle to make it unique (until it
1240      * wraps of course) while preserving the least significant word
1241      */
1242     vrq->scsi.handle = (a->cmd_ref_no++ << 16) | (u16)vrq->scsi.handle;
1243 
1244     /*
1245      * the following formats a SCSI request.  the caller can override as
1246      * necessary.  clear_vda_request can be called to clear the VDA
1247      * request for another type of request.
1248      */
1249     vrq->scsi.function = VDA_FUNC_SCSI;
1250     vrq->scsi.sense_len = SENSE_DATA_SZ;
1251 
1252     /* clear out sg_list_offset and chain_offset */
1253     vrq->scsi.sg_list_offset = 0;
1254     vrq->scsi.chain_offset = 0;
1255     vrq->scsi.flags = 0;
1256     vrq->scsi.reserved = 0;
1257 
1258     /* set the sense buffer to be the data payload buffer */
1259     vrq->scsi.ppsense_buf
1260         = cpu_to_le64(rq->vrq_md->phys_addr +
1261                   sizeof(union atto_vda_req));
1262 }
1263 
1264 static inline void esas2r_rq_free_sg_lists(struct esas2r_request *rq,
1265                        struct esas2r_adapter *a)
1266 {
1267     unsigned long flags;
1268 
1269     if (list_empty(&rq->sg_table_head))
1270         return;
1271 
1272     spin_lock_irqsave(&a->sg_list_lock, flags);
1273     list_splice_tail_init(&rq->sg_table_head, &a->free_sg_list_head);
1274     spin_unlock_irqrestore(&a->sg_list_lock, flags);
1275 }
1276 
1277 static inline void esas2r_rq_destroy_request(struct esas2r_request *rq,
1278                          struct esas2r_adapter *a)
1279 
1280 {
1281     esas2r_rq_free_sg_lists(rq, a);
1282     a->req_table[LOWORD(rq->vrq->scsi.handle)] = NULL;
1283     rq->data_buf = NULL;
1284 }
1285 
1286 static inline bool esas2r_is_tasklet_pending(struct esas2r_adapter *a)
1287 {
1288 
1289     return test_bit(AF_BUSRST_NEEDED, &a->flags) ||
1290            test_bit(AF_BUSRST_DETECTED, &a->flags) ||
1291            test_bit(AF_CHPRST_NEEDED, &a->flags) ||
1292            test_bit(AF_CHPRST_DETECTED, &a->flags) ||
1293            test_bit(AF_PORT_CHANGE, &a->flags);
1294 
1295 }
1296 
1297 /*
1298  * Build the scatter/gather list for an I/O request according to the
1299  * specifications placed in the esas2r_sg_context.  The caller must initialize
1300  * struct esas2r_sg_context prior to the initial call by calling
1301  * esas2r_sgc_init()
1302  */
1303 static inline bool esas2r_build_sg_list(struct esas2r_adapter *a,
1304                     struct esas2r_request *rq,
1305                     struct esas2r_sg_context *sgc)
1306 {
1307     if (unlikely(le32_to_cpu(rq->vrq->scsi.length) == 0))
1308         return true;
1309 
1310     return (*a->build_sgl)(a, sgc);
1311 }
1312 
1313 static inline void esas2r_disable_chip_interrupts(struct esas2r_adapter *a)
1314 {
1315     if (atomic_inc_return(&a->dis_ints_cnt) == 1)
1316         esas2r_write_register_dword(a, MU_INT_MASK_OUT,
1317                         ESAS2R_INT_DIS_MASK);
1318 }
1319 
1320 static inline void esas2r_enable_chip_interrupts(struct esas2r_adapter *a)
1321 {
1322     if (atomic_dec_return(&a->dis_ints_cnt) == 0)
1323         esas2r_write_register_dword(a, MU_INT_MASK_OUT,
1324                         ESAS2R_INT_ENB_MASK);
1325 }
1326 
1327 /* Schedule a TASKLET to perform non-interrupt tasks that may require delays
1328  * or long completion times.
1329  */
1330 static inline void esas2r_schedule_tasklet(struct esas2r_adapter *a)
1331 {
1332     /* make sure we don't schedule twice */
1333     if (!test_and_set_bit(AF_TASKLET_SCHEDULED, &a->flags))
1334         tasklet_hi_schedule(&a->tasklet);
1335 }
1336 
1337 static inline void esas2r_enable_heartbeat(struct esas2r_adapter *a)
1338 {
1339     if (!test_bit(AF_DEGRADED_MODE, &a->flags) &&
1340         !test_bit(AF_CHPRST_PENDING, &a->flags) &&
1341         (a->nvram->options2 & SASNVR2_HEARTBEAT))
1342         set_bit(AF_HEARTBEAT_ENB, &a->flags);
1343     else
1344         clear_bit(AF_HEARTBEAT_ENB, &a->flags);
1345 }
1346 
1347 static inline void esas2r_disable_heartbeat(struct esas2r_adapter *a)
1348 {
1349     clear_bit(AF_HEARTBEAT_ENB, &a->flags);
1350     clear_bit(AF_HEARTBEAT, &a->flags);
1351 }
1352 
1353 /* Set the initial state for resetting the adapter on the next pass through
1354  * esas2r_do_deferred.
1355  */
1356 static inline void esas2r_local_reset_adapter(struct esas2r_adapter *a)
1357 {
1358     esas2r_disable_heartbeat(a);
1359 
1360     set_bit(AF_CHPRST_NEEDED, &a->flags);
1361     set_bit(AF_CHPRST_PENDING, &a->flags);
1362     set_bit(AF_DISC_PENDING, &a->flags);
1363 }
1364 
1365 /* See if an interrupt is pending on the adapter. */
1366 static inline bool esas2r_adapter_interrupt_pending(struct esas2r_adapter *a)
1367 {
1368     u32 intstat;
1369 
1370     if (a->int_mask == 0)
1371         return false;
1372 
1373     intstat = esas2r_read_register_dword(a, MU_INT_STATUS_OUT);
1374 
1375     if ((intstat & a->int_mask) == 0)
1376         return false;
1377 
1378     esas2r_disable_chip_interrupts(a);
1379 
1380     a->int_stat = intstat;
1381     a->int_mask = 0;
1382 
1383     return true;
1384 }
1385 
1386 static inline u16 esas2r_targ_get_id(struct esas2r_target *t,
1387                      struct esas2r_adapter *a)
1388 {
1389     return (u16)(uintptr_t)(t - a->targetdb);
1390 }
1391 
1392 /*  Build and start an asynchronous event request */
1393 static inline void esas2r_start_ae_request(struct esas2r_adapter *a,
1394                        struct esas2r_request *rq)
1395 {
1396     unsigned long flags;
1397 
1398     esas2r_build_ae_req(a, rq);
1399 
1400     spin_lock_irqsave(&a->queue_lock, flags);
1401     esas2r_start_vda_request(a, rq);
1402     spin_unlock_irqrestore(&a->queue_lock, flags);
1403 }
1404 
1405 static inline void esas2r_comp_list_drain(struct esas2r_adapter *a,
1406                       struct list_head *comp_list)
1407 {
1408     struct esas2r_request *rq;
1409     struct list_head *element, *next;
1410 
1411     list_for_each_safe(element, next, comp_list) {
1412         rq = list_entry(element, struct esas2r_request, comp_list);
1413         list_del_init(element);
1414         esas2r_complete_request(a, rq);
1415     }
1416 }
1417 
1418 /* sysfs handlers */
1419 extern struct bin_attribute bin_attr_fw;
1420 extern struct bin_attribute bin_attr_fs;
1421 extern struct bin_attribute bin_attr_vda;
1422 extern struct bin_attribute bin_attr_hw;
1423 extern struct bin_attribute bin_attr_live_nvram;
1424 extern struct bin_attribute bin_attr_default_nvram;
1425 
1426 #endif /* ESAS2R_H */
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