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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 2021 Broadcom. All Rights Reserved. The term
0004  * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.
0005  */
0006 
0007 #ifndef _EFCT_HW_H
0008 #define _EFCT_HW_H
0009 
0010 #include "../libefc_sli/sli4.h"
0011 
0012 /*
0013  * EFCT PCI IDs
0014  */
0015 #define EFCT_VENDOR_ID          0x10df
0016 /* LightPulse 16Gb x 4 FC (lancer-g6) */
0017 #define EFCT_DEVICE_LANCER_G6       0xe307
0018 /* LightPulse 32Gb x 4 FC (lancer-g7) */
0019 #define EFCT_DEVICE_LANCER_G7       0xf407
0020 
0021 /*Default RQ entries len used by driver*/
0022 #define EFCT_HW_RQ_ENTRIES_MIN      512
0023 #define EFCT_HW_RQ_ENTRIES_DEF      1024
0024 #define EFCT_HW_RQ_ENTRIES_MAX      4096
0025 
0026 /*Defines the size of the RQ buffers used for each RQ*/
0027 #define EFCT_HW_RQ_SIZE_HDR             128
0028 #define EFCT_HW_RQ_SIZE_PAYLOAD         1024
0029 
0030 /*Define the maximum number of multi-receive queues*/
0031 #define EFCT_HW_MAX_MRQS        8
0032 
0033 /*
0034  * Define count of when to set the WQEC bit in a submitted
0035  * WQE, causing a consummed/released completion to be posted.
0036  */
0037 #define EFCT_HW_WQEC_SET_COUNT      32
0038 
0039 /*Send frame timeout in seconds*/
0040 #define EFCT_HW_SEND_FRAME_TIMEOUT  10
0041 
0042 /*
0043  * FDT Transfer Hint value, reads greater than this value
0044  * will be segmented to implement fairness. A value of zero disables
0045  * the feature.
0046  */
0047 #define EFCT_HW_FDT_XFER_HINT       8192
0048 
0049 #define EFCT_HW_TIMECHECK_ITERATIONS    100
0050 #define EFCT_HW_MAX_NUM_MQ      1
0051 #define EFCT_HW_MAX_NUM_RQ      32
0052 #define EFCT_HW_MAX_NUM_EQ      16
0053 #define EFCT_HW_MAX_NUM_WQ      32
0054 #define EFCT_HW_DEF_NUM_EQ      1
0055 
0056 #define OCE_HW_MAX_NUM_MRQ_PAIRS    16
0057 
0058 #define EFCT_HW_MQ_DEPTH        128
0059 #define EFCT_HW_EQ_DEPTH        1024
0060 
0061 /*
0062  * A CQ will be assinged to each WQ
0063  * (CQ must have 2X entries of the WQ for abort
0064  * processing), plus a separate one for each RQ PAIR and one for MQ
0065  */
0066 #define EFCT_HW_MAX_NUM_CQ \
0067     ((EFCT_HW_MAX_NUM_WQ * 2) + 1 + (OCE_HW_MAX_NUM_MRQ_PAIRS * 2))
0068 
0069 #define EFCT_HW_Q_HASH_SIZE     128
0070 #define EFCT_HW_RQ_HEADER_SIZE      128
0071 #define EFCT_HW_RQ_HEADER_INDEX     0
0072 
0073 #define EFCT_HW_REQUE_XRI_REGTAG    65534
0074 
0075 /* Options for efct_hw_command() */
0076 enum efct_cmd_opts {
0077     /* command executes synchronously and busy-waits for completion */
0078     EFCT_CMD_POLL,
0079     /* command executes asynchronously. Uses callback */
0080     EFCT_CMD_NOWAIT,
0081 };
0082 
0083 enum efct_hw_reset {
0084     EFCT_HW_RESET_FUNCTION,
0085     EFCT_HW_RESET_FIRMWARE,
0086     EFCT_HW_RESET_MAX
0087 };
0088 
0089 enum efct_hw_topo {
0090     EFCT_HW_TOPOLOGY_AUTO,
0091     EFCT_HW_TOPOLOGY_NPORT,
0092     EFCT_HW_TOPOLOGY_LOOP,
0093     EFCT_HW_TOPOLOGY_NONE,
0094     EFCT_HW_TOPOLOGY_MAX
0095 };
0096 
0097 /* pack fw revision values into a single uint64_t */
0098 #define HW_FWREV(a, b, c, d) (((uint64_t)(a) << 48) | ((uint64_t)(b) << 32) \
0099             | ((uint64_t)(c) << 16) | ((uint64_t)(d)))
0100 
0101 #define EFCT_FW_VER_STR(a, b, c, d) (#a "." #b "." #c "." #d)
0102 
0103 enum efct_hw_io_type {
0104     EFCT_HW_ELS_REQ,
0105     EFCT_HW_ELS_RSP,
0106     EFCT_HW_FC_CT,
0107     EFCT_HW_FC_CT_RSP,
0108     EFCT_HW_BLS_ACC,
0109     EFCT_HW_BLS_RJT,
0110     EFCT_HW_IO_TARGET_READ,
0111     EFCT_HW_IO_TARGET_WRITE,
0112     EFCT_HW_IO_TARGET_RSP,
0113     EFCT_HW_IO_DNRX_REQUEUE,
0114     EFCT_HW_IO_MAX,
0115 };
0116 
0117 enum efct_hw_io_state {
0118     EFCT_HW_IO_STATE_FREE,
0119     EFCT_HW_IO_STATE_INUSE,
0120     EFCT_HW_IO_STATE_WAIT_FREE,
0121     EFCT_HW_IO_STATE_WAIT_SEC_HIO,
0122 };
0123 
0124 #define EFCT_TARGET_WRITE_SKIPS 1
0125 #define EFCT_TARGET_READ_SKIPS  2
0126 
0127 struct efct_hw;
0128 struct efct_io;
0129 
0130 #define EFCT_CMD_CTX_POOL_SZ    32
0131 /**
0132  * HW command context.
0133  * Stores the state for the asynchronous commands sent to the hardware.
0134  */
0135 struct efct_command_ctx {
0136     struct list_head    list_entry;
0137     int (*cb)(struct efct_hw *hw, int status, u8 *mqe, void *arg);
0138     void            *arg;   /* Argument for callback */
0139     /* buffer holding command / results */
0140     u8          buf[SLI4_BMBX_SIZE];
0141     void            *ctx;   /* upper layer context */
0142 };
0143 
0144 struct efct_hw_sgl {
0145     uintptr_t       addr;
0146     size_t          len;
0147 };
0148 
0149 union efct_hw_io_param_u {
0150     struct sli_bls_params bls;
0151     struct sli_els_params els;
0152     struct sli_ct_params fc_ct;
0153     struct sli_fcp_tgt_params fcp_tgt;
0154 };
0155 
0156 /* WQ steering mode */
0157 enum efct_hw_wq_steering {
0158     EFCT_HW_WQ_STEERING_CLASS,
0159     EFCT_HW_WQ_STEERING_REQUEST,
0160     EFCT_HW_WQ_STEERING_CPU,
0161 };
0162 
0163 /* HW wqe object */
0164 struct efct_hw_wqe {
0165     struct list_head    list_entry;
0166     bool            abort_wqe_submit_needed;
0167     bool            send_abts;
0168     u32         id;
0169     u32         abort_reqtag;
0170     u8          *wqebuf;
0171 };
0172 
0173 struct efct_hw_io;
0174 /* Typedef for HW "done" callback */
0175 typedef int (*efct_hw_done_t)(struct efct_hw_io *, u32 len, int status,
0176                   u32 ext, void *ul_arg);
0177 
0178 /**
0179  * HW IO object.
0180  *
0181  * Stores the per-IO information necessary
0182  * for both SLI and efct.
0183  * @ref:        reference counter for hw io object
0184  * @state:      state of IO: free, busy, wait_free
0185  * @list_entry      used for busy, wait_free, free lists
0186  * @wqe         Work queue object, with link for pending
0187  * @hw          pointer back to hardware context
0188  * @xfer_rdy        transfer ready data
0189  * @type        IO type
0190  * @xbusy       Exchange is active in FW
0191  * @abort_in_progress   if TRUE, abort is in progress
0192  * @status_saved    if TRUE, latched status should be returned
0193  * @wq_class        WQ class if steering mode is Class
0194  * @reqtag      request tag for this HW IO
0195  * @wq          WQ assigned to the exchange
0196  * @done        Function called on IO completion
0197  * @arg         argument passed to IO done callback
0198  * @abort_done      Function called on abort completion
0199  * @abort_arg       argument passed to abort done callback
0200  * @wq_steering     WQ steering mode request
0201  * @saved_status    Saved status
0202  * @saved_len       Status length
0203  * @saved_ext       Saved extended status
0204  * @eq          EQ on which this HIO came up
0205  * @sge_offset      SGE data offset
0206  * @def_sgl_count   Count of SGEs in default SGL
0207  * @abort_reqtag    request tag for an abort of this HW IO
0208  * @indicator       Exchange indicator
0209  * @def_sgl     default SGL
0210  * @sgl         pointer to current active SGL
0211  * @sgl_count       count of SGEs in io->sgl
0212  * @first_data_sge  index of first data SGE
0213  * @n_sge       number of active SGEs
0214  */
0215 struct efct_hw_io {
0216     struct kref     ref;
0217     enum efct_hw_io_state   state;
0218     void            (*release)(struct kref *arg);
0219     struct list_head    list_entry;
0220     struct efct_hw_wqe  wqe;
0221 
0222     struct efct_hw      *hw;
0223     struct efc_dma      xfer_rdy;
0224     u16         type;
0225     bool            xbusy;
0226     int         abort_in_progress;
0227     bool            status_saved;
0228     u8          wq_class;
0229     u16         reqtag;
0230 
0231     struct hw_wq        *wq;
0232     efct_hw_done_t      done;
0233     void            *arg;
0234     efct_hw_done_t      abort_done;
0235     void            *abort_arg;
0236 
0237     enum efct_hw_wq_steering wq_steering;
0238 
0239     u32         saved_status;
0240     u32         saved_len;
0241     u32         saved_ext;
0242 
0243     struct hw_eq        *eq;
0244     u32         sge_offset;
0245     u32         def_sgl_count;
0246     u32         abort_reqtag;
0247     u32         indicator;
0248     struct efc_dma      def_sgl;
0249     struct efc_dma      *sgl;
0250     u32         sgl_count;
0251     u32         first_data_sge;
0252     u32         n_sge;
0253 };
0254 
0255 enum efct_hw_port {
0256     EFCT_HW_PORT_INIT,
0257     EFCT_HW_PORT_SHUTDOWN,
0258 };
0259 
0260 /* Node group rpi reference */
0261 struct efct_hw_rpi_ref {
0262     atomic_t rpi_count;
0263     atomic_t rpi_attached;
0264 };
0265 
0266 enum efct_hw_link_stat {
0267     EFCT_HW_LINK_STAT_LINK_FAILURE_COUNT,
0268     EFCT_HW_LINK_STAT_LOSS_OF_SYNC_COUNT,
0269     EFCT_HW_LINK_STAT_LOSS_OF_SIGNAL_COUNT,
0270     EFCT_HW_LINK_STAT_PRIMITIVE_SEQ_COUNT,
0271     EFCT_HW_LINK_STAT_INVALID_XMIT_WORD_COUNT,
0272     EFCT_HW_LINK_STAT_CRC_COUNT,
0273     EFCT_HW_LINK_STAT_PRIMITIVE_SEQ_TIMEOUT_COUNT,
0274     EFCT_HW_LINK_STAT_ELASTIC_BUFFER_OVERRUN_COUNT,
0275     EFCT_HW_LINK_STAT_ARB_TIMEOUT_COUNT,
0276     EFCT_HW_LINK_STAT_ADVERTISED_RCV_B2B_CREDIT,
0277     EFCT_HW_LINK_STAT_CURR_RCV_B2B_CREDIT,
0278     EFCT_HW_LINK_STAT_ADVERTISED_XMIT_B2B_CREDIT,
0279     EFCT_HW_LINK_STAT_CURR_XMIT_B2B_CREDIT,
0280     EFCT_HW_LINK_STAT_RCV_EOFA_COUNT,
0281     EFCT_HW_LINK_STAT_RCV_EOFDTI_COUNT,
0282     EFCT_HW_LINK_STAT_RCV_EOFNI_COUNT,
0283     EFCT_HW_LINK_STAT_RCV_SOFF_COUNT,
0284     EFCT_HW_LINK_STAT_RCV_DROPPED_NO_AER_COUNT,
0285     EFCT_HW_LINK_STAT_RCV_DROPPED_NO_RPI_COUNT,
0286     EFCT_HW_LINK_STAT_RCV_DROPPED_NO_XRI_COUNT,
0287     EFCT_HW_LINK_STAT_MAX,
0288 };
0289 
0290 enum efct_hw_host_stat {
0291     EFCT_HW_HOST_STAT_TX_KBYTE_COUNT,
0292     EFCT_HW_HOST_STAT_RX_KBYTE_COUNT,
0293     EFCT_HW_HOST_STAT_TX_FRAME_COUNT,
0294     EFCT_HW_HOST_STAT_RX_FRAME_COUNT,
0295     EFCT_HW_HOST_STAT_TX_SEQ_COUNT,
0296     EFCT_HW_HOST_STAT_RX_SEQ_COUNT,
0297     EFCT_HW_HOST_STAT_TOTAL_EXCH_ORIG,
0298     EFCT_HW_HOST_STAT_TOTAL_EXCH_RESP,
0299     EFCT_HW_HOSY_STAT_RX_P_BSY_COUNT,
0300     EFCT_HW_HOST_STAT_RX_F_BSY_COUNT,
0301     EFCT_HW_HOST_STAT_DROP_FRM_DUE_TO_NO_RQ_BUF_COUNT,
0302     EFCT_HW_HOST_STAT_EMPTY_RQ_TIMEOUT_COUNT,
0303     EFCT_HW_HOST_STAT_DROP_FRM_DUE_TO_NO_XRI_COUNT,
0304     EFCT_HW_HOST_STAT_EMPTY_XRI_POOL_COUNT,
0305     EFCT_HW_HOST_STAT_MAX,
0306 };
0307 
0308 enum efct_hw_state {
0309     EFCT_HW_STATE_UNINITIALIZED,
0310     EFCT_HW_STATE_QUEUES_ALLOCATED,
0311     EFCT_HW_STATE_ACTIVE,
0312     EFCT_HW_STATE_RESET_IN_PROGRESS,
0313     EFCT_HW_STATE_TEARDOWN_IN_PROGRESS,
0314 };
0315 
0316 struct efct_hw_link_stat_counts {
0317     u8      overflow;
0318     u32     counter;
0319 };
0320 
0321 struct efct_hw_host_stat_counts {
0322     u32     counter;
0323 };
0324 
0325 /* Structure used for the hash lookup of queue IDs */
0326 struct efct_queue_hash {
0327     bool        in_use;
0328     u16     id;
0329     u16     index;
0330 };
0331 
0332 /* WQ callback object */
0333 struct hw_wq_callback {
0334     u16     instance_index; /* use for request tag */
0335     void (*callback)(void *arg, u8 *cqe, int status);
0336     void        *arg;
0337     struct list_head list_entry;
0338 };
0339 
0340 struct reqtag_pool {
0341     spinlock_t lock;    /* pool lock */
0342     struct hw_wq_callback *tags[U16_MAX];
0343     struct list_head freelist;
0344 };
0345 
0346 struct efct_hw_config {
0347     u32     n_eq;
0348     u32     n_cq;
0349     u32     n_mq;
0350     u32     n_rq;
0351     u32     n_wq;
0352     u32     n_io;
0353     u32     n_sgl;
0354     u32     speed;
0355     u32     topology;
0356     /* size of the buffers for first burst */
0357     u32     rq_default_buffer_size;
0358     u8      esoc;
0359     /* MRQ RQ selection policy */
0360     u8      rq_selection_policy;
0361     /* RQ quanta if rq_selection_policy == 2 */
0362     u8      rr_quanta;
0363     u32     filter_def[SLI4_CMD_REG_FCFI_NUM_RQ_CFG];
0364 };
0365 
0366 struct efct_hw {
0367     struct efct     *os;
0368     struct sli4     sli;
0369     u16         ulp_start;
0370     u16         ulp_max;
0371     u32         dump_size;
0372     enum efct_hw_state  state;
0373     bool            hw_setup_called;
0374     u8          sliport_healthcheck;
0375     u16         fcf_indicator;
0376 
0377     /* HW configuration */
0378     struct efct_hw_config   config;
0379 
0380     /* calculated queue sizes for each type */
0381     u32         num_qentries[SLI4_QTYPE_MAX];
0382 
0383     /* Storage for SLI queue objects */
0384     struct sli4_queue   wq[EFCT_HW_MAX_NUM_WQ];
0385     struct sli4_queue   rq[EFCT_HW_MAX_NUM_RQ];
0386     u16         hw_rq_lookup[EFCT_HW_MAX_NUM_RQ];
0387     struct sli4_queue   mq[EFCT_HW_MAX_NUM_MQ];
0388     struct sli4_queue   cq[EFCT_HW_MAX_NUM_CQ];
0389     struct sli4_queue   eq[EFCT_HW_MAX_NUM_EQ];
0390 
0391     /* HW queue */
0392     u32         eq_count;
0393     u32         cq_count;
0394     u32         mq_count;
0395     u32         wq_count;
0396     u32         rq_count;
0397     u32         cmd_head_count;
0398     struct list_head    eq_list;
0399 
0400     struct efct_queue_hash  cq_hash[EFCT_HW_Q_HASH_SIZE];
0401     struct efct_queue_hash  rq_hash[EFCT_HW_Q_HASH_SIZE];
0402     struct efct_queue_hash  wq_hash[EFCT_HW_Q_HASH_SIZE];
0403 
0404     /* Storage for HW queue objects */
0405     struct hw_wq        *hw_wq[EFCT_HW_MAX_NUM_WQ];
0406     struct hw_rq        *hw_rq[EFCT_HW_MAX_NUM_RQ];
0407     struct hw_mq        *hw_mq[EFCT_HW_MAX_NUM_MQ];
0408     struct hw_cq        *hw_cq[EFCT_HW_MAX_NUM_CQ];
0409     struct hw_eq        *hw_eq[EFCT_HW_MAX_NUM_EQ];
0410     /* count of hw_rq[] entries */
0411     u32         hw_rq_count;
0412     /* count of multirq RQs */
0413     u32         hw_mrq_count;
0414 
0415     struct hw_wq        **wq_cpu_array;
0416 
0417     /* Sequence objects used in incoming frame processing */
0418     struct efc_hw_sequence  *seq_pool;
0419 
0420     /* Maintain an ordered, linked list of outstanding HW commands. */
0421     struct mutex            bmbx_lock;
0422     spinlock_t      cmd_lock;
0423     struct list_head    cmd_head;
0424     struct list_head    cmd_pending;
0425     mempool_t       *cmd_ctx_pool;
0426     mempool_t       *mbox_rqst_pool;
0427 
0428     struct sli4_link_event  link;
0429 
0430     /* pointer array of IO objects */
0431     struct efct_hw_io   **io;
0432     /* array of WQE buffs mapped to IO objects */
0433     u8          *wqe_buffs;
0434 
0435     /* IO lock to synchronize list access */
0436     spinlock_t      io_lock;
0437     /* List of IO objects in use */
0438     struct list_head    io_inuse;
0439     /* List of IO objects waiting to be freed */
0440     struct list_head    io_wait_free;
0441     /* List of IO objects available for allocation */
0442     struct list_head    io_free;
0443 
0444     struct efc_dma      loop_map;
0445 
0446     struct efc_dma      xfer_rdy;
0447 
0448     struct efc_dma      rnode_mem;
0449 
0450     atomic_t        io_alloc_failed_count;
0451 
0452     /* stat: wq sumbit count */
0453     u32         tcmd_wq_submit[EFCT_HW_MAX_NUM_WQ];
0454     /* stat: wq complete count */
0455     u32         tcmd_wq_complete[EFCT_HW_MAX_NUM_WQ];
0456 
0457     atomic_t        send_frame_seq_id;
0458     struct reqtag_pool  *wq_reqtag_pool;
0459 };
0460 
0461 enum efct_hw_io_count_type {
0462     EFCT_HW_IO_INUSE_COUNT,
0463     EFCT_HW_IO_FREE_COUNT,
0464     EFCT_HW_IO_WAIT_FREE_COUNT,
0465     EFCT_HW_IO_N_TOTAL_IO_COUNT,
0466 };
0467 
0468 /* HW queue data structures */
0469 struct hw_eq {
0470     struct list_head    list_entry;
0471     enum sli4_qtype     type;
0472     u32         instance;
0473     u32         entry_count;
0474     u32         entry_size;
0475     struct efct_hw      *hw;
0476     struct sli4_queue   *queue;
0477     struct list_head    cq_list;
0478     u32         use_count;
0479 };
0480 
0481 struct hw_cq {
0482     struct list_head    list_entry;
0483     enum sli4_qtype     type;
0484     u32         instance;
0485     u32         entry_count;
0486     u32         entry_size;
0487     struct hw_eq        *eq;
0488     struct sli4_queue   *queue;
0489     struct list_head    q_list;
0490     u32         use_count;
0491 };
0492 
0493 struct hw_q {
0494     struct list_head    list_entry;
0495     enum sli4_qtype     type;
0496 };
0497 
0498 struct hw_mq {
0499     struct list_head    list_entry;
0500     enum sli4_qtype     type;
0501     u32         instance;
0502 
0503     u32         entry_count;
0504     u32         entry_size;
0505     struct hw_cq        *cq;
0506     struct sli4_queue   *queue;
0507 
0508     u32         use_count;
0509 };
0510 
0511 struct hw_wq {
0512     struct list_head    list_entry;
0513     enum sli4_qtype     type;
0514     u32         instance;
0515     struct efct_hw      *hw;
0516 
0517     u32         entry_count;
0518     u32         entry_size;
0519     struct hw_cq        *cq;
0520     struct sli4_queue   *queue;
0521     u32         class;
0522 
0523     /* WQ consumed */
0524     u32         wqec_set_count;
0525     u32         wqec_count;
0526     u32         free_count;
0527     u32         total_submit_count;
0528     struct list_head    pending_list;
0529 
0530     /* HW IO allocated for use with Send Frame */
0531     struct efct_hw_io   *send_frame_io;
0532 
0533     /* Stats */
0534     u32         use_count;
0535     u32         wq_pending_count;
0536 };
0537 
0538 struct hw_rq {
0539     struct list_head    list_entry;
0540     enum sli4_qtype     type;
0541     u32         instance;
0542 
0543     u32         entry_count;
0544     u32         use_count;
0545     u32         hdr_entry_size;
0546     u32         first_burst_entry_size;
0547     u32         data_entry_size;
0548     bool            is_mrq;
0549     u32         base_mrq_id;
0550 
0551     struct hw_cq        *cq;
0552 
0553     u8          filter_mask;
0554     struct sli4_queue   *hdr;
0555     struct sli4_queue   *first_burst;
0556     struct sli4_queue   *data;
0557 
0558     struct efc_hw_rq_buffer *hdr_buf;
0559     struct efc_hw_rq_buffer *fb_buf;
0560     struct efc_hw_rq_buffer *payload_buf;
0561     /* RQ tracker for this RQ */
0562     struct efc_hw_sequence  **rq_tracker;
0563 };
0564 
0565 struct efct_hw_send_frame_context {
0566     struct efct_hw      *hw;
0567     struct hw_wq_callback   *wqcb;
0568     struct efct_hw_wqe  wqe;
0569     void (*callback)(int status, void *arg);
0570     void            *arg;
0571 
0572     /* General purpose elements */
0573     struct efc_hw_sequence  *seq;
0574     struct efc_dma      payload;
0575 };
0576 
0577 struct efct_hw_grp_hdr {
0578     u32         size;
0579     __be32          magic_number;
0580     u32         word2;
0581     u8          rev_name[128];
0582     u8          date[12];
0583     u8          revision[32];
0584 };
0585 
0586 static inline int
0587 efct_hw_get_link_speed(struct efct_hw *hw) {
0588     return hw->link.speed;
0589 }
0590 
0591 int
0592 efct_hw_setup(struct efct_hw *hw, void *os, struct pci_dev *pdev);
0593 int efct_hw_init(struct efct_hw *hw);
0594 int
0595 efct_hw_parse_filter(struct efct_hw *hw, void *value);
0596 int
0597 efct_hw_init_queues(struct efct_hw *hw);
0598 int
0599 efct_hw_map_wq_cpu(struct efct_hw *hw);
0600 uint64_t
0601 efct_get_wwnn(struct efct_hw *hw);
0602 uint64_t
0603 efct_get_wwpn(struct efct_hw *hw);
0604 
0605 int efct_hw_rx_allocate(struct efct_hw *hw);
0606 int efct_hw_rx_post(struct efct_hw *hw);
0607 void efct_hw_rx_free(struct efct_hw *hw);
0608 int
0609 efct_hw_command(struct efct_hw *hw, u8 *cmd, u32 opts, void *cb,
0610         void *arg);
0611 int
0612 efct_issue_mbox_rqst(void *base, void *cmd, void *cb, void *arg);
0613 
0614 struct efct_hw_io *efct_hw_io_alloc(struct efct_hw *hw);
0615 int efct_hw_io_free(struct efct_hw *hw, struct efct_hw_io *io);
0616 u8 efct_hw_io_inuse(struct efct_hw *hw, struct efct_hw_io *io);
0617 int
0618 efct_hw_io_send(struct efct_hw *hw, enum efct_hw_io_type type,
0619         struct efct_hw_io *io, union efct_hw_io_param_u *iparam,
0620         void *cb, void *arg);
0621 int
0622 efct_hw_io_register_sgl(struct efct_hw *hw, struct efct_hw_io *io,
0623             struct efc_dma *sgl,
0624             u32 sgl_count);
0625 int
0626 efct_hw_io_init_sges(struct efct_hw *hw,
0627              struct efct_hw_io *io, enum efct_hw_io_type type);
0628 
0629 int
0630 efct_hw_io_add_sge(struct efct_hw *hw, struct efct_hw_io *io,
0631            uintptr_t addr, u32 length);
0632 int
0633 efct_hw_io_abort(struct efct_hw *hw, struct efct_hw_io *io_to_abort,
0634          bool send_abts, void *cb, void *arg);
0635 u32
0636 efct_hw_io_get_count(struct efct_hw *hw,
0637              enum efct_hw_io_count_type io_count_type);
0638 struct efct_hw_io
0639 *efct_hw_io_lookup(struct efct_hw *hw, u32 indicator);
0640 void efct_hw_io_abort_all(struct efct_hw *hw);
0641 void efct_hw_io_free_internal(struct kref *arg);
0642 
0643 /* HW WQ request tag API */
0644 struct reqtag_pool *efct_hw_reqtag_pool_alloc(struct efct_hw *hw);
0645 void efct_hw_reqtag_pool_free(struct efct_hw *hw);
0646 struct hw_wq_callback
0647 *efct_hw_reqtag_alloc(struct efct_hw *hw,
0648             void (*callback)(void *arg, u8 *cqe,
0649                      int status), void *arg);
0650 void
0651 efct_hw_reqtag_free(struct efct_hw *hw, struct hw_wq_callback *wqcb);
0652 struct hw_wq_callback
0653 *efct_hw_reqtag_get_instance(struct efct_hw *hw, u32 instance_index);
0654 
0655 /* RQ completion handlers for RQ pair mode */
0656 int
0657 efct_hw_rqpair_process_rq(struct efct_hw *hw,
0658               struct hw_cq *cq, u8 *cqe);
0659 int
0660 efct_hw_rqpair_sequence_free(struct efct_hw *hw, struct efc_hw_sequence *seq);
0661 static inline void
0662 efct_hw_sequence_copy(struct efc_hw_sequence *dst,
0663               struct efc_hw_sequence *src)
0664 {
0665     /* Copy src to dst, then zero out the linked list link */
0666     *dst = *src;
0667 }
0668 
0669 int
0670 efct_efc_hw_sequence_free(struct efc *efc, struct efc_hw_sequence *seq);
0671 
0672 static inline int
0673 efct_hw_sequence_free(struct efct_hw *hw, struct efc_hw_sequence *seq)
0674 {
0675     /* Only RQ pair mode is supported */
0676     return efct_hw_rqpair_sequence_free(hw, seq);
0677 }
0678 
0679 int
0680 efct_hw_eq_process(struct efct_hw *hw, struct hw_eq *eq,
0681            u32 max_isr_time_msec);
0682 void efct_hw_cq_process(struct efct_hw *hw, struct hw_cq *cq);
0683 void
0684 efct_hw_wq_process(struct efct_hw *hw, struct hw_cq *cq,
0685            u8 *cqe, int status, u16 rid);
0686 void
0687 efct_hw_xabt_process(struct efct_hw *hw, struct hw_cq *cq,
0688              u8 *cqe, u16 rid);
0689 int
0690 efct_hw_process(struct efct_hw *hw, u32 vector, u32 max_isr_time_msec);
0691 int
0692 efct_hw_queue_hash_find(struct efct_queue_hash *hash, u16 id);
0693 int efct_hw_wq_write(struct hw_wq *wq, struct efct_hw_wqe *wqe);
0694 int
0695 efct_hw_send_frame(struct efct_hw *hw, struct fc_frame_header *hdr,
0696            u8 sof, u8 eof, struct efc_dma *payload,
0697         struct efct_hw_send_frame_context *ctx,
0698         void (*callback)(void *arg, u8 *cqe, int status),
0699         void *arg);
0700 int
0701 efct_els_hw_srrs_send(struct efc *efc, struct efc_disc_io *io);
0702 int
0703 efct_efc_bls_send(struct efc *efc, u32 type, struct sli_bls_params *bls);
0704 int
0705 efct_hw_bls_send(struct efct *efct, u32 type, struct sli_bls_params *bls_params,
0706          void *cb, void *arg);
0707 
0708 /* Function for retrieving link statistics */
0709 int
0710 efct_hw_get_link_stats(struct efct_hw *hw,
0711                u8 req_ext_counters,
0712                u8 clear_overflow_flags,
0713                u8 clear_all_counters,
0714                void (*efct_hw_link_stat_cb_t)(int status,
0715                               u32 num_counters,
0716                struct efct_hw_link_stat_counts *counters, void *arg),
0717                void *arg);
0718 /* Function for retrieving host statistics */
0719 int
0720 efct_hw_get_host_stats(struct efct_hw *hw,
0721                u8 cc,
0722                void (*efct_hw_host_stat_cb_t)(int status,
0723                               u32 num_counters,
0724                struct efct_hw_host_stat_counts *counters, void *arg),
0725                void *arg);
0726 int
0727 efct_hw_firmware_write(struct efct_hw *hw, struct efc_dma *dma,
0728                u32 size, u32 offset, int last,
0729                void (*cb)(int status, u32 bytes_written,
0730                   u32 change_status, void *arg),
0731                void *arg);
0732 typedef void (*efct_hw_async_cb_t)(struct efct_hw *hw, int status,
0733                   u8 *mqe, void *arg);
0734 int
0735 efct_hw_async_call(struct efct_hw *hw, efct_hw_async_cb_t callback, void *arg);
0736 
0737 struct hw_eq *efct_hw_new_eq(struct efct_hw *hw, u32 entry_count);
0738 struct hw_cq *efct_hw_new_cq(struct hw_eq *eq, u32 entry_count);
0739 u32
0740 efct_hw_new_cq_set(struct hw_eq *eqs[], struct hw_cq *cqs[],
0741            u32 num_cqs, u32 entry_count);
0742 struct hw_mq *efct_hw_new_mq(struct hw_cq *cq, u32 entry_count);
0743 struct hw_wq
0744 *efct_hw_new_wq(struct hw_cq *cq, u32 entry_count);
0745 u32
0746 efct_hw_new_rq_set(struct hw_cq *cqs[], struct hw_rq *rqs[],
0747            u32 num_rq_pairs, u32 entry_count);
0748 void efct_hw_del_eq(struct hw_eq *eq);
0749 void efct_hw_del_cq(struct hw_cq *cq);
0750 void efct_hw_del_mq(struct hw_mq *mq);
0751 void efct_hw_del_wq(struct hw_wq *wq);
0752 void efct_hw_del_rq(struct hw_rq *rq);
0753 void efct_hw_queue_teardown(struct efct_hw *hw);
0754 void efct_hw_teardown(struct efct_hw *hw);
0755 int
0756 efct_hw_reset(struct efct_hw *hw, enum efct_hw_reset reset);
0757 
0758 int
0759 efct_hw_port_control(struct efct_hw *hw, enum efct_hw_port ctrl,
0760              uintptr_t value,
0761         void (*cb)(int status, uintptr_t value, void *arg),
0762         void *arg);
0763 
0764 #endif /* __EFCT_H__ */
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