scsi/cxlflash/ocxl_hw.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * CXL Flash Device Driver
0004  *
0005  * Written by: Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
0006  *         Uma Krishnan <ukrishn@linux.vnet.ibm.com>, IBM Corporation
0007  *
0008  * Copyright (C) 2018 IBM Corporation
0009  */
0010
0011 #define OCXL_MAX_IRQS   4   /* Max interrupts per process */
0012
0013 struct ocxlflash_irqs {
0014     int hwirq;
0015     u32 virq;
0016     void __iomem *vtrig;
0017 };
0018
0019 /* OCXL hardware AFU associated with the host */
0020 struct ocxl_hw_afu {
0021     struct ocxlflash_context *ocxl_ctx; /* Host context */
0022     struct pci_dev *pdev;       /* PCI device */
0023     struct device *dev;     /* Generic device */
0024     bool perst_same_image;      /* Same image loaded on perst */
0025
0026     struct ocxl_fn_config fcfg; /* DVSEC config of the function */
0027     struct ocxl_afu_config acfg;    /* AFU configuration data */
0028
0029     int fn_actag_base;      /* Function acTag base */
0030     int fn_actag_enabled;       /* Function acTag number enabled */
0031     int afu_actag_base;     /* AFU acTag base */
0032     int afu_actag_enabled;      /* AFU acTag number enabled */
0033
0034     phys_addr_t ppmmio_phys;    /* Per process MMIO space */
0035     phys_addr_t gmmio_phys;     /* Global AFU MMIO space */
0036     void __iomem *gmmio_virt;   /* Global MMIO map */
0037
0038     void *link_token;       /* Link token for the SPA */
0039     struct idr idr;         /* IDR to manage contexts */
0040     int max_pasid;          /* Maximum number of contexts */
0041     bool is_present;        /* Function has AFUs defined */
0042 };
0043
0044 enum ocxlflash_ctx_state {
0045     CLOSED,
0046     OPENED,
0047     STARTED
0048 };
0049
0050 struct ocxlflash_context {
0051     struct ocxl_hw_afu *hw_afu; /* HW AFU back pointer */
0052     struct address_space *mapping;  /* Mapping for pseudo filesystem */
0053     bool master;            /* Whether this is a master context */
0054     int pe;             /* Process element */
0055
0056     phys_addr_t psn_phys;       /* Process mapping */
0057     u64 psn_size;           /* Process mapping size */
0058
0059     spinlock_t slock;       /* Protects irq/fault/event updates */
0060     wait_queue_head_t wq;       /* Wait queue for poll and interrupts */
0061     struct mutex state_mutex;   /* Mutex to update context state */
0062     enum ocxlflash_ctx_state state; /* Context state */
0063
0064     struct ocxlflash_irqs *irqs;    /* Pointer to array of structures */
0065     int num_irqs;           /* Number of interrupts */
0066     bool pending_irq;       /* Pending interrupt on the context */
0067     ulong irq_bitmap;       /* Bits indicating pending irq num */
0068
0069     u64 fault_addr;         /* Address that triggered the fault */
0070     u64 fault_dsisr;        /* Value of dsisr register at fault */
0071     bool pending_fault;     /* Pending translation fault */
0072 };