scsi/cxlflash/main.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * CXL Flash Device Driver
0004  *
0005  * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation
0006  *             Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
0007  *
0008  * Copyright (C) 2015 IBM Corporation
0009  */
0010
0011 #ifndef _CXLFLASH_MAIN_H
0012 #define _CXLFLASH_MAIN_H
0013
0014 #include <linux/list.h>
0015 #include <linux/types.h>
0016 #include <scsi/scsi.h>
0017 #include <scsi/scsi_device.h>
0018
0019 #include "backend.h"
0020
0021 #define CXLFLASH_NAME       "cxlflash"
0022 #define CXLFLASH_ADAPTER_NAME   "IBM POWER CXL Flash Adapter"
0023 #define CXLFLASH_MAX_ADAPTERS   32
0024
0025 #define PCI_DEVICE_ID_IBM_CORSA     0x04F0
0026 #define PCI_DEVICE_ID_IBM_FLASH_GT  0x0600
0027 #define PCI_DEVICE_ID_IBM_BRIARD    0x0624
0028
0029 /* Since there is only one target, make it 0 */
0030 #define CXLFLASH_TARGET     0
0031 #define CXLFLASH_MAX_CDB_LEN    16
0032
0033 /* Really only one target per bus since the Texan is directly attached */
0034 #define CXLFLASH_MAX_NUM_TARGETS_PER_BUS    1
0035 #define CXLFLASH_MAX_NUM_LUNS_PER_TARGET    65536
0036
0037 #define CXLFLASH_PCI_ERROR_RECOVERY_TIMEOUT (120 * HZ)
0038
0039 /* FC defines */
0040 #define FC_MTIP_CMDCONFIG 0x010
0041 #define FC_MTIP_STATUS 0x018
0042 #define FC_MAX_NUM_LUNS 0x080 /* Max LUNs host can provision for port */
0043 #define FC_CUR_NUM_LUNS 0x088 /* Cur number LUNs provisioned for port */
0044 #define FC_MAX_CAP_PORT 0x090 /* Max capacity all LUNs for port (4K blocks) */
0045 #define FC_CUR_CAP_PORT 0x098 /* Cur capacity all LUNs for port (4K blocks) */
0046
0047 #define FC_PNAME 0x300
0048 #define FC_CONFIG 0x320
0049 #define FC_CONFIG2 0x328
0050 #define FC_STATUS 0x330
0051 #define FC_ERROR 0x380
0052 #define FC_ERRCAP 0x388
0053 #define FC_ERRMSK 0x390
0054 #define FC_CNT_CRCERR 0x538
0055 #define FC_CRC_THRESH 0x580
0056
0057 #define FC_MTIP_CMDCONFIG_ONLINE    0x20ULL
0058 #define FC_MTIP_CMDCONFIG_OFFLINE   0x40ULL
0059
0060 #define FC_MTIP_STATUS_MASK     0x30ULL
0061 #define FC_MTIP_STATUS_ONLINE       0x20ULL
0062 #define FC_MTIP_STATUS_OFFLINE      0x10ULL
0063
0064 /* TIMEOUT and RETRY definitions */
0065
0066 /* AFU command timeout values */
0067 #define MC_AFU_SYNC_TIMEOUT 5   /* 5 secs */
0068 #define MC_LUN_PROV_TIMEOUT 5   /* 5 secs */
0069 #define MC_AFU_DEBUG_TIMEOUT    5   /* 5 secs */
0070
0071 /* AFU command room retry limit */
0072 #define MC_ROOM_RETRY_CNT   10
0073
0074 /* FC CRC clear periodic timer */
0075 #define MC_CRC_THRESH 100   /* threshold in 5 mins */
0076
0077 #define FC_PORT_STATUS_RETRY_CNT 100    /* 100 100ms retries = 10 seconds */
0078 #define FC_PORT_STATUS_RETRY_INTERVAL_US 100000 /* microseconds */
0079
0080 /* VPD defines */
0081 #define CXLFLASH_VPD_LEN    256
0082 #define WWPN_LEN    16
0083 #define WWPN_BUF_LEN    (WWPN_LEN + 1)
0084
0085 enum undo_level {
0086     UNDO_NOOP = 0,
0087     FREE_IRQ,
0088     UNMAP_ONE,
0089     UNMAP_TWO,
0090     UNMAP_THREE
0091 };
0092
0093 struct dev_dependent_vals {
0094     u64 max_sectors;
0095     u64 flags;
0096 #define CXLFLASH_NOTIFY_SHUTDOWN    0x0000000000000001ULL
0097 #define CXLFLASH_WWPN_VPD_REQUIRED  0x0000000000000002ULL
0098 #define CXLFLASH_OCXL_DEV       0x0000000000000004ULL
0099 };
0100
0101 static inline const struct cxlflash_backend_ops *
0102 cxlflash_assign_ops(struct dev_dependent_vals *ddv)
0103 {
0104     const struct cxlflash_backend_ops *ops = NULL;
0105
0106 #ifdef CONFIG_OCXL_BASE
0107     if (ddv->flags & CXLFLASH_OCXL_DEV)
0108         ops = &cxlflash_ocxl_ops;
0109 #endif
0110
0111 #ifdef CONFIG_CXL_BASE
0112     if (!(ddv->flags & CXLFLASH_OCXL_DEV))
0113         ops = &cxlflash_cxl_ops;
0114 #endif
0115
0116     return ops;
0117 }
0118
0119 struct asyc_intr_info {
0120     u64 status;
0121     char *desc;
0122     u8 port;
0123     u8 action;
0124 #define CLR_FC_ERROR    0x01
0125 #define LINK_RESET  0x02
0126 #define SCAN_HOST   0x04
0127 };
0128
0129 #endif /* _CXLFLASH_MAIN_H */