scsi/csiostor/csio_hw_t5.c

0001 /*
0002  * This file is part of the Chelsio FCoE driver for Linux.
0003  *
0004  * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
0005  *
0006  * This software is available to you under a choice of one of two
0007  * licenses.  You may choose to be licensed under the terms of the GNU
0008  * General Public License (GPL) Version 2, available from the file
0009  * OpenIB.org BSD license below:
0010  *
0011  *     Redistribution and use in source and binary forms, with or
0012  *     without modification, are permitted provided that the following
0013  *     conditions are met:
0014  *
0015  *      - Redistributions of source code must retain the above
0016  *        copyright notice, this list of conditions and the following
0017  *        disclaimer.
0018  *
0019  *      - Redistributions in binary form must reproduce the above
0020  *        copyright notice, this list of conditions and the following
0021  *        disclaimer in the documentation and/or other materials
0022  *        provided with the distribution.
0023  *
0024  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0025  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0026  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0027  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0028  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0029  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0030  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0031  * SOFTWARE.
0032  */
0033
0034 #include "csio_hw.h"
0035 #include "csio_init.h"
0036
0037 static int
0038 csio_t5_set_mem_win(struct csio_hw *hw, uint32_t win)
0039 {
0040     u32 mem_win_base;
0041     /*
0042      * Truncation intentional: we only read the bottom 32-bits of the
0043      * 64-bit BAR0/BAR1 ...  We use the hardware backdoor mechanism to
0044      * read BAR0 instead of using pci_resource_start() because we could be
0045      * operating from within a Virtual Machine which is trapping our
0046      * accesses to our Configuration Space and we need to set up the PCI-E
0047      * Memory Window decoders with the actual addresses which will be
0048      * coming across the PCI-E link.
0049      */
0050
0051     /* For T5, only relative offset inside the PCIe BAR is passed */
0052     mem_win_base = MEMWIN_BASE;
0053
0054     /*
0055      * Set up memory window for accessing adapter memory ranges.  (Read
0056      * back MA register to ensure that changes propagate before we attempt
0057      * to use the new values.)
0058      */
0059     csio_wr_reg32(hw, mem_win_base | BIR_V(0) |
0060               WINDOW_V(ilog2(MEMWIN_APERTURE) - 10),
0061               PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
0062     csio_rd_reg32(hw,
0063               PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
0064
0065     return 0;
0066 }
0067
0068 /*
0069  * Interrupt handler for the PCIE module.
0070  */
0071 static void
0072 csio_t5_pcie_intr_handler(struct csio_hw *hw)
0073 {
0074     static struct intr_info pcie_intr_info[] = {
0075         { MSTGRPPERR_F, "Master Response Read Queue parity error",
0076         -1, 1 },
0077         { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
0078         { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
0079         { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
0080         { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
0081         { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
0082         { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
0083         { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
0084         -1, 1 },
0085         { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
0086         -1, 1 },
0087         { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
0088         { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
0089         { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
0090         { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
0091         { DREQWRPERR_F, "PCI DMA channel write request parity error",
0092         -1, 1 },
0093         { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
0094         { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
0095         { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
0096         { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
0097         { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
0098         { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
0099         { FIDPERR_F, "PCI FID parity error", -1, 1 },
0100         { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
0101         { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
0102         { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
0103         { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
0104         -1, 1 },
0105         { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
0106         -1, 1 },
0107         { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
0108         { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
0109         { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
0110         { READRSPERR_F, "Outbound read error", -1, 0 },
0111         { 0, NULL, 0, 0 }
0112     };
0113
0114     int fat;
0115     fat = csio_handle_intr_status(hw, PCIE_INT_CAUSE_A, pcie_intr_info);
0116     if (fat)
0117         csio_hw_fatal_err(hw);
0118 }
0119
0120 /*
0121  * csio_t5_flash_cfg_addr - return the address of the flash configuration file
0122  * @hw: the HW module
0123  *
0124  * Return the address within the flash where the Firmware Configuration
0125  * File is stored.
0126  */
0127 static unsigned int
0128 csio_t5_flash_cfg_addr(struct csio_hw *hw)
0129 {
0130     return FLASH_CFG_START;
0131 }
0132
0133 /*
0134  *      csio_t5_mc_read - read from MC through backdoor accesses
0135  *      @hw: the hw module
0136  *      @idx: index to the register
0137  *      @addr: address of first byte requested
0138  *      @data: 64 bytes of data containing the requested address
0139  *      @ecc: where to store the corresponding 64-bit ECC word
0140  *
0141  *      Read 64 bytes of data from MC starting at a 64-byte-aligned address
0142  *      that covers the requested address @addr.  If @parity is not %NULL it
0143  *      is assigned the 64-bit ECC word for the read data.
0144  */
0145 static int
0146 csio_t5_mc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data,
0147         uint64_t *ecc)
0148 {
0149     int i;
0150     uint32_t mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg;
0151     uint32_t mc_bist_data_pattern_reg;
0152
0153     mc_bist_cmd_reg = MC_REG(MC_P_BIST_CMD_A, idx);
0154     mc_bist_cmd_addr_reg = MC_REG(MC_P_BIST_CMD_ADDR_A, idx);
0155     mc_bist_cmd_len_reg = MC_REG(MC_P_BIST_CMD_LEN_A, idx);
0156     mc_bist_data_pattern_reg = MC_REG(MC_P_BIST_DATA_PATTERN_A, idx);
0157
0158     if (csio_rd_reg32(hw, mc_bist_cmd_reg) & START_BIST_F)
0159         return -EBUSY;
0160     csio_wr_reg32(hw, addr & ~0x3fU, mc_bist_cmd_addr_reg);
0161     csio_wr_reg32(hw, 64, mc_bist_cmd_len_reg);
0162     csio_wr_reg32(hw, 0xc, mc_bist_data_pattern_reg);
0163     csio_wr_reg32(hw, BIST_OPCODE_V(1) | START_BIST_F |  BIST_CMD_GAP_V(1),
0164               mc_bist_cmd_reg);
0165     i = csio_hw_wait_op_done_val(hw, mc_bist_cmd_reg, START_BIST_F,
0166                      0, 10, 1, NULL);
0167     if (i)
0168         return i;
0169
0170 #define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA_A, i)
0171
0172     for (i = 15; i >= 0; i--)
0173         *data++ = htonl(csio_rd_reg32(hw, MC_DATA(i)));
0174     if (ecc)
0175         *ecc = csio_rd_reg64(hw, MC_DATA(16));
0176 #undef MC_DATA
0177     return 0;
0178 }
0179
0180 /*
0181  *      csio_t5_edc_read - read from EDC through backdoor accesses
0182  *      @hw: the hw module
0183  *      @idx: which EDC to access
0184  *      @addr: address of first byte requested
0185  *      @data: 64 bytes of data containing the requested address
0186  *      @ecc: where to store the corresponding 64-bit ECC word
0187  *
0188  *      Read 64 bytes of data from EDC starting at a 64-byte-aligned address
0189  *      that covers the requested address @addr.  If @parity is not %NULL it
0190  *      is assigned the 64-bit ECC word for the read data.
0191  */
0192 static int
0193 csio_t5_edc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data,
0194         uint64_t *ecc)
0195 {
0196     int i;
0197     uint32_t edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg;
0198     uint32_t edc_bist_cmd_data_pattern;
0199
0200 /*
0201  * These macro are missing in t4_regs.h file.
0202  */
0203 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
0204 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
0205
0206     edc_bist_cmd_reg = EDC_REG_T5(EDC_H_BIST_CMD_A, idx);
0207     edc_bist_cmd_addr_reg = EDC_REG_T5(EDC_H_BIST_CMD_ADDR_A, idx);
0208     edc_bist_cmd_len_reg = EDC_REG_T5(EDC_H_BIST_CMD_LEN_A, idx);
0209     edc_bist_cmd_data_pattern = EDC_REG_T5(EDC_H_BIST_DATA_PATTERN_A, idx);
0210 #undef EDC_REG_T5
0211 #undef EDC_STRIDE_T5
0212
0213     if (csio_rd_reg32(hw, edc_bist_cmd_reg) & START_BIST_F)
0214         return -EBUSY;
0215     csio_wr_reg32(hw, addr & ~0x3fU, edc_bist_cmd_addr_reg);
0216     csio_wr_reg32(hw, 64, edc_bist_cmd_len_reg);
0217     csio_wr_reg32(hw, 0xc, edc_bist_cmd_data_pattern);
0218     csio_wr_reg32(hw, BIST_OPCODE_V(1) | START_BIST_F |  BIST_CMD_GAP_V(1),
0219               edc_bist_cmd_reg);
0220     i = csio_hw_wait_op_done_val(hw, edc_bist_cmd_reg, START_BIST_F,
0221                      0, 10, 1, NULL);
0222     if (i)
0223         return i;
0224
0225 #define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA_A, i) + idx)
0226
0227     for (i = 15; i >= 0; i--)
0228         *data++ = htonl(csio_rd_reg32(hw, EDC_DATA(i)));
0229     if (ecc)
0230         *ecc = csio_rd_reg64(hw, EDC_DATA(16));
0231 #undef EDC_DATA
0232     return 0;
0233 }
0234
0235 /*
0236  * csio_t5_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
0237  * @hw: the csio_hw
0238  * @win: PCI-E memory Window to use
0239  * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_MC0 (or MEM_MC) or MEM_MC1
0240  * @addr: address within indicated memory type
0241  * @len: amount of memory to transfer
0242  * @buf: host memory buffer
0243  * @dir: direction of transfer 1 => read, 0 => write
0244  *
0245  * Reads/writes an [almost] arbitrary memory region in the firmware: the
0246  * firmware memory address, length and host buffer must be aligned on
0247  * 32-bit boundaries.  The memory is transferred as a raw byte sequence
0248  * from/to the firmware's memory.  If this memory contains data
0249  * structures which contain multi-byte integers, it's the callers
0250  * responsibility to perform appropriate byte order conversions.
0251  */
0252 static int
0253 csio_t5_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
0254         u32 len, uint32_t *buf, int dir)
0255 {
0256     u32 pos, start, offset, memoffset;
0257     u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
0258
0259     /*
0260      * Argument sanity checks ...
0261      */
0262     if ((addr & 0x3) || (len & 0x3))
0263         return -EINVAL;
0264
0265     /* Offset into the region of memory which is being accessed
0266      * MEM_EDC0 = 0
0267      * MEM_EDC1 = 1
0268      * MEM_MC   = 2 -- T4
0269      * MEM_MC0  = 2 -- For T5
0270      * MEM_MC1  = 3 -- For T5
0271      */
0272     edc_size  = EDRAM0_SIZE_G(csio_rd_reg32(hw, MA_EDRAM0_BAR_A));
0273     if (mtype != MEM_MC1)
0274         memoffset = (mtype * (edc_size * 1024 * 1024));
0275     else {
0276         mc_size = EXT_MEM_SIZE_G(csio_rd_reg32(hw,
0277                                MA_EXT_MEMORY_BAR_A));
0278         memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
0279     }
0280
0281     /* Determine the PCIE_MEM_ACCESS_OFFSET */
0282     addr = addr + memoffset;
0283
0284     /*
0285      * Each PCI-E Memory Window is programmed with a window size -- or
0286      * "aperture" -- which controls the granularity of its mapping onto
0287      * adapter memory.  We need to grab that aperture in order to know
0288      * how to use the specified window.  The window is also programmed
0289      * with the base address of the Memory Window in BAR0's address
0290      * space.  For T4 this is an absolute PCI-E Bus Address.  For T5
0291      * the address is relative to BAR0.
0292      */
0293     mem_reg = csio_rd_reg32(hw,
0294             PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
0295     mem_aperture = 1 << (WINDOW_V(mem_reg) + 10);
0296     mem_base = PCIEOFST_G(mem_reg) << 10;
0297
0298     start = addr & ~(mem_aperture-1);
0299     offset = addr - start;
0300     win_pf = PFNUM_V(hw->pfn);
0301
0302     csio_dbg(hw, "csio_t5_memory_rw: mem_reg: 0x%x, mem_aperture: 0x%x\n",
0303          mem_reg, mem_aperture);
0304     csio_dbg(hw, "csio_t5_memory_rw: mem_base: 0x%x, mem_offset: 0x%x\n",
0305          mem_base, memoffset);
0306     csio_dbg(hw, "csio_t5_memory_rw: start:0x%x, offset:0x%x, win_pf:%d\n",
0307          start, offset, win_pf);
0308     csio_dbg(hw, "csio_t5_memory_rw: mtype: %d, addr: 0x%x, len: %d\n",
0309          mtype, addr, len);
0310
0311     for (pos = start; len > 0; pos += mem_aperture, offset = 0) {
0312         /*
0313          * Move PCI-E Memory Window to our current transfer
0314          * position.  Read it back to ensure that changes propagate
0315          * before we attempt to use the new value.
0316          */
0317         csio_wr_reg32(hw, pos | win_pf,
0318             PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
0319         csio_rd_reg32(hw,
0320             PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
0321
0322         while (offset < mem_aperture && len > 0) {
0323             if (dir)
0324                 *buf++ = csio_rd_reg32(hw, mem_base + offset);
0325             else
0326                 csio_wr_reg32(hw, *buf++, mem_base + offset);
0327
0328             offset += sizeof(__be32);
0329             len -= sizeof(__be32);
0330         }
0331     }
0332     return 0;
0333 }
0334
0335 /*
0336  * csio_t5_dfs_create_ext_mem - setup debugfs for MC0 or MC1 to read the values
0337  * @hw: the csio_hw
0338  *
0339  * This function creates files in the debugfs with external memory region
0340  * MC0 & MC1.
0341  */
0342 static void
0343 csio_t5_dfs_create_ext_mem(struct csio_hw *hw)
0344 {
0345     u32 size;
0346     int i = csio_rd_reg32(hw, MA_TARGET_MEM_ENABLE_A);
0347
0348     if (i & EXT_MEM_ENABLE_F) {
0349         size = csio_rd_reg32(hw, MA_EXT_MEMORY_BAR_A);
0350         csio_add_debugfs_mem(hw, "mc0", MEM_MC0,
0351                      EXT_MEM_SIZE_G(size));
0352     }
0353     if (i & EXT_MEM1_ENABLE_F) {
0354         size = csio_rd_reg32(hw, MA_EXT_MEMORY1_BAR_A);
0355         csio_add_debugfs_mem(hw, "mc1", MEM_MC1,
0356                      EXT_MEM_SIZE_G(size));
0357     }
0358 }
0359
0360 /* T5 adapter specific function */
0361 struct csio_hw_chip_ops t5_ops = {
0362     .chip_set_mem_win       = csio_t5_set_mem_win,
0363     .chip_pcie_intr_handler     = csio_t5_pcie_intr_handler,
0364     .chip_flash_cfg_addr        = csio_t5_flash_cfg_addr,
0365     .chip_mc_read           = csio_t5_mc_read,
0366     .chip_edc_read          = csio_t5_edc_read,
0367     .chip_memory_rw         = csio_t5_memory_rw,
0368     .chip_dfs_create_ext_mem    = csio_t5_dfs_create_ext_mem,
0369 };