scsi/csiostor/csio_hw_chip.h

0001 /*
0002  * This file is part of the Chelsio FCoE driver for Linux.
0003  *
0004  * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
0005  *
0006  * This software is available to you under a choice of one of two
0007  * licenses.  You may choose to be licensed under the terms of the GNU
0008  * General Public License (GPL) Version 2, available from the file
0009  * OpenIB.org BSD license below:
0010  *
0011  *     Redistribution and use in source and binary forms, with or
0012  *     without modification, are permitted provided that the following
0013  *     conditions are met:
0014  *
0015  *      - Redistributions of source code must retain the above
0016  *        copyright notice, this list of conditions and the following
0017  *        disclaimer.
0018  *
0019  *      - Redistributions in binary form must reproduce the above
0020  *        copyright notice, this list of conditions and the following
0021  *        disclaimer in the documentation and/or other materials
0022  *        provided with the distribution.
0023  *
0024  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0025  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0026  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0027  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0028  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0029  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0030  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0031  * SOFTWARE.
0032  */
0033
0034 #ifndef __CSIO_HW_CHIP_H__
0035 #define __CSIO_HW_CHIP_H__
0036
0037 #include "csio_defs.h"
0038
0039 /* Define MACRO values */
0040 #define CSIO_HW_T5              0x5000
0041 #define CSIO_T5_FCOE_ASIC           0x5600
0042 #define CSIO_HW_T6              0x6000
0043 #define CSIO_T6_FCOE_ASIC           0x6600
0044 #define CSIO_HW_CHIP_MASK           0xF000
0045
0046 #define T5_REGMAP_SIZE              (332 * 1024)
0047 #define FW_FNAME_T5             "cxgb4/t5fw.bin"
0048 #define FW_CFG_NAME_T5              "cxgb4/t5-config.txt"
0049 #define FW_FNAME_T6             "cxgb4/t6fw.bin"
0050 #define FW_CFG_NAME_T6              "cxgb4/t6-config.txt"
0051
0052 #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
0053 #define CHELSIO_CHIP_FPGA          0x100
0054 #define CHELSIO_CHIP_VERSION(code) (((code) >> 12) & 0xf)
0055 #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
0056
0057 #define CHELSIO_T5      0x5
0058 #define CHELSIO_T6      0x6
0059
0060 enum chip_type {
0061     T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
0062     T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
0063     T5_FIRST_REV    = T5_A0,
0064     T5_LAST_REV = T5_A1,
0065
0066     T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0),
0067     T6_FIRST_REV    = T6_A0,
0068     T6_LAST_REV     = T6_A0,
0069 };
0070
0071 static inline int csio_is_t5(uint16_t chip)
0072 {
0073     return (chip == CSIO_HW_T5);
0074 }
0075
0076 static inline int csio_is_t6(uint16_t chip)
0077 {
0078     return (chip == CSIO_HW_T6);
0079 }
0080
0081 /* Define MACRO DEFINITIONS */
0082 #define CSIO_DEVICE(devid, idx)                     \
0083     { PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) }
0084
0085 #include "t4fw_api.h"
0086 #include "t4fw_version.h"
0087
0088 #define FW_VERSION(chip) ( \
0089         FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
0090         FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
0091         FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
0092         FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
0093 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
0094
0095 struct fw_info {
0096     u8 chip;
0097     char *fs_name;
0098     char *fw_mod_name;
0099     struct fw_hdr fw_hdr;
0100 };
0101
0102 /* Declare ENUMS */
0103 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
0104
0105 enum {
0106     MEMWIN_APERTURE = 2048,
0107     MEMWIN_BASE     = 0x1b800,
0108 };
0109
0110 /* Slow path handlers */
0111 struct intr_info {
0112     unsigned int mask;       /* bits to check in interrupt status */
0113     const char *msg;         /* message to print or NULL */
0114     short stat_idx;          /* stat counter to increment or -1 */
0115     unsigned short fatal;    /* whether the condition reported is fatal */
0116 };
0117
0118 /* T4/T5 Chip specific ops */
0119 struct csio_hw;
0120 struct csio_hw_chip_ops {
0121     int (*chip_set_mem_win)(struct csio_hw *, uint32_t);
0122     void (*chip_pcie_intr_handler)(struct csio_hw *);
0123     uint32_t (*chip_flash_cfg_addr)(struct csio_hw *);
0124     int (*chip_mc_read)(struct csio_hw *, int, uint32_t,
0125                     __be32 *, uint64_t *);
0126     int (*chip_edc_read)(struct csio_hw *, int, uint32_t,
0127                     __be32 *, uint64_t *);
0128     int (*chip_memory_rw)(struct csio_hw *, u32, int, u32,
0129                     u32, uint32_t *, int);
0130     void (*chip_dfs_create_ext_mem)(struct csio_hw *);
0131 };
0132
0133 extern struct csio_hw_chip_ops t5_ops;
0134
0135 #endif /* #ifndef __CSIO_HW_CHIP_H__ */