scsi/bnx2fc/57xx_hsi_bnx2fc.h

0001 /* 57xx_hsi_bnx2fc.h: QLogic Linux FCoE offload driver.
0002  * Handles operations such as session offload/upload etc, and manages
0003  * session resources such as connection id and qp resources.
0004  *
0005  * Copyright (c) 2008-2013 Broadcom Corporation
0006  * Copyright (c) 2014-2016 QLogic Corporation
0007  * Copyright (c) 2016-2017 Cavium Inc.
0008  *
0009  * This program is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License as published by
0011  * the Free Software Foundation.
0012  *
0013  */
0014
0015 #ifndef __57XX_FCOE_HSI_LINUX_LE__
0016 #define __57XX_FCOE_HSI_LINUX_LE__
0017
0018 /*
0019  * common data for all protocols
0020  */
0021 struct b577xx_doorbell_hdr {
0022     u8 header;
0023 #define B577XX_DOORBELL_HDR_RX (0x1<<0)
0024 #define B577XX_DOORBELL_HDR_RX_SHIFT 0
0025 #define B577XX_DOORBELL_HDR_DB_TYPE (0x1<<1)
0026 #define B577XX_DOORBELL_HDR_DB_TYPE_SHIFT 1
0027 #define B577XX_DOORBELL_HDR_DPM_SIZE (0x3<<2)
0028 #define B577XX_DOORBELL_HDR_DPM_SIZE_SHIFT 2
0029 #define B577XX_DOORBELL_HDR_CONN_TYPE (0xF<<4)
0030 #define B577XX_DOORBELL_HDR_CONN_TYPE_SHIFT 4
0031 };
0032
0033 /*
0034  * doorbell message sent to the chip
0035  */
0036 struct b577xx_doorbell {
0037 #if defined(__BIG_ENDIAN)
0038     u16 zero_fill2;
0039     u8 zero_fill1;
0040     struct b577xx_doorbell_hdr header;
0041 #elif defined(__LITTLE_ENDIAN)
0042     struct b577xx_doorbell_hdr header;
0043     u8 zero_fill1;
0044     u16 zero_fill2;
0045 #endif
0046 };
0047
0048
0049
0050 /*
0051  * doorbell message sent to the chip
0052  */
0053 struct b577xx_doorbell_set_prod {
0054 #if defined(__BIG_ENDIAN)
0055     u16 prod;
0056     u8 zero_fill1;
0057     struct b577xx_doorbell_hdr header;
0058 #elif defined(__LITTLE_ENDIAN)
0059     struct b577xx_doorbell_hdr header;
0060     u8 zero_fill1;
0061     u16 prod;
0062 #endif
0063 };
0064
0065
0066 struct regpair {
0067     __le32 lo;
0068     __le32 hi;
0069 };
0070
0071
0072 /*
0073  * ABTS info $$KEEP_ENDIANNESS$$
0074  */
0075 struct fcoe_abts_info {
0076     __le16 aborted_task_id;
0077     __le16 reserved0;
0078     __le32 reserved1;
0079 };
0080
0081
0082 /*
0083  * Fixed size structure in order to plant it in Union structure
0084  * $$KEEP_ENDIANNESS$$
0085  */
0086 struct fcoe_abts_rsp_union {
0087     u8 r_ctl;
0088     u8 rsrv[3];
0089     __le32 abts_rsp_payload[7];
0090 };
0091
0092
0093 /*
0094  * 4 regs size $$KEEP_ENDIANNESS$$
0095  */
0096 struct fcoe_bd_ctx {
0097     __le32 buf_addr_hi;
0098     __le32 buf_addr_lo;
0099     __le16 buf_len;
0100     __le16 rsrv0;
0101     __le16 flags;
0102     __le16 rsrv1;
0103 };
0104
0105
0106 /*
0107  * FCoE cached sges context $$KEEP_ENDIANNESS$$
0108  */
0109 struct fcoe_cached_sge_ctx {
0110     struct regpair cur_buf_addr;
0111     __le16 cur_buf_rem;
0112     __le16 second_buf_rem;
0113     struct regpair second_buf_addr;
0114 };
0115
0116
0117 /*
0118  * Cleanup info $$KEEP_ENDIANNESS$$
0119  */
0120 struct fcoe_cleanup_info {
0121     __le16 cleaned_task_id;
0122     __le16 rolled_tx_seq_cnt;
0123     __le32 rolled_tx_data_offset;
0124 };
0125
0126
0127 /*
0128  * Fcp RSP flags $$KEEP_ENDIANNESS$$
0129  */
0130 struct fcoe_fcp_rsp_flags {
0131     u8 flags;
0132 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0)
0133 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID_SHIFT 0
0134 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID (0x1<<1)
0135 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID_SHIFT 1
0136 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER (0x1<<2)
0137 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER_SHIFT 2
0138 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER (0x1<<3)
0139 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER_SHIFT 3
0140 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ (0x1<<4)
0141 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ_SHIFT 4
0142 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS (0x7<<5)
0143 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5
0144 };
0145
0146 /*
0147  * Fcp RSP payload $$KEEP_ENDIANNESS$$
0148  */
0149 struct fcoe_fcp_rsp_payload {
0150     struct regpair reserved0;
0151     __le32 fcp_resid;
0152     u8 scsi_status_code;
0153     struct fcoe_fcp_rsp_flags fcp_flags;
0154     __le16 retry_delay_timer;
0155     __le32 fcp_rsp_len;
0156     __le32 fcp_sns_len;
0157 };
0158
0159 /*
0160  * Fixed size structure in order to plant it in Union structure
0161  * $$KEEP_ENDIANNESS$$
0162  */
0163 struct fcoe_fcp_rsp_union {
0164     struct fcoe_fcp_rsp_payload payload;
0165     struct regpair reserved0;
0166 };
0167
0168 /*
0169  * FC header $$KEEP_ENDIANNESS$$
0170  */
0171 struct fcoe_fc_hdr {
0172     u8 s_id[3];
0173     u8 cs_ctl;
0174     u8 d_id[3];
0175     u8 r_ctl;
0176     __le16 seq_cnt;
0177     u8 df_ctl;
0178     u8 seq_id;
0179     u8 f_ctl[3];
0180     u8 type;
0181     __le32 parameters;
0182     __le16 rx_id;
0183     __le16 ox_id;
0184 };
0185
0186 /*
0187  * FC header union $$KEEP_ENDIANNESS$$
0188  */
0189 struct fcoe_mp_rsp_union {
0190     struct fcoe_fc_hdr fc_hdr;
0191     __le32 mp_payload_len;
0192     __le32 rsrv;
0193 };
0194
0195 /*
0196  * Completion information $$KEEP_ENDIANNESS$$
0197  */
0198 union fcoe_comp_flow_info {
0199     struct fcoe_fcp_rsp_union fcp_rsp;
0200     struct fcoe_abts_rsp_union abts_rsp;
0201     struct fcoe_mp_rsp_union mp_rsp;
0202     __le32 opaque[8];
0203 };
0204
0205
0206 /*
0207  * External ABTS info $$KEEP_ENDIANNESS$$
0208  */
0209 struct fcoe_ext_abts_info {
0210     __le32 rsrv0[6];
0211     struct fcoe_abts_info ctx;
0212 };
0213
0214
0215 /*
0216  * External cleanup info $$KEEP_ENDIANNESS$$
0217  */
0218 struct fcoe_ext_cleanup_info {
0219     __le32 rsrv0[6];
0220     struct fcoe_cleanup_info ctx;
0221 };
0222
0223
0224 /*
0225  * Fcoe FW Tx sequence context $$KEEP_ENDIANNESS$$
0226  */
0227 struct fcoe_fw_tx_seq_ctx {
0228     __le32 data_offset;
0229     __le16 seq_cnt;
0230     __le16 rsrv0;
0231 };
0232
0233 /*
0234  * Fcoe external FW Tx sequence context $$KEEP_ENDIANNESS$$
0235  */
0236 struct fcoe_ext_fw_tx_seq_ctx {
0237     __le32 rsrv0[6];
0238     struct fcoe_fw_tx_seq_ctx ctx;
0239 };
0240
0241
0242 /*
0243  * FCoE multiple sges context $$KEEP_ENDIANNESS$$
0244  */
0245 struct fcoe_mul_sges_ctx {
0246     struct regpair cur_sge_addr;
0247     __le16 cur_sge_off;
0248     u8 cur_sge_idx;
0249     u8 sgl_size;
0250 };
0251
0252 /*
0253  * FCoE external multiple sges context $$KEEP_ENDIANNESS$$
0254  */
0255 struct fcoe_ext_mul_sges_ctx {
0256     struct fcoe_mul_sges_ctx mul_sgl;
0257     struct regpair rsrv0;
0258 };
0259
0260
0261 /*
0262  * FCP CMD payload $$KEEP_ENDIANNESS$$
0263  */
0264 struct fcoe_fcp_cmd_payload {
0265     __le32 opaque[8];
0266 };
0267
0268
0269
0270
0271
0272 /*
0273  * Fcp xfr rdy payload $$KEEP_ENDIANNESS$$
0274  */
0275 struct fcoe_fcp_xfr_rdy_payload {
0276     __le32 burst_len;
0277     __le32 data_ro;
0278 };
0279
0280
0281 /*
0282  * FC frame $$KEEP_ENDIANNESS$$
0283  */
0284 struct fcoe_fc_frame {
0285     struct fcoe_fc_hdr fc_hdr;
0286     __le32 reserved0[2];
0287 };
0288
0289
0290
0291
0292 /*
0293  * FCoE KCQ CQE parameters $$KEEP_ENDIANNESS$$
0294  */
0295 union fcoe_kcqe_params {
0296     __le32 reserved0[4];
0297 };
0298
0299 /*
0300  * FCoE KCQ CQE $$KEEP_ENDIANNESS$$
0301  */
0302 struct fcoe_kcqe {
0303     __le32 fcoe_conn_id;
0304     __le32 completion_status;
0305     __le32 fcoe_conn_context_id;
0306     union fcoe_kcqe_params params;
0307     __le16 qe_self_seq;
0308     u8 op_code;
0309     u8 flags;
0310 #define FCOE_KCQE_RESERVED0 (0x7<<0)
0311 #define FCOE_KCQE_RESERVED0_SHIFT 0
0312 #define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3)
0313 #define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3
0314 #define FCOE_KCQE_LAYER_CODE (0x7<<4)
0315 #define FCOE_KCQE_LAYER_CODE_SHIFT 4
0316 #define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7)
0317 #define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7
0318 };
0319
0320
0321
0322 /*
0323  * FCoE KWQE header $$KEEP_ENDIANNESS$$
0324  */
0325 struct fcoe_kwqe_header {
0326     u8 op_code;
0327     u8 flags;
0328 #define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0)
0329 #define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0
0330 #define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4)
0331 #define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4
0332 #define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7)
0333 #define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7
0334 };
0335
0336 /*
0337  * FCoE firmware init request 1 $$KEEP_ENDIANNESS$$
0338  */
0339 struct fcoe_kwqe_init1 {
0340     __le16 num_tasks;
0341     struct fcoe_kwqe_header hdr;
0342     __le32 task_list_pbl_addr_lo;
0343     __le32 task_list_pbl_addr_hi;
0344     __le32 dummy_buffer_addr_lo;
0345     __le32 dummy_buffer_addr_hi;
0346     __le16 sq_num_wqes;
0347     __le16 rq_num_wqes;
0348     __le16 rq_buffer_log_size;
0349     __le16 cq_num_wqes;
0350     __le16 mtu;
0351     u8 num_sessions_log;
0352     u8 flags;
0353 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0)
0354 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0
0355 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4)
0356 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4
0357 #define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7)
0358 #define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7
0359 };
0360
0361 /*
0362  * FCoE firmware init request 2 $$KEEP_ENDIANNESS$$
0363  */
0364 struct fcoe_kwqe_init2 {
0365     u8 hsi_major_version;
0366     u8 hsi_minor_version;
0367     struct fcoe_kwqe_header hdr;
0368     __le32 hash_tbl_pbl_addr_lo;
0369     __le32 hash_tbl_pbl_addr_hi;
0370     __le32 t2_hash_tbl_addr_lo;
0371     __le32 t2_hash_tbl_addr_hi;
0372     __le32 t2_ptr_hash_tbl_addr_lo;
0373     __le32 t2_ptr_hash_tbl_addr_hi;
0374     __le32 free_list_count;
0375 };
0376
0377 /*
0378  * FCoE firmware init request 3 $$KEEP_ENDIANNESS$$
0379  */
0380 struct fcoe_kwqe_init3 {
0381     __le16 reserved0;
0382     struct fcoe_kwqe_header hdr;
0383     __le32 error_bit_map_lo;
0384     __le32 error_bit_map_hi;
0385     u8 perf_config;
0386     u8 reserved21[3];
0387     __le32 reserved2[4];
0388 };
0389
0390 /*
0391  * FCoE connection offload request 1 $$KEEP_ENDIANNESS$$
0392  */
0393 struct fcoe_kwqe_conn_offload1 {
0394     __le16 fcoe_conn_id;
0395     struct fcoe_kwqe_header hdr;
0396     __le32 sq_addr_lo;
0397     __le32 sq_addr_hi;
0398     __le32 rq_pbl_addr_lo;
0399     __le32 rq_pbl_addr_hi;
0400     __le32 rq_first_pbe_addr_lo;
0401     __le32 rq_first_pbe_addr_hi;
0402     __le16 rq_prod;
0403     __le16 reserved0;
0404 };
0405
0406 /*
0407  * FCoE connection offload request 2 $$KEEP_ENDIANNESS$$
0408  */
0409 struct fcoe_kwqe_conn_offload2 {
0410     __le16 tx_max_fc_pay_len;
0411     struct fcoe_kwqe_header hdr;
0412     __le32 cq_addr_lo;
0413     __le32 cq_addr_hi;
0414     __le32 xferq_addr_lo;
0415     __le32 xferq_addr_hi;
0416     __le32 conn_db_addr_lo;
0417     __le32 conn_db_addr_hi;
0418     __le32 reserved1;
0419 };
0420
0421 /*
0422  * FCoE connection offload request 3 $$KEEP_ENDIANNESS$$
0423  */
0424 struct fcoe_kwqe_conn_offload3 {
0425     __le16 vlan_tag;
0426 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0)
0427 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0
0428 #define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12)
0429 #define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12
0430 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13)
0431 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13
0432     struct fcoe_kwqe_header hdr;
0433     u8 s_id[3];
0434     u8 tx_max_conc_seqs_c3;
0435     u8 d_id[3];
0436     u8 flags;
0437 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0)
0438 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0
0439 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1)
0440 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1
0441 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2)
0442 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2
0443 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3)
0444 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3
0445 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4)
0446 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4
0447 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5)
0448 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5
0449 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6)
0450 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6
0451 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7)
0452 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7
0453     __le32 reserved;
0454     __le32 confq_first_pbe_addr_lo;
0455     __le32 confq_first_pbe_addr_hi;
0456     __le16 tx_total_conc_seqs;
0457     __le16 rx_max_fc_pay_len;
0458     __le16 rx_total_conc_seqs;
0459     u8 rx_max_conc_seqs_c3;
0460     u8 rx_open_seqs_exch_c3;
0461 };
0462
0463 /*
0464  * FCoE connection offload request 4 $$KEEP_ENDIANNESS$$
0465  */
0466 struct fcoe_kwqe_conn_offload4 {
0467     u8 e_d_tov_timer_val;
0468     u8 reserved2;
0469     struct fcoe_kwqe_header hdr;
0470     u8 src_mac_addr_lo[2];
0471     u8 src_mac_addr_mid[2];
0472     u8 src_mac_addr_hi[2];
0473     u8 dst_mac_addr_hi[2];
0474     u8 dst_mac_addr_lo[2];
0475     u8 dst_mac_addr_mid[2];
0476     __le32 lcq_addr_lo;
0477     __le32 lcq_addr_hi;
0478     __le32 confq_pbl_base_addr_lo;
0479     __le32 confq_pbl_base_addr_hi;
0480 };
0481
0482 /*
0483  * FCoE connection enable request $$KEEP_ENDIANNESS$$
0484  */
0485 struct fcoe_kwqe_conn_enable_disable {
0486     __le16 reserved0;
0487     struct fcoe_kwqe_header hdr;
0488     u8 src_mac_addr_lo[2];
0489     u8 src_mac_addr_mid[2];
0490     u8 src_mac_addr_hi[2];
0491     u16 vlan_tag;
0492 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0)
0493 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0
0494 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12)
0495 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12
0496 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13)
0497 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13
0498     u8 dst_mac_addr_lo[2];
0499     u8 dst_mac_addr_mid[2];
0500     u8 dst_mac_addr_hi[2];
0501     __le16 reserved1;
0502     u8 s_id[3];
0503     u8 vlan_flag;
0504     u8 d_id[3];
0505     u8 reserved3;
0506     __le32 context_id;
0507     __le32 conn_id;
0508     __le32 reserved4;
0509 };
0510
0511 /*
0512  * FCoE connection destroy request $$KEEP_ENDIANNESS$$
0513  */
0514 struct fcoe_kwqe_conn_destroy {
0515     __le16 reserved0;
0516     struct fcoe_kwqe_header hdr;
0517     __le32 context_id;
0518     __le32 conn_id;
0519     __le32 reserved1[5];
0520 };
0521
0522 /*
0523  * FCoe destroy request $$KEEP_ENDIANNESS$$
0524  */
0525 struct fcoe_kwqe_destroy {
0526     __le16 reserved0;
0527     struct fcoe_kwqe_header hdr;
0528     __le32 reserved1[7];
0529 };
0530
0531 /*
0532  * FCoe statistics request $$KEEP_ENDIANNESS$$
0533  */
0534 struct fcoe_kwqe_stat {
0535     __le16 reserved0;
0536     struct fcoe_kwqe_header hdr;
0537     __le32 stat_params_addr_lo;
0538     __le32 stat_params_addr_hi;
0539     __le32 reserved1[5];
0540 };
0541
0542 /*
0543  * FCoE KWQ WQE $$KEEP_ENDIANNESS$$
0544  */
0545 union fcoe_kwqe {
0546     struct fcoe_kwqe_init1 init1;
0547     struct fcoe_kwqe_init2 init2;
0548     struct fcoe_kwqe_init3 init3;
0549     struct fcoe_kwqe_conn_offload1 conn_offload1;
0550     struct fcoe_kwqe_conn_offload2 conn_offload2;
0551     struct fcoe_kwqe_conn_offload3 conn_offload3;
0552     struct fcoe_kwqe_conn_offload4 conn_offload4;
0553     struct fcoe_kwqe_conn_enable_disable conn_enable_disable;
0554     struct fcoe_kwqe_conn_destroy conn_destroy;
0555     struct fcoe_kwqe_destroy destroy;
0556     struct fcoe_kwqe_stat statistics;
0557 };
0558
0559
0560
0561
0562
0563
0564
0565
0566
0567
0568
0569
0570
0571
0572
0573
0574 /*
0575  * TX SGL context $$KEEP_ENDIANNESS$$
0576  */
0577 union fcoe_sgl_union_ctx {
0578     struct fcoe_cached_sge_ctx cached_sge;
0579     struct fcoe_ext_mul_sges_ctx sgl;
0580     __le32 opaque[5];
0581 };
0582
0583 /*
0584  * Data-In/ELS/BLS information $$KEEP_ENDIANNESS$$
0585  */
0586 struct fcoe_read_flow_info {
0587     union fcoe_sgl_union_ctx sgl_ctx;
0588     __le32 rsrv0[3];
0589 };
0590
0591
0592 /*
0593  * Fcoe stat context $$KEEP_ENDIANNESS$$
0594  */
0595 struct fcoe_s_stat_ctx {
0596     u8 flags;
0597 #define FCOE_S_STAT_CTX_ACTIVE (0x1<<0)
0598 #define FCOE_S_STAT_CTX_ACTIVE_SHIFT 0
0599 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND (0x1<<1)
0600 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND_SHIFT 1
0601 #define FCOE_S_STAT_CTX_ABTS_PERFORMED (0x1<<2)
0602 #define FCOE_S_STAT_CTX_ABTS_PERFORMED_SHIFT 2
0603 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT (0x1<<3)
0604 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT_SHIFT 3
0605 #define FCOE_S_STAT_CTX_P_RJT (0x1<<4)
0606 #define FCOE_S_STAT_CTX_P_RJT_SHIFT 4
0607 #define FCOE_S_STAT_CTX_ACK_EOFT (0x1<<5)
0608 #define FCOE_S_STAT_CTX_ACK_EOFT_SHIFT 5
0609 #define FCOE_S_STAT_CTX_RSRV1 (0x3<<6)
0610 #define FCOE_S_STAT_CTX_RSRV1_SHIFT 6
0611 };
0612
0613 /*
0614  * Fcoe rx seq context $$KEEP_ENDIANNESS$$
0615  */
0616 struct fcoe_rx_seq_ctx {
0617     u8 seq_id;
0618     struct fcoe_s_stat_ctx s_stat;
0619     __le16 seq_cnt;
0620     __le32 low_exp_ro;
0621     __le32 high_exp_ro;
0622 };
0623
0624
0625 /*
0626  * Fcoe rx_wr union context $$KEEP_ENDIANNESS$$
0627  */
0628 union fcoe_rx_wr_union_ctx {
0629     struct fcoe_read_flow_info read_info;
0630     union fcoe_comp_flow_info comp_info;
0631     __le32 opaque[8];
0632 };
0633
0634
0635
0636 /*
0637  * FCoE SQ element $$KEEP_ENDIANNESS$$
0638  */
0639 struct fcoe_sqe {
0640     __le16 wqe;
0641 #define FCOE_SQE_TASK_ID (0x7FFF<<0)
0642 #define FCOE_SQE_TASK_ID_SHIFT 0
0643 #define FCOE_SQE_TOGGLE_BIT (0x1<<15)
0644 #define FCOE_SQE_TOGGLE_BIT_SHIFT 15
0645 };
0646
0647
0648
0649 /*
0650  * 14 regs $$KEEP_ENDIANNESS$$
0651  */
0652 struct fcoe_tce_tx_only {
0653     union fcoe_sgl_union_ctx sgl_ctx;
0654     __le32 rsrv0;
0655 };
0656
0657 /*
0658  * 32 bytes (8 regs) used for TX only purposes $$KEEP_ENDIANNESS$$
0659  */
0660 union fcoe_tx_wr_rx_rd_union_ctx {
0661     struct fcoe_fc_frame tx_frame;
0662     struct fcoe_fcp_cmd_payload fcp_cmd;
0663     struct fcoe_ext_cleanup_info cleanup;
0664     struct fcoe_ext_abts_info abts;
0665     struct fcoe_ext_fw_tx_seq_ctx tx_seq;
0666     __le32 opaque[8];
0667 };
0668
0669 /*
0670  * tce_tx_wr_rx_rd_const $$KEEP_ENDIANNESS$$
0671  */
0672 struct fcoe_tce_tx_wr_rx_rd_const {
0673     u8 init_flags;
0674 #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE (0x7<<0)
0675 #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT 0
0676 #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE (0x1<<3)
0677 #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT 3
0678 #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE (0x1<<4)
0679 #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT 4
0680 #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE (0x3<<5)
0681 #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT 5
0682 #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV (0x1<<7)
0683 #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV_SHIFT 7
0684     u8 tx_flags;
0685 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID (0x1<<0)
0686 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID_SHIFT 0
0687 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE (0xF<<1)
0688 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT 1
0689 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1 (0x1<<5)
0690 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1_SHIFT 5
0691 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT (0x1<<6)
0692 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT_SHIFT 6
0693 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV2 (0x1<<7)
0694 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV2_SHIFT 7
0695     __le16 rsrv3;
0696     __le32 verify_tx_seq;
0697 };
0698
0699 /*
0700  * tce_tx_wr_rx_rd $$KEEP_ENDIANNESS$$
0701  */
0702 struct fcoe_tce_tx_wr_rx_rd {
0703     union fcoe_tx_wr_rx_rd_union_ctx union_ctx;
0704     struct fcoe_tce_tx_wr_rx_rd_const const_ctx;
0705 };
0706
0707 /*
0708  * tce_rx_wr_tx_rd_const $$KEEP_ENDIANNESS$$
0709  */
0710 struct fcoe_tce_rx_wr_tx_rd_const {
0711     __le32 data_2_trns;
0712     __le32 init_flags;
0713 #define FCOE_TCE_RX_WR_TX_RD_CONST_CID (0xFFFFFF<<0)
0714 #define FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT 0
0715 #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0 (0xFF<<24)
0716 #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0_SHIFT 24
0717 };
0718
0719 /*
0720  * tce_rx_wr_tx_rd_var $$KEEP_ENDIANNESS$$
0721  */
0722 struct fcoe_tce_rx_wr_tx_rd_var {
0723     __le16 rx_flags;
0724 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1 (0xF<<0)
0725 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1_SHIFT 0
0726 #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE (0x7<<4)
0727 #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT 4
0728 #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ (0x1<<7)
0729 #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ_SHIFT 7
0730 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE (0xF<<8)
0731 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT 8
0732 #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME (0x1<<12)
0733 #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT 12
0734 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT (0x1<<13)
0735 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT_SHIFT 13
0736 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2 (0x1<<14)
0737 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2_SHIFT 14
0738 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID (0x1<<15)
0739 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID_SHIFT 15
0740     __le16 rx_id;
0741     struct fcoe_fcp_xfr_rdy_payload fcp_xfr_rdy;
0742 };
0743
0744 /*
0745  * tce_rx_wr_tx_rd $$KEEP_ENDIANNESS$$
0746  */
0747 struct fcoe_tce_rx_wr_tx_rd {
0748     struct fcoe_tce_rx_wr_tx_rd_const const_ctx;
0749     struct fcoe_tce_rx_wr_tx_rd_var var_ctx;
0750 };
0751
0752 /*
0753  * tce_rx_only $$KEEP_ENDIANNESS$$
0754  */
0755 struct fcoe_tce_rx_only {
0756     struct fcoe_rx_seq_ctx rx_seq_ctx;
0757     union fcoe_rx_wr_union_ctx union_ctx;
0758 };
0759
0760 /*
0761  * task_ctx_entry $$KEEP_ENDIANNESS$$
0762  */
0763 struct fcoe_task_ctx_entry {
0764     struct fcoe_tce_tx_only txwr_only;
0765     struct fcoe_tce_tx_wr_rx_rd txwr_rxrd;
0766     struct fcoe_tce_rx_wr_tx_rd rxwr_txrd;
0767     struct fcoe_tce_rx_only rxwr_only;
0768 };
0769
0770
0771
0772
0773
0774
0775
0776
0777
0778
0779 /*
0780  * FCoE XFRQ element $$KEEP_ENDIANNESS$$
0781  */
0782 struct fcoe_xfrqe {
0783     __le16 wqe;
0784 #define FCOE_XFRQE_TASK_ID (0x7FFF<<0)
0785 #define FCOE_XFRQE_TASK_ID_SHIFT 0
0786 #define FCOE_XFRQE_TOGGLE_BIT (0x1<<15)
0787 #define FCOE_XFRQE_TOGGLE_BIT_SHIFT 15
0788 };
0789
0790
0791 /*
0792  * fcoe rx doorbell message sent to the chip $$KEEP_ENDIANNESS$$
0793  */
0794 struct b577xx_fcoe_rx_doorbell {
0795     struct b577xx_doorbell_hdr hdr;
0796     u8 params;
0797 #define B577XX_FCOE_RX_DOORBELL_NEGATIVE_ARM (0x1F<<0)
0798 #define B577XX_FCOE_RX_DOORBELL_NEGATIVE_ARM_SHIFT 0
0799 #define B577XX_FCOE_RX_DOORBELL_OPCODE (0x7<<5)
0800 #define B577XX_FCOE_RX_DOORBELL_OPCODE_SHIFT 5
0801     __le16 doorbell_cq_cons;
0802 };
0803
0804
0805 /*
0806  * FCoE CONFQ element $$KEEP_ENDIANNESS$$
0807  */
0808 struct fcoe_confqe {
0809     __le16 ox_id;
0810     __le16 rx_id;
0811     __le32 param;
0812 };
0813
0814
0815 /*
0816  * FCoE connection data base
0817  */
0818 struct fcoe_conn_db {
0819 #if defined(__BIG_ENDIAN)
0820     u16 rsrv0;
0821     u16 rq_prod;
0822 #elif defined(__LITTLE_ENDIAN)
0823     u16 rq_prod;
0824     u16 rsrv0;
0825 #endif
0826     u32 rsrv1;
0827     struct regpair cq_arm;
0828 };
0829
0830
0831 /*
0832  * FCoE CQ element $$KEEP_ENDIANNESS$$
0833  */
0834 struct fcoe_cqe {
0835     __le16 wqe;
0836 #define FCOE_CQE_CQE_INFO (0x3FFF<<0)
0837 #define FCOE_CQE_CQE_INFO_SHIFT 0
0838 #define FCOE_CQE_CQE_TYPE (0x1<<14)
0839 #define FCOE_CQE_CQE_TYPE_SHIFT 14
0840 #define FCOE_CQE_TOGGLE_BIT (0x1<<15)
0841 #define FCOE_CQE_TOGGLE_BIT_SHIFT 15
0842 };
0843
0844
0845 /*
0846  * FCoE error/warning reporting entry $$KEEP_ENDIANNESS$$
0847  */
0848 struct fcoe_partial_err_report_entry {
0849     __le32 err_warn_bitmap_lo;
0850     __le32 err_warn_bitmap_hi;
0851     __le32 tx_buf_off;
0852     __le32 rx_buf_off;
0853 };
0854
0855 /*
0856  * FCoE error/warning reporting entry $$KEEP_ENDIANNESS$$
0857  */
0858 struct fcoe_err_report_entry {
0859     struct fcoe_partial_err_report_entry data;
0860     struct fcoe_fc_hdr fc_hdr;
0861 };
0862
0863
0864 /*
0865  * FCoE hash table entry (32 bytes) $$KEEP_ENDIANNESS$$
0866  */
0867 struct fcoe_hash_table_entry {
0868     u8 s_id_0;
0869     u8 s_id_1;
0870     u8 s_id_2;
0871     u8 d_id_0;
0872     u8 d_id_1;
0873     u8 d_id_2;
0874     __le16 dst_mac_addr_hi;
0875     __le16 dst_mac_addr_mid;
0876     __le16 dst_mac_addr_lo;
0877     __le16 src_mac_addr_hi;
0878     __le16 vlan_id;
0879     __le16 src_mac_addr_lo;
0880     __le16 src_mac_addr_mid;
0881     u8 vlan_flag;
0882     u8 reserved0;
0883     __le16 reserved1;
0884     __le32 reserved2;
0885     __le32 field_id;
0886 #define FCOE_HASH_TABLE_ENTRY_CID (0xFFFFFF<<0)
0887 #define FCOE_HASH_TABLE_ENTRY_CID_SHIFT 0
0888 #define FCOE_HASH_TABLE_ENTRY_RESERVED3 (0x7F<<24)
0889 #define FCOE_HASH_TABLE_ENTRY_RESERVED3_SHIFT 24
0890 #define FCOE_HASH_TABLE_ENTRY_VALID (0x1<<31)
0891 #define FCOE_HASH_TABLE_ENTRY_VALID_SHIFT 31
0892 };
0893
0894
0895 /*
0896  * FCoE LCQ element $$KEEP_ENDIANNESS$$
0897  */
0898 struct fcoe_lcqe {
0899     __le32 wqe;
0900 #define FCOE_LCQE_TASK_ID (0xFFFF<<0)
0901 #define FCOE_LCQE_TASK_ID_SHIFT 0
0902 #define FCOE_LCQE_LCQE_TYPE (0xFF<<16)
0903 #define FCOE_LCQE_LCQE_TYPE_SHIFT 16
0904 #define FCOE_LCQE_RESERVED (0xFF<<24)
0905 #define FCOE_LCQE_RESERVED_SHIFT 24
0906 };
0907
0908
0909
0910 /*
0911  * FCoE pending work request CQE $$KEEP_ENDIANNESS$$
0912  */
0913 struct fcoe_pend_wq_cqe {
0914     __le16 wqe;
0915 #define FCOE_PEND_WQ_CQE_TASK_ID (0x3FFF<<0)
0916 #define FCOE_PEND_WQ_CQE_TASK_ID_SHIFT 0
0917 #define FCOE_PEND_WQ_CQE_CQE_TYPE (0x1<<14)
0918 #define FCOE_PEND_WQ_CQE_CQE_TYPE_SHIFT 14
0919 #define FCOE_PEND_WQ_CQE_TOGGLE_BIT (0x1<<15)
0920 #define FCOE_PEND_WQ_CQE_TOGGLE_BIT_SHIFT 15
0921 };
0922
0923
0924 /*
0925  * FCoE RX statistics parameters section#0 $$KEEP_ENDIANNESS$$
0926  */
0927 struct fcoe_rx_stat_params_section0 {
0928     __le32 fcoe_rx_pkt_cnt;
0929     __le32 fcoe_rx_byte_cnt;
0930 };
0931
0932
0933 /*
0934  * FCoE RX statistics parameters section#1 $$KEEP_ENDIANNESS$$
0935  */
0936 struct fcoe_rx_stat_params_section1 {
0937     __le32 fcoe_ver_cnt;
0938     __le32 fcoe_rx_drop_pkt_cnt;
0939 };
0940
0941
0942 /*
0943  * FCoE RX statistics parameters section#2 $$KEEP_ENDIANNESS$$
0944  */
0945 struct fcoe_rx_stat_params_section2 {
0946     __le32 fc_crc_cnt;
0947     __le32 eofa_del_cnt;
0948     __le32 miss_frame_cnt;
0949     __le32 seq_timeout_cnt;
0950     __le32 drop_seq_cnt;
0951     __le32 fcoe_rx_drop_pkt_cnt;
0952     __le32 fcp_rx_pkt_cnt;
0953     __le32 reserved0;
0954 };
0955
0956
0957 /*
0958  * FCoE TX statistics parameters $$KEEP_ENDIANNESS$$
0959  */
0960 struct fcoe_tx_stat_params {
0961     __le32 fcoe_tx_pkt_cnt;
0962     __le32 fcoe_tx_byte_cnt;
0963     __le32 fcp_tx_pkt_cnt;
0964     __le32 reserved0;
0965 };
0966
0967 /*
0968  * FCoE statistics parameters $$KEEP_ENDIANNESS$$
0969  */
0970 struct fcoe_statistics_params {
0971     struct fcoe_tx_stat_params tx_stat;
0972     struct fcoe_rx_stat_params_section0 rx_stat0;
0973     struct fcoe_rx_stat_params_section1 rx_stat1;
0974     struct fcoe_rx_stat_params_section2 rx_stat2;
0975 };
0976
0977
0978 /*
0979  * FCoE t2 hash table entry (64 bytes) $$KEEP_ENDIANNESS$$
0980  */
0981 struct fcoe_t2_hash_table_entry {
0982     struct fcoe_hash_table_entry data;
0983     struct regpair next;
0984     struct regpair reserved0[3];
0985 };
0986
0987
0988
0989 /*
0990  * FCoE unsolicited CQE $$KEEP_ENDIANNESS$$
0991  */
0992 struct fcoe_unsolicited_cqe {
0993     __le16 wqe;
0994 #define FCOE_UNSOLICITED_CQE_SUBTYPE (0x3<<0)
0995 #define FCOE_UNSOLICITED_CQE_SUBTYPE_SHIFT 0
0996 #define FCOE_UNSOLICITED_CQE_PKT_LEN (0xFFF<<2)
0997 #define FCOE_UNSOLICITED_CQE_PKT_LEN_SHIFT 2
0998 #define FCOE_UNSOLICITED_CQE_CQE_TYPE (0x1<<14)
0999 #define FCOE_UNSOLICITED_CQE_CQE_TYPE_SHIFT 14
1000 #define FCOE_UNSOLICITED_CQE_TOGGLE_BIT (0x1<<15)
1001 #define FCOE_UNSOLICITED_CQE_TOGGLE_BIT_SHIFT 15
1002 };
1003
1004 #endif /* __57XX_FCOE_HSI_LINUX_LE__ */