scsi/bfa/bfa_ioc_cb.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
0004  * Copyright (c) 2014- QLogic Corporation.
0005  * All rights reserved
0006  * www.qlogic.com
0007  *
0008  * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
0009  */
0010
0011 #include "bfad_drv.h"
0012 #include "bfa_ioc.h"
0013 #include "bfi_reg.h"
0014 #include "bfa_defs.h"
0015
0016 BFA_TRC_FILE(CNA, IOC_CB);
0017
0018 #define bfa_ioc_cb_join_pos(__ioc) ((u32) (1 << BFA_IOC_CB_JOIN_SH))
0019
0020 /*
0021  * forward declarations
0022  */
0023 static bfa_boolean_t bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc);
0024 static void bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc);
0025 static void bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc);
0026 static void bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc);
0027 static void bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix);
0028 static void bfa_ioc_cb_notify_fail(struct bfa_ioc_s *ioc);
0029 static void bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc);
0030 static bfa_boolean_t bfa_ioc_cb_sync_start(struct bfa_ioc_s *ioc);
0031 static void bfa_ioc_cb_sync_join(struct bfa_ioc_s *ioc);
0032 static void bfa_ioc_cb_sync_leave(struct bfa_ioc_s *ioc);
0033 static void bfa_ioc_cb_sync_ack(struct bfa_ioc_s *ioc);
0034 static bfa_boolean_t bfa_ioc_cb_sync_complete(struct bfa_ioc_s *ioc);
0035 static void bfa_ioc_cb_set_cur_ioc_fwstate(
0036             struct bfa_ioc_s *ioc, enum bfi_ioc_state fwstate);
0037 static enum bfi_ioc_state bfa_ioc_cb_get_cur_ioc_fwstate(struct bfa_ioc_s *ioc);
0038 static void bfa_ioc_cb_set_alt_ioc_fwstate(
0039             struct bfa_ioc_s *ioc, enum bfi_ioc_state fwstate);
0040 static enum bfi_ioc_state bfa_ioc_cb_get_alt_ioc_fwstate(struct bfa_ioc_s *ioc);
0041
0042 static struct bfa_ioc_hwif_s hwif_cb;
0043
0044 /*
0045  * Called from bfa_ioc_attach() to map asic specific calls.
0046  */
0047 void
0048 bfa_ioc_set_cb_hwif(struct bfa_ioc_s *ioc)
0049 {
0050     hwif_cb.ioc_pll_init = bfa_ioc_cb_pll_init;
0051     hwif_cb.ioc_firmware_lock = bfa_ioc_cb_firmware_lock;
0052     hwif_cb.ioc_firmware_unlock = bfa_ioc_cb_firmware_unlock;
0053     hwif_cb.ioc_reg_init = bfa_ioc_cb_reg_init;
0054     hwif_cb.ioc_map_port = bfa_ioc_cb_map_port;
0055     hwif_cb.ioc_isr_mode_set = bfa_ioc_cb_isr_mode_set;
0056     hwif_cb.ioc_notify_fail = bfa_ioc_cb_notify_fail;
0057     hwif_cb.ioc_ownership_reset = bfa_ioc_cb_ownership_reset;
0058     hwif_cb.ioc_sync_start = bfa_ioc_cb_sync_start;
0059     hwif_cb.ioc_sync_join = bfa_ioc_cb_sync_join;
0060     hwif_cb.ioc_sync_leave = bfa_ioc_cb_sync_leave;
0061     hwif_cb.ioc_sync_ack = bfa_ioc_cb_sync_ack;
0062     hwif_cb.ioc_sync_complete = bfa_ioc_cb_sync_complete;
0063     hwif_cb.ioc_set_fwstate = bfa_ioc_cb_set_cur_ioc_fwstate;
0064     hwif_cb.ioc_get_fwstate = bfa_ioc_cb_get_cur_ioc_fwstate;
0065     hwif_cb.ioc_set_alt_fwstate = bfa_ioc_cb_set_alt_ioc_fwstate;
0066     hwif_cb.ioc_get_alt_fwstate = bfa_ioc_cb_get_alt_ioc_fwstate;
0067
0068     ioc->ioc_hwif = &hwif_cb;
0069 }
0070
0071 /*
0072  * Return true if firmware of current driver matches the running firmware.
0073  */
0074 static bfa_boolean_t
0075 bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc)
0076 {
0077     enum bfi_ioc_state alt_fwstate, cur_fwstate;
0078     struct bfi_ioc_image_hdr_s fwhdr;
0079
0080     cur_fwstate = bfa_ioc_cb_get_cur_ioc_fwstate(ioc);
0081     bfa_trc(ioc, cur_fwstate);
0082     alt_fwstate = bfa_ioc_cb_get_alt_ioc_fwstate(ioc);
0083     bfa_trc(ioc, alt_fwstate);
0084
0085     /*
0086      * Uninit implies this is the only driver as of now.
0087      */
0088     if (cur_fwstate == BFI_IOC_UNINIT)
0089         return BFA_TRUE;
0090     /*
0091      * Check if another driver with a different firmware is active
0092      */
0093     bfa_ioc_fwver_get(ioc, &fwhdr);
0094     if (!bfa_ioc_fwver_cmp(ioc, &fwhdr) &&
0095         alt_fwstate != BFI_IOC_DISABLED) {
0096         bfa_trc(ioc, alt_fwstate);
0097         return BFA_FALSE;
0098     }
0099
0100     return BFA_TRUE;
0101 }
0102
0103 static void
0104 bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc)
0105 {
0106 }
0107
0108 /*
0109  * Notify other functions on HB failure.
0110  */
0111 static void
0112 bfa_ioc_cb_notify_fail(struct bfa_ioc_s *ioc)
0113 {
0114     writel(~0U, ioc->ioc_regs.err_set);
0115     readl(ioc->ioc_regs.err_set);
0116 }
0117
0118 /*
0119  * Host to LPU mailbox message addresses
0120  */
0121 static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = {
0122     { HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 },
0123     { HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 }
0124 };
0125
0126 /*
0127  * Host <-> LPU mailbox command/status registers
0128  */
0129 static struct { u32 hfn, lpu; } iocreg_mbcmd[] = {
0130
0131     { HOSTFN0_LPU0_CMD_STAT, LPU0_HOSTFN0_CMD_STAT },
0132     { HOSTFN1_LPU1_CMD_STAT, LPU1_HOSTFN1_CMD_STAT }
0133 };
0134
0135 static void
0136 bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc)
0137 {
0138     void __iomem *rb;
0139     int     pcifn = bfa_ioc_pcifn(ioc);
0140
0141     rb = bfa_ioc_bar0(ioc);
0142
0143     ioc->ioc_regs.hfn_mbox = rb + iocreg_fnreg[pcifn].hfn_mbox;
0144     ioc->ioc_regs.lpu_mbox = rb + iocreg_fnreg[pcifn].lpu_mbox;
0145     ioc->ioc_regs.host_page_num_fn = rb + iocreg_fnreg[pcifn].hfn_pgn;
0146
0147     if (ioc->port_id == 0) {
0148         ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG;
0149         ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG;
0150         ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG;
0151     } else {
0152         ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);
0153         ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);
0154         ioc->ioc_regs.alt_ioc_fwstate = (rb + BFA_IOC0_STATE_REG);
0155     }
0156
0157     /*
0158      * Host <-> LPU mailbox command/status registers
0159      */
0160     ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd[pcifn].hfn;
0161     ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd[pcifn].lpu;
0162
0163     /*
0164      * PSS control registers
0165      */
0166     ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
0167     ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
0168     ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_LCLK_CTL_REG);
0169     ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_SCLK_CTL_REG);
0170
0171     /*
0172      * IOC semaphore registers and serialization
0173      */
0174     ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG);
0175     ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);
0176
0177     /*
0178      * sram memory access
0179      */
0180     ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);
0181     ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CB;
0182
0183     /*
0184      * err set reg : for notification of hb failure
0185      */
0186     ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
0187 }
0188
0189 /*
0190  * Initialize IOC to port mapping.
0191  */
0192
0193 static void
0194 bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc)
0195 {
0196     /*
0197      * For crossbow, port id is same as pci function.
0198      */
0199     ioc->port_id = bfa_ioc_pcifn(ioc);
0200
0201     bfa_trc(ioc, ioc->port_id);
0202 }
0203
0204 /*
0205  * Set interrupt mode for a function: INTX or MSIX
0206  */
0207 static void
0208 bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix)
0209 {
0210 }
0211
0212 /*
0213  * Synchronized IOC failure processing routines
0214  */
0215 static bfa_boolean_t
0216 bfa_ioc_cb_sync_start(struct bfa_ioc_s *ioc)
0217 {
0218     u32 ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate);
0219
0220     /**
0221      * Driver load time.  If the join bit is set,
0222      * it is due to an unclean exit by the driver for this
0223      * PCI fn in the previous incarnation. Whoever comes here first
0224      * should clean it up, no matter which PCI fn.
0225      */
0226     if (ioc_fwstate & BFA_IOC_CB_JOIN_MASK) {
0227         writel(BFI_IOC_UNINIT, ioc->ioc_regs.ioc_fwstate);
0228         writel(BFI_IOC_UNINIT, ioc->ioc_regs.alt_ioc_fwstate);
0229         return BFA_TRUE;
0230     }
0231
0232     return bfa_ioc_cb_sync_complete(ioc);
0233 }
0234
0235 /*
0236  * Cleanup hw semaphore and usecnt registers
0237  */
0238 static void
0239 bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc)
0240 {
0241
0242     /*
0243      * Read the hw sem reg to make sure that it is locked
0244      * before we clear it. If it is not locked, writing 1
0245      * will lock it instead of clearing it.
0246      */
0247     readl(ioc->ioc_regs.ioc_sem_reg);
0248     writel(1, ioc->ioc_regs.ioc_sem_reg);
0249 }
0250
0251 /*
0252  * Synchronized IOC failure processing routines
0253  */
0254 static void
0255 bfa_ioc_cb_sync_join(struct bfa_ioc_s *ioc)
0256 {
0257     u32 r32 = readl(ioc->ioc_regs.ioc_fwstate);
0258     u32 join_pos = bfa_ioc_cb_join_pos(ioc);
0259
0260     writel((r32 | join_pos), ioc->ioc_regs.ioc_fwstate);
0261 }
0262
0263 static void
0264 bfa_ioc_cb_sync_leave(struct bfa_ioc_s *ioc)
0265 {
0266     u32 r32 = readl(ioc->ioc_regs.ioc_fwstate);
0267     u32 join_pos = bfa_ioc_cb_join_pos(ioc);
0268
0269     writel((r32 & ~join_pos), ioc->ioc_regs.ioc_fwstate);
0270 }
0271
0272 static void
0273 bfa_ioc_cb_set_cur_ioc_fwstate(struct bfa_ioc_s *ioc,
0274             enum bfi_ioc_state fwstate)
0275 {
0276     u32 r32 = readl(ioc->ioc_regs.ioc_fwstate);
0277
0278     writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)),
0279                 ioc->ioc_regs.ioc_fwstate);
0280 }
0281
0282 static enum bfi_ioc_state
0283 bfa_ioc_cb_get_cur_ioc_fwstate(struct bfa_ioc_s *ioc)
0284 {
0285     return (enum bfi_ioc_state)(readl(ioc->ioc_regs.ioc_fwstate) &
0286             BFA_IOC_CB_FWSTATE_MASK);
0287 }
0288
0289 static void
0290 bfa_ioc_cb_set_alt_ioc_fwstate(struct bfa_ioc_s *ioc,
0291             enum bfi_ioc_state fwstate)
0292 {
0293     u32 r32 = readl(ioc->ioc_regs.alt_ioc_fwstate);
0294
0295     writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)),
0296                 ioc->ioc_regs.alt_ioc_fwstate);
0297 }
0298
0299 static enum bfi_ioc_state
0300 bfa_ioc_cb_get_alt_ioc_fwstate(struct bfa_ioc_s *ioc)
0301 {
0302     return (enum bfi_ioc_state)(readl(ioc->ioc_regs.alt_ioc_fwstate) &
0303             BFA_IOC_CB_FWSTATE_MASK);
0304 }
0305
0306 static void
0307 bfa_ioc_cb_sync_ack(struct bfa_ioc_s *ioc)
0308 {
0309     bfa_ioc_cb_set_cur_ioc_fwstate(ioc, BFI_IOC_FAIL);
0310 }
0311
0312 static bfa_boolean_t
0313 bfa_ioc_cb_sync_complete(struct bfa_ioc_s *ioc)
0314 {
0315     u32 fwstate, alt_fwstate;
0316     fwstate = bfa_ioc_cb_get_cur_ioc_fwstate(ioc);
0317
0318     /*
0319      * At this point, this IOC is hoding the hw sem in the
0320      * start path (fwcheck) OR in the disable/enable path
0321      * OR to check if the other IOC has acknowledged failure.
0322      *
0323      * So, this IOC can be in UNINIT, INITING, DISABLED, FAIL
0324      * or in MEMTEST states. In a normal scenario, this IOC
0325      * can not be in OP state when this function is called.
0326      *
0327      * However, this IOC could still be in OP state when
0328      * the OS driver is starting up, if the OptROM code has
0329      * left it in that state.
0330      *
0331      * If we had marked this IOC's fwstate as BFI_IOC_FAIL
0332      * in the failure case and now, if the fwstate is not
0333      * BFI_IOC_FAIL it implies that the other PCI fn have
0334      * reinitialized the ASIC or this IOC got disabled, so
0335      * return TRUE.
0336      */
0337     if (fwstate == BFI_IOC_UNINIT ||
0338         fwstate == BFI_IOC_INITING ||
0339         fwstate == BFI_IOC_DISABLED ||
0340         fwstate == BFI_IOC_MEMTEST ||
0341         fwstate == BFI_IOC_OP)
0342         return BFA_TRUE;
0343     else {
0344         alt_fwstate = bfa_ioc_cb_get_alt_ioc_fwstate(ioc);
0345         if (alt_fwstate == BFI_IOC_FAIL ||
0346             alt_fwstate == BFI_IOC_DISABLED ||
0347             alt_fwstate == BFI_IOC_UNINIT ||
0348             alt_fwstate == BFI_IOC_INITING ||
0349             alt_fwstate == BFI_IOC_MEMTEST)
0350             return BFA_TRUE;
0351         else
0352             return BFA_FALSE;
0353     }
0354 }
0355
0356 bfa_status_t
0357 bfa_ioc_cb_pll_init(void __iomem *rb, enum bfi_asic_mode fcmode)
0358 {
0359     u32 pll_sclk, pll_fclk, join_bits;
0360
0361     pll_sclk = __APP_PLL_SCLK_ENABLE | __APP_PLL_SCLK_LRESETN |
0362         __APP_PLL_SCLK_P0_1(3U) |
0363         __APP_PLL_SCLK_JITLMT0_1(3U) |
0364         __APP_PLL_SCLK_CNTLMT0_1(3U);
0365     pll_fclk = __APP_PLL_LCLK_ENABLE | __APP_PLL_LCLK_LRESETN |
0366         __APP_PLL_LCLK_RSEL200500 | __APP_PLL_LCLK_P0_1(3U) |
0367         __APP_PLL_LCLK_JITLMT0_1(3U) |
0368         __APP_PLL_LCLK_CNTLMT0_1(3U);
0369     join_bits = readl(rb + BFA_IOC0_STATE_REG) &
0370             BFA_IOC_CB_JOIN_MASK;
0371     writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC0_STATE_REG));
0372     join_bits = readl(rb + BFA_IOC1_STATE_REG) &
0373             BFA_IOC_CB_JOIN_MASK;
0374     writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC1_STATE_REG));
0375     writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
0376     writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
0377     writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
0378     writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
0379     writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
0380     writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
0381     writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG);
0382     writel(__APP_PLL_SCLK_BYPASS | __APP_PLL_SCLK_LOGIC_SOFT_RESET,
0383             rb + APP_PLL_SCLK_CTL_REG);
0384     writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG);
0385     writel(__APP_PLL_LCLK_BYPASS | __APP_PLL_LCLK_LOGIC_SOFT_RESET,
0386             rb + APP_PLL_LCLK_CTL_REG);
0387     udelay(2);
0388     writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG);
0389     writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG);
0390     writel(pll_sclk | __APP_PLL_SCLK_LOGIC_SOFT_RESET,
0391             rb + APP_PLL_SCLK_CTL_REG);
0392     writel(pll_fclk | __APP_PLL_LCLK_LOGIC_SOFT_RESET,
0393             rb + APP_PLL_LCLK_CTL_REG);
0394     udelay(2000);
0395     writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
0396     writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
0397     writel(pll_sclk, (rb + APP_PLL_SCLK_CTL_REG));
0398     writel(pll_fclk, (rb + APP_PLL_LCLK_CTL_REG));
0399
0400     return BFA_STATUS_OK;
0401 }