scsi/bfa/bfa_hw_ct.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
0004  * Copyright (c) 2014- QLogic Corporation.
0005  * All rights reserved
0006  * www.qlogic.com
0007  *
0008  * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
0009  */
0010
0011 #include "bfad_drv.h"
0012 #include "bfa_modules.h"
0013 #include "bfi_reg.h"
0014
0015 BFA_TRC_FILE(HAL, IOCFC_CT);
0016
0017 /*
0018  * Dummy interrupt handler for handling spurious interrupt during chip-reinit.
0019  */
0020 static void
0021 bfa_hwct_msix_dummy(struct bfa_s *bfa, int vec)
0022 {
0023 }
0024
0025 void
0026 bfa_hwct_reginit(struct bfa_s *bfa)
0027 {
0028     struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
0029     void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
0030     int fn = bfa_ioc_pcifn(&bfa->ioc);
0031
0032     if (fn == 0) {
0033         bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS);
0034         bfa_regs->intr_mask   = (kva + HOSTFN0_INT_MSK);
0035     } else {
0036         bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS);
0037         bfa_regs->intr_mask   = (kva + HOSTFN1_INT_MSK);
0038     }
0039 }
0040
0041 void
0042 bfa_hwct2_reginit(struct bfa_s *bfa)
0043 {
0044     struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
0045     void __iomem    *kva = bfa_ioc_bar0(&bfa->ioc);
0046
0047     bfa_regs->intr_status = (kva + CT2_HOSTFN_INT_STATUS);
0048     bfa_regs->intr_mask   = (kva + CT2_HOSTFN_INTR_MASK);
0049 }
0050
0051 void
0052 bfa_hwct_reqq_ack(struct bfa_s *bfa, int reqq)
0053 {
0054     u32 r32;
0055
0056     r32 = readl(bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
0057     writel(r32, bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
0058 }
0059
0060 /*
0061  * Actions to respond RME Interrupt for Catapult ASIC:
0062  * - Write 1 to Interrupt Status register (INTx only - done in bfa_intx())
0063  * - Acknowledge by writing to RME Queue Control register
0064  * - Update CI
0065  */
0066 void
0067 bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci)
0068 {
0069     u32 r32;
0070
0071     r32 = readl(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
0072     writel(r32, bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
0073
0074     bfa_rspq_ci(bfa, rspq) = ci;
0075     writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]);
0076 }
0077
0078 /*
0079  * Actions to respond RME Interrupt for Catapult2 ASIC:
0080  * - Write 1 to Interrupt Status register (INTx only - done in bfa_intx())
0081  * - Update CI
0082  */
0083 void
0084 bfa_hwct2_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci)
0085 {
0086     bfa_rspq_ci(bfa, rspq) = ci;
0087     writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]);
0088 }
0089
0090 void
0091 bfa_hwct_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap,
0092          u32 *num_vecs, u32 *max_vec_bit)
0093 {
0094     *msix_vecs_bmap = (1 << BFI_MSIX_CT_MAX) - 1;
0095     *max_vec_bit = (1 << (BFI_MSIX_CT_MAX - 1));
0096     *num_vecs = BFI_MSIX_CT_MAX;
0097 }
0098
0099 /*
0100  * Setup MSI-X vector for catapult
0101  */
0102 void
0103 bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs)
0104 {
0105     WARN_ON((nvecs != 1) && (nvecs != BFI_MSIX_CT_MAX));
0106     bfa_trc(bfa, nvecs);
0107
0108     bfa->msix.nvecs = nvecs;
0109     bfa_hwct_msix_uninstall(bfa);
0110 }
0111
0112 void
0113 bfa_hwct_msix_ctrl_install(struct bfa_s *bfa)
0114 {
0115     if (bfa->msix.nvecs == 0)
0116         return;
0117
0118     if (bfa->msix.nvecs == 1)
0119         bfa->msix.handler[BFI_MSIX_LPU_ERR_CT] = bfa_msix_all;
0120     else
0121         bfa->msix.handler[BFI_MSIX_LPU_ERR_CT] = bfa_msix_lpu_err;
0122 }
0123
0124 void
0125 bfa_hwct_msix_queue_install(struct bfa_s *bfa)
0126 {
0127     int i;
0128
0129     if (bfa->msix.nvecs == 0)
0130         return;
0131
0132     if (bfa->msix.nvecs == 1) {
0133         for (i = BFI_MSIX_CPE_QMIN_CT; i < BFI_MSIX_CT_MAX; i++)
0134             bfa->msix.handler[i] = bfa_msix_all;
0135         return;
0136     }
0137
0138     for (i = BFI_MSIX_CPE_QMIN_CT; i <= BFI_MSIX_CPE_QMAX_CT; i++)
0139         bfa->msix.handler[i] = bfa_msix_reqq;
0140
0141     for (i = BFI_MSIX_RME_QMIN_CT; i <= BFI_MSIX_RME_QMAX_CT; i++)
0142         bfa->msix.handler[i] = bfa_msix_rspq;
0143 }
0144
0145 void
0146 bfa_hwct_msix_uninstall(struct bfa_s *bfa)
0147 {
0148     int i;
0149
0150     for (i = 0; i < BFI_MSIX_CT_MAX; i++)
0151         bfa->msix.handler[i] = bfa_hwct_msix_dummy;
0152 }
0153
0154 /*
0155  * Enable MSI-X vectors
0156  */
0157 void
0158 bfa_hwct_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix)
0159 {
0160     bfa_trc(bfa, 0);
0161     bfa_ioc_isr_mode_set(&bfa->ioc, msix);
0162 }
0163
0164 void
0165 bfa_hwct_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end)
0166 {
0167     *start = BFI_MSIX_RME_QMIN_CT;
0168     *end = BFI_MSIX_RME_QMAX_CT;
0169 }