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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright 2017 Broadcom. All Rights Reserved.
0004  * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries.
0005  *
0006  * Contact Information:
0007  * linux-drivers@broadcom.com
0008  */
0009 
0010 #ifndef _BEISCSI_MAIN_
0011 #define _BEISCSI_MAIN_
0012 
0013 #include <linux/kernel.h>
0014 #include <linux/pci.h>
0015 #include <linux/if_ether.h>
0016 #include <linux/in.h>
0017 #include <linux/ctype.h>
0018 #include <linux/module.h>
0019 #include <linux/aer.h>
0020 #include <scsi/scsi.h>
0021 #include <scsi/scsi_cmnd.h>
0022 #include <scsi/scsi_device.h>
0023 #include <scsi/scsi_host.h>
0024 #include <scsi/iscsi_proto.h>
0025 #include <scsi/libiscsi.h>
0026 #include <scsi/scsi_transport_iscsi.h>
0027 
0028 #define DRV_NAME        "be2iscsi"
0029 #define BUILD_STR       "11.4.0.1"
0030 #define BE_NAME         "Emulex OneConnect" \
0031                 "Open-iSCSI Driver version" BUILD_STR
0032 #define DRV_DESC        BE_NAME " " "Driver"
0033 
0034 #define BE_VENDOR_ID        0x19A2
0035 #define ELX_VENDOR_ID       0x10DF
0036 /* DEVICE ID's for BE2 */
0037 #define BE_DEVICE_ID1       0x212
0038 #define OC_DEVICE_ID1       0x702
0039 #define OC_DEVICE_ID2       0x703
0040 
0041 /* DEVICE ID's for BE3 */
0042 #define BE_DEVICE_ID2       0x222
0043 #define OC_DEVICE_ID3       0x712
0044 
0045 /* DEVICE ID for SKH */
0046 #define OC_SKH_ID1      0x722
0047 
0048 #define BE2_IO_DEPTH        1024
0049 #define BE2_MAX_SESSIONS    256
0050 #define BE2_TMFS        16
0051 #define BE2_NOPOUT_REQ      16
0052 #define BE2_SGE         32
0053 #define BE2_DEFPDU_HDR_SZ   64
0054 #define BE2_DEFPDU_DATA_SZ  8192
0055 #define BE2_MAX_NUM_CQ_PROC 512
0056 
0057 #define MAX_CPUS        64U
0058 #define BEISCSI_MAX_NUM_CPUS    7
0059 
0060 #define BEISCSI_VER_STRLEN 32
0061 
0062 #define BEISCSI_SGLIST_ELEMENTS 30
0063 
0064 /**
0065  * BE_INVLDT_CMD_TBL_SZ is 128 which is total number commands that can
0066  * be invalidated at a time, consider it before changing the value of
0067  * BEISCSI_CMD_PER_LUN.
0068  */
0069 #define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
0070 #define BEISCSI_MAX_SECTORS 1024    /* scsi_host->max_sectors */
0071 #define BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE 128 /* Template size per cxn */
0072 
0073 #define BEISCSI_MAX_CMD_LEN 16  /* scsi_host->max_cmd_len */
0074 #define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
0075 #define BEISCSI_MAX_FRAGS_INIT  192
0076 
0077 #define BE_SENSE_INFO_SIZE      258
0078 #define BE_ISCSI_PDU_HEADER_SIZE    64
0079 #define BE_MIN_MEM_SIZE         16384
0080 #define MAX_CMD_SZ          65536
0081 #define IIOC_SCSI_DATA                  0x05    /* Write Operation */
0082 
0083 /**
0084  * hardware needs the async PDU buffers to be posted in multiples of 8
0085  * So have atleast 8 of them by default
0086  */
0087 
0088 #define HWI_GET_ASYNC_PDU_CTX(phwi, ulp_num)    \
0089     (phwi->phwi_ctxt->pasync_ctx[ulp_num])
0090 
0091 /********* Memory BAR register ************/
0092 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET  0xfc
0093 /**
0094  * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
0095  * Disable" may still globally block interrupts in addition to individual
0096  * interrupt masks; a mechanism for the device driver to block all interrupts
0097  * atomically without having to arbitrate for the PCI Interrupt Disable bit
0098  * with the OS.
0099  */
0100 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK  (1 << 29)   /* bit 29 */
0101 
0102 /********* ISR0 Register offset **********/
0103 #define CEV_ISR0_OFFSET             0xC18
0104 #define CEV_ISR_SIZE                4
0105 
0106 /**
0107  * Macros for reading/writing a protection domain or CSR registers
0108  * in BladeEngine.
0109  */
0110 
0111 #define DB_TXULP0_OFFSET 0x40
0112 #define DB_RXULP0_OFFSET 0xA0
0113 /********* Event Q door bell *************/
0114 #define DB_EQ_OFFSET            DB_CQ_OFFSET
0115 #define DB_EQ_RING_ID_LOW_MASK      0x1FF   /* bits 0 - 8 */
0116 /* Clear the interrupt for this eq */
0117 #define DB_EQ_CLR_SHIFT         (9) /* bit 9 */
0118 /* Must be 1 */
0119 #define DB_EQ_EVNT_SHIFT        (10)    /* bit 10 */
0120 /* Higher Order EQ_ID bit */
0121 #define DB_EQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
0122 #define DB_EQ_HIGH_SET_SHIFT    11
0123 #define DB_EQ_HIGH_FEILD_SHIFT  9
0124 /* Number of event entries processed */
0125 #define DB_EQ_NUM_POPPED_SHIFT      (16)    /* bits 16 - 28 */
0126 /* Rearm bit */
0127 #define DB_EQ_REARM_SHIFT       (29)    /* bit 29 */
0128 
0129 /********* Compl Q door bell *************/
0130 #define DB_CQ_OFFSET            0x120
0131 #define DB_CQ_RING_ID_LOW_MASK      0x3FF   /* bits 0 - 9 */
0132 /* Higher Order CQ_ID bit */
0133 #define DB_CQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
0134 #define DB_CQ_HIGH_SET_SHIFT    11
0135 #define DB_CQ_HIGH_FEILD_SHIFT  10
0136 
0137 /* Number of event entries processed */
0138 #define DB_CQ_NUM_POPPED_SHIFT      (16)    /* bits 16 - 28 */
0139 /* Rearm bit */
0140 #define DB_CQ_REARM_SHIFT       (29)    /* bit 29 */
0141 
0142 #define GET_HWI_CONTROLLER_WS(pc)   (pc->phwi_ctrlr)
0143 #define HWI_GET_DEF_BUFQ_ID(pc, ulp_num) (((struct hwi_controller *)\
0144         (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data[ulp_num].id)
0145 #define HWI_GET_DEF_HDRQ_ID(pc, ulp_num) (((struct hwi_controller *)\
0146         (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr[ulp_num].id)
0147 
0148 #define PAGES_REQUIRED(x) \
0149     ((x < PAGE_SIZE) ? 1 :  ((x + PAGE_SIZE - 1) / PAGE_SIZE))
0150 
0151 #define MEM_DESCR_OFFSET 8
0152 #define BEISCSI_DEFQ_HDR 1
0153 #define BEISCSI_DEFQ_DATA 0
0154 enum be_mem_enum {
0155     HWI_MEM_ADDN_CONTEXT,
0156     HWI_MEM_WRB,
0157     HWI_MEM_WRBH,
0158     HWI_MEM_SGLH,
0159     HWI_MEM_SGE,
0160     HWI_MEM_TEMPLATE_HDR_ULP0,
0161     HWI_MEM_ASYNC_HEADER_BUF_ULP0,  /* 6 */
0162     HWI_MEM_ASYNC_DATA_BUF_ULP0,
0163     HWI_MEM_ASYNC_HEADER_RING_ULP0,
0164     HWI_MEM_ASYNC_DATA_RING_ULP0,
0165     HWI_MEM_ASYNC_HEADER_HANDLE_ULP0,
0166     HWI_MEM_ASYNC_DATA_HANDLE_ULP0, /* 11 */
0167     HWI_MEM_ASYNC_PDU_CONTEXT_ULP0,
0168     HWI_MEM_TEMPLATE_HDR_ULP1,
0169     HWI_MEM_ASYNC_HEADER_BUF_ULP1,  /* 14 */
0170     HWI_MEM_ASYNC_DATA_BUF_ULP1,
0171     HWI_MEM_ASYNC_HEADER_RING_ULP1,
0172     HWI_MEM_ASYNC_DATA_RING_ULP1,
0173     HWI_MEM_ASYNC_HEADER_HANDLE_ULP1,
0174     HWI_MEM_ASYNC_DATA_HANDLE_ULP1, /* 19 */
0175     HWI_MEM_ASYNC_PDU_CONTEXT_ULP1,
0176     ISCSI_MEM_GLOBAL_HEADER,
0177     SE_MEM_MAX
0178 };
0179 
0180 struct be_bus_address32 {
0181     unsigned int address_lo;
0182     unsigned int address_hi;
0183 };
0184 
0185 struct be_bus_address64 {
0186     unsigned long long address;
0187 };
0188 
0189 struct be_bus_address {
0190     union {
0191         struct be_bus_address32 a32;
0192         struct be_bus_address64 a64;
0193     } u;
0194 };
0195 
0196 struct mem_array {
0197     struct be_bus_address bus_address;  /* Bus address of location */
0198     void *virtual_address;      /* virtual address to the location */
0199     unsigned int size;      /* Size required by memory block */
0200 };
0201 
0202 struct be_mem_descriptor {
0203     unsigned int size_in_bytes; /* Size required by memory block */
0204     unsigned int num_elements;
0205     struct mem_array *mem_array;
0206 };
0207 
0208 struct sgl_handle {
0209     unsigned int sgl_index;
0210     unsigned int type;
0211     unsigned int cid;
0212     struct iscsi_task *task;
0213     struct iscsi_sge *pfrag;
0214 };
0215 
0216 struct hba_parameters {
0217     unsigned int ios_per_ctrl;
0218     unsigned int cxns_per_ctrl;
0219     unsigned int icds_per_ctrl;
0220     unsigned int num_sge_per_io;
0221     unsigned int defpdu_hdr_sz;
0222     unsigned int defpdu_data_sz;
0223     unsigned int num_cq_entries;
0224     unsigned int num_eq_entries;
0225     unsigned int wrbs_per_cxn;
0226     unsigned int hwi_ws_sz;
0227 };
0228 
0229 #define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \
0230     (phwi_ctrlr->wrb_context[cri].ulp_num)
0231 struct hwi_wrb_context {
0232     spinlock_t wrb_lock;
0233     struct wrb_handle **pwrb_handle_base;
0234     struct wrb_handle **pwrb_handle_basestd;
0235     struct iscsi_wrb *plast_wrb;
0236     unsigned short alloc_index;
0237     unsigned short free_index;
0238     unsigned short wrb_handles_available;
0239     unsigned short cid;
0240     uint8_t ulp_num;    /* ULP to which CID binded */
0241     uint32_t doorbell_offset;
0242 };
0243 
0244 struct ulp_cid_info {
0245     unsigned short *cid_array;
0246     unsigned short avlbl_cids;
0247     unsigned short cid_alloc;
0248     unsigned short cid_free;
0249 };
0250 
0251 #include "be.h"
0252 #define chip_be2(phba)      (phba->generation == BE_GEN2)
0253 #define chip_be3_r(phba)    (phba->generation == BE_GEN3)
0254 #define is_chip_be2_be3r(phba) (chip_be3_r(phba) || (chip_be2(phba)))
0255 
0256 #define BEISCSI_ULP0    0
0257 #define BEISCSI_ULP1    1
0258 #define BEISCSI_ULP_COUNT   2
0259 #define BEISCSI_ULP0_LOADED 0x01
0260 #define BEISCSI_ULP1_LOADED 0x02
0261 
0262 #define BEISCSI_ULP_AVLBL_CID(phba, ulp_num) \
0263     (((struct ulp_cid_info *)phba->cid_array_info[ulp_num])->avlbl_cids)
0264 #define BEISCSI_ULP0_AVLBL_CID(phba) \
0265     BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP0)
0266 #define BEISCSI_ULP1_AVLBL_CID(phba) \
0267     BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP1)
0268 
0269 struct beiscsi_hba {
0270     struct hba_parameters params;
0271     struct hwi_controller *phwi_ctrlr;
0272     unsigned int mem_req[SE_MEM_MAX];
0273     /* PCI BAR mapped addresses */
0274     u8 __iomem *csr_va; /* CSR */
0275     u8 __iomem *db_va;  /* Door  Bell  */
0276     u8 __iomem *pci_va; /* PCI Config */
0277     /* PCI representation of our HBA */
0278     struct pci_dev *pcidev;
0279     unsigned int num_cpus;
0280     unsigned int nxt_cqid;
0281     char *msi_name[MAX_CPUS];
0282     struct be_mem_descriptor *init_mem;
0283 
0284     unsigned short io_sgl_alloc_index;
0285     unsigned short io_sgl_free_index;
0286     unsigned short io_sgl_hndl_avbl;
0287     struct sgl_handle **io_sgl_hndl_base;
0288 
0289     unsigned short eh_sgl_alloc_index;
0290     unsigned short eh_sgl_free_index;
0291     unsigned short eh_sgl_hndl_avbl;
0292     struct sgl_handle **eh_sgl_hndl_base;
0293     spinlock_t io_sgl_lock;
0294     spinlock_t mgmt_sgl_lock;
0295     spinlock_t async_pdu_lock;
0296     struct list_head hba_queue;
0297 #define BE_MAX_SESSION 2048
0298 #define BE_INVALID_CID 0xffff
0299 #define BE_SET_CID_TO_CRI(cri_index, cid) \
0300               (phba->cid_to_cri_map[cid] = cri_index)
0301 #define BE_GET_CRI_FROM_CID(cid) (phba->cid_to_cri_map[cid])
0302     unsigned short cid_to_cri_map[BE_MAX_SESSION];
0303     struct ulp_cid_info *cid_array_info[BEISCSI_ULP_COUNT];
0304     struct iscsi_endpoint **ep_array;
0305     struct beiscsi_conn **conn_table;
0306     struct Scsi_Host *shost;
0307     struct iscsi_iface *ipv4_iface;
0308     struct iscsi_iface *ipv6_iface;
0309     struct {
0310         /**
0311          * group together since they are used most frequently
0312          * for cid to cri conversion
0313          */
0314 #define BEISCSI_PHYS_PORT_MAX   4
0315         unsigned int phys_port;
0316         /* valid values of phys_port id are 0, 1, 2, 3 */
0317         unsigned int eqid_count;
0318         unsigned int cqid_count;
0319         unsigned int iscsi_cid_start[BEISCSI_ULP_COUNT];
0320 #define BEISCSI_GET_CID_COUNT(phba, ulp_num) \
0321         (phba->fw_config.iscsi_cid_count[ulp_num])
0322         unsigned int iscsi_cid_count[BEISCSI_ULP_COUNT];
0323         unsigned int iscsi_icd_count[BEISCSI_ULP_COUNT];
0324         unsigned int iscsi_icd_start[BEISCSI_ULP_COUNT];
0325         unsigned int iscsi_chain_start[BEISCSI_ULP_COUNT];
0326         unsigned int iscsi_chain_count[BEISCSI_ULP_COUNT];
0327 
0328         unsigned short iscsi_features;
0329         uint16_t dual_ulp_aware;
0330         unsigned long ulp_supported;
0331     } fw_config;
0332 
0333     unsigned long state;
0334 #define BEISCSI_HBA_ONLINE  0
0335 #define BEISCSI_HBA_LINK_UP 1
0336 #define BEISCSI_HBA_BOOT_FOUND  2
0337 #define BEISCSI_HBA_BOOT_WORK   3
0338 #define BEISCSI_HBA_UER_SUPP    4
0339 #define BEISCSI_HBA_PCI_ERR 5
0340 #define BEISCSI_HBA_FW_TIMEOUT  6
0341 #define BEISCSI_HBA_IN_UE   7
0342 #define BEISCSI_HBA_IN_TPE  8
0343 
0344 /* error bits */
0345 #define BEISCSI_HBA_IN_ERR  ((1 << BEISCSI_HBA_PCI_ERR) | \
0346                  (1 << BEISCSI_HBA_FW_TIMEOUT) | \
0347                  (1 << BEISCSI_HBA_IN_UE) | \
0348                  (1 << BEISCSI_HBA_IN_TPE))
0349 
0350     u8 optic_state;
0351     struct delayed_work eqd_update;
0352     /* update EQ delay timer every 1000ms */
0353 #define BEISCSI_EQD_UPDATE_INTERVAL 1000
0354     struct timer_list hw_check;
0355     /* check for UE every 1000ms */
0356 #define BEISCSI_UE_DETECT_INTERVAL  1000
0357     u32 ue2rp;
0358     struct delayed_work recover_port;
0359     struct work_struct sess_work;
0360 
0361     bool mac_addr_set;
0362     u8 mac_address[ETH_ALEN];
0363     u8 port_name;
0364     u8 port_speed;
0365     char fw_ver_str[BEISCSI_VER_STRLEN];
0366     struct workqueue_struct *wq;    /* The actuak work queue */
0367     struct be_ctrl_info ctrl;
0368     unsigned int generation;
0369     unsigned int interface_handle;
0370 
0371     struct be_aic_obj aic_obj[MAX_CPUS];
0372     unsigned int attr_log_enable;
0373     int (*iotask_fn)(struct iscsi_task *,
0374             struct scatterlist *sg,
0375             uint32_t num_sg, uint32_t xferlen,
0376             uint32_t writedir);
0377     struct boot_struct {
0378         int retry;
0379         unsigned int tag;
0380         unsigned int s_handle;
0381         struct be_dma_mem nonemb_cmd;
0382         enum {
0383             BEISCSI_BOOT_REOPEN_SESS = 1,
0384             BEISCSI_BOOT_GET_SHANDLE,
0385             BEISCSI_BOOT_GET_SINFO,
0386             BEISCSI_BOOT_LOGOUT_SESS,
0387             BEISCSI_BOOT_CREATE_KSET,
0388         } action;
0389         struct mgmt_session_info boot_sess;
0390         struct iscsi_boot_kset *boot_kset;
0391     } boot_struct;
0392     struct work_struct boot_work;
0393 };
0394 
0395 #define beiscsi_hba_in_error(phba) ((phba)->state & BEISCSI_HBA_IN_ERR)
0396 #define beiscsi_hba_is_online(phba) \
0397     (!beiscsi_hba_in_error((phba)) && \
0398      test_bit(BEISCSI_HBA_ONLINE, &phba->state))
0399 
0400 struct beiscsi_session {
0401     struct dma_pool *bhs_pool;
0402 };
0403 
0404 /**
0405  * struct beiscsi_conn - iscsi connection structure
0406  */
0407 struct beiscsi_conn {
0408     struct iscsi_conn *conn;
0409     struct beiscsi_hba *phba;
0410     u32 exp_statsn;
0411     u32 doorbell_offset;
0412     u32 beiscsi_conn_cid;
0413     struct beiscsi_endpoint *ep;
0414     unsigned short login_in_progress;
0415     struct wrb_handle *plogin_wrb_handle;
0416     struct sgl_handle *plogin_sgl_handle;
0417     struct beiscsi_session *beiscsi_sess;
0418     struct iscsi_task *task;
0419 };
0420 
0421 /* This structure is used by the chip */
0422 struct pdu_data_out {
0423     u32 dw[12];
0424 };
0425 /**
0426  * Pseudo amap definition in which each bit of the actual structure is defined
0427  * as a byte: used to calculate offset/shift/mask of each field
0428  */
0429 struct amap_pdu_data_out {
0430     u8 opcode[6];       /* opcode */
0431     u8 rsvd0[2];        /* should be 0 */
0432     u8 rsvd1[7];
0433     u8 final_bit;       /* F bit */
0434     u8 rsvd2[16];
0435     u8 ahs_length[8];   /* no AHS */
0436     u8 data_len_hi[8];
0437     u8 data_len_lo[16]; /* DataSegmentLength */
0438     u8 lun[64];
0439     u8 itt[32];     /* ITT; initiator task tag */
0440     u8 ttt[32];     /* TTT; valid for R2T or 0xffffffff */
0441     u8 rsvd3[32];
0442     u8 exp_stat_sn[32];
0443     u8 rsvd4[32];
0444     u8 data_sn[32];
0445     u8 buffer_offset[32];
0446     u8 rsvd5[32];
0447 };
0448 
0449 struct be_cmd_bhs {
0450     struct iscsi_scsi_req iscsi_hdr;
0451     unsigned char pad1[16];
0452     struct pdu_data_out iscsi_data_pdu;
0453     unsigned char pad2[BE_SENSE_INFO_SIZE -
0454             sizeof(struct pdu_data_out)];
0455 };
0456 
0457 struct beiscsi_io_task {
0458     struct wrb_handle *pwrb_handle;
0459     struct sgl_handle *psgl_handle;
0460     struct beiscsi_conn *conn;
0461     struct scsi_cmnd *scsi_cmnd;
0462     int num_sg;
0463     struct hwi_wrb_context *pwrb_context;
0464     itt_t libiscsi_itt;
0465     struct be_cmd_bhs *cmd_bhs;
0466     struct be_bus_address bhs_pa;
0467     unsigned short bhs_len;
0468     dma_addr_t mtask_addr;
0469     uint32_t mtask_data_count;
0470     uint8_t wrb_type;
0471 };
0472 
0473 struct be_nonio_bhs {
0474     struct iscsi_hdr iscsi_hdr;
0475     unsigned char pad1[16];
0476     struct pdu_data_out iscsi_data_pdu;
0477     unsigned char pad2[BE_SENSE_INFO_SIZE -
0478             sizeof(struct pdu_data_out)];
0479 };
0480 
0481 struct be_status_bhs {
0482     struct iscsi_scsi_req iscsi_hdr;
0483     unsigned char pad1[16];
0484     /**
0485      * The plus 2 below is to hold the sense info length that gets
0486      * DMA'ed by RxULP
0487      */
0488     unsigned char sense_info[BE_SENSE_INFO_SIZE];
0489 };
0490 
0491 struct iscsi_sge {
0492     u32 dw[4];
0493 };
0494 
0495 /**
0496  * Pseudo amap definition in which each bit of the actual structure is defined
0497  * as a byte: used to calculate offset/shift/mask of each field
0498  */
0499 struct amap_iscsi_sge {
0500     u8 addr_hi[32];
0501     u8 addr_lo[32];
0502     u8 sge_offset[22];  /* DWORD 2 */
0503     u8 rsvd0[9];        /* DWORD 2 */
0504     u8 last_sge;        /* DWORD 2 */
0505     u8 len[17];     /* DWORD 3 */
0506     u8 rsvd1[15];       /* DWORD 3 */
0507 };
0508 
0509 struct beiscsi_offload_params {
0510     u32 dw[6];
0511 };
0512 
0513 #define OFFLD_PARAMS_ERL    0x00000003
0514 #define OFFLD_PARAMS_DDE    0x00000004
0515 #define OFFLD_PARAMS_HDE    0x00000008
0516 #define OFFLD_PARAMS_IR2T   0x00000010
0517 #define OFFLD_PARAMS_IMD    0x00000020
0518 #define OFFLD_PARAMS_DATA_SEQ_INORDER   0x00000040
0519 #define OFFLD_PARAMS_PDU_SEQ_INORDER    0x00000080
0520 #define OFFLD_PARAMS_MAX_R2T 0x00FFFF00
0521 
0522 /**
0523  * Pseudo amap definition in which each bit of the actual structure is defined
0524  * as a byte: used to calculate offset/shift/mask of each field
0525  */
0526 struct amap_beiscsi_offload_params {
0527     u8 max_burst_length[32];
0528     u8 max_send_data_segment_length[32];
0529     u8 first_burst_length[32];
0530     u8 erl[2];
0531     u8 dde[1];
0532     u8 hde[1];
0533     u8 ir2t[1];
0534     u8 imd[1];
0535     u8 data_seq_inorder[1];
0536     u8 pdu_seq_inorder[1];
0537     u8 max_r2t[16];
0538     u8 pad[8];
0539     u8 exp_statsn[32];
0540     u8 max_recv_data_segment_length[32];
0541 };
0542 
0543 struct hd_async_handle {
0544     struct list_head link;
0545     struct be_bus_address pa;
0546     void *pbuffer;
0547     u32 buffer_len;
0548     u16 index;
0549     u16 cri;
0550     u8 is_header;
0551     u8 is_final;
0552     u8 in_use;
0553 };
0554 
0555 #define BEISCSI_ASYNC_HDQ_SIZE(phba, ulp) \
0556     (BEISCSI_GET_CID_COUNT((phba), (ulp)) * 2)
0557 
0558 /**
0559  * This has list of async PDUs that are waiting to be processed.
0560  * Buffers live in this list for a brief duration before they get
0561  * processed and posted back to hardware.
0562  * Note that we don't really need one cri_wait_queue per async_entry.
0563  * We need one cri_wait_queue per CRI. Its easier to manage if this
0564  * is tagged along with the async_entry.
0565  */
0566 struct hd_async_entry {
0567     struct cri_wait_queue {
0568         unsigned short hdr_len;
0569         unsigned int bytes_received;
0570         unsigned int bytes_needed;
0571         struct list_head list;
0572     } wq;
0573     /* handles posted to FW resides here */
0574     struct hd_async_handle *header;
0575     struct hd_async_handle *data;
0576 };
0577 
0578 struct hd_async_buf_context {
0579     struct be_bus_address pa_base;
0580     void *va_base;
0581     void *ring_base;
0582     struct hd_async_handle *handle_base;
0583     u32 buffer_size;
0584     u16 pi;
0585 };
0586 
0587 /**
0588  * hd_async_context is declared for each ULP supporting iSCSI function.
0589  */
0590 struct hd_async_context {
0591     struct hd_async_buf_context async_header;
0592     struct hd_async_buf_context async_data;
0593     u16 num_entries;
0594     /**
0595      * When unsol PDU is in, it needs to be chained till all the bytes are
0596      * received and then processing is done. hd_async_entry is created
0597      * based on the cid_count for each ULP. When unsol PDU comes in based
0598      * on the conn_id it needs to be added to the correct async_entry wq.
0599      * Below defined cid_to_async_cri_map is used to reterive the
0600      * async_cri_map for a particular connection.
0601      *
0602      * This array is initialized after beiscsi_create_wrb_rings returns.
0603      *
0604      * - this method takes more memory space, fixed to 2K
0605      * - any support for connections greater than this the array size needs
0606      * to be incremented
0607      */
0608 #define BE_GET_ASYNC_CRI_FROM_CID(cid) (pasync_ctx->cid_to_async_cri_map[cid])
0609     unsigned short cid_to_async_cri_map[BE_MAX_SESSION];
0610     /**
0611      * This is a variable size array. Don`t add anything after this field!!
0612      */
0613     struct hd_async_entry *async_entry;
0614 };
0615 
0616 struct i_t_dpdu_cqe {
0617     u32 dw[4];
0618 } __packed;
0619 
0620 /**
0621  * Pseudo amap definition in which each bit of the actual structure is defined
0622  * as a byte: used to calculate offset/shift/mask of each field
0623  */
0624 struct amap_i_t_dpdu_cqe {
0625     u8 db_addr_hi[32];
0626     u8 db_addr_lo[32];
0627     u8 code[6];
0628     u8 cid[10];
0629     u8 dpl[16];
0630     u8 index[16];
0631     u8 num_cons[10];
0632     u8 rsvd0[4];
0633     u8 final;
0634     u8 valid;
0635 } __packed;
0636 
0637 struct amap_i_t_dpdu_cqe_v2 {
0638     u8 db_addr_hi[32];  /* DWORD 0 */
0639     u8 db_addr_lo[32];  /* DWORD 1 */
0640     u8 code[6]; /* DWORD 2 */
0641     u8 num_cons; /* DWORD 2*/
0642     u8 rsvd0[8]; /* DWORD 2 */
0643     u8 dpl[17]; /* DWORD 2 */
0644     u8 index[16]; /* DWORD 3 */
0645     u8 cid[13]; /* DWORD 3 */
0646     u8 rsvd1; /* DWORD 3 */
0647     u8 final; /* DWORD 3 */
0648     u8 valid; /* DWORD 3 */
0649 } __packed;
0650 
0651 #define CQE_VALID_MASK  0x80000000
0652 #define CQE_CODE_MASK   0x0000003F
0653 #define CQE_CID_MASK    0x0000FFC0
0654 
0655 #define EQE_VALID_MASK      0x00000001
0656 #define EQE_MAJORCODE_MASK  0x0000000E
0657 #define EQE_RESID_MASK      0xFFFF0000
0658 
0659 struct be_eq_entry {
0660     u32 dw[1];
0661 } __packed;
0662 
0663 /**
0664  * Pseudo amap definition in which each bit of the actual structure is defined
0665  * as a byte: used to calculate offset/shift/mask of each field
0666  */
0667 struct amap_eq_entry {
0668     u8 valid;       /* DWORD 0 */
0669     u8 major_code[3];   /* DWORD 0 */
0670     u8 minor_code[12];  /* DWORD 0 */
0671     u8 resource_id[16]; /* DWORD 0 */
0672 
0673 } __packed;
0674 
0675 struct cq_db {
0676     u32 dw[1];
0677 } __packed;
0678 
0679 /**
0680  * Pseudo amap definition in which each bit of the actual structure is defined
0681  * as a byte: used to calculate offset/shift/mask of each field
0682  */
0683 struct amap_cq_db {
0684     u8 qid[10];
0685     u8 event[1];
0686     u8 rsvd0[5];
0687     u8 num_popped[13];
0688     u8 rearm[1];
0689     u8 rsvd1[2];
0690 } __packed;
0691 
0692 void beiscsi_process_eq(struct beiscsi_hba *phba);
0693 
0694 struct iscsi_wrb {
0695     u32 dw[16];
0696 } __packed;
0697 
0698 #define WRB_TYPE_MASK 0xF0000000
0699 #define SKH_WRB_TYPE_OFFSET 27
0700 #define BE_WRB_TYPE_OFFSET  28
0701 
0702 #define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \
0703         (pwrb->dw[0] |= (wrb_type << type_offset))
0704 
0705 /**
0706  * Pseudo amap definition in which each bit of the actual structure is defined
0707  * as a byte: used to calculate offset/shift/mask of each field
0708  */
0709 struct amap_iscsi_wrb {
0710     u8 lun[14];     /* DWORD 0 */
0711     u8 lt;          /* DWORD 0 */
0712     u8 invld;       /* DWORD 0 */
0713     u8 wrb_idx[8];      /* DWORD 0 */
0714     u8 dsp;         /* DWORD 0 */
0715     u8 dmsg;        /* DWORD 0 */
0716     u8 undr_run;        /* DWORD 0 */
0717     u8 over_run;        /* DWORD 0 */
0718     u8 type[4];     /* DWORD 0 */
0719     u8 ptr2nextwrb[8];  /* DWORD 1 */
0720     u8 r2t_exp_dtl[24]; /* DWORD 1 */
0721     u8 sgl_icd_idx[12]; /* DWORD 2 */
0722     u8 rsvd0[20];       /* DWORD 2 */
0723     u8 exp_data_sn[32]; /* DWORD 3 */
0724     u8 iscsi_bhs_addr_hi[32];   /* DWORD 4 */
0725     u8 iscsi_bhs_addr_lo[32];   /* DWORD 5 */
0726     u8 cmdsn_itt[32];   /* DWORD 6 */
0727     u8 dif_ref_tag[32]; /* DWORD 7 */
0728     u8 sge0_addr_hi[32];    /* DWORD 8 */
0729     u8 sge0_addr_lo[32];    /* DWORD 9  */
0730     u8 sge0_offset[22]; /* DWORD 10 */
0731     u8 pbs;         /* DWORD 10 */
0732     u8 dif_mode[2];     /* DWORD 10 */
0733     u8 rsvd1[6];        /* DWORD 10 */
0734     u8 sge0_last;       /* DWORD 10 */
0735     u8 sge0_len[17];    /* DWORD 11 */
0736     u8 dif_meta_tag[14];    /* DWORD 11 */
0737     u8 sge0_in_ddr;     /* DWORD 11 */
0738     u8 sge1_addr_hi[32];    /* DWORD 12 */
0739     u8 sge1_addr_lo[32];    /* DWORD 13 */
0740     u8 sge1_r2t_offset[22]; /* DWORD 14 */
0741     u8 rsvd2[9];        /* DWORD 14 */
0742     u8 sge1_last;       /* DWORD 14 */
0743     u8 sge1_len[17];    /* DWORD 15 */
0744     u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
0745     u8 rsvd3[2];        /* DWORD 15 */
0746     u8 sge1_in_ddr;     /* DWORD 15 */
0747 
0748 } __packed;
0749 
0750 struct amap_iscsi_wrb_v2 {
0751     u8 r2t_exp_dtl[25]; /* DWORD 0 */
0752     u8 rsvd0[2];    /* DWORD 0*/
0753     u8 type[5];     /* DWORD 0 */
0754     u8 ptr2nextwrb[8];  /* DWORD 1 */
0755     u8 wrb_idx[8];      /* DWORD 1 */
0756     u8 lun[16];     /* DWORD 1 */
0757     u8 sgl_idx[16]; /* DWORD 2 */
0758     u8 ref_sgl_icd_idx[16]; /* DWORD 2 */
0759     u8 exp_data_sn[32]; /* DWORD 3 */
0760     u8 iscsi_bhs_addr_hi[32];   /* DWORD 4 */
0761     u8 iscsi_bhs_addr_lo[32];   /* DWORD 5 */
0762     u8 cq_id[16];   /* DWORD 6 */
0763     u8 rsvd1[16];   /* DWORD 6 */
0764     u8 cmdsn_itt[32];   /* DWORD 7 */
0765     u8 sge0_addr_hi[32];    /* DWORD 8 */
0766     u8 sge0_addr_lo[32];    /* DWORD 9 */
0767     u8 sge0_offset[24]; /* DWORD 10 */
0768     u8 rsvd2[7];    /* DWORD 10 */
0769     u8 sge0_last;   /* DWORD 10 */
0770     u8 sge0_len[17];    /* DWORD 11 */
0771     u8 rsvd3[7];    /* DWORD 11 */
0772     u8 diff_enbl;   /* DWORD 11 */
0773     u8 u_run;       /* DWORD 11 */
0774     u8 o_run;       /* DWORD 11 */
0775     u8 invld;     /* DWORD 11 */
0776     u8 dsp;         /* DWORD 11 */
0777     u8 dmsg;        /* DWORD 11 */
0778     u8 rsvd4;       /* DWORD 11 */
0779     u8 lt;          /* DWORD 11 */
0780     u8 sge1_addr_hi[32];    /* DWORD 12 */
0781     u8 sge1_addr_lo[32];    /* DWORD 13 */
0782     u8 sge1_r2t_offset[24]; /* DWORD 14 */
0783     u8 rsvd5[7];    /* DWORD 14 */
0784     u8 sge1_last;   /* DWORD 14 */
0785     u8 sge1_len[17];    /* DWORD 15 */
0786     u8 rsvd6[15];   /* DWORD 15 */
0787 } __packed;
0788 
0789 
0790 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid,
0791                      struct hwi_wrb_context **pcontext);
0792 void
0793 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
0794 
0795 void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
0796                      struct iscsi_task *task);
0797 
0798 void hwi_ring_cq_db(struct beiscsi_hba *phba,
0799              unsigned int id, unsigned int num_processed,
0800              unsigned char rearm);
0801 
0802 unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq, int budget);
0803 void beiscsi_process_mcc_cq(struct beiscsi_hba *phba);
0804 
0805 struct pdu_nop_out {
0806     u32 dw[12];
0807 };
0808 
0809 /**
0810  * Pseudo amap definition in which each bit of the actual structure is defined
0811  * as a byte: used to calculate offset/shift/mask of each field
0812  */
0813 struct amap_pdu_nop_out {
0814     u8 opcode[6];       /* opcode 0x00 */
0815     u8 i_bit;       /* I Bit */
0816     u8 x_bit;       /* reserved; should be 0 */
0817     u8 fp_bit_filler1[7];
0818     u8 f_bit;       /* always 1 */
0819     u8 reserved1[16];
0820     u8 ahs_length[8];   /* no AHS */
0821     u8 data_len_hi[8];
0822     u8 data_len_lo[16]; /* DataSegmentLength */
0823     u8 lun[64];
0824     u8 itt[32];     /* initiator id for ping or 0xffffffff */
0825     u8 ttt[32];     /* target id for ping or 0xffffffff */
0826     u8 cmd_sn[32];
0827     u8 exp_stat_sn[32];
0828     u8 reserved5[128];
0829 };
0830 
0831 #define PDUBASE_OPCODE_MASK 0x0000003F
0832 #define PDUBASE_DATALENHI_MASK  0x0000FF00
0833 #define PDUBASE_DATALENLO_MASK  0xFFFF0000
0834 
0835 struct pdu_base {
0836     u32 dw[16];
0837 } __packed;
0838 
0839 /**
0840  * Pseudo amap definition in which each bit of the actual structure is defined
0841  * as a byte: used to calculate offset/shift/mask of each field
0842  */
0843 struct amap_pdu_base {
0844     u8 opcode[6];
0845     u8 i_bit;       /* immediate bit */
0846     u8 x_bit;       /* reserved, always 0 */
0847     u8 reserved1[24];   /* opcode-specific fields */
0848     u8 ahs_length[8];   /* length units is 4 byte words */
0849     u8 data_len_hi[8];
0850     u8 data_len_lo[16]; /* DatasegmentLength */
0851     u8 lun[64];     /* lun or opcode-specific fields */
0852     u8 itt[32];     /* initiator task tag */
0853     u8 reserved4[224];
0854 };
0855 
0856 struct iscsi_target_context_update_wrb {
0857     u32 dw[16];
0858 } __packed;
0859 
0860 /**
0861  * Pseudo amap definition in which each bit of the actual structure is defined
0862  * as a byte: used to calculate offset/shift/mask of each field
0863  */
0864 #define BE_TGT_CTX_UPDT_CMD 0x07
0865 struct amap_iscsi_target_context_update_wrb {
0866     u8 lun[14];     /* DWORD 0 */
0867     u8 lt;          /* DWORD 0 */
0868     u8 invld;       /* DWORD 0 */
0869     u8 wrb_idx[8];      /* DWORD 0 */
0870     u8 dsp;         /* DWORD 0 */
0871     u8 dmsg;        /* DWORD 0 */
0872     u8 undr_run;        /* DWORD 0 */
0873     u8 over_run;        /* DWORD 0 */
0874     u8 type[4];     /* DWORD 0 */
0875     u8 ptr2nextwrb[8];  /* DWORD 1 */
0876     u8 max_burst_length[19];    /* DWORD 1 */
0877     u8 rsvd0[5];        /* DWORD 1 */
0878     u8 rsvd1[15];       /* DWORD 2 */
0879     u8 max_send_data_segment_length[17];    /* DWORD 2 */
0880     u8 first_burst_length[14];  /* DWORD 3 */
0881     u8 rsvd2[2];        /* DWORD 3 */
0882     u8 tx_wrbindex_drv_msg[8];  /* DWORD 3 */
0883     u8 rsvd3[5];        /* DWORD 3 */
0884     u8 session_state[3];    /* DWORD 3 */
0885     u8 rsvd4[16];       /* DWORD 4 */
0886     u8 tx_jumbo;        /* DWORD 4 */
0887     u8 hde;         /* DWORD 4 */
0888     u8 dde;         /* DWORD 4 */
0889     u8 erl[2];      /* DWORD 4 */
0890     u8 domain_id[5];        /* DWORD 4 */
0891     u8 mode;        /* DWORD 4 */
0892     u8 imd;         /* DWORD 4 */
0893     u8 ir2t;        /* DWORD 4 */
0894     u8 notpredblq[2];   /* DWORD 4 */
0895     u8 compltonack;     /* DWORD 4 */
0896     u8 stat_sn[32];     /* DWORD 5 */
0897     u8 pad_buffer_addr_hi[32];  /* DWORD 6 */
0898     u8 pad_buffer_addr_lo[32];  /* DWORD 7 */
0899     u8 pad_addr_hi[32]; /* DWORD 8 */
0900     u8 pad_addr_lo[32]; /* DWORD 9 */
0901     u8 rsvd5[32];       /* DWORD 10 */
0902     u8 rsvd6[32];       /* DWORD 11 */
0903     u8 rsvd7[32];       /* DWORD 12 */
0904     u8 rsvd8[32];       /* DWORD 13 */
0905     u8 rsvd9[32];       /* DWORD 14 */
0906     u8 rsvd10[32];      /* DWORD 15 */
0907 
0908 } __packed;
0909 
0910 #define BEISCSI_MAX_RECV_DATASEG_LEN    (64 * 1024)
0911 #define BEISCSI_MAX_CXNS    1
0912 struct amap_iscsi_target_context_update_wrb_v2 {
0913     u8 max_burst_length[24];    /* DWORD 0 */
0914     u8 rsvd0[3];    /* DWORD 0 */
0915     u8 type[5];     /* DWORD 0 */
0916     u8 ptr2nextwrb[8];  /* DWORD 1 */
0917     u8 wrb_idx[8];      /* DWORD 1 */
0918     u8 rsvd1[16];       /* DWORD 1 */
0919     u8 max_send_data_segment_length[24];    /* DWORD 2 */
0920     u8 rsvd2[8];    /* DWORD 2 */
0921     u8 first_burst_length[24]; /* DWORD 3 */
0922     u8 rsvd3[8]; /* DOWRD 3 */
0923     u8 max_r2t[16]; /* DWORD 4 */
0924     u8 rsvd4;       /* DWORD 4 */
0925     u8 hde;         /* DWORD 4 */
0926     u8 dde;         /* DWORD 4 */
0927     u8 erl[2];      /* DWORD 4 */
0928     u8 rsvd5[6];    /* DWORD 4 */
0929     u8 imd;         /* DWORD 4 */
0930     u8 ir2t;        /* DWORD 4 */
0931     u8 rsvd6[3];    /* DWORD 4 */
0932     u8 stat_sn[32];     /* DWORD 5 */
0933     u8 rsvd7[32];   /* DWORD 6 */
0934     u8 rsvd8[32];   /* DWORD 7 */
0935     u8 max_recv_dataseg_len[24];    /* DWORD 8 */
0936     u8 rsvd9[8]; /* DWORD 8 */
0937     u8 rsvd10[32];   /* DWORD 9 */
0938     u8 rsvd11[32];   /* DWORD 10 */
0939     u8 max_cxns[16]; /* DWORD 11 */
0940     u8 rsvd12[11]; /* DWORD  11*/
0941     u8 invld; /* DWORD 11 */
0942     u8 rsvd13;/* DWORD 11*/
0943     u8 dmsg; /* DWORD 11 */
0944     u8 data_seq_inorder; /* DWORD 11 */
0945     u8 pdu_seq_inorder; /* DWORD 11 */
0946     u8 rsvd14[32]; /*DWORD 12 */
0947     u8 rsvd15[32]; /* DWORD 13 */
0948     u8 rsvd16[32]; /* DWORD 14 */
0949     u8 rsvd17[32]; /* DWORD 15 */
0950 } __packed;
0951 
0952 
0953 struct be_ring {
0954     u32 pages;      /* queue size in pages */
0955     u32 id;         /* queue id assigned by beklib */
0956     u32 num;        /* number of elements in queue */
0957     u32 cidx;       /* consumer index */
0958     u32 pidx;       /* producer index -- not used by most rings */
0959     u32 item_size;      /* size in bytes of one object */
0960     u8 ulp_num; /* ULP to which CID binded */
0961     u16 register_set;
0962     u16 doorbell_format;
0963     u32 doorbell_offset;
0964 
0965     void *va;       /* The virtual address of the ring.  This
0966                  * should be last to allow 32 & 64 bit debugger
0967                  * extensions to work.
0968                  */
0969 };
0970 
0971 struct hwi_controller {
0972     struct hwi_wrb_context *wrb_context;
0973     struct be_ring default_pdu_hdr[BEISCSI_ULP_COUNT];
0974     struct be_ring default_pdu_data[BEISCSI_ULP_COUNT];
0975     struct hwi_context_memory *phwi_ctxt;
0976 };
0977 
0978 enum hwh_type_enum {
0979     HWH_TYPE_IO = 1,
0980     HWH_TYPE_LOGOUT = 2,
0981     HWH_TYPE_TMF = 3,
0982     HWH_TYPE_NOP = 4,
0983     HWH_TYPE_IO_RD = 5,
0984     HWH_TYPE_LOGIN = 11,
0985     HWH_TYPE_INVALID = 0xFFFFFFFF
0986 };
0987 
0988 struct wrb_handle {
0989     unsigned short wrb_index;
0990     struct iscsi_task *pio_handle;
0991     struct iscsi_wrb *pwrb;
0992 };
0993 
0994 struct hwi_context_memory {
0995     struct be_eq_obj be_eq[MAX_CPUS];
0996     struct be_queue_info be_cq[MAX_CPUS - 1];
0997 
0998     struct be_queue_info *be_wrbq;
0999     /**
1000      * Create array of ULP number for below entries as DEFQ
1001      * will be created for both ULP if iSCSI Protocol is
1002      * loaded on both ULP.
1003      */
1004     struct be_queue_info be_def_hdrq[BEISCSI_ULP_COUNT];
1005     struct be_queue_info be_def_dataq[BEISCSI_ULP_COUNT];
1006     struct hd_async_context *pasync_ctx[BEISCSI_ULP_COUNT];
1007 };
1008 
1009 void beiscsi_start_boot_work(struct beiscsi_hba *phba, unsigned int s_handle);
1010 
1011 /* Logging related definitions */
1012 #define BEISCSI_LOG_INIT    0x0001  /* Initialization events */
1013 #define BEISCSI_LOG_MBOX    0x0002  /* Mailbox Events */
1014 #define BEISCSI_LOG_MISC    0x0004  /* Miscllaneous Events */
1015 #define BEISCSI_LOG_EH      0x0008  /* Error Handler */
1016 #define BEISCSI_LOG_IO      0x0010  /* IO Code Path */
1017 #define BEISCSI_LOG_CONFIG  0x0020  /* CONFIG Code Path */
1018 #define BEISCSI_LOG_ISCSI   0x0040  /* SCSI/iSCSI Protocol related Logs */
1019 
1020 #define __beiscsi_log(phba, level, fmt, arg...) \
1021     shost_printk(level, phba->shost, fmt, __LINE__, ##arg)
1022 
1023 #define beiscsi_log(phba, level, mask, fmt, arg...) \
1024 do { \
1025     uint32_t log_value = phba->attr_log_enable; \
1026         if (((mask) & log_value) || (level[1] <= '3')) \
1027             __beiscsi_log(phba, level, fmt, ##arg); \
1028 } while (0);
1029 
1030 #endif
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