scsi/arm/acornscsi.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  linux/drivers/acorn/scsi/acornscsi.h
0004  *
0005  *  Copyright (C) 1997 Russell King
0006  *
0007  *  Acorn SCSI driver
0008  */
0009 #ifndef ACORNSCSI_H
0010 #define ACORNSCSI_H
0011
0012 /* SBIC registers */
0013 #define SBIC_OWNID      0
0014 #define OWNID_FS1       (1<<7)
0015 #define OWNID_FS2       (1<<6)
0016 #define OWNID_EHP       (1<<4)
0017 #define OWNID_EAF       (1<<3)
0018
0019 #define SBIC_CTRL       1
0020 #define CTRL_DMAMODE        (1<<7)
0021 #define CTRL_DMADBAMODE     (1<<6)
0022 #define CTRL_DMABURST       (1<<5)
0023 #define CTRL_DMAPOLLED      0
0024 #define CTRL_HHP        (1<<4)
0025 #define CTRL_EDI        (1<<3)
0026 #define CTRL_IDI        (1<<2)
0027 #define CTRL_HA         (1<<1)
0028 #define CTRL_HSP        (1<<0)
0029
0030 #define SBIC_TIMEOUT        2
0031 #define SBIC_TOTSECTS       3
0032 #define SBIC_TOTHEADS       4
0033 #define SBIC_TOTCYLH        5
0034 #define SBIC_TOTCYLL        6
0035 #define SBIC_LOGADDRH       7
0036 #define SBIC_LOGADDRM2      8
0037 #define SBIC_LOGADDRM1      9
0038 #define SBIC_LOGADDRL       10
0039 #define SBIC_SECTORNUM      11
0040 #define SBIC_HEADNUM        12
0041 #define SBIC_CYLH       13
0042 #define SBIC_CYLL       14
0043 #define SBIC_TARGETLUN      15
0044 #define TARGETLUN_TLV       (1<<7)
0045 #define TARGETLUN_DOK       (1<<6)
0046
0047 #define SBIC_CMNDPHASE      16
0048 #define SBIC_SYNCHTRANSFER  17
0049 #define SYNCHTRANSFER_OF0   0x00
0050 #define SYNCHTRANSFER_OF1   0x01
0051 #define SYNCHTRANSFER_OF2   0x02
0052 #define SYNCHTRANSFER_OF3   0x03
0053 #define SYNCHTRANSFER_OF4   0x04
0054 #define SYNCHTRANSFER_OF5   0x05
0055 #define SYNCHTRANSFER_OF6   0x06
0056 #define SYNCHTRANSFER_OF7   0x07
0057 #define SYNCHTRANSFER_OF8   0x08
0058 #define SYNCHTRANSFER_OF9   0x09
0059 #define SYNCHTRANSFER_OF10  0x0A
0060 #define SYNCHTRANSFER_OF11  0x0B
0061 #define SYNCHTRANSFER_OF12  0x0C
0062 #define SYNCHTRANSFER_8DBA  0x00
0063 #define SYNCHTRANSFER_2DBA  0x20
0064 #define SYNCHTRANSFER_3DBA  0x30
0065 #define SYNCHTRANSFER_4DBA  0x40
0066 #define SYNCHTRANSFER_5DBA  0x50
0067 #define SYNCHTRANSFER_6DBA  0x60
0068 #define SYNCHTRANSFER_7DBA  0x70
0069
0070 #define SBIC_TRANSCNTH      18
0071 #define SBIC_TRANSCNTM      19
0072 #define SBIC_TRANSCNTL      20
0073 #define SBIC_DESTID     21
0074 #define DESTID_SCC      (1<<7)
0075 #define DESTID_DPD      (1<<6)
0076
0077 #define SBIC_SOURCEID       22
0078 #define SOURCEID_ER     (1<<7)
0079 #define SOURCEID_ES     (1<<6)
0080 #define SOURCEID_DSP        (1<<5)
0081 #define SOURCEID_SIV        (1<<4)
0082
0083 #define SBIC_SSR        23
0084 #define SBIC_CMND       24
0085 #define CMND_RESET      0x00
0086 #define CMND_ABORT      0x01
0087 #define CMND_ASSERTATN      0x02
0088 #define CMND_NEGATEACK      0x03
0089 #define CMND_DISCONNECT     0x04
0090 #define CMND_RESELECT       0x05
0091 #define CMND_SELWITHATN     0x06
0092 #define CMND_SELECT     0x07
0093 #define CMND_SELECTATNTRANSFER  0x08
0094 #define CMND_SELECTTRANSFER 0x09
0095 #define CMND_RESELECTRXDATA 0x0A
0096 #define CMND_RESELECTTXDATA 0x0B
0097 #define CMND_WAITFORSELRECV 0x0C
0098 #define CMND_SENDSTATCMD    0x0D
0099 #define CMND_SENDDISCONNECT 0x0E
0100 #define CMND_SETIDI     0x0F
0101 #define CMND_RECEIVECMD     0x10
0102 #define CMND_RECEIVEDTA     0x11
0103 #define CMND_RECEIVEMSG     0x12
0104 #define CMND_RECEIVEUSP     0x13
0105 #define CMND_SENDCMD        0x14
0106 #define CMND_SENDDATA       0x15
0107 #define CMND_SENDMSG        0x16
0108 #define CMND_SENDUSP        0x17
0109 #define CMND_TRANSLATEADDR  0x18
0110 #define CMND_XFERINFO       0x20
0111 #define CMND_SBT        (1<<7)
0112
0113 #define SBIC_DATA       25
0114 #define SBIC_ASR        26
0115 #define ASR_INT         (1<<7)
0116 #define ASR_LCI         (1<<6)
0117 #define ASR_BSY         (1<<5)
0118 #define ASR_CIP         (1<<4)
0119 #define ASR_PE          (1<<1)
0120 #define ASR_DBR         (1<<0)
0121
0122 /* DMAC registers */
0123 #define DMAC_INIT       0x00
0124 #define INIT_8BIT       (1)
0125
0126 #define DMAC_CHANNEL        0x80
0127 #define CHANNEL_0       0x00
0128 #define CHANNEL_1       0x01
0129 #define CHANNEL_2       0x02
0130 #define CHANNEL_3       0x03
0131
0132 #define DMAC_TXCNTLO        0x01
0133 #define DMAC_TXCNTHI        0x81
0134 #define DMAC_TXADRLO        0x02
0135 #define DMAC_TXADRMD        0x82
0136 #define DMAC_TXADRHI        0x03
0137
0138 #define DMAC_DEVCON0        0x04
0139 #define DEVCON0_AKL     (1<<7)
0140 #define DEVCON0_RQL     (1<<6)
0141 #define DEVCON0_EXW     (1<<5)
0142 #define DEVCON0_ROT     (1<<4)
0143 #define DEVCON0_CMP     (1<<3)
0144 #define DEVCON0_DDMA        (1<<2)
0145 #define DEVCON0_AHLD        (1<<1)
0146 #define DEVCON0_MTM     (1<<0)
0147
0148 #define DMAC_DEVCON1        0x84
0149 #define DEVCON1_WEV     (1<<1)
0150 #define DEVCON1_BHLD        (1<<0)
0151
0152 #define DMAC_MODECON        0x05
0153 #define MODECON_WOED        0x01
0154 #define MODECON_VERIFY      0x00
0155 #define MODECON_READ        0x04
0156 #define MODECON_WRITE       0x08
0157 #define MODECON_AUTOINIT    0x10
0158 #define MODECON_ADDRDIR     0x20
0159 #define MODECON_DEMAND      0x00
0160 #define MODECON_SINGLE      0x40
0161 #define MODECON_BLOCK       0x80
0162 #define MODECON_CASCADE     0xC0
0163
0164 #define DMAC_STATUS     0x85
0165 #define STATUS_TC0      (1<<0)
0166 #define STATUS_RQ0      (1<<4)
0167
0168 #define DMAC_TEMPLO     0x06
0169 #define DMAC_TEMPHI     0x86
0170 #define DMAC_REQREG     0x07
0171 #define DMAC_MASKREG        0x87
0172 #define MASKREG_M0      0x01
0173 #define MASKREG_M1      0x02
0174 #define MASKREG_M2      0x04
0175 #define MASKREG_M3      0x08
0176
0177 /* miscellaneous internal variables */
0178
0179 #define MASK_ON     (MASKREG_M3|MASKREG_M2|MASKREG_M1|MASKREG_M0)
0180 #define MASK_OFF    (MASKREG_M3|MASKREG_M2|MASKREG_M1)
0181
0182 /*
0183  * SCSI driver phases
0184  */
0185 typedef enum {
0186     PHASE_IDLE,                 /* we're not planning on doing anything  */
0187     PHASE_CONNECTING,               /* connecting to a target        */
0188     PHASE_CONNECTED,                /* connected to a target         */
0189     PHASE_MSGOUT,               /* message out to device         */
0190     PHASE_RECONNECTED,              /* reconnected               */
0191     PHASE_COMMANDPAUSED,            /* command partly sent           */
0192     PHASE_COMMAND,              /* command all sent          */
0193     PHASE_DATAOUT,              /* data out to device            */
0194     PHASE_DATAIN,               /* data in from device           */
0195     PHASE_STATUSIN,             /* status in from device         */
0196     PHASE_MSGIN,                /* message in from device        */
0197     PHASE_DONE,                 /* finished              */
0198     PHASE_ABORTED,              /* aborted               */
0199     PHASE_DISCONNECT,               /* disconnecting             */
0200 } phase_t;
0201
0202 /*
0203  * After interrupt, what to do now
0204  */
0205 typedef enum {
0206     INTR_IDLE,                  /* not expecting another IRQ         */
0207     INTR_NEXT_COMMAND,              /* start next command            */
0208     INTR_PROCESSING,                /* interrupt routine still processing    */
0209 } intr_ret_t;
0210
0211 /*
0212  * DMA direction
0213  */
0214 typedef enum {
0215     DMA_OUT,                    /* DMA from memory to chip      */
0216     DMA_IN                  /* DMA from chip to memory      */
0217 } dmadir_t;
0218
0219 /*
0220  * Synchronous transfer state
0221  */
0222 typedef enum {                  /* Synchronous transfer state       */
0223     SYNC_ASYNCHRONOUS,              /* don't negotiate synchronous transfers*/
0224     SYNC_NEGOCIATE,             /* start negotiation            */
0225     SYNC_SENT_REQUEST,              /* sent SDTR message            */
0226     SYNC_COMPLETED,             /* received SDTR reply          */
0227 } syncxfer_t;
0228
0229 /*
0230  * Command type
0231  */
0232 typedef enum {                  /* command type             */
0233     CMD_READ,                   /* READ_6, READ_10, READ_12     */
0234     CMD_WRITE,                  /* WRITE_6, WRITE_10, WRITE_12      */
0235     CMD_MISC,                   /* Others               */
0236 } cmdtype_t;
0237
0238 /*
0239  * Data phase direction
0240  */
0241 typedef enum {                  /* Data direction           */
0242     DATADIR_IN,                 /* Data in phase expected       */
0243     DATADIR_OUT                 /* Data out phase expected      */
0244 } datadir_t;
0245
0246 #include "queue.h"
0247 #include "msgqueue.h"
0248
0249 #define STATUS_BUFFER_SIZE  32
0250 /*
0251  * This is used to dump the previous states of the SBIC
0252  */
0253 struct status_entry {
0254     unsigned long   when;
0255     unsigned char   ssr;
0256     unsigned char   ph;
0257     unsigned char   irq;
0258     unsigned char   unused;
0259 };
0260
0261 #define ADD_STATUS(_q,_ssr,_ph,_irq) \
0262 ({                                  \
0263     host->status[(_q)][host->status_ptr[(_q)]].when = jiffies;  \
0264     host->status[(_q)][host->status_ptr[(_q)]].ssr  = (_ssr);   \
0265     host->status[(_q)][host->status_ptr[(_q)]].ph   = (_ph);    \
0266     host->status[(_q)][host->status_ptr[(_q)]].irq  = (_irq);   \
0267     host->status_ptr[(_q)] = (host->status_ptr[(_q)] + 1) & (STATUS_BUFFER_SIZE - 1); \
0268 })
0269
0270 /*
0271  * AcornSCSI host specific data
0272  */
0273 typedef struct acornscsi_hostdata {
0274     /* miscellaneous */
0275     struct Scsi_Host    *host;          /* host                 */
0276     struct scsi_cmnd    *SCpnt;         /* currently processing command     */
0277     struct scsi_cmnd    *origSCpnt;     /* original connecting command      */
0278     void __iomem    *base;          /* memc base address            */
0279     void __iomem    *fast;          /* fast ioc base address        */
0280
0281     /* driver information */
0282     struct {
0283     unsigned int    irq;            /* interrupt                */
0284     phase_t     phase;          /* current phase            */
0285
0286     struct {
0287         unsigned char   target;     /* reconnected target           */
0288         unsigned char   lun;        /* reconnected lun          */
0289         unsigned char   tag;        /* reconnected tag          */
0290     } reconnected;
0291
0292     struct scsi_pointer SCp;            /* current commands data pointer    */
0293
0294     MsgQueue_t  msgs;
0295
0296     unsigned short  last_message;       /* last message to be sent      */
0297     unsigned char   disconnectable:1;   /* this command can be disconnected */
0298     } scsi;
0299
0300     /* statistics information */
0301     struct {
0302     unsigned int    queues;
0303     unsigned int    removes;
0304     unsigned int    fins;
0305     unsigned int    reads;
0306     unsigned int    writes;
0307     unsigned int    miscs;
0308     unsigned int    disconnects;
0309     unsigned int    aborts;
0310     unsigned int    resets;
0311     } stats;
0312
0313     /* queue handling */
0314     struct {
0315     Queue_t     issue;          /* issue queue              */
0316     Queue_t     disconnected;       /* disconnected command queue       */
0317     } queues;
0318
0319     /* per-device info */
0320     struct {
0321     unsigned char   sync_xfer;      /* synchronous transfer (SBIC value)    */
0322     syncxfer_t  sync_state;     /* sync xfer negotiation state      */
0323     unsigned char   disconnect_ok:1;    /* device can disconnect        */
0324     } device[8];
0325     unsigned long   busyluns[64 / sizeof(unsigned long)];/* array of bits indicating LUNs busy  */
0326
0327     /* DMA info */
0328     struct {
0329     unsigned int    free_addr;      /* next free address            */
0330     unsigned int    start_addr;     /* start address of current transfer    */
0331     dmadir_t    direction;      /* dma direction            */
0332     unsigned int    transferred;        /* number of bytes transferred      */
0333     unsigned int    xfer_start;     /* scheduled DMA transfer start     */
0334     unsigned int    xfer_length;        /* scheduled DMA transfer length    */
0335     char        *xfer_ptr;      /* pointer to area          */
0336     unsigned char   xfer_required:1;    /* set if we need to transfer something */
0337     unsigned char   xfer_setup:1;       /* set if DMA is setup          */
0338     unsigned char   xfer_done:1;        /* set if DMA reached end of BH list    */
0339     } dma;
0340
0341     /* card info */
0342     struct {
0343     unsigned char   page_reg;       /* current setting of page reg      */
0344     } card;
0345
0346     unsigned char status_ptr[9];
0347     struct status_entry status[9][STATUS_BUFFER_SIZE];
0348 } AS_Host;
0349
0350 #endif /* ACORNSCSI_H */