0001 /*
0002 * DO NOT EDIT - This file is automatically generated
0003 * from the following source files:
0004 *
0005 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#58 $
0006 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $
0007 */
0008 typedef int (ahc_reg_print_t)(u_int, u_int *, u_int);
0009 typedef struct ahc_reg_parse_entry {
0010 char *name;
0011 uint8_t value;
0012 uint8_t mask;
0013 } ahc_reg_parse_entry_t;
0014
0015 #if AIC_DEBUG_REGISTERS
0016 ahc_reg_print_t ahc_scsiseq_print;
0017 #else
0018 #define ahc_scsiseq_print(regvalue, cur_col, wrap) \
0019 ahc_print_register(NULL, 0, "SCSISEQ", 0x00, regvalue, cur_col, wrap)
0020 #endif
0021
0022 #if AIC_DEBUG_REGISTERS
0023 ahc_reg_print_t ahc_sxfrctl0_print;
0024 #else
0025 #define ahc_sxfrctl0_print(regvalue, cur_col, wrap) \
0026 ahc_print_register(NULL, 0, "SXFRCTL0", 0x01, regvalue, cur_col, wrap)
0027 #endif
0028
0029 #if AIC_DEBUG_REGISTERS
0030 ahc_reg_print_t ahc_scsisigi_print;
0031 #else
0032 #define ahc_scsisigi_print(regvalue, cur_col, wrap) \
0033 ahc_print_register(NULL, 0, "SCSISIGI", 0x03, regvalue, cur_col, wrap)
0034 #endif
0035
0036 #if AIC_DEBUG_REGISTERS
0037 ahc_reg_print_t ahc_scsirate_print;
0038 #else
0039 #define ahc_scsirate_print(regvalue, cur_col, wrap) \
0040 ahc_print_register(NULL, 0, "SCSIRATE", 0x04, regvalue, cur_col, wrap)
0041 #endif
0042
0043 #if AIC_DEBUG_REGISTERS
0044 ahc_reg_print_t ahc_sstat0_print;
0045 #else
0046 #define ahc_sstat0_print(regvalue, cur_col, wrap) \
0047 ahc_print_register(NULL, 0, "SSTAT0", 0x0b, regvalue, cur_col, wrap)
0048 #endif
0049
0050 #if AIC_DEBUG_REGISTERS
0051 ahc_reg_print_t ahc_sstat1_print;
0052 #else
0053 #define ahc_sstat1_print(regvalue, cur_col, wrap) \
0054 ahc_print_register(NULL, 0, "SSTAT1", 0x0c, regvalue, cur_col, wrap)
0055 #endif
0056
0057 #if AIC_DEBUG_REGISTERS
0058 ahc_reg_print_t ahc_sstat2_print;
0059 #else
0060 #define ahc_sstat2_print(regvalue, cur_col, wrap) \
0061 ahc_print_register(NULL, 0, "SSTAT2", 0x0d, regvalue, cur_col, wrap)
0062 #endif
0063
0064 #if AIC_DEBUG_REGISTERS
0065 ahc_reg_print_t ahc_sstat3_print;
0066 #else
0067 #define ahc_sstat3_print(regvalue, cur_col, wrap) \
0068 ahc_print_register(NULL, 0, "SSTAT3", 0x0e, regvalue, cur_col, wrap)
0069 #endif
0070
0071 #if AIC_DEBUG_REGISTERS
0072 ahc_reg_print_t ahc_simode0_print;
0073 #else
0074 #define ahc_simode0_print(regvalue, cur_col, wrap) \
0075 ahc_print_register(NULL, 0, "SIMODE0", 0x10, regvalue, cur_col, wrap)
0076 #endif
0077
0078 #if AIC_DEBUG_REGISTERS
0079 ahc_reg_print_t ahc_simode1_print;
0080 #else
0081 #define ahc_simode1_print(regvalue, cur_col, wrap) \
0082 ahc_print_register(NULL, 0, "SIMODE1", 0x11, regvalue, cur_col, wrap)
0083 #endif
0084
0085 #if AIC_DEBUG_REGISTERS
0086 ahc_reg_print_t ahc_scsibusl_print;
0087 #else
0088 #define ahc_scsibusl_print(regvalue, cur_col, wrap) \
0089 ahc_print_register(NULL, 0, "SCSIBUSL", 0x12, regvalue, cur_col, wrap)
0090 #endif
0091
0092 #if AIC_DEBUG_REGISTERS
0093 ahc_reg_print_t ahc_sblkctl_print;
0094 #else
0095 #define ahc_sblkctl_print(regvalue, cur_col, wrap) \
0096 ahc_print_register(NULL, 0, "SBLKCTL", 0x1f, regvalue, cur_col, wrap)
0097 #endif
0098
0099 #if AIC_DEBUG_REGISTERS
0100 ahc_reg_print_t ahc_seq_flags_print;
0101 #else
0102 #define ahc_seq_flags_print(regvalue, cur_col, wrap) \
0103 ahc_print_register(NULL, 0, "SEQ_FLAGS", 0x3c, regvalue, cur_col, wrap)
0104 #endif
0105
0106 #if AIC_DEBUG_REGISTERS
0107 ahc_reg_print_t ahc_lastphase_print;
0108 #else
0109 #define ahc_lastphase_print(regvalue, cur_col, wrap) \
0110 ahc_print_register(NULL, 0, "LASTPHASE", 0x3f, regvalue, cur_col, wrap)
0111 #endif
0112
0113 #if AIC_DEBUG_REGISTERS
0114 ahc_reg_print_t ahc_seqctl_print;
0115 #else
0116 #define ahc_seqctl_print(regvalue, cur_col, wrap) \
0117 ahc_print_register(NULL, 0, "SEQCTL", 0x60, regvalue, cur_col, wrap)
0118 #endif
0119
0120 #if AIC_DEBUG_REGISTERS
0121 ahc_reg_print_t ahc_sram_base_print;
0122 #else
0123 #define ahc_sram_base_print(regvalue, cur_col, wrap) \
0124 ahc_print_register(NULL, 0, "SRAM_BASE", 0x70, regvalue, cur_col, wrap)
0125 #endif
0126
0127 #if AIC_DEBUG_REGISTERS
0128 ahc_reg_print_t ahc_error_print;
0129 #else
0130 #define ahc_error_print(regvalue, cur_col, wrap) \
0131 ahc_print_register(NULL, 0, "ERROR", 0x92, regvalue, cur_col, wrap)
0132 #endif
0133
0134 #if AIC_DEBUG_REGISTERS
0135 ahc_reg_print_t ahc_dfcntrl_print;
0136 #else
0137 #define ahc_dfcntrl_print(regvalue, cur_col, wrap) \
0138 ahc_print_register(NULL, 0, "DFCNTRL", 0x93, regvalue, cur_col, wrap)
0139 #endif
0140
0141 #if AIC_DEBUG_REGISTERS
0142 ahc_reg_print_t ahc_dfstatus_print;
0143 #else
0144 #define ahc_dfstatus_print(regvalue, cur_col, wrap) \
0145 ahc_print_register(NULL, 0, "DFSTATUS", 0x94, regvalue, cur_col, wrap)
0146 #endif
0147
0148 #if AIC_DEBUG_REGISTERS
0149 ahc_reg_print_t ahc_scsiphase_print;
0150 #else
0151 #define ahc_scsiphase_print(regvalue, cur_col, wrap) \
0152 ahc_print_register(NULL, 0, "SCSIPHASE", 0x9e, regvalue, cur_col, wrap)
0153 #endif
0154
0155 #if AIC_DEBUG_REGISTERS
0156 ahc_reg_print_t ahc_scb_base_print;
0157 #else
0158 #define ahc_scb_base_print(regvalue, cur_col, wrap) \
0159 ahc_print_register(NULL, 0, "SCB_BASE", 0xa0, regvalue, cur_col, wrap)
0160 #endif
0161
0162 #if AIC_DEBUG_REGISTERS
0163 ahc_reg_print_t ahc_scb_control_print;
0164 #else
0165 #define ahc_scb_control_print(regvalue, cur_col, wrap) \
0166 ahc_print_register(NULL, 0, "SCB_CONTROL", 0xb8, regvalue, cur_col, wrap)
0167 #endif
0168
0169 #if AIC_DEBUG_REGISTERS
0170 ahc_reg_print_t ahc_scb_scsiid_print;
0171 #else
0172 #define ahc_scb_scsiid_print(regvalue, cur_col, wrap) \
0173 ahc_print_register(NULL, 0, "SCB_SCSIID", 0xb9, regvalue, cur_col, wrap)
0174 #endif
0175
0176 #if AIC_DEBUG_REGISTERS
0177 ahc_reg_print_t ahc_scb_lun_print;
0178 #else
0179 #define ahc_scb_lun_print(regvalue, cur_col, wrap) \
0180 ahc_print_register(NULL, 0, "SCB_LUN", 0xba, regvalue, cur_col, wrap)
0181 #endif
0182
0183 #if AIC_DEBUG_REGISTERS
0184 ahc_reg_print_t ahc_scb_tag_print;
0185 #else
0186 #define ahc_scb_tag_print(regvalue, cur_col, wrap) \
0187 ahc_print_register(NULL, 0, "SCB_TAG", 0xbb, regvalue, cur_col, wrap)
0188 #endif
0189
0190
0191 #define SCSISEQ 0x00
0192 #define TEMODE 0x80
0193 #define SCSIRSTO 0x01
0194
0195 #define SXFRCTL0 0x01
0196 #define DFON 0x80
0197 #define DFPEXP 0x40
0198 #define FAST20 0x20
0199 #define CLRSTCNT 0x10
0200 #define SPIOEN 0x08
0201 #define SCAMEN 0x04
0202 #define CLRCHN 0x02
0203
0204 #define SXFRCTL1 0x02
0205 #define STIMESEL 0x18
0206 #define BITBUCKET 0x80
0207 #define SWRAPEN 0x40
0208 #define ENSTIMER 0x04
0209 #define ACTNEGEN 0x02
0210 #define STPWEN 0x01
0211
0212 #define SCSISIGO 0x03
0213 #define CDO 0x80
0214 #define IOO 0x40
0215 #define MSGO 0x20
0216 #define ATNO 0x10
0217 #define SELO 0x08
0218 #define BSYO 0x04
0219 #define REQO 0x02
0220 #define ACKO 0x01
0221
0222 #define SCSISIGI 0x03
0223 #define P_DATAIN_DT 0x60
0224 #define P_DATAOUT_DT 0x20
0225 #define ATNI 0x10
0226 #define SELI 0x08
0227 #define BSYI 0x04
0228 #define REQI 0x02
0229 #define ACKI 0x01
0230
0231 #define SCSIRATE 0x04
0232 #define SXFR 0x70
0233 #define SOFS 0x0f
0234 #define SXFR_ULTRA2 0x0f
0235 #define WIDEXFER 0x80
0236 #define ENABLE_CRC 0x40
0237 #define SINGLE_EDGE 0x10
0238
0239 #define SCSIID 0x05
0240 #define SCSIOFFSET 0x05
0241 #define SOFS_ULTRA2 0x7f
0242
0243 #define SCSIDATL 0x06
0244
0245 #define SCSIDATH 0x07
0246
0247 #define OPTIONMODE 0x08
0248 #define OPTIONMODE_DEFAULTS 0x03
0249 #define AUTORATEEN 0x80
0250 #define AUTOACKEN 0x40
0251 #define ATNMGMNTEN 0x20
0252 #define BUSFREEREV 0x10
0253 #define EXPPHASEDIS 0x08
0254 #define SCSIDATL_IMGEN 0x04
0255 #define AUTO_MSGOUT_DE 0x02
0256 #define DIS_MSGIN_DUALEDGE 0x01
0257
0258 #define STCNT 0x08
0259
0260 #define TARGCRCCNT 0x0a
0261
0262 #define CLRSINT0 0x0b
0263 #define CLRSELDO 0x40
0264 #define CLRSELDI 0x20
0265 #define CLRSELINGO 0x10
0266 #define CLRIOERR 0x08
0267 #define CLRSWRAP 0x08
0268 #define CLRSPIORDY 0x02
0269
0270 #define SSTAT0 0x0b
0271 #define TARGET 0x80
0272 #define SELDO 0x40
0273 #define SELDI 0x20
0274 #define SELINGO 0x10
0275 #define SWRAP 0x08
0276 #define IOERR 0x08
0277 #define SDONE 0x04
0278 #define SPIORDY 0x02
0279 #define DMADONE 0x01
0280
0281 #define CLRSINT1 0x0c
0282 #define CLRSELTIMEO 0x80
0283 #define CLRATNO 0x40
0284 #define CLRSCSIRSTI 0x20
0285 #define CLRBUSFREE 0x08
0286 #define CLRSCSIPERR 0x04
0287 #define CLRPHASECHG 0x02
0288 #define CLRREQINIT 0x01
0289
0290 #define SSTAT1 0x0c
0291 #define SELTO 0x80
0292 #define ATNTARG 0x40
0293 #define SCSIRSTI 0x20
0294 #define PHASEMIS 0x10
0295 #define BUSFREE 0x08
0296 #define SCSIPERR 0x04
0297 #define PHASECHG 0x02
0298 #define REQINIT 0x01
0299
0300 #define SSTAT2 0x0d
0301 #define SFCNT 0x1f
0302 #define OVERRUN 0x80
0303 #define SHVALID 0x40
0304 #define EXP_ACTIVE 0x10
0305 #define CRCVALERR 0x08
0306 #define CRCENDERR 0x04
0307 #define CRCREQERR 0x02
0308 #define DUAL_EDGE_ERR 0x01
0309
0310 #define SSTAT3 0x0e
0311 #define SCSICNT 0xf0
0312 #define U2OFFCNT 0x7f
0313 #define OFFCNT 0x0f
0314
0315 #define SCSIID_ULTRA2 0x0f
0316
0317 #define SIMODE0 0x10
0318 #define ENSELDO 0x40
0319 #define ENSELDI 0x20
0320 #define ENSELINGO 0x10
0321 #define ENIOERR 0x08
0322 #define ENSWRAP 0x08
0323 #define ENSDONE 0x04
0324 #define ENSPIORDY 0x02
0325 #define ENDMADONE 0x01
0326
0327 #define SIMODE1 0x11
0328 #define ENSELTIMO 0x80
0329 #define ENATNTARG 0x40
0330 #define ENSCSIRST 0x20
0331 #define ENPHASEMIS 0x10
0332 #define ENBUSFREE 0x08
0333 #define ENSCSIPERR 0x04
0334 #define ENPHASECHG 0x02
0335 #define ENREQINIT 0x01
0336
0337 #define SCSIBUSL 0x12
0338
0339 #define SCSIBUSH 0x13
0340
0341 #define SXFRCTL2 0x13
0342 #define ASYNC_SETUP 0x07
0343 #define AUTORSTDIS 0x10
0344 #define CMDDMAEN 0x08
0345
0346 #define SHADDR 0x14
0347
0348 #define SELTIMER 0x18
0349 #define TARGIDIN 0x18
0350 #define STAGE6 0x20
0351 #define STAGE5 0x10
0352 #define STAGE4 0x08
0353 #define STAGE3 0x04
0354 #define STAGE2 0x02
0355 #define STAGE1 0x01
0356
0357 #define SELID 0x19
0358 #define SELID_MASK 0xf0
0359 #define ONEBIT 0x08
0360
0361 #define SCAMCTL 0x1a
0362 #define SCAMLVL 0x03
0363 #define ENSCAMSELO 0x80
0364 #define CLRSCAMSELID 0x40
0365 #define ALTSTIM 0x20
0366 #define DFLTTID 0x10
0367
0368 #define SPIOCAP 0x1b
0369 #define SOFT1 0x80
0370 #define SOFT0 0x40
0371 #define SOFTCMDEN 0x20
0372 #define EXT_BRDCTL 0x10
0373 #define SEEPROM 0x08
0374 #define EEPROM 0x04
0375 #define ROM 0x02
0376 #define SSPIOCPS 0x01
0377
0378 #define TARGID 0x1b
0379
0380 #define BRDCTL 0x1d
0381 #define BRDDAT7 0x80
0382 #define BRDDAT6 0x40
0383 #define BRDDAT5 0x20
0384 #define BRDSTB 0x10
0385 #define BRDDAT4 0x10
0386 #define BRDDAT3 0x08
0387 #define BRDCS 0x08
0388 #define BRDDAT2 0x04
0389 #define BRDRW 0x04
0390 #define BRDRW_ULTRA2 0x02
0391 #define BRDCTL1 0x02
0392 #define BRDCTL0 0x01
0393 #define BRDSTB_ULTRA2 0x01
0394
0395 #define SEECTL 0x1e
0396 #define EXTARBACK 0x80
0397 #define EXTARBREQ 0x40
0398 #define SEEMS 0x20
0399 #define SEERDY 0x10
0400 #define SEECS 0x08
0401 #define SEECK 0x04
0402 #define SEEDO 0x02
0403 #define SEEDI 0x01
0404
0405 #define SBLKCTL 0x1f
0406 #define DIAGLEDEN 0x80
0407 #define DIAGLEDON 0x40
0408 #define AUTOFLUSHDIS 0x20
0409 #define SELBUSB 0x08
0410 #define ENAB40 0x08
0411 #define ENAB20 0x04
0412 #define SELWIDE 0x02
0413 #define XCVR 0x01
0414
0415 #define BUSY_TARGETS 0x20
0416 #define TARG_SCSIRATE 0x20
0417
0418 #define ULTRA_ENB 0x30
0419 #define CMDSIZE_TABLE 0x30
0420
0421 #define DISC_DSB 0x32
0422
0423 #define CMDSIZE_TABLE_TAIL 0x34
0424
0425 #define MWI_RESIDUAL 0x38
0426
0427 #define NEXT_QUEUED_SCB 0x39
0428
0429 #define MSG_OUT 0x3a
0430
0431 #define DMAPARAMS 0x3b
0432 #define PRELOADEN 0x80
0433 #define WIDEODD 0x40
0434 #define SCSIEN 0x20
0435 #define SDMAEN 0x10
0436 #define SDMAENACK 0x10
0437 #define HDMAEN 0x08
0438 #define HDMAENACK 0x08
0439 #define DIRECTION 0x04
0440 #define FIFOFLUSH 0x02
0441 #define FIFORESET 0x01
0442
0443 #define SEQ_FLAGS 0x3c
0444 #define NOT_IDENTIFIED 0x80
0445 #define NO_CDB_SENT 0x40
0446 #define TARGET_CMD_IS_TAGGED 0x40
0447 #define DPHASE 0x20
0448 #define TARG_CMD_PENDING 0x10
0449 #define CMDPHASE_PENDING 0x08
0450 #define DPHASE_PENDING 0x04
0451 #define SPHASE_PENDING 0x02
0452 #define NO_DISCONNECT 0x01
0453
0454 #define SAVED_SCSIID 0x3d
0455
0456 #define SAVED_LUN 0x3e
0457
0458 #define LASTPHASE 0x3f
0459 #define P_MESGIN 0xe0
0460 #define PHASE_MASK 0xe0
0461 #define P_STATUS 0xc0
0462 #define P_MESGOUT 0xa0
0463 #define P_COMMAND 0x80
0464 #define P_DATAIN 0x40
0465 #define P_BUSFREE 0x01
0466 #define P_DATAOUT 0x00
0467 #define CDI 0x80
0468 #define IOI 0x40
0469 #define MSGI 0x20
0470
0471 #define WAITING_SCBH 0x40
0472
0473 #define DISCONNECTED_SCBH 0x41
0474
0475 #define FREE_SCBH 0x42
0476
0477 #define COMPLETE_SCBH 0x43
0478
0479 #define HSCB_ADDR 0x44
0480
0481 #define SHARED_DATA_ADDR 0x48
0482
0483 #define KERNEL_QINPOS 0x4c
0484
0485 #define QINPOS 0x4d
0486
0487 #define QOUTPOS 0x4e
0488
0489 #define KERNEL_TQINPOS 0x4f
0490
0491 #define TQINPOS 0x50
0492
0493 #define ARG_1 0x51
0494 #define RETURN_1 0x51
0495 #define SEND_MSG 0x80
0496 #define SEND_SENSE 0x40
0497 #define SEND_REJ 0x20
0498 #define MSGOUT_PHASEMIS 0x10
0499 #define EXIT_MSG_LOOP 0x08
0500 #define CONT_MSG_LOOP 0x04
0501 #define CONT_TARG_SESSION 0x02
0502
0503 #define ARG_2 0x52
0504 #define RETURN_2 0x52
0505
0506 #define LAST_MSG 0x53
0507 #define TARG_IMMEDIATE_SCB 0x53
0508
0509 #define SCSISEQ_TEMPLATE 0x54
0510 #define ENSELO 0x40
0511 #define ENSELI 0x20
0512 #define ENRSELI 0x10
0513 #define ENAUTOATNO 0x08
0514 #define ENAUTOATNI 0x04
0515 #define ENAUTOATNP 0x02
0516
0517 #define HA_274_BIOSGLOBAL 0x56
0518 #define INITIATOR_TAG 0x56
0519 #define HA_274_EXTENDED_TRANS 0x01
0520
0521 #define SEQ_FLAGS2 0x57
0522 #define TARGET_MSG_PENDING 0x02
0523 #define SCB_DMA 0x01
0524
0525 #define SCSICONF 0x5a
0526 #define HWSCSIID 0x0f
0527 #define HSCSIID 0x07
0528 #define TERM_ENB 0x80
0529 #define RESET_SCSI 0x40
0530 #define ENSPCHK 0x20
0531
0532 #define INTDEF 0x5c
0533 #define VECTOR 0x0f
0534 #define EDGE_TRIG 0x80
0535
0536 #define HOSTCONF 0x5d
0537
0538 #define HA_274_BIOSCTRL 0x5f
0539 #define BIOSDISABLED 0x30
0540 #define BIOSMODE 0x30
0541 #define CHANNEL_B_PRIMARY 0x08
0542
0543 #define SEQCTL 0x60
0544 #define PERRORDIS 0x80
0545 #define PAUSEDIS 0x40
0546 #define FAILDIS 0x20
0547 #define FASTMODE 0x10
0548 #define BRKADRINTEN 0x08
0549 #define STEP 0x04
0550 #define SEQRESET 0x02
0551 #define LOADRAM 0x01
0552
0553 #define SEQRAM 0x61
0554
0555 #define SEQADDR0 0x62
0556
0557 #define SEQADDR1 0x63
0558 #define SEQADDR1_MASK 0x01
0559
0560 #define ACCUM 0x64
0561
0562 #define SINDEX 0x65
0563
0564 #define DINDEX 0x66
0565
0566 #define ALLONES 0x69
0567
0568 #define ALLZEROS 0x6a
0569
0570 #define NONE 0x6a
0571
0572 #define FLAGS 0x6b
0573 #define ZERO 0x02
0574 #define CARRY 0x01
0575
0576 #define SINDIR 0x6c
0577
0578 #define DINDIR 0x6d
0579
0580 #define FUNCTION1 0x6e
0581
0582 #define STACK 0x6f
0583
0584 #define TARG_OFFSET 0x70
0585
0586 #define SRAM_BASE 0x70
0587
0588 #define BCTL 0x84
0589 #define ACE 0x08
0590 #define ENABLE 0x01
0591
0592 #define DSCOMMAND0 0x84
0593 #define CACHETHEN 0x80
0594 #define DPARCKEN 0x40
0595 #define MPARCKEN 0x20
0596 #define EXTREQLCK 0x10
0597 #define INTSCBRAMSEL 0x08
0598 #define RAMPS 0x04
0599 #define USCBSIZE32 0x02
0600 #define CIOPARCKEN 0x01
0601
0602 #define BUSTIME 0x85
0603 #define BOFF 0xf0
0604 #define BON 0x0f
0605
0606 #define DSCOMMAND1 0x85
0607 #define DSLATT 0xfc
0608 #define HADDLDSEL1 0x02
0609 #define HADDLDSEL0 0x01
0610
0611 #define BUSSPD 0x86
0612 #define DFTHRSH 0xc0
0613 #define DFTHRSH_75 0x80
0614 #define STBOFF 0x38
0615 #define STBON 0x07
0616
0617 #define HS_MAILBOX 0x86
0618 #define HOST_MAILBOX 0xf0
0619 #define HOST_TQINPOS 0x80
0620 #define SEQ_MAILBOX 0x0f
0621
0622 #define DSPCISTATUS 0x86
0623 #define DFTHRSH_100 0xc0
0624
0625 #define HCNTRL 0x87
0626 #define POWRDN 0x40
0627 #define SWINT 0x10
0628 #define IRQMS 0x08
0629 #define PAUSE 0x04
0630 #define INTEN 0x02
0631 #define CHIPRST 0x01
0632 #define CHIPRSTACK 0x01
0633
0634 #define HADDR 0x88
0635
0636 #define HCNT 0x8c
0637
0638 #define SCBPTR 0x90
0639
0640 #define INTSTAT 0x91
0641 #define SEQINT_MASK 0xf1
0642 #define OUT_OF_RANGE 0xe1
0643 #define NO_FREE_SCB 0xd1
0644 #define SCB_MISMATCH 0xc1
0645 #define MISSED_BUSFREE 0xb1
0646 #define MKMSG_FAILED 0xa1
0647 #define DATA_OVERRUN 0x91
0648 #define PERR_DETECTED 0x81
0649 #define BAD_STATUS 0x71
0650 #define HOST_MSG_LOOP 0x61
0651 #define PDATA_REINIT 0x51
0652 #define IGN_WIDE_RES 0x41
0653 #define NO_MATCH 0x31
0654 #define PROTO_VIOLATION 0x21
0655 #define SEND_REJECT 0x11
0656 #define INT_PEND 0x0f
0657 #define BAD_PHASE 0x01
0658 #define BRKADRINT 0x08
0659 #define SCSIINT 0x04
0660 #define CMDCMPLT 0x02
0661 #define SEQINT 0x01
0662
0663 #define CLRINT 0x92
0664 #define CLRPARERR 0x10
0665 #define CLRBRKADRINT 0x08
0666 #define CLRSCSIINT 0x04
0667 #define CLRCMDINT 0x02
0668 #define CLRSEQINT 0x01
0669
0670 #define ERROR 0x92
0671 #define CIOPARERR 0x80
0672 #define PCIERRSTAT 0x40
0673 #define MPARERR 0x20
0674 #define DPARERR 0x10
0675 #define SQPARERR 0x08
0676 #define ILLOPCODE 0x04
0677 #define ILLSADDR 0x02
0678 #define ILLHADDR 0x01
0679
0680 #define DFCNTRL 0x93
0681
0682 #define DFSTATUS 0x94
0683 #define PRELOAD_AVAIL 0x80
0684 #define DFCACHETH 0x40
0685 #define FIFOQWDEMP 0x20
0686 #define MREQPEND 0x10
0687 #define HDONE 0x08
0688 #define DFTHRESH 0x04
0689 #define FIFOFULL 0x02
0690 #define FIFOEMP 0x01
0691
0692 #define DFWADDR 0x95
0693
0694 #define DFRADDR 0x97
0695
0696 #define DFDAT 0x99
0697
0698 #define SCBCNT 0x9a
0699 #define SCBCNT_MASK 0x1f
0700 #define SCBAUTO 0x80
0701
0702 #define QINFIFO 0x9b
0703
0704 #define QINCNT 0x9c
0705
0706 #define QOUTFIFO 0x9d
0707
0708 #define CRCCONTROL1 0x9d
0709 #define CRCONSEEN 0x80
0710 #define CRCVALCHKEN 0x40
0711 #define CRCENDCHKEN 0x20
0712 #define CRCREQCHKEN 0x10
0713 #define TARGCRCENDEN 0x08
0714 #define TARGCRCCNTEN 0x04
0715
0716 #define QOUTCNT 0x9e
0717
0718 #define SCSIPHASE 0x9e
0719 #define DATA_PHASE_MASK 0x03
0720 #define STATUS_PHASE 0x20
0721 #define COMMAND_PHASE 0x10
0722 #define MSG_IN_PHASE 0x08
0723 #define MSG_OUT_PHASE 0x04
0724 #define DATA_IN_PHASE 0x02
0725 #define DATA_OUT_PHASE 0x01
0726
0727 #define SFUNCT 0x9f
0728 #define ALT_MODE 0x80
0729
0730 #define SCB_BASE 0xa0
0731
0732 #define SCB_CDB_PTR 0xa0
0733 #define SCB_CDB_STORE 0xa0
0734 #define SCB_RESIDUAL_DATACNT 0xa0
0735
0736 #define SCB_RESIDUAL_SGPTR 0xa4
0737
0738 #define SCB_SCSI_STATUS 0xa8
0739
0740 #define SCB_TARGET_PHASES 0xa9
0741
0742 #define SCB_TARGET_DATA_DIR 0xaa
0743
0744 #define SCB_TARGET_ITAG 0xab
0745
0746 #define SCB_DATAPTR 0xac
0747
0748 #define SCB_DATACNT 0xb0
0749 #define SG_HIGH_ADDR_BITS 0x7f
0750 #define SG_LAST_SEG 0x80
0751
0752 #define SCB_SGPTR 0xb4
0753 #define SG_RESID_VALID 0x04
0754 #define SG_FULL_RESID 0x02
0755 #define SG_LIST_NULL 0x01
0756
0757 #define SCB_CONTROL 0xb8
0758 #define SCB_TAG_TYPE 0x03
0759 #define TARGET_SCB 0x80
0760 #define STATUS_RCVD 0x80
0761 #define DISCENB 0x40
0762 #define TAG_ENB 0x20
0763 #define MK_MESSAGE 0x10
0764 #define ULTRAENB 0x08
0765 #define DISCONNECTED 0x04
0766
0767 #define SCB_SCSIID 0xb9
0768 #define TID 0xf0
0769 #define TWIN_TID 0x70
0770 #define OID 0x0f
0771 #define TWIN_CHNLB 0x80
0772
0773 #define SCB_LUN 0xba
0774 #define LID 0x3f
0775 #define SCB_XFERLEN_ODD 0x80
0776
0777 #define SCB_TAG 0xbb
0778
0779 #define SCB_CDB_LEN 0xbc
0780
0781 #define SCB_SCSIRATE 0xbd
0782
0783 #define SCB_SCSIOFFSET 0xbe
0784
0785 #define SCB_NEXT 0xbf
0786
0787 #define SCB_64_SPARE 0xc0
0788
0789 #define SEECTL_2840 0xc0
0790 #define CS_2840 0x04
0791 #define CK_2840 0x02
0792 #define DO_2840 0x01
0793
0794 #define STATUS_2840 0xc1
0795 #define BIOS_SEL 0x60
0796 #define ADSEL 0x1e
0797 #define EEPROM_TF 0x80
0798 #define DI_2840 0x01
0799
0800 #define SCB_64_BTT 0xd0
0801
0802 #define CCHADDR 0xe0
0803
0804 #define CCHCNT 0xe8
0805
0806 #define CCSGRAM 0xe9
0807
0808 #define CCSGADDR 0xea
0809
0810 #define CCSGCTL 0xeb
0811 #define CCSGDONE 0x80
0812 #define CCSGEN 0x08
0813 #define SG_FETCH_NEEDED 0x02
0814 #define CCSGRESET 0x01
0815
0816 #define CCSCBRAM 0xec
0817
0818 #define CCSCBADDR 0xed
0819
0820 #define CCSCBCTL 0xee
0821 #define CCSCBDONE 0x80
0822 #define ARRDONE 0x40
0823 #define CCARREN 0x10
0824 #define CCSCBEN 0x08
0825 #define CCSCBDIR 0x04
0826 #define CCSCBRESET 0x01
0827
0828 #define CCSCBCNT 0xef
0829
0830 #define SCBBADDR 0xf0
0831
0832 #define CCSCBPTR 0xf1
0833
0834 #define HNSCB_QOFF 0xf4
0835
0836 #define SNSCB_QOFF 0xf6
0837
0838 #define SDSCB_QOFF 0xf8
0839
0840 #define QOFF_CTLSTA 0xfa
0841 #define SCB_QSIZE 0x07
0842 #define SCB_QSIZE_256 0x06
0843 #define SCB_AVAIL 0x40
0844 #define SNSCB_ROLLOVER 0x20
0845 #define SDSCB_ROLLOVER 0x10
0846
0847 #define DFF_THRSH 0xfb
0848 #define WR_DFTHRSH 0x70
0849 #define WR_DFTHRSH_MAX 0x70
0850 #define WR_DFTHRSH_90 0x60
0851 #define WR_DFTHRSH_85 0x50
0852 #define WR_DFTHRSH_75 0x40
0853 #define WR_DFTHRSH_63 0x30
0854 #define WR_DFTHRSH_50 0x20
0855 #define WR_DFTHRSH_25 0x10
0856 #define RD_DFTHRSH 0x07
0857 #define RD_DFTHRSH_MAX 0x07
0858 #define RD_DFTHRSH_90 0x06
0859 #define RD_DFTHRSH_85 0x05
0860 #define RD_DFTHRSH_75 0x04
0861 #define RD_DFTHRSH_63 0x03
0862 #define RD_DFTHRSH_50 0x02
0863 #define RD_DFTHRSH_25 0x01
0864 #define RD_DFTHRSH_MIN 0x00
0865 #define WR_DFTHRSH_MIN 0x00
0866
0867 #define SG_CACHE_SHADOW 0xfc
0868 #define SG_ADDR_MASK 0xf8
0869 #define LAST_SEG 0x02
0870 #define LAST_SEG_DONE 0x01
0871
0872 #define SG_CACHE_PRE 0xfc
0873
0874
0875 #define TARGET_CMD_CMPLT 0xfe
0876 #define MAX_OFFSET_ULTRA2 0x7f
0877 #define MAX_OFFSET_16BIT 0x08
0878 #define BUS_8_BIT 0x00
0879 #define TID_SHIFT 0x04
0880 #define STATUS_QUEUE_FULL 0x28
0881 #define STATUS_BUSY 0x08
0882 #define SCB_DOWNLOAD_SIZE_64 0x30
0883 #define MAX_OFFSET_8BIT 0x0f
0884 #define HOST_MAILBOX_SHIFT 0x04
0885 #define CCSGADDR_MAX 0x80
0886 #define BUS_32_BIT 0x02
0887 #define SG_SIZEOF 0x08
0888 #define SEQ_MAILBOX_SHIFT 0x00
0889 #define SCB_LIST_NULL 0xff
0890 #define SCB_DOWNLOAD_SIZE 0x20
0891 #define CMD_GROUP_CODE_SHIFT 0x05
0892 #define CCSGRAM_MAXSEGS 0x10
0893 #define TARGET_DATA_IN 0x01
0894 #define STACK_SIZE 0x04
0895 #define SCB_UPLOAD_SIZE 0x20
0896 #define MAX_OFFSET 0x7f
0897 #define HOST_MSG 0xff
0898 #define BUS_16_BIT 0x01
0899
0900
0901 /* Downloaded Constant Definitions */
0902 #define INVERTED_CACHESIZE_MASK 0x03
0903 #define SG_PREFETCH_ALIGN_MASK 0x05
0904 #define SG_PREFETCH_ADDR_MASK 0x06
0905 #define QOUTFIFO_OFFSET 0x00
0906 #define SG_PREFETCH_CNT 0x04
0907 #define QINFIFO_OFFSET 0x01
0908 #define CACHESIZE_MASK 0x02
0909 #define DOWNLOAD_CONST_COUNT 0x07
0910
0911
0912 /* Exported Labels */
