scsi/aic7xxx/aic7xxx_93cx6.c

0001 /*
0002  * Interface for the 93C66/56/46/26/06 serial eeprom parts.
0003  *
0004  * Copyright (c) 1995, 1996 Daniel M. Eischen
0005  * All rights reserved.
0006  *
0007  * Redistribution and use in source and binary forms, with or without
0008  * modification, are permitted provided that the following conditions
0009  * are met:
0010  * 1. Redistributions of source code must retain the above copyright
0011  *    notice, this list of conditions, and the following disclaimer,
0012  *    without modification.
0013  * 2. The name of the author may not be used to endorse or promote products
0014  *    derived from this software without specific prior written permission.
0015  *
0016  * Alternatively, this software may be distributed under the terms of the
0017  * GNU General Public License ("GPL").
0018  *
0019  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
0020  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0021  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0022  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
0023  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0024  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
0025  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
0026  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
0027  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
0028  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
0029  * SUCH DAMAGE.
0030  *
0031  * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_93cx6.c#19 $
0032  */
0033
0034 /*
0035  *   The instruction set of the 93C66/56/46/26/06 chips are as follows:
0036  *
0037  *               Start  OP      *
0038  *     Function   Bit  Code  Address**  Data     Description
0039  *     -------------------------------------------------------------------
0040  *     READ        1    10   A5 - A0             Reads data stored in memory,
0041  *                                               starting at specified address
0042  *     EWEN        1    00   11XXXX              Write enable must precede
0043  *                                               all programming modes
0044  *     ERASE       1    11   A5 - A0             Erase register A5A4A3A2A1A0
0045  *     WRITE       1    01   A5 - A0   D15 - D0  Writes register
0046  *     ERAL        1    00   10XXXX              Erase all registers
0047  *     WRAL        1    00   01XXXX    D15 - D0  Writes to all registers
0048  *     EWDS        1    00   00XXXX              Disables all programming
0049  *                                               instructions
0050  *     *Note: A value of X for address is a don't care condition.
0051  *    **Note: There are 8 address bits for the 93C56/66 chips unlike
0052  *        the 93C46/26/06 chips which have 6 address bits.
0053  *
0054  *   The 93C46 has a four wire interface: clock, chip select, data in, and
0055  *   data out.  In order to perform one of the above functions, you need
0056  *   to enable the chip select for a clock period (typically a minimum of
0057  *   1 usec, with the clock high and low a minimum of 750 and 250 nsec
0058  *   respectively).  While the chip select remains high, you can clock in
0059  *   the instructions (above) starting with the start bit, followed by the
0060  *   OP code, Address, and Data (if needed).  For the READ instruction, the
0061  *   requested 16-bit register contents is read from the data out line but
0062  *   is preceded by an initial zero (leading 0, followed by 16-bits, MSB
0063  *   first).  The clock cycling from low to high initiates the next data
0064  *   bit to be sent from the chip.
0065  */
0066
0067 #include "aic7xxx_osm.h"
0068 #include "aic7xxx_inline.h"
0069 #include "aic7xxx_93cx6.h"
0070
0071 /*
0072  * Right now, we only have to read the SEEPROM.  But we make it easier to
0073  * add other 93Cx6 functions.
0074  */
0075 struct seeprom_cmd {
0076     uint8_t len;
0077     uint8_t bits[11];
0078 };
0079
0080 /* Short opcodes for the c46 */
0081 static const struct seeprom_cmd seeprom_ewen = {9, {1, 0, 0, 1, 1, 0, 0, 0, 0}};
0082 static const struct seeprom_cmd seeprom_ewds = {9, {1, 0, 0, 0, 0, 0, 0, 0, 0}};
0083
0084 /* Long opcodes for the C56/C66 */
0085 static const struct seeprom_cmd seeprom_long_ewen = {11, {1, 0, 0, 1, 1, 0, 0, 0, 0}};
0086 static const struct seeprom_cmd seeprom_long_ewds = {11, {1, 0, 0, 0, 0, 0, 0, 0, 0}};
0087
0088 /* Common opcodes */
0089 static const struct seeprom_cmd seeprom_write = {3, {1, 0, 1}};
0090 static const struct seeprom_cmd seeprom_read  = {3, {1, 1, 0}};
0091
0092 /*
0093  * Wait for the SEERDY to go high; about 800 ns.
0094  */
0095 #define CLOCK_PULSE(sd, rdy)                \
0096     while ((SEEPROM_STATUS_INB(sd) & rdy) == 0) {   \
0097         ;  /* Do nothing */         \
0098     }                       \
0099     (void)SEEPROM_INB(sd);  /* Clear clock */
0100
0101 /*
0102  * Send a START condition and the given command
0103  */
0104 static void
0105 send_seeprom_cmd(struct seeprom_descriptor *sd, const struct seeprom_cmd *cmd)
0106 {
0107     uint8_t temp;
0108     int i = 0;
0109
0110     /* Send chip select for one clock cycle. */
0111     temp = sd->sd_MS ^ sd->sd_CS;
0112     SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
0113     CLOCK_PULSE(sd, sd->sd_RDY);
0114
0115     for (i = 0; i < cmd->len; i++) {
0116         if (cmd->bits[i] != 0)
0117             temp ^= sd->sd_DO;
0118         SEEPROM_OUTB(sd, temp);
0119         CLOCK_PULSE(sd, sd->sd_RDY);
0120         SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
0121         CLOCK_PULSE(sd, sd->sd_RDY);
0122         if (cmd->bits[i] != 0)
0123             temp ^= sd->sd_DO;
0124     }
0125 }
0126
0127 /*
0128  * Clear CS put the chip in the reset state, where it can wait for new commands.
0129  */
0130 static void
0131 reset_seeprom(struct seeprom_descriptor *sd)
0132 {
0133     uint8_t temp;
0134
0135     temp = sd->sd_MS;
0136     SEEPROM_OUTB(sd, temp);
0137     CLOCK_PULSE(sd, sd->sd_RDY);
0138     SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
0139     CLOCK_PULSE(sd, sd->sd_RDY);
0140     SEEPROM_OUTB(sd, temp);
0141     CLOCK_PULSE(sd, sd->sd_RDY);
0142 }
0143
0144 /*
0145  * Read the serial EEPROM and returns 1 if successful and 0 if
0146  * not successful.
0147  */
0148 int
0149 ahc_read_seeprom(struct seeprom_descriptor *sd, uint16_t *buf,
0150          u_int start_addr, u_int count)
0151 {
0152     int i = 0;
0153     u_int k = 0;
0154     uint16_t v;
0155     uint8_t temp;
0156
0157     /*
0158      * Read the requested registers of the seeprom.  The loop
0159      * will range from 0 to count-1.
0160      */
0161     for (k = start_addr; k < count + start_addr; k++) {
0162         /*
0163          * Now we're ready to send the read command followed by the
0164          * address of the 16-bit register we want to read.
0165          */
0166         send_seeprom_cmd(sd, &seeprom_read);
0167
0168         /* Send the 6 or 8 bit address (MSB first, LSB last). */
0169         temp = sd->sd_MS ^ sd->sd_CS;
0170         for (i = (sd->sd_chip - 1); i >= 0; i--) {
0171             if ((k & (1 << i)) != 0)
0172                 temp ^= sd->sd_DO;
0173             SEEPROM_OUTB(sd, temp);
0174             CLOCK_PULSE(sd, sd->sd_RDY);
0175             SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
0176             CLOCK_PULSE(sd, sd->sd_RDY);
0177             if ((k & (1 << i)) != 0)
0178                 temp ^= sd->sd_DO;
0179         }
0180
0181         /*
0182          * Now read the 16 bit register.  An initial 0 precedes the
0183          * register contents which begins with bit 15 (MSB) and ends
0184          * with bit 0 (LSB).  The initial 0 will be shifted off the
0185          * top of our word as we let the loop run from 0 to 16.
0186          */
0187         v = 0;
0188         for (i = 16; i >= 0; i--) {
0189             SEEPROM_OUTB(sd, temp);
0190             CLOCK_PULSE(sd, sd->sd_RDY);
0191             v <<= 1;
0192             if (SEEPROM_DATA_INB(sd) & sd->sd_DI)
0193                 v |= 1;
0194             SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
0195             CLOCK_PULSE(sd, sd->sd_RDY);
0196         }
0197
0198         buf[k - start_addr] = v;
0199
0200         /* Reset the chip select for the next command cycle. */
0201         reset_seeprom(sd);
0202     }
0203 #ifdef AHC_DUMP_EEPROM
0204     printk("\nSerial EEPROM:\n\t");
0205     for (k = 0; k < count; k = k + 1) {
0206         if (((k % 8) == 0) && (k != 0)) {
0207             printk(KERN_CONT "\n\t");
0208         }
0209         printk(KERN_CONT " 0x%x", buf[k]);
0210     }
0211     printk(KERN_CONT "\n");
0212 #endif
0213     return (1);
0214 }
0215
0216 /*
0217  * Write the serial EEPROM and return 1 if successful and 0 if
0218  * not successful.
0219  */
0220 int
0221 ahc_write_seeprom(struct seeprom_descriptor *sd, uint16_t *buf,
0222           u_int start_addr, u_int count)
0223 {
0224     const struct seeprom_cmd *ewen, *ewds;
0225     uint16_t v;
0226     uint8_t temp;
0227     int i, k;
0228
0229     /* Place the chip into write-enable mode */
0230     if (sd->sd_chip == C46) {
0231         ewen = &seeprom_ewen;
0232         ewds = &seeprom_ewds;
0233     } else if (sd->sd_chip == C56_66) {
0234         ewen = &seeprom_long_ewen;
0235         ewds = &seeprom_long_ewds;
0236     } else {
0237         printk("ahc_write_seeprom: unsupported seeprom type %d\n",
0238                sd->sd_chip);
0239         return (0);
0240     }
0241
0242     send_seeprom_cmd(sd, ewen);
0243     reset_seeprom(sd);
0244
0245     /* Write all requested data out to the seeprom. */
0246     temp = sd->sd_MS ^ sd->sd_CS;
0247     for (k = start_addr; k < count + start_addr; k++) {
0248         /* Send the write command */
0249         send_seeprom_cmd(sd, &seeprom_write);
0250
0251         /* Send the 6 or 8 bit address (MSB first). */
0252         for (i = (sd->sd_chip - 1); i >= 0; i--) {
0253             if ((k & (1 << i)) != 0)
0254                 temp ^= sd->sd_DO;
0255             SEEPROM_OUTB(sd, temp);
0256             CLOCK_PULSE(sd, sd->sd_RDY);
0257             SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
0258             CLOCK_PULSE(sd, sd->sd_RDY);
0259             if ((k & (1 << i)) != 0)
0260                 temp ^= sd->sd_DO;
0261         }
0262
0263         /* Write the 16 bit value, MSB first */
0264         v = buf[k - start_addr];
0265         for (i = 15; i >= 0; i--) {
0266             if ((v & (1 << i)) != 0)
0267                 temp ^= sd->sd_DO;
0268             SEEPROM_OUTB(sd, temp);
0269             CLOCK_PULSE(sd, sd->sd_RDY);
0270             SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
0271             CLOCK_PULSE(sd, sd->sd_RDY);
0272             if ((v & (1 << i)) != 0)
0273                 temp ^= sd->sd_DO;
0274         }
0275
0276         /* Wait for the chip to complete the write */
0277         temp = sd->sd_MS;
0278         SEEPROM_OUTB(sd, temp);
0279         CLOCK_PULSE(sd, sd->sd_RDY);
0280         temp = sd->sd_MS ^ sd->sd_CS;
0281         do {
0282             SEEPROM_OUTB(sd, temp);
0283             CLOCK_PULSE(sd, sd->sd_RDY);
0284             SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
0285             CLOCK_PULSE(sd, sd->sd_RDY);
0286         } while ((SEEPROM_DATA_INB(sd) & sd->sd_DI) == 0);
0287
0288         reset_seeprom(sd);
0289     }
0290
0291     /* Put the chip back into write-protect mode */
0292     send_seeprom_cmd(sd, ewds);
0293     reset_seeprom(sd);
0294
0295     return (1);
0296 }
0297
0298 int
0299 ahc_verify_cksum(struct seeprom_config *sc)
0300 {
0301     int i;
0302     int maxaddr;
0303     uint32_t checksum;
0304     uint16_t *scarray;
0305
0306     maxaddr = (sizeof(*sc)/2) - 1;
0307     checksum = 0;
0308     scarray = (uint16_t *)sc;
0309
0310     for (i = 0; i < maxaddr; i++)
0311         checksum = checksum + scarray[i];
0312     if (checksum == 0
0313      || (checksum & 0xFFFF) != sc->checksum) {
0314         return (0);
0315     } else {
0316         return(1);
0317     }
0318 }