0001 /*
0002 * Adaptec 274x/284x/294x device driver firmware for Linux and FreeBSD.
0003 *
0004 * Copyright (c) 1994-2001 Justin T. Gibbs.
0005 * Copyright (c) 2000-2001 Adaptec Inc.
0006 * All rights reserved.
0007 *
0008 * Redistribution and use in source and binary forms, with or without
0009 * modification, are permitted provided that the following conditions
0010 * are met:
0011 * 1. Redistributions of source code must retain the above copyright
0012 * notice, this list of conditions, and the following disclaimer,
0013 * without modification.
0014 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
0015 * substantially similar to the "NO WARRANTY" disclaimer below
0016 * ("Disclaimer") and any redistribution must be conditioned upon
0017 * including a substantially similar Disclaimer requirement for further
0018 * binary redistribution.
0019 * 3. Neither the names of the above-listed copyright holders nor the names
0020 * of any contributors may be used to endorse or promote products derived
0021 * from this software without specific prior written permission.
0022 *
0023 * Alternatively, this software may be distributed under the terms of the
0024 * GNU General Public License ("GPL") version 2 as published by the Free
0025 * Software Foundation.
0026 *
0027 * NO WARRANTY
0028 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0029 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0030 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
0031 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0032 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0033 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
0034 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
0035 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
0036 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
0037 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0038 * POSSIBILITY OF SUCH DAMAGES.
0039 *
0040 * $FreeBSD$
0041 */
0042
0043 VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#58 $"
0044 PATCH_ARG_LIST = "struct ahc_softc *ahc"
0045 PREFIX = "ahc_"
0046
0047 #include "aic7xxx.reg"
0048 #include "scsi_message.h"
0049
0050 /*
0051 * A few words on the waiting SCB list:
0052 * After starting the selection hardware, we check for reconnecting targets
0053 * as well as for our selection to complete just in case the reselection wins
0054 * bus arbitration. The problem with this is that we must keep track of the
0055 * SCB that we've already pulled from the QINFIFO and started the selection
0056 * on just in case the reselection wins so that we can retry the selection at
0057 * a later time. This problem cannot be resolved by holding a single entry
0058 * in scratch ram since a reconnecting target can request sense and this will
0059 * create yet another SCB waiting for selection. The solution used here is to
0060 * use byte 27 of the SCB as a pseudo-next pointer and to thread a list
0061 * of SCBs that are awaiting selection. Since 0-0xfe are valid SCB indexes,
0062 * SCB_LIST_NULL is 0xff which is out of range. An entry is also added to
0063 * this list every time a request sense occurs or after completing a non-tagged
0064 * command for which a second SCB has been queued. The sequencer will
0065 * automatically consume the entries.
0066 */
0067
0068 bus_free_sel:
0069 /*
0070 * Turn off the selection hardware. We need to reset the
0071 * selection request in order to perform a new selection.
0072 */
0073 and SCSISEQ, TEMODE|ENSELI|ENRSELI|ENAUTOATNP;
0074 and SIMODE1, ~ENBUSFREE;
0075 poll_for_work:
0076 call clear_target_state;
0077 and SXFRCTL0, ~SPIOEN;
0078 if ((ahc->features & AHC_ULTRA2) != 0) {
0079 clr SCSIBUSL;
0080 }
0081 test SCSISEQ, ENSELO jnz poll_for_selection;
0082 if ((ahc->features & AHC_TWIN) != 0) {
0083 xor SBLKCTL,SELBUSB; /* Toggle to the other bus */
0084 test SCSISEQ, ENSELO jnz poll_for_selection;
0085 }
0086 cmp WAITING_SCBH,SCB_LIST_NULL jne start_waiting;
0087 poll_for_work_loop:
0088 if ((ahc->features & AHC_TWIN) != 0) {
0089 xor SBLKCTL,SELBUSB; /* Toggle to the other bus */
0090 }
0091 test SSTAT0, SELDO|SELDI jnz selection;
0092 test_queue:
0093 /* Has the driver posted any work for us? */
0094 BEGIN_CRITICAL;
0095 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
0096 test QOFF_CTLSTA, SCB_AVAIL jz poll_for_work_loop;
0097 } else {
0098 mov A, QINPOS;
0099 cmp KERNEL_QINPOS, A je poll_for_work_loop;
0100 }
0101 mov ARG_1, NEXT_QUEUED_SCB;
0102
0103 /*
0104 * We have at least one queued SCB now and we don't have any
0105 * SCBs in the list of SCBs awaiting selection. Allocate a
0106 * card SCB for the host's SCB and get to work on it.
0107 */
0108 if ((ahc->flags & AHC_PAGESCBS) != 0) {
0109 mov ALLZEROS call get_free_or_disc_scb;
0110 } else {
0111 /* In the non-paging case, the SCBID == hardware SCB index */
0112 mov SCBPTR, ARG_1;
0113 }
0114 or SEQ_FLAGS2, SCB_DMA;
0115 END_CRITICAL;
0116 dma_queued_scb:
0117 /*
0118 * DMA the SCB from host ram into the current SCB location.
0119 */
0120 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
0121 mov ARG_1 call dma_scb;
0122 /*
0123 * Check one last time to see if this SCB was canceled
0124 * before we completed the DMA operation. If it was,
0125 * the QINFIFO next pointer will not match our saved
0126 * value.
0127 */
0128 mov A, ARG_1;
0129 BEGIN_CRITICAL;
0130 cmp NEXT_QUEUED_SCB, A jne abort_qinscb;
0131 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
0132 cmp SCB_TAG, A je . + 2;
0133 mvi SCB_MISMATCH call set_seqint;
0134 }
0135 mov NEXT_QUEUED_SCB, SCB_NEXT;
0136 mov SCB_NEXT,WAITING_SCBH;
0137 mov WAITING_SCBH, SCBPTR;
0138 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
0139 mov NONE, SNSCB_QOFF;
0140 } else {
0141 inc QINPOS;
0142 }
0143 and SEQ_FLAGS2, ~SCB_DMA;
0144 END_CRITICAL;
0145 start_waiting:
0146 /*
0147 * Start the first entry on the waiting SCB list.
0148 */
0149 mov SCBPTR, WAITING_SCBH;
0150 call start_selection;
0151
0152 poll_for_selection:
0153 /*
0154 * Twin channel devices cannot handle things like SELTO
0155 * interrupts on the "background" channel. So, while
0156 * selecting, keep polling the current channel until
0157 * either a selection or reselection occurs.
0158 */
0159 test SSTAT0, SELDO|SELDI jz poll_for_selection;
0160
0161 selection:
0162 /*
0163 * We aren't expecting a bus free, so interrupt
0164 * the kernel driver if it happens.
0165 */
0166 mvi CLRSINT1,CLRBUSFREE;
0167 if ((ahc->features & AHC_DT) == 0) {
0168 or SIMODE1, ENBUSFREE;
0169 }
0170
0171 /*
0172 * Guard against a bus free after (re)selection
0173 * but prior to enabling the busfree interrupt. SELDI
0174 * and SELDO will be cleared in that case.
0175 */
0176 test SSTAT0, SELDI|SELDO jz bus_free_sel;
0177 test SSTAT0,SELDO jnz select_out;
0178 select_in:
0179 if ((ahc->flags & AHC_TARGETROLE) != 0) {
0180 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
0181 test SSTAT0, TARGET jz initiator_reselect;
0182 }
0183 mvi CLRSINT0, CLRSELDI;
0184
0185 /*
0186 * We've just been selected. Assert BSY and
0187 * setup the phase for receiving messages
0188 * from the target.
0189 */
0190 mvi SCSISIGO, P_MESGOUT|BSYO;
0191
0192 /*
0193 * Setup the DMA for sending the identify and
0194 * command information.
0195 */
0196 mvi SEQ_FLAGS, CMDPHASE_PENDING;
0197
0198 mov A, TQINPOS;
0199 if ((ahc->features & AHC_CMD_CHAN) != 0) {
0200 mvi DINDEX, CCHADDR;
0201 mvi SHARED_DATA_ADDR call set_32byte_addr;
0202 mvi CCSCBCTL, CCSCBRESET;
0203 } else {
0204 mvi DINDEX, HADDR;
0205 mvi SHARED_DATA_ADDR call set_32byte_addr;
0206 mvi DFCNTRL, FIFORESET;
0207 }
0208
0209 /* Initiator that selected us */
0210 and SAVED_SCSIID, SELID_MASK, SELID;
0211 /* The Target ID we were selected at */
0212 if ((ahc->features & AHC_MULTI_TID) != 0) {
0213 and A, OID, TARGIDIN;
0214 } else if ((ahc->features & AHC_ULTRA2) != 0) {
0215 and A, OID, SCSIID_ULTRA2;
0216 } else {
0217 and A, OID, SCSIID;
0218 }
0219 or SAVED_SCSIID, A;
0220 if ((ahc->features & AHC_TWIN) != 0) {
0221 test SBLKCTL, SELBUSB jz . + 2;
0222 or SAVED_SCSIID, TWIN_CHNLB;
0223 }
0224 if ((ahc->features & AHC_CMD_CHAN) != 0) {
0225 mov CCSCBRAM, SAVED_SCSIID;
0226 } else {
0227 mov DFDAT, SAVED_SCSIID;
0228 }
0229
0230 /*
0231 * If ATN isn't asserted, the target isn't interested
0232 * in talking to us. Go directly to bus free.
0233 * XXX SCSI-1 may require us to assume lun 0 if
0234 * ATN is false.
0235 */
0236 test SCSISIGI, ATNI jz target_busfree;
0237
0238 /*
0239 * Watch ATN closely now as we pull in messages from the
0240 * initiator. We follow the guidlines from section 6.5
0241 * of the SCSI-2 spec for what messages are allowed when.
0242 */
0243 call target_inb;
0244
0245 /*
0246 * Our first message must be one of IDENTIFY, ABORT, or
0247 * BUS_DEVICE_RESET.
0248 */
0249 test DINDEX, MSG_IDENTIFYFLAG jz host_target_message_loop;
0250 /* Store for host */
0251 if ((ahc->features & AHC_CMD_CHAN) != 0) {
0252 mov CCSCBRAM, DINDEX;
0253 } else {
0254 mov DFDAT, DINDEX;
0255 }
0256 and SAVED_LUN, MSG_IDENTIFY_LUNMASK, DINDEX;
0257
0258 /* Remember for disconnection decision */
0259 test DINDEX, MSG_IDENTIFY_DISCFLAG jnz . + 2;
0260 /* XXX Honor per target settings too */
0261 or SEQ_FLAGS, NO_DISCONNECT;
0262
0263 test SCSISIGI, ATNI jz ident_messages_done;
0264 call target_inb;
0265 /*
0266 * If this is a tagged request, the tagged message must
0267 * immediately follow the identify. We test for a valid
0268 * tag message by seeing if it is >= MSG_SIMPLE_Q_TAG and
0269 * < MSG_IGN_WIDE_RESIDUE.
0270 */
0271 add A, -MSG_SIMPLE_Q_TAG, DINDEX;
0272 jnc ident_messages_done_msg_pending;
0273 add A, -MSG_IGN_WIDE_RESIDUE, DINDEX;
0274 jc ident_messages_done_msg_pending;
0275
0276 /* Store for host */
0277 if ((ahc->features & AHC_CMD_CHAN) != 0) {
0278 mov CCSCBRAM, DINDEX;
0279 } else {
0280 mov DFDAT, DINDEX;
0281 }
0282
0283 /*
0284 * If the initiator doesn't feel like providing a tag number,
0285 * we've got a failed selection and must transition to bus
0286 * free.
0287 */
0288 test SCSISIGI, ATNI jz target_busfree;
0289
0290 /*
0291 * Store the tag for the host.
0292 */
0293 call target_inb;
0294 if ((ahc->features & AHC_CMD_CHAN) != 0) {
0295 mov CCSCBRAM, DINDEX;
0296 } else {
0297 mov DFDAT, DINDEX;
0298 }
0299 mov INITIATOR_TAG, DINDEX;
0300 or SEQ_FLAGS, TARGET_CMD_IS_TAGGED;
0301
0302 ident_messages_done:
0303 /* Terminate the ident list */
0304 if ((ahc->features & AHC_CMD_CHAN) != 0) {
0305 mvi CCSCBRAM, SCB_LIST_NULL;
0306 } else {
0307 mvi DFDAT, SCB_LIST_NULL;
0308 }
0309 or SEQ_FLAGS, TARG_CMD_PENDING;
0310 test SEQ_FLAGS2, TARGET_MSG_PENDING
0311 jnz target_mesgout_pending;
0312 test SCSISIGI, ATNI jnz target_mesgout_continue;
0313 jmp target_ITloop;
0314
0315
0316 ident_messages_done_msg_pending:
0317 or SEQ_FLAGS2, TARGET_MSG_PENDING;
0318 jmp ident_messages_done;
0319
0320 /*
0321 * Pushed message loop to allow the kernel to
0322 * run it's own target mode message state engine.
0323 */
0324 host_target_message_loop:
0325 mvi HOST_MSG_LOOP call set_seqint;
0326 cmp RETURN_1, EXIT_MSG_LOOP je target_ITloop;
0327 test SSTAT0, SPIORDY jz .;
0328 jmp host_target_message_loop;
0329 }
0330
0331 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
0332 /*
0333 * Reselection has been initiated by a target. Make a note that we've been
0334 * reselected, but haven't seen an IDENTIFY message from the target yet.
0335 */
0336 initiator_reselect:
0337 /* XXX test for and handle ONE BIT condition */
0338 or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN;
0339 and SAVED_SCSIID, SELID_MASK, SELID;
0340 if ((ahc->features & AHC_ULTRA2) != 0) {
0341 and A, OID, SCSIID_ULTRA2;
0342 } else {
0343 and A, OID, SCSIID;
0344 }
0345 or SAVED_SCSIID, A;
0346 if ((ahc->features & AHC_TWIN) != 0) {
0347 test SBLKCTL, SELBUSB jz . + 2;
0348 or SAVED_SCSIID, TWIN_CHNLB;
0349 }
0350 mvi CLRSINT0, CLRSELDI;
0351 jmp ITloop;
0352 }
0353
0354 abort_qinscb:
0355 call add_scb_to_free_list;
0356 jmp poll_for_work_loop;
0357
0358 start_selection:
0359 /*
0360 * If bus reset interrupts have been disabled (from a previous
0361 * reset), re-enable them now. Resets are only of interest
0362 * when we have outstanding transactions, so we can safely
0363 * defer re-enabling the interrupt until, as an initiator,
0364 * we start sending out transactions again.
0365 */
0366 test SIMODE1, ENSCSIRST jnz . + 3;
0367 mvi CLRSINT1, CLRSCSIRSTI;
0368 or SIMODE1, ENSCSIRST;
0369 if ((ahc->features & AHC_TWIN) != 0) {
0370 and SINDEX,~SELBUSB,SBLKCTL;/* Clear channel select bit */
0371 test SCB_SCSIID, TWIN_CHNLB jz . + 2;
0372 or SINDEX, SELBUSB;
0373 mov SBLKCTL,SINDEX; /* select channel */
0374 }
0375 initialize_scsiid:
0376 if ((ahc->features & AHC_ULTRA2) != 0) {
0377 mov SCSIID_ULTRA2, SCB_SCSIID;
0378 } else if ((ahc->features & AHC_TWIN) != 0) {
0379 and SCSIID, TWIN_TID|OID, SCB_SCSIID;
0380 } else {
0381 mov SCSIID, SCB_SCSIID;
0382 }
0383 if ((ahc->flags & AHC_TARGETROLE) != 0) {
0384 mov SINDEX, SCSISEQ_TEMPLATE;
0385 test SCB_CONTROL, TARGET_SCB jz . + 2;
0386 or SINDEX, TEMODE;
0387 mov SCSISEQ, SINDEX ret;
0388 } else {
0389 mov SCSISEQ, SCSISEQ_TEMPLATE ret;
0390 }
0391
0392 /*
0393 * Initialize transfer settings with SCB provided settings.
0394 */
0395 set_transfer_settings:
0396 if ((ahc->features & AHC_ULTRA) != 0) {
0397 test SCB_CONTROL, ULTRAENB jz . + 2;
0398 or SXFRCTL0, FAST20;
0399 }
0400 /*
0401 * Initialize SCSIRATE with the appropriate value for this target.
0402 */
0403 if ((ahc->features & AHC_ULTRA2) != 0) {
0404 bmov SCSIRATE, SCB_SCSIRATE, 2 ret;
0405 } else {
0406 mov SCSIRATE, SCB_SCSIRATE ret;
0407 }
0408
0409 if ((ahc->flags & AHC_TARGETROLE) != 0) {
0410 /*
0411 * We carefully toggle SPIOEN to allow us to return the
0412 * message byte we receive so it can be checked prior to
0413 * driving REQ on the bus for the next byte.
0414 */
0415 target_inb:
0416 /*
0417 * Drive REQ on the bus by enabling SCSI PIO.
0418 */
0419 or SXFRCTL0, SPIOEN;
0420 /* Wait for the byte */
0421 test SSTAT0, SPIORDY jz .;
0422 /* Prevent our read from triggering another REQ */
0423 and SXFRCTL0, ~SPIOEN;
0424 /* Save latched contents */
0425 mov DINDEX, SCSIDATL ret;
0426 }
0427
0428 /*
0429 * After the selection, remove this SCB from the "waiting SCB"
0430 * list. This is achieved by simply moving our "next" pointer into
0431 * WAITING_SCBH. Our next pointer will be set to null the next time this
0432 * SCB is used, so don't bother with it now.
0433 */
0434 select_out:
0435 /* Turn off the selection hardware */
0436 and SCSISEQ, TEMODE|ENSELI|ENRSELI|ENAUTOATNP, SCSISEQ;
0437 mov SCBPTR, WAITING_SCBH;
0438 mov WAITING_SCBH,SCB_NEXT;
0439 mov SAVED_SCSIID, SCB_SCSIID;
0440 and SAVED_LUN, LID, SCB_LUN;
0441 call set_transfer_settings;
0442 if ((ahc->flags & AHC_TARGETROLE) != 0) {
0443 test SSTAT0, TARGET jz initiator_select;
0444
0445 or SXFRCTL0, CLRSTCNT|CLRCHN;
0446
0447 /*
0448 * Put tag in connonical location since not
0449 * all connections have an SCB.
0450 */
0451 mov INITIATOR_TAG, SCB_TARGET_ITAG;
0452
0453 /*
0454 * We've just re-selected an initiator.
0455 * Assert BSY and setup the phase for
0456 * sending our identify messages.
0457 */
0458 mvi P_MESGIN|BSYO call change_phase;
0459 mvi CLRSINT0, CLRSELDO;
0460
0461 /*
0462 * Start out with a simple identify message.
0463 */
0464 or SAVED_LUN, MSG_IDENTIFYFLAG call target_outb;
0465
0466 /*
0467 * If we are the result of a tagged command, send
0468 * a simple Q tag and the tag id.
0469 */
0470 test SCB_CONTROL, TAG_ENB jz . + 3;
0471 mvi MSG_SIMPLE_Q_TAG call target_outb;
0472 mov SCB_TARGET_ITAG call target_outb;
0473 target_synccmd:
0474 /*
0475 * Now determine what phases the host wants us
0476 * to go through.
0477 */
0478 mov SEQ_FLAGS, SCB_TARGET_PHASES;
0479
0480 test SCB_CONTROL, MK_MESSAGE jz target_ITloop;
0481 mvi P_MESGIN|BSYO call change_phase;
0482 jmp host_target_message_loop;
0483 target_ITloop:
0484 /*
0485 * Start honoring ATN signals now that
0486 * we properly identified ourselves.
0487 */
0488 test SCSISIGI, ATNI jnz target_mesgout;
0489 test SEQ_FLAGS, CMDPHASE_PENDING jnz target_cmdphase;
0490 test SEQ_FLAGS, DPHASE_PENDING jnz target_dphase;
0491 test SEQ_FLAGS, SPHASE_PENDING jnz target_sphase;
0492
0493 /*
0494 * No more work to do. Either disconnect or not depending
0495 * on the state of NO_DISCONNECT.
0496 */
0497 test SEQ_FLAGS, NO_DISCONNECT jz target_disconnect;
0498 mvi TARG_IMMEDIATE_SCB, SCB_LIST_NULL;
0499 call complete_target_cmd;
0500 if ((ahc->flags & AHC_PAGESCBS) != 0) {
0501 mov ALLZEROS call get_free_or_disc_scb;
0502 }
0503 cmp TARG_IMMEDIATE_SCB, SCB_LIST_NULL je .;
0504 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
0505 mov TARG_IMMEDIATE_SCB call dma_scb;
0506 call set_transfer_settings;
0507 or SXFRCTL0, CLRSTCNT|CLRCHN;
0508 jmp target_synccmd;
0509
0510 target_mesgout:
0511 mvi SCSISIGO, P_MESGOUT|BSYO;
0512 target_mesgout_continue:
0513 call target_inb;
0514 target_mesgout_pending:
0515 and SEQ_FLAGS2, ~TARGET_MSG_PENDING;
0516 /* Local Processing goes here... */
0517 jmp host_target_message_loop;
0518
0519 target_disconnect:
0520 mvi P_MESGIN|BSYO call change_phase;
0521 test SEQ_FLAGS, DPHASE jz . + 2;
0522 mvi MSG_SAVEDATAPOINTER call target_outb;
0523 mvi MSG_DISCONNECT call target_outb;
0524
0525 target_busfree_wait:
0526 /* Wait for preceding I/O session to complete. */
0527 test SCSISIGI, ACKI jnz .;
0528 target_busfree:
0529 and SIMODE1, ~ENBUSFREE;
0530 if ((ahc->features & AHC_ULTRA2) != 0) {
0531 clr SCSIBUSL;
0532 }
0533 clr SCSISIGO;
0534 mvi LASTPHASE, P_BUSFREE;
0535 call complete_target_cmd;
0536 jmp poll_for_work;
0537
0538 target_cmdphase:
0539 /*
0540 * The target has dropped ATN (doesn't want to abort or BDR)
0541 * and we believe this selection to be valid. If the ring
0542 * buffer for new commands is full, return busy or queue full.
0543 */
0544 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
0545 and A, HOST_TQINPOS, HS_MAILBOX;
0546 } else {
0547 mov A, KERNEL_TQINPOS;
0548 }
0549 cmp TQINPOS, A jne tqinfifo_has_space;
0550 mvi P_STATUS|BSYO call change_phase;
0551 test SEQ_FLAGS, TARGET_CMD_IS_TAGGED jz . + 3;
0552 mvi STATUS_QUEUE_FULL call target_outb;
0553 jmp target_busfree_wait;
0554 mvi STATUS_BUSY call target_outb;
0555 jmp target_busfree_wait;
0556 tqinfifo_has_space:
0557 mvi P_COMMAND|BSYO call change_phase;
0558 call target_inb;
0559 mov A, DINDEX;
0560 /* Store for host */
0561 if ((ahc->features & AHC_CMD_CHAN) != 0) {
0562 mov CCSCBRAM, A;
0563 } else {
0564 mov DFDAT, A;
0565 }
0566
0567 /*
0568 * Determine the number of bytes to read
0569 * based on the command group code via table lookup.
0570 * We reuse the first 8 bytes of the TARG_SCSIRATE
0571 * BIOS array for this table. Count is one less than
0572 * the total for the command since we've already fetched
0573 * the first byte.
0574 */
0575 shr A, CMD_GROUP_CODE_SHIFT;
0576 add SINDEX, CMDSIZE_TABLE, A;
0577 mov A, SINDIR;
0578
0579 test A, 0xFF jz command_phase_done;
0580 or SXFRCTL0, SPIOEN;
0581 command_loop:
0582 test SSTAT0, SPIORDY jz .;
0583 cmp A, 1 jne . + 2;
0584 and SXFRCTL0, ~SPIOEN; /* Last Byte */
0585 if ((ahc->features & AHC_CMD_CHAN) != 0) {
0586 mov CCSCBRAM, SCSIDATL;
0587 } else {
0588 mov DFDAT, SCSIDATL;
0589 }
0590 dec A;
0591 test A, 0xFF jnz command_loop;
0592
0593 command_phase_done:
0594 and SEQ_FLAGS, ~CMDPHASE_PENDING;
0595 jmp target_ITloop;
0596
0597 target_dphase:
0598 /*
0599 * Data phases on the bus are from the
0600 * perspective of the initiator. The dma
0601 * code looks at LASTPHASE to determine the
0602 * data direction of the DMA. Toggle it for
0603 * target transfers.
0604 */
0605 xor LASTPHASE, IOI, SCB_TARGET_DATA_DIR;
0606 or SCB_TARGET_DATA_DIR, BSYO call change_phase;
0607 jmp p_data;
0608
0609 target_sphase:
0610 mvi P_STATUS|BSYO call change_phase;
0611 mvi LASTPHASE, P_STATUS;
0612 mov SCB_SCSI_STATUS call target_outb;
0613 /* XXX Watch for ATN or parity errors??? */
0614 mvi SCSISIGO, P_MESGIN|BSYO;
0615 /* MSG_CMDCMPLT is 0, but we can't do an immediate of 0 */
0616 mov ALLZEROS call target_outb;
0617 jmp target_busfree_wait;
0618
0619 complete_target_cmd:
0620 test SEQ_FLAGS, TARG_CMD_PENDING jnz . + 2;
0621 mov SCB_TAG jmp complete_post;
0622 if ((ahc->features & AHC_CMD_CHAN) != 0) {
0623 /* Set the valid byte */
0624 mvi CCSCBADDR, 24;
0625 mov CCSCBRAM, ALLONES;
0626 mvi CCHCNT, 28;
0627 or CCSCBCTL, CCSCBEN|CCSCBRESET;
0628 test CCSCBCTL, CCSCBDONE jz .;
0629 clr CCSCBCTL;
0630 } else {
0631 /* Set the valid byte */
0632 or DFCNTRL, FIFORESET;
0633 mvi DFWADDR, 3; /* Third 64bit word or byte 24 */
0634 mov DFDAT, ALLONES;
0635 mvi 28 call set_hcnt;
0636 or DFCNTRL, HDMAEN|FIFOFLUSH;
0637 call dma_finish;
0638 }
0639 inc TQINPOS;
0640 mvi INTSTAT,CMDCMPLT ret;
0641 }
0642
0643 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
0644 initiator_select:
0645 or SXFRCTL0, SPIOEN|CLRSTCNT|CLRCHN;
0646 /*
0647 * As soon as we get a successful selection, the target
0648 * should go into the message out phase since we have ATN
0649 * asserted.
0650 */
0651 mvi MSG_OUT, MSG_IDENTIFYFLAG;
0652 mvi SEQ_FLAGS, NO_CDB_SENT;
0653 mvi CLRSINT0, CLRSELDO;
0654
0655 /*
0656 * Main loop for information transfer phases. Wait for the
0657 * target to assert REQ before checking MSG, C/D and I/O for
0658 * the bus phase.
0659 */
0660 mesgin_phasemis:
0661 ITloop:
0662 call phase_lock;
0663
0664 mov A, LASTPHASE;
0665
0666 test A, ~P_DATAIN jz p_data;
0667 cmp A,P_COMMAND je p_command;
0668 cmp A,P_MESGOUT je p_mesgout;
0669 cmp A,P_STATUS je p_status;
0670 cmp A,P_MESGIN je p_mesgin;
0671
0672 mvi BAD_PHASE call set_seqint;
0673 jmp ITloop; /* Try reading the bus again. */
0674
0675 await_busfree:
0676 and SIMODE1, ~ENBUSFREE;
0677 mov NONE, SCSIDATL; /* Ack the last byte */
0678 if ((ahc->features & AHC_ULTRA2) != 0) {
0679 clr SCSIBUSL; /* Prevent bit leakage durint SELTO */
0680 }
0681 and SXFRCTL0, ~SPIOEN;
0682 mvi SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT;
0683 test SSTAT1,REQINIT|BUSFREE jz .;
0684 test SSTAT1, BUSFREE jnz poll_for_work;
0685 mvi MISSED_BUSFREE call set_seqint;
0686 }
0687
0688 clear_target_state:
0689 /*
0690 * We assume that the kernel driver may reset us
0691 * at any time, even in the middle of a DMA, so
0692 * clear DFCNTRL too.
0693 */
0694 clr DFCNTRL;
0695 or SXFRCTL0, CLRSTCNT|CLRCHN;
0696
0697 /*
0698 * We don't know the target we will connect to,
0699 * so default to narrow transfers to avoid
0700 * parity problems.
0701 */
0702 if ((ahc->features & AHC_ULTRA2) != 0) {
0703 bmov SCSIRATE, ALLZEROS, 2;
0704 } else {
0705 clr SCSIRATE;
0706 if ((ahc->features & AHC_ULTRA) != 0) {
0707 and SXFRCTL0, ~(FAST20);
0708 }
0709 }
0710 mvi LASTPHASE, P_BUSFREE;
0711 /* clear target specific flags */
0712 mvi SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT ret;
0713
0714 sg_advance:
0715 clr A; /* add sizeof(struct scatter) */
0716 add SCB_RESIDUAL_SGPTR[0],SG_SIZEOF;
0717 adc SCB_RESIDUAL_SGPTR[1],A;
0718 adc SCB_RESIDUAL_SGPTR[2],A;
0719 adc SCB_RESIDUAL_SGPTR[3],A ret;
0720
0721 if ((ahc->features & AHC_CMD_CHAN) != 0) {
0722 disable_ccsgen:
0723 test CCSGCTL, CCSGEN jz return;
0724 test CCSGCTL, CCSGDONE jz .;
0725 disable_ccsgen_fetch_done:
0726 clr CCSGCTL;
0727 test CCSGCTL, CCSGEN jnz .;
0728 ret;
0729 idle_loop:
0730 /*
0731 * Do we need any more segments for this transfer?
0732 */
0733 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jnz return;
0734
0735 /* Did we just finish fetching segs? */
0736 cmp CCSGCTL, CCSGEN|CCSGDONE je idle_sgfetch_complete;
0737
0738 /* Are we actively fetching segments? */
0739 test CCSGCTL, CCSGEN jnz return;
0740
0741 /*
0742 * Do we have any prefetch left???
0743 */
0744 cmp CCSGADDR, SG_PREFETCH_CNT jne idle_sg_avail;
0745
0746 /*
0747 * Need to fetch segments, but we can only do that
0748 * if the command channel is completely idle. Make
0749 * sure we don't have an SCB prefetch going on.
0750 */
0751 test CCSCBCTL, CCSCBEN jnz return;
0752
0753 /*
0754 * We fetch a "cacheline aligned" and sized amount of data
0755 * so we don't end up referencing a non-existent page.
0756 * Cacheline aligned is in quotes because the kernel will
0757 * set the prefetch amount to a reasonable level if the
0758 * cacheline size is unknown.
0759 */
0760 mvi CCHCNT, SG_PREFETCH_CNT;
0761 and CCHADDR[0], SG_PREFETCH_ALIGN_MASK, SCB_RESIDUAL_SGPTR;
0762 bmov CCHADDR[1], SCB_RESIDUAL_SGPTR[1], 3;
0763 mvi CCSGCTL, CCSGEN|CCSGRESET ret;
0764 idle_sgfetch_complete:
0765 call disable_ccsgen_fetch_done;
0766 and CCSGADDR, SG_PREFETCH_ADDR_MASK, SCB_RESIDUAL_SGPTR;
0767 idle_sg_avail:
0768 if ((ahc->features & AHC_ULTRA2) != 0) {
0769 /* Does the hardware have space for another SG entry? */
0770 test DFSTATUS, PRELOAD_AVAIL jz return;
0771 bmov HADDR, CCSGRAM, 7;
0772 bmov SCB_RESIDUAL_DATACNT[3], CCSGRAM, 1;
0773 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
0774 mov SCB_RESIDUAL_DATACNT[3] call set_hhaddr;
0775 }
0776 call sg_advance;
0777 mov SINDEX, SCB_RESIDUAL_SGPTR[0];
0778 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2;
0779 or SINDEX, LAST_SEG;
0780 mov SG_CACHE_PRE, SINDEX;
0781 /* Load the segment */
0782 or DFCNTRL, PRELOADEN;
0783 }
0784 ret;
0785 }
0786
0787 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) {
0788 /*
0789 * Calculate the trailing portion of this S/G segment that cannot
0790 * be transferred using memory write and invalidate PCI transactions.
0791 * XXX Can we optimize this for PCI writes only???
0792 */
0793 calc_mwi_residual:
0794 /*
0795 * If the ending address is on a cacheline boundary,
0796 * there is no need for an extra segment.
0797 */
0798 mov A, HCNT[0];
0799 add A, A, HADDR[0];
0800 and A, CACHESIZE_MASK;
0801 test A, 0xFF jz return;
0802
0803 /*
0804 * If the transfer is less than a cachline,
0805 * there is no need for an extra segment.
0806 */
0807 test HCNT[1], 0xFF jnz calc_mwi_residual_final;
0808 test HCNT[2], 0xFF jnz calc_mwi_residual_final;
0809 add NONE, INVERTED_CACHESIZE_MASK, HCNT[0];
0810 jnc return;
0811
0812 calc_mwi_residual_final:
0813 mov MWI_RESIDUAL, A;
0814 not A;
0815 inc A;
0816 add HCNT[0], A;
0817 adc HCNT[1], -1;
0818 adc HCNT[2], -1 ret;
0819 }
0820
0821 p_data:
0822 test SEQ_FLAGS,NOT_IDENTIFIED|NO_CDB_SENT jz p_data_allowed;
0823 mvi PROTO_VIOLATION call set_seqint;
0824 p_data_allowed:
0825 if ((ahc->features & AHC_ULTRA2) != 0) {
0826 mvi DMAPARAMS, PRELOADEN|SCSIEN|HDMAEN;
0827 } else {
0828 mvi DMAPARAMS, WIDEODD|SCSIEN|SDMAEN|HDMAEN|FIFORESET;
0829 }
0830 test LASTPHASE, IOI jnz . + 2;
0831 or DMAPARAMS, DIRECTION;
0832 if ((ahc->features & AHC_CMD_CHAN) != 0) {
0833 /* We don't have any valid S/G elements */
0834 mvi CCSGADDR, SG_PREFETCH_CNT;
0835 }
0836 test SEQ_FLAGS, DPHASE jz data_phase_initialize;
0837
0838 /*
0839 * If we re-enter the data phase after going through another
0840 * phase, our transfer location has almost certainly been
0841 * corrupted by the interveining, non-data, transfers. Ask
0842 * the host driver to fix us up based on the transfer residual.
0843 */
0844 mvi PDATA_REINIT call set_seqint;
0845 jmp data_phase_loop;
0846
0847 data_phase_initialize:
0848 /* We have seen a data phase for the first time */
0849 or SEQ_FLAGS, DPHASE;
0850
0851 /*
0852 * Initialize the DMA address and counter from the SCB.
0853 * Also set SCB_RESIDUAL_SGPTR, including the LAST_SEG
0854 * flag in the highest byte of the data count. We cannot
0855 * modify the saved values in the SCB until we see a save
0856 * data pointers message.
0857 */
0858 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
0859 /* The lowest address byte must be loaded last. */
0860 mov SCB_DATACNT[3] call set_hhaddr;
0861 }
0862 if ((ahc->features & AHC_CMD_CHAN) != 0) {
0863 bmov HADDR, SCB_DATAPTR, 7;
0864 bmov SCB_RESIDUAL_DATACNT[3], SCB_DATACNT[3], 5;
0865 } else {
0866 mvi DINDEX, HADDR;
0867 mvi SCB_DATAPTR call bcopy_7;
0868 mvi DINDEX, SCB_RESIDUAL_DATACNT + 3;
0869 mvi SCB_DATACNT + 3 call bcopy_5;
0870 }
0871 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) {
0872 call calc_mwi_residual;
0873 }
0874 and SCB_RESIDUAL_SGPTR[0], ~SG_FULL_RESID;
0875
0876 if ((ahc->features & AHC_ULTRA2) == 0) {
0877 if ((ahc->features & AHC_CMD_CHAN) != 0) {
0878 bmov STCNT, HCNT, 3;
0879 } else {
0880 call set_stcnt_from_hcnt;
0881 }
0882 }
0883
0884 data_phase_loop:
0885 /* Guard against overruns */
0886 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz data_phase_inbounds;
0887
0888 /*
0889 * Turn on `Bit Bucket' mode, wait until the target takes
0890 * us to another phase, and then notify the host.
0891 */
0892 and DMAPARAMS, DIRECTION;
0893 mov DFCNTRL, DMAPARAMS;
0894 or SXFRCTL1,BITBUCKET;
0895 if ((ahc->features & AHC_DT) == 0) {
0896 test SSTAT1,PHASEMIS jz .;
0897 } else {
0898 test SCSIPHASE, DATA_PHASE_MASK jnz .;
0899 }
0900 and SXFRCTL1, ~BITBUCKET;
0901 mvi DATA_OVERRUN call set_seqint;
0902 jmp ITloop;
0903
0904 data_phase_inbounds:
0905 if ((ahc->features & AHC_ULTRA2) != 0) {
0906 mov SINDEX, SCB_RESIDUAL_SGPTR[0];
0907 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2;
0908 or SINDEX, LAST_SEG;
0909 mov SG_CACHE_PRE, SINDEX;
0910 mov DFCNTRL, DMAPARAMS;
0911 ultra2_dma_loop:
0912 call idle_loop;
0913 /*
0914 * The transfer is complete if either the last segment
0915 * completes or the target changes phase.
0916 */
0917 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz ultra2_dmafinish;
0918 if ((ahc->features & AHC_DT) == 0) {
0919 if ((ahc->flags & AHC_TARGETROLE) != 0) {
0920 /*
0921 * As a target, we control the phases,
0922 * so ignore PHASEMIS.
0923 */
0924 test SSTAT0, TARGET jnz ultra2_dma_loop;
0925 }
0926 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
0927 test SSTAT1,PHASEMIS jz ultra2_dma_loop;
0928 }
0929 } else {
0930 test DFCNTRL, SCSIEN jnz ultra2_dma_loop;
0931 }
0932
0933 ultra2_dmafinish:
0934 /*
0935 * The transfer has terminated either due to a phase
0936 * change, and/or the completion of the last segment.
0937 * We have two goals here. Do as much other work
0938 * as possible while the data fifo drains on a read
0939 * and respond as quickly as possible to the standard
0940 * messages (save data pointers/disconnect and command
0941 * complete) that usually follow a data phase.
0942 */
0943 if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) {
0944 /*
0945 * On chips with broken auto-flush, start
0946 * the flushing process now. We'll poke
0947 * the chip from time to time to keep the
0948 * flush process going as we complete the
0949 * data phase.
0950 */
0951 or DFCNTRL, FIFOFLUSH;
0952 }
0953 /*
0954 * We assume that, even though data may still be
0955 * transferring to the host, that the SCSI side of
0956 * the DMA engine is now in a static state. This
0957 * allows us to update our notion of where we are
0958 * in this transfer.
0959 *
0960 * If, by chance, we stopped before being able
0961 * to fetch additional segments for this transfer,
0962 * yet the last S/G was completely exhausted,
0963 * call our idle loop until it is able to load
0964 * another segment. This will allow us to immediately
0965 * pickup on the next segment on the next data phase.
0966 *
0967 * If we happened to stop on the last segment, then
0968 * our residual information is still correct from
0969 * the idle loop and there is no need to perform
0970 * any fixups.
0971 */
0972 ultra2_ensure_sg:
0973 test SG_CACHE_SHADOW, LAST_SEG jz ultra2_shvalid;
0974 /* Record if we've consumed all S/G entries */
0975 test SSTAT2, SHVALID jnz residuals_correct;
0976 or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL;
0977 jmp residuals_correct;
0978
0979 ultra2_shvalid:
0980 test SSTAT2, SHVALID jnz sgptr_fixup;
0981 call idle_loop;
0982 jmp ultra2_ensure_sg;
0983
0984 sgptr_fixup:
0985 /*
0986 * Fixup the residual next S/G pointer. The S/G preload
0987 * feature of the chip allows us to load two elements
0988 * in addition to the currently active element. We
0989 * store the bottom byte of the next S/G pointer in
0990 * the SG_CACEPTR register so we can restore the
0991 * correct value when the DMA completes. If the next
0992 * sg ptr value has advanced to the point where higher
0993 * bytes in the address have been affected, fix them
0994 * too.
0995 */
0996 test SG_CACHE_SHADOW, 0x80 jz sgptr_fixup_done;
0997 test SCB_RESIDUAL_SGPTR[0], 0x80 jnz sgptr_fixup_done;
0998 add SCB_RESIDUAL_SGPTR[1], -1;
0999 adc SCB_RESIDUAL_SGPTR[2], -1;
1000 adc SCB_RESIDUAL_SGPTR[3], -1;
1001 sgptr_fixup_done:
1002 and SCB_RESIDUAL_SGPTR[0], SG_ADDR_MASK, SG_CACHE_SHADOW;
1003 /* We are not the last seg */
1004 and SCB_RESIDUAL_DATACNT[3], ~SG_LAST_SEG;
1005 residuals_correct:
1006 /*
1007 * Go ahead and shut down the DMA engine now.
1008 * In the future, we'll want to handle end of
1009 * transfer messages prior to doing this, but this
1010 * requires similar restructuring for pre-ULTRA2
1011 * controllers.
1012 */
1013 test DMAPARAMS, DIRECTION jnz ultra2_fifoempty;
1014 ultra2_fifoflush:
1015 if ((ahc->features & AHC_DT) == 0) {
1016 if ((ahc->bugs & AHC_AUTOFLUSH_BUG) != 0) {
1017 /*
1018 * On Rev A of the aic7890, the autoflush
1019 * feature doesn't function correctly.
1020 * Perform an explicit manual flush. During
1021 * a manual flush, the FIFOEMP bit becomes
1022 * true every time the PCI FIFO empties
1023 * regardless of the state of the SCSI FIFO.
1024 * It can take up to 4 clock cycles for the
1025 * SCSI FIFO to get data into the PCI FIFO
1026 * and for FIFOEMP to de-assert. Here we
1027 * guard against this condition by making
1028 * sure the FIFOEMP bit stays on for 5 full
1029 * clock cycles.
1030 */
1031 or DFCNTRL, FIFOFLUSH;
1032 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1033 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1034 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1035 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1036 }
1037 test DFSTATUS, FIFOEMP jz ultra2_fifoflush;
1038 } else {
1039 /*
1040 * We enable the auto-ack feature on DT capable
1041 * controllers. This means that the controller may
1042 * have already transferred some overrun bytes into
1043 * the data FIFO and acked them on the bus. The only
1044 * way to detect this situation is to wait for
1045 * LAST_SEG_DONE to come true on a completed transfer
1046 * and then test to see if the data FIFO is non-empty.
1047 */
1048 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL
1049 jz ultra2_wait_fifoemp;
1050 test SG_CACHE_SHADOW, LAST_SEG_DONE jz .;
1051 /*
1052 * FIFOEMP can lag LAST_SEG_DONE. Wait a few
1053 * clocks before calling this an overrun.
1054 */
1055 test DFSTATUS, FIFOEMP jnz ultra2_fifoempty;
1056 test DFSTATUS, FIFOEMP jnz ultra2_fifoempty;
1057 test DFSTATUS, FIFOEMP jnz ultra2_fifoempty;
1058 /* Overrun */
1059 jmp data_phase_loop;
1060 ultra2_wait_fifoemp:
1061 test DFSTATUS, FIFOEMP jz .;
1062 }
1063 ultra2_fifoempty:
1064 /* Don't clobber an inprogress host data transfer */
1065 test DFSTATUS, MREQPEND jnz ultra2_fifoempty;
1066 ultra2_dmahalt:
1067 and DFCNTRL, ~(SCSIEN|HDMAEN);
1068 test DFCNTRL, SCSIEN|HDMAEN jnz .;
1069 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1070 /*
1071 * Keep HHADDR cleared for future, 32bit addressed
1072 * only, DMA operations.
1073 *
1074 * Due to bayonette style S/G handling, our residual
1075 * data must be "fixed up" once the transfer is halted.
1076 * Here we fixup the HSHADDR stored in the high byte
1077 * of the residual data cnt. By postponing the fixup,
1078 * we can batch the clearing of HADDR with the fixup.
1079 * If we halted on the last segment, the residual is
1080 * already correct. If we are not on the last
1081 * segment, copy the high address directly from HSHADDR.
1082 * We don't need to worry about maintaining the
1083 * SG_LAST_SEG flag as it will always be false in the
1084 * case where an update is required.
1085 */
1086 or DSCOMMAND1, HADDLDSEL0;
1087 test SG_CACHE_SHADOW, LAST_SEG jnz . + 2;
1088 mov SCB_RESIDUAL_DATACNT[3], SHADDR;
1089 clr HADDR;
1090 and DSCOMMAND1, ~HADDLDSEL0;
1091 }
1092 } else {
1093 /* If we are the last SG block, tell the hardware. */
1094 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1095 && ahc->pci_cachesize != 0) {
1096 test MWI_RESIDUAL, 0xFF jnz dma_mid_sg;
1097 }
1098 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz dma_mid_sg;
1099 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1100 test SSTAT0, TARGET jz dma_last_sg;
1101 if ((ahc->bugs & AHC_TMODE_WIDEODD_BUG) != 0) {
1102 test DMAPARAMS, DIRECTION jz dma_mid_sg;
1103 }
1104 }
1105 dma_last_sg:
1106 and DMAPARAMS, ~WIDEODD;
1107 dma_mid_sg:
1108 /* Start DMA data transfer. */
1109 mov DFCNTRL, DMAPARAMS;
1110 dma_loop:
1111 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1112 call idle_loop;
1113 }
1114 test SSTAT0,DMADONE jnz dma_dmadone;
1115 test SSTAT1,PHASEMIS jz dma_loop; /* ie. underrun */
1116 dma_phasemis:
1117 /*
1118 * We will be "done" DMAing when the transfer count goes to
1119 * zero, or the target changes the phase (in light of this,
1120 * it makes sense that the DMA circuitry doesn't ACK when
1121 * PHASEMIS is active). If we are doing a SCSI->Host transfer,
1122 * the data FIFO should be flushed auto-magically on STCNT=0
1123 * or a phase change, so just wait for FIFO empty status.
1124 */
1125 dma_checkfifo:
1126 test DFCNTRL,DIRECTION jnz dma_fifoempty;
1127 dma_fifoflush:
1128 test DFSTATUS,FIFOEMP jz dma_fifoflush;
1129 dma_fifoempty:
1130 /* Don't clobber an inprogress host data transfer */
1131 test DFSTATUS, MREQPEND jnz dma_fifoempty;
1132
1133 /*
1134 * Now shut off the DMA and make sure that the DMA
1135 * hardware has actually stopped. Touching the DMA
1136 * counters, etc. while a DMA is active will result
1137 * in an ILLSADDR exception.
1138 */
1139 dma_dmadone:
1140 and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN);
1141 dma_halt:
1142 /*
1143 * Some revisions of the aic78XX have a problem where, if the
1144 * data fifo is full, but the PCI input latch is not empty,
1145 * HDMAEN cannot be cleared. The fix used here is to drain
1146 * the prefetched but unused data from the data fifo until
1147 * there is space for the input latch to drain.
1148 */
1149 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) {
1150 mov NONE, DFDAT;
1151 }
1152 test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz dma_halt;
1153
1154 /* See if we have completed this last segment */
1155 test STCNT[0], 0xff jnz data_phase_finish;
1156 test STCNT[1], 0xff jnz data_phase_finish;
1157 test STCNT[2], 0xff jnz data_phase_finish;
1158
1159 /*
1160 * Advance the scatter-gather pointers if needed
1161 */
1162 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1163 && ahc->pci_cachesize != 0) {
1164 test MWI_RESIDUAL, 0xFF jz no_mwi_resid;
1165 /*
1166 * Reload HADDR from SHADDR and setup the
1167 * count to be the size of our residual.
1168 */
1169 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1170 bmov HADDR, SHADDR, 4;
1171 mov HCNT, MWI_RESIDUAL;
1172 bmov HCNT[1], ALLZEROS, 2;
1173 } else {
1174 mvi DINDEX, HADDR;
1175 mvi SHADDR call bcopy_4;
1176 mov MWI_RESIDUAL call set_hcnt;
1177 }
1178 clr MWI_RESIDUAL;
1179 jmp sg_load_done;
1180 no_mwi_resid:
1181 }
1182 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz sg_load;
1183 or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL;
1184 jmp data_phase_finish;
1185 sg_load:
1186 /*
1187 * Load the next SG element's data address and length
1188 * into the DMA engine. If we don't have hardware
1189 * to perform a prefetch, we'll have to fetch the
1190 * segment from host memory first.
1191 */
1192 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1193 /* Wait for the idle loop to complete */
1194 test CCSGCTL, CCSGEN jz . + 3;
1195 call idle_loop;
1196 test CCSGCTL, CCSGEN jnz . - 1;
1197 bmov HADDR, CCSGRAM, 7;
1198 /*
1199 * Workaround for flaky external SCB RAM
1200 * on certain aic7895 setups. It seems
1201 * unable to handle direct transfers from
1202 * S/G ram to certain SCB locations.
1203 */
1204 mov SINDEX, CCSGRAM;
1205 mov SCB_RESIDUAL_DATACNT[3], SINDEX;
1206 } else {
1207 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1208 mov ALLZEROS call set_hhaddr;
1209 }
1210 mvi DINDEX, HADDR;
1211 mvi SCB_RESIDUAL_SGPTR call bcopy_4;
1212
1213 mvi SG_SIZEOF call set_hcnt;
1214
1215 or DFCNTRL, HDMAEN|DIRECTION|FIFORESET;
1216
1217 call dma_finish;
1218
1219 mvi DINDEX, HADDR;
1220 call dfdat_in_7;
1221 mov SCB_RESIDUAL_DATACNT[3], DFDAT;
1222 }
1223
1224 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1225 mov SCB_RESIDUAL_DATACNT[3] call set_hhaddr;
1226
1227 /*
1228 * The lowest address byte must be loaded
1229 * last as it triggers the computation of
1230 * some items in the PCI block. The ULTRA2
1231 * chips do this on PRELOAD.
1232 */
1233 mov HADDR, HADDR;
1234 }
1235 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1236 && ahc->pci_cachesize != 0) {
1237 call calc_mwi_residual;
1238 }
1239
1240 /* Point to the new next sg in memory */
1241 call sg_advance;
1242
1243 sg_load_done:
1244 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1245 bmov STCNT, HCNT, 3;
1246 } else {
1247 call set_stcnt_from_hcnt;
1248 }
1249
1250 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1251 test SSTAT0, TARGET jnz data_phase_loop;
1252 }
1253 }
1254 data_phase_finish:
1255 /*
1256 * If the target has left us in data phase, loop through
1257 * the dma code again. In the case of ULTRA2 adapters,
1258 * we should only loop if there is a data overrun. For
1259 * all other adapters, we'll loop after each S/G element
1260 * is loaded as well as if there is an overrun.
1261 */
1262 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1263 test SSTAT0, TARGET jnz data_phase_done;
1264 }
1265 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
1266 test SSTAT1, REQINIT jz .;
1267 if ((ahc->features & AHC_DT) == 0) {
1268 test SSTAT1,PHASEMIS jz data_phase_loop;
1269 } else {
1270 test SCSIPHASE, DATA_PHASE_MASK jnz data_phase_loop;
1271 }
1272 }
1273
1274 data_phase_done:
1275 /*
1276 * After a DMA finishes, save the SG and STCNT residuals back into
1277 * the SCB. We use STCNT instead of HCNT, since it's a reflection
1278 * of how many bytes were transferred on the SCSI (as opposed to the
1279 * host) bus.
1280 */
1281 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1282 /* Kill off any pending prefetch */
1283 call disable_ccsgen;
1284 }
1285
1286 if ((ahc->features & AHC_ULTRA2) == 0) {
1287 /*
1288 * Clear the high address byte so that all other DMA
1289 * operations, which use 32bit addressing, can assume
1290 * HHADDR is 0.
1291 */
1292 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1293 mov ALLZEROS call set_hhaddr;
1294 }
1295 }
1296
1297 /*
1298 * Update our residual information before the information is
1299 * lost by some other type of SCSI I/O (e.g. PIO). If we have
1300 * transferred all data, no update is needed.
1301 *
1302 */
1303 test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jnz residual_update_done;
1304 if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0
1305 && ahc->pci_cachesize != 0) {
1306 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1307 test MWI_RESIDUAL, 0xFF jz bmov_resid;
1308 }
1309 mov A, MWI_RESIDUAL;
1310 add SCB_RESIDUAL_DATACNT[0], A, STCNT[0];
1311 clr A;
1312 adc SCB_RESIDUAL_DATACNT[1], A, STCNT[1];
1313 adc SCB_RESIDUAL_DATACNT[2], A, STCNT[2];
1314 clr MWI_RESIDUAL;
1315 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1316 jmp . + 2;
1317 bmov_resid:
1318 bmov SCB_RESIDUAL_DATACNT, STCNT, 3;
1319 }
1320 } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
1321 bmov SCB_RESIDUAL_DATACNT, STCNT, 3;
1322 } else {
1323 mov SCB_RESIDUAL_DATACNT[0], STCNT[0];
1324 mov SCB_RESIDUAL_DATACNT[1], STCNT[1];
1325 mov SCB_RESIDUAL_DATACNT[2], STCNT[2];
1326 }
1327 residual_update_done:
1328 /*
1329 * Since we've been through a data phase, the SCB_RESID* fields
1330 * are now initialized. Clear the full residual flag.
1331 */
1332 and SCB_SGPTR[0], ~SG_FULL_RESID;
1333
1334 if ((ahc->features & AHC_ULTRA2) != 0) {
1335 /* Clear the channel in case we return to data phase later */
1336 or SXFRCTL0, CLRSTCNT|CLRCHN;
1337 or SXFRCTL0, CLRSTCNT|CLRCHN;
1338 }
1339
1340 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1341 test SEQ_FLAGS, DPHASE_PENDING jz ITloop;
1342 and SEQ_FLAGS, ~DPHASE_PENDING;
1343 /*
1344 * For data-in phases, wait for any pending acks from the
1345 * initiator before changing phase. We only need to
1346 * send Ignore Wide Residue messages for data-in phases.
1347 */
1348 test DFCNTRL, DIRECTION jz target_ITloop;
1349 test SSTAT1, REQINIT jnz .;
1350 test SCB_LUN, SCB_XFERLEN_ODD jz target_ITloop;
1351 test SCSIRATE, WIDEXFER jz target_ITloop;
1352 /*
1353 * Issue an Ignore Wide Residue Message.
1354 */
1355 mvi P_MESGIN|BSYO call change_phase;
1356 mvi MSG_IGN_WIDE_RESIDUE call target_outb;
1357 mvi 1 call target_outb;
1358 jmp target_ITloop;
1359 } else {
1360 jmp ITloop;
1361 }
1362
1363 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
1364 /*
1365 * Command phase. Set up the DMA registers and let 'er rip.
1366 */
1367 p_command:
1368 test SEQ_FLAGS, NOT_IDENTIFIED jz p_command_okay;
1369 mvi PROTO_VIOLATION call set_seqint;
1370 p_command_okay:
1371
1372 if ((ahc->features & AHC_ULTRA2) != 0) {
1373 bmov HCNT[0], SCB_CDB_LEN, 1;
1374 bmov HCNT[1], ALLZEROS, 2;
1375 mvi SG_CACHE_PRE, LAST_SEG;
1376 } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
1377 bmov STCNT[0], SCB_CDB_LEN, 1;
1378 bmov STCNT[1], ALLZEROS, 2;
1379 } else {
1380 mov STCNT[0], SCB_CDB_LEN;
1381 clr STCNT[1];
1382 clr STCNT[2];
1383 }
1384 add NONE, -13, SCB_CDB_LEN;
1385 mvi SCB_CDB_STORE jnc p_command_embedded;
1386 p_command_from_host:
1387 if ((ahc->features & AHC_ULTRA2) != 0) {
1388 bmov HADDR[0], SCB_CDB_PTR, 4;
1389 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN|DIRECTION);
1390 } else {
1391 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1392 bmov HADDR[0], SCB_CDB_PTR, 4;
1393 bmov HCNT, STCNT, 3;
1394 } else {
1395 mvi DINDEX, HADDR;
1396 mvi SCB_CDB_PTR call bcopy_4;
1397 mov SCB_CDB_LEN call set_hcnt;
1398 }
1399 mvi DFCNTRL, (SCSIEN|SDMAEN|HDMAEN|DIRECTION|FIFORESET);
1400 }
1401 jmp p_command_xfer;
1402 p_command_embedded:
1403 /*
1404 * The data fifo seems to require 4 byte aligned
1405 * transfers from the sequencer. Force this to
1406 * be the case by clearing HADDR[0] even though
1407 * we aren't going to touch host memory.
1408 */
1409 clr HADDR[0];
1410 if ((ahc->features & AHC_ULTRA2) != 0) {
1411 mvi DFCNTRL, (PRELOADEN|SCSIEN|DIRECTION);
1412 bmov DFDAT, SCB_CDB_STORE, 12;
1413 } else if ((ahc->features & AHC_CMD_CHAN) != 0) {
1414 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1415 /*
1416 * On the 7895 the data FIFO will
1417 * get corrupted if you try to dump
1418 * data from external SCB memory into
1419 * the FIFO while it is enabled. So,
1420 * fill the fifo and then enable SCSI
1421 * transfers.
1422 */
1423 mvi DFCNTRL, (DIRECTION|FIFORESET);
1424 } else {
1425 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET);
1426 }
1427 bmov DFDAT, SCB_CDB_STORE, 12;
1428 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1429 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFOFLUSH);
1430 } else {
1431 or DFCNTRL, FIFOFLUSH;
1432 }
1433 } else {
1434 mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET);
1435 call copy_to_fifo_6;
1436 call copy_to_fifo_6;
1437 or DFCNTRL, FIFOFLUSH;
1438 }
1439 p_command_xfer:
1440 and SEQ_FLAGS, ~NO_CDB_SENT;
1441 if ((ahc->features & AHC_DT) == 0) {
1442 test SSTAT0, SDONE jnz . + 2;
1443 test SSTAT1, PHASEMIS jz . - 1;
1444 /*
1445 * Wait for our ACK to go-away on it's own
1446 * instead of being killed by SCSIEN getting cleared.
1447 */
1448 test SCSISIGI, ACKI jnz .;
1449 } else {
1450 test DFCNTRL, SCSIEN jnz .;
1451 }
1452 test SSTAT0, SDONE jnz p_command_successful;
1453 /*
1454 * Don't allow a data phase if the command
1455 * was not fully transferred.
1456 */
1457 or SEQ_FLAGS, NO_CDB_SENT;
1458 p_command_successful:
1459 and DFCNTRL, ~(SCSIEN|SDMAEN|HDMAEN);
1460 test DFCNTRL, (SCSIEN|SDMAEN|HDMAEN) jnz .;
1461 jmp ITloop;
1462
1463 /*
1464 * Status phase. Wait for the data byte to appear, then read it
1465 * and store it into the SCB.
1466 */
1467 p_status:
1468 test SEQ_FLAGS, NOT_IDENTIFIED jnz mesgin_proto_violation;
1469 p_status_okay:
1470 mov SCB_SCSI_STATUS, SCSIDATL;
1471 or SCB_CONTROL, STATUS_RCVD;
1472 jmp ITloop;
1473
1474 /*
1475 * Message out phase. If MSG_OUT is MSG_IDENTIFYFLAG, build a full
1476 * indentify message sequence and send it to the target. The host may
1477 * override this behavior by setting the MK_MESSAGE bit in the SCB
1478 * control byte. This will cause us to interrupt the host and allow
1479 * it to handle the message phase completely on its own. If the bit
1480 * associated with this target is set, we will also interrupt the host,
1481 * thereby allowing it to send a message on the next selection regardless
1482 * of the transaction being sent.
1483 *
1484 * If MSG_OUT is == HOST_MSG, also interrupt the host and take a message.
1485 * This is done to allow the host to send messages outside of an identify
1486 * sequence while protecting the seqencer from testing the MK_MESSAGE bit
1487 * on an SCB that might not be for the current nexus. (For example, a
1488 * BDR message in response to a bad reselection would leave us pointed to
1489 * an SCB that doesn't have anything to do with the current target).
1490 *
1491 * Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag,
1492 * bus device reset).
1493 *
1494 * When there are no messages to send, MSG_OUT should be set to MSG_NOOP,
1495 * in case the target decides to put us in this phase for some strange
1496 * reason.
1497 */
1498 p_mesgout_retry:
1499 /* Turn on ATN for the retry */
1500 if ((ahc->features & AHC_DT) == 0) {
1501 or SCSISIGO, ATNO, LASTPHASE;
1502 } else {
1503 mvi SCSISIGO, ATNO;
1504 }
1505 p_mesgout:
1506 mov SINDEX, MSG_OUT;
1507 cmp SINDEX, MSG_IDENTIFYFLAG jne p_mesgout_from_host;
1508 test SCB_CONTROL,MK_MESSAGE jnz host_message_loop;
1509 p_mesgout_identify:
1510 or SINDEX, MSG_IDENTIFYFLAG|DISCENB, SAVED_LUN;
1511 test SCB_CONTROL, DISCENB jnz . + 2;
1512 and SINDEX, ~DISCENB;
1513 /*
1514 * Send a tag message if TAG_ENB is set in the SCB control block.
1515 * Use SCB_TAG (the position in the kernel's SCB array) as the tag value.
1516 */
1517 p_mesgout_tag:
1518 test SCB_CONTROL,TAG_ENB jz p_mesgout_onebyte;
1519 mov SCSIDATL, SINDEX; /* Send the identify message */
1520 call phase_lock;
1521 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
1522 and SCSIDATL,TAG_ENB|SCB_TAG_TYPE,SCB_CONTROL;
1523 call phase_lock;
1524 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
1525 mov SCB_TAG jmp p_mesgout_onebyte;
1526 /*
1527 * Interrupt the driver, and allow it to handle this message
1528 * phase and any required retries.
1529 */
1530 p_mesgout_from_host:
1531 cmp SINDEX, HOST_MSG jne p_mesgout_onebyte;
1532 jmp host_message_loop;
1533
1534 p_mesgout_onebyte:
1535 mvi CLRSINT1, CLRATNO;
1536 mov SCSIDATL, SINDEX;
1537
1538 /*
1539 * If the next bus phase after ATN drops is message out, it means
1540 * that the target is requesting that the last message(s) be resent.
1541 */
1542 call phase_lock;
1543 cmp LASTPHASE, P_MESGOUT je p_mesgout_retry;
1544
1545 p_mesgout_done:
1546 mvi CLRSINT1,CLRATNO; /* Be sure to turn ATNO off */
1547 mov LAST_MSG, MSG_OUT;
1548 mvi MSG_OUT, MSG_NOOP; /* No message left */
1549 jmp ITloop;
1550
1551 /*
1552 * Message in phase. Bytes are read using Automatic PIO mode.
1553 */
1554 p_mesgin:
1555 mvi ACCUM call inb_first; /* read the 1st message byte */
1556
1557 test A,MSG_IDENTIFYFLAG jnz mesgin_identify;
1558 cmp A,MSG_DISCONNECT je mesgin_disconnect;
1559 cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs;
1560 cmp ALLZEROS,A je mesgin_complete;
1561 cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs;
1562 cmp A,MSG_IGN_WIDE_RESIDUE je mesgin_ign_wide_residue;
1563 cmp A,MSG_NOOP je mesgin_done;
1564
1565 /*
1566 * Pushed message loop to allow the kernel to
1567 * run it's own message state engine. To avoid an
1568 * extra nop instruction after signaling the kernel,
1569 * we perform the phase_lock before checking to see
1570 * if we should exit the loop and skip the phase_lock
1571 * in the ITloop. Performing back to back phase_locks
1572 * shouldn't hurt, but why do it twice...
1573 */
1574 host_message_loop:
1575 mvi HOST_MSG_LOOP call set_seqint;
1576 call phase_lock;
1577 cmp RETURN_1, EXIT_MSG_LOOP je ITloop + 1;
1578 jmp host_message_loop;
1579
1580 mesgin_ign_wide_residue:
1581 if ((ahc->features & AHC_WIDE) != 0) {
1582 test SCSIRATE, WIDEXFER jz mesgin_reject;
1583 /* Pull the residue byte */
1584 mvi ARG_1 call inb_next;
1585 cmp ARG_1, 0x01 jne mesgin_reject;
1586 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 2;
1587 test SCB_LUN, SCB_XFERLEN_ODD jnz mesgin_done;
1588 mvi IGN_WIDE_RES call set_seqint;
1589 jmp mesgin_done;
1590 }
1591
1592 mesgin_proto_violation:
1593 mvi PROTO_VIOLATION call set_seqint;
1594 jmp mesgin_done;
1595 mesgin_reject:
1596 mvi MSG_MESSAGE_REJECT call mk_mesg;
1597 mesgin_done:
1598 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1599 jmp ITloop;
1600
1601 /*
1602 * We received a "command complete" message. Put the SCB_TAG into the QOUTFIFO,
1603 * and trigger a completion interrupt. Before doing so, check to see if there
1604 * is a residual or the status byte is something other than STATUS_GOOD (0).
1605 * In either of these conditions, we upload the SCB back to the host so it can
1606 * process this information. In the case of a non zero status byte, we
1607 * additionally interrupt the kernel driver synchronously, allowing it to
1608 * decide if sense should be retrieved. If the kernel driver wishes to request
1609 * sense, it will fill the kernel SCB with a request sense command, requeue
1610 * it to the QINFIFO and tell us not to post to the QOUTFIFO by setting
1611 * RETURN_1 to SEND_SENSE.
1612 */
1613 mesgin_complete:
1614
1615 /*
1616 * If ATN is raised, we still want to give the target a message.
1617 * Perhaps there was a parity error on this last message byte.
1618 * Either way, the target should take us to message out phase
1619 * and then attempt to complete the command again. We should use a
1620 * critical section here to guard against a timeout triggering
1621 * for this command and setting ATN while we are still processing
1622 * the completion.
1623 test SCSISIGI, ATNI jnz mesgin_done;
1624 */
1625
1626 /*
1627 * If we are identified and have successfully sent the CDB,
1628 * any status will do. Optimize this fast path.
1629 */
1630 test SCB_CONTROL, STATUS_RCVD jz mesgin_proto_violation;
1631 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz complete_accepted;
1632
1633 /*
1634 * If the target never sent an identify message but instead went
1635 * to mesgin to give an invalid message, let the host abort us.
1636 */
1637 test SEQ_FLAGS, NOT_IDENTIFIED jnz mesgin_proto_violation;
1638
1639 /*
1640 * If we recevied good status but never successfully sent the
1641 * cdb, abort the command.
1642 */
1643 test SCB_SCSI_STATUS,0xff jnz complete_accepted;
1644 test SEQ_FLAGS, NO_CDB_SENT jnz mesgin_proto_violation;
1645
1646 complete_accepted:
1647 /*
1648 * See if we attempted to deliver a message but the target ingnored us.
1649 */
1650 test SCB_CONTROL, MK_MESSAGE jz . + 2;
1651 mvi MKMSG_FAILED call set_seqint;
1652
1653 /*
1654 * Check for residuals
1655 */
1656 test SCB_SGPTR, SG_LIST_NULL jnz check_status;/* No xfer */
1657 test SCB_SGPTR, SG_FULL_RESID jnz upload_scb;/* Never xfered */
1658 test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jz upload_scb;
1659 check_status:
1660 test SCB_SCSI_STATUS,0xff jz complete; /* Good Status? */
1661 upload_scb:
1662 or SCB_SGPTR, SG_RESID_VALID;
1663 mvi DMAPARAMS, FIFORESET;
1664 mov SCB_TAG call dma_scb;
1665 test SCB_SCSI_STATUS, 0xff jz complete; /* Just a residual? */
1666 mvi BAD_STATUS call set_seqint; /* let driver know */
1667 cmp RETURN_1, SEND_SENSE jne complete;
1668 call add_scb_to_free_list;
1669 jmp await_busfree;
1670 complete:
1671 mov SCB_TAG call complete_post;
1672 jmp await_busfree;
1673 }
1674
1675 complete_post:
1676 /* Post the SCBID in SINDEX and issue an interrupt */
1677 call add_scb_to_free_list;
1678 mov ARG_1, SINDEX;
1679 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
1680 mov A, SDSCB_QOFF;
1681 } else {
1682 mov A, QOUTPOS;
1683 }
1684 mvi QOUTFIFO_OFFSET call post_byte_setup;
1685 mov ARG_1 call post_byte;
1686 if ((ahc->features & AHC_QUEUE_REGS) == 0) {
1687 inc QOUTPOS;
1688 }
1689 mvi INTSTAT,CMDCMPLT ret;
1690
1691 if ((ahc->flags & AHC_INITIATORROLE) != 0) {
1692 /*
1693 * Is it a disconnect message? Set a flag in the SCB to remind us
1694 * and await the bus going free. If this is an untagged transaction
1695 * store the SCB id for it in our untagged target table for lookup on
1696 * a reselection.
1697 */
1698 mesgin_disconnect:
1699 /*
1700 * If ATN is raised, we still want to give the target a message.
1701 * Perhaps there was a parity error on this last message byte
1702 * or we want to abort this command. Either way, the target
1703 * should take us to message out phase and then attempt to
1704 * disconnect again.
1705 * XXX - Wait for more testing.
1706 test SCSISIGI, ATNI jnz mesgin_done;
1707 */
1708 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT
1709 jnz mesgin_proto_violation;
1710 or SCB_CONTROL,DISCONNECTED;
1711 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1712 call add_scb_to_disc_list;
1713 }
1714 test SCB_CONTROL, TAG_ENB jnz await_busfree;
1715 mov ARG_1, SCB_TAG;
1716 and SAVED_LUN, LID, SCB_LUN;
1717 mov SCB_SCSIID call set_busy_target;
1718 jmp await_busfree;
1719
1720 /*
1721 * Save data pointers message:
1722 * Copying RAM values back to SCB, for Save Data Pointers message, but
1723 * only if we've actually been into a data phase to change them. This
1724 * protects against bogus data in scratch ram and the residual counts
1725 * since they are only initialized when we go into data_in or data_out.
1726 * Ack the message as soon as possible. For chips without S/G pipelining,
1727 * we can only ack the message after SHADDR has been saved. On these
1728 * chips, SHADDR increments with every bus transaction, even PIO.
1729 */
1730 mesgin_sdptrs:
1731 if ((ahc->features & AHC_ULTRA2) != 0) {
1732 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1733 test SEQ_FLAGS, DPHASE jz ITloop;
1734 } else {
1735 test SEQ_FLAGS, DPHASE jz mesgin_done;
1736 }
1737
1738 /*
1739 * If we are asked to save our position at the end of the
1740 * transfer, just mark us at the end rather than perform a
1741 * full save.
1742 */
1743 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz mesgin_sdptrs_full;
1744 or SCB_SGPTR, SG_LIST_NULL;
1745 if ((ahc->features & AHC_ULTRA2) != 0) {
1746 jmp ITloop;
1747 } else {
1748 jmp mesgin_done;
1749 }
1750
1751 mesgin_sdptrs_full:
1752
1753 /*
1754 * The SCB_SGPTR becomes the next one we'll download,
1755 * and the SCB_DATAPTR becomes the current SHADDR.
1756 * Use the residual number since STCNT is corrupted by
1757 * any message transfer.
1758 */
1759 if ((ahc->features & AHC_CMD_CHAN) != 0) {
1760 bmov SCB_DATAPTR, SHADDR, 4;
1761 if ((ahc->features & AHC_ULTRA2) == 0) {
1762 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1763 }
1764 bmov SCB_DATACNT, SCB_RESIDUAL_DATACNT, 8;
1765 } else {
1766 mvi DINDEX, SCB_DATAPTR;
1767 mvi SHADDR call bcopy_4;
1768 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1769 mvi SCB_RESIDUAL_DATACNT call bcopy_8;
1770 }
1771 jmp ITloop;
1772
1773 /*
1774 * Restore pointers message? Data pointers are recopied from the
1775 * SCB anytime we enter a data phase for the first time, so all
1776 * we need to do is clear the DPHASE flag and let the data phase
1777 * code do the rest. We also reset/reallocate the FIFO to make
1778 * sure we have a clean start for the next data or command phase.
1779 */
1780 mesgin_rdptrs:
1781 and SEQ_FLAGS, ~DPHASE; /*
1782 * We'll reload them
1783 * the next time through
1784 * the dataphase.
1785 */
1786 or SXFRCTL0, CLRSTCNT|CLRCHN;
1787 jmp mesgin_done;
1788
1789 /*
1790 * Index into our Busy Target table. SINDEX and DINDEX are modified
1791 * upon return. SCBPTR may be modified by this action.
1792 */
1793 set_busy_target:
1794 shr DINDEX, 4, SINDEX;
1795 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1796 mov SCBPTR, SAVED_LUN;
1797 add DINDEX, SCB_64_BTT;
1798 } else {
1799 add DINDEX, BUSY_TARGETS;
1800 }
1801 mov DINDIR, ARG_1 ret;
1802
1803 /*
1804 * Identify message? For a reconnecting target, this tells us the lun
1805 * that the reconnection is for - find the correct SCB and switch to it,
1806 * clearing the "disconnected" bit so we don't "find" it by accident later.
1807 */
1808 mesgin_identify:
1809 /*
1810 * Determine whether a target is using tagged or non-tagged
1811 * transactions by first looking at the transaction stored in
1812 * the busy target array. If there is no untagged transaction
1813 * for this target or the transaction is for a different lun, then
1814 * this must be a tagged transaction.
1815 */
1816 shr SINDEX, 4, SAVED_SCSIID;
1817 and SAVED_LUN, MSG_IDENTIFY_LUNMASK, A;
1818 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1819 add SINDEX, SCB_64_BTT;
1820 mov SCBPTR, SAVED_LUN;
1821 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1822 add NONE, -SCB_64_BTT, SINDEX;
1823 jc . + 2;
1824 mvi INTSTAT, OUT_OF_RANGE;
1825 nop;
1826 add NONE, -(SCB_64_BTT + 16), SINDEX;
1827 jnc . + 2;
1828 mvi INTSTAT, OUT_OF_RANGE;
1829 nop;
1830 }
1831 } else {
1832 add SINDEX, BUSY_TARGETS;
1833 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1834 add NONE, -BUSY_TARGETS, SINDEX;
1835 jc . + 2;
1836 mvi INTSTAT, OUT_OF_RANGE;
1837 nop;
1838 add NONE, -(BUSY_TARGETS + 16), SINDEX;
1839 jnc . + 2;
1840 mvi INTSTAT, OUT_OF_RANGE;
1841 nop;
1842 }
1843 }
1844 mov ARG_1, SINDIR;
1845 cmp ARG_1, SCB_LIST_NULL je snoop_tag;
1846 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1847 mov ARG_1 call findSCB;
1848 } else {
1849 mov SCBPTR, ARG_1;
1850 }
1851 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1852 jmp setup_SCB_id_lun_okay;
1853 } else {
1854 /*
1855 * We only allow one untagged command per-target
1856 * at a time. So, if the lun doesn't match, look
1857 * for a tag message.
1858 */
1859 and A, LID, SCB_LUN;
1860 cmp SAVED_LUN, A je setup_SCB_id_lun_okay;
1861 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1862 /*
1863 * findSCB removes the SCB from the
1864 * disconnected list, so we must replace
1865 * it there should this SCB be for another
1866 * lun.
1867 */
1868 call cleanup_scb;
1869 }
1870 }
1871
1872 /*
1873 * Here we "snoop" the bus looking for a SIMPLE QUEUE TAG message.
1874 * If we get one, we use the tag returned to find the proper
1875 * SCB. With SCB paging, we must search for non-tagged
1876 * transactions since the SCB may exist in any slot. If we're not
1877 * using SCB paging, we can use the tag as the direct index to the
1878 * SCB.
1879 */
1880 snoop_tag:
1881 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1882 or SEQ_FLAGS, 0x80;
1883 }
1884 mov NONE,SCSIDATL; /* ACK Identify MSG */
1885 call phase_lock;
1886 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1887 or SEQ_FLAGS, 0x1;
1888 }
1889 cmp LASTPHASE, P_MESGIN jne not_found;
1890 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1891 or SEQ_FLAGS, 0x2;
1892 }
1893 cmp SCSIBUSL,MSG_SIMPLE_Q_TAG jne not_found;
1894 get_tag:
1895 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1896 mvi ARG_1 call inb_next; /* tag value */
1897 mov ARG_1 call findSCB;
1898 } else {
1899 mvi ARG_1 call inb_next; /* tag value */
1900 mov SCBPTR, ARG_1;
1901 }
1902
1903 /*
1904 * Ensure that the SCB the tag points to is for
1905 * an SCB transaction to the reconnecting target.
1906 */
1907 setup_SCB:
1908 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1909 or SEQ_FLAGS, 0x4;
1910 }
1911 mov A, SCB_SCSIID;
1912 cmp SAVED_SCSIID, A jne not_found_cleanup_scb;
1913 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1914 or SEQ_FLAGS, 0x8;
1915 }
1916 setup_SCB_id_okay:
1917 and A, LID, SCB_LUN;
1918 cmp SAVED_LUN, A jne not_found_cleanup_scb;
1919 setup_SCB_id_lun_okay:
1920 if ((ahc->flags & AHC_SEQUENCER_DEBUG) != 0) {
1921 or SEQ_FLAGS, 0x10;
1922 }
1923 test SCB_CONTROL,DISCONNECTED jz not_found_cleanup_scb;
1924 and SCB_CONTROL,~DISCONNECTED;
1925 test SCB_CONTROL, TAG_ENB jnz setup_SCB_tagged;
1926 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1927 mov A, SCBPTR;
1928 }
1929 mvi ARG_1, SCB_LIST_NULL;
1930 mov SAVED_SCSIID call set_busy_target;
1931 if ((ahc->flags & AHC_SCB_BTT) != 0) {
1932 mov SCBPTR, A;
1933 }
1934 setup_SCB_tagged:
1935 clr SEQ_FLAGS; /* make note of IDENTIFY */
1936 call set_transfer_settings;
1937 /* See if the host wants to send a message upon reconnection */
1938 test SCB_CONTROL, MK_MESSAGE jz mesgin_done;
1939 mvi HOST_MSG call mk_mesg;
1940 jmp mesgin_done;
1941
1942 not_found_cleanup_scb:
1943 if ((ahc->flags & AHC_PAGESCBS) != 0) {
1944 call cleanup_scb;
1945 }
1946 not_found:
1947 mvi NO_MATCH call set_seqint;
1948 jmp mesgin_done;
1949
1950 mk_mesg:
1951 if ((ahc->features & AHC_DT) == 0) {
1952 or SCSISIGO, ATNO, LASTPHASE;
1953 } else {
1954 mvi SCSISIGO, ATNO;
1955 }
1956 mov MSG_OUT,SINDEX ret;
1957
1958 /*
1959 * Functions to read data in Automatic PIO mode.
1960 *
1961 * According to Adaptec's documentation, an ACK is not sent on input from
1962 * the target until SCSIDATL is read from. So we wait until SCSIDATL is
1963 * latched (the usual way), then read the data byte directly off the bus
1964 * using SCSIBUSL. When we have pulled the ATN line, or we just want to
1965 * acknowledge the byte, then we do a dummy read from SCISDATL. The SCSI
1966 * spec guarantees that the target will hold the data byte on the bus until
1967 * we send our ACK.
1968 *
1969 * The assumption here is that these are called in a particular sequence,
1970 * and that REQ is already set when inb_first is called. inb_{first,next}
1971 * use the same calling convention as inb.
1972 */
1973 inb_next_wait_perr:
1974 mvi PERR_DETECTED call set_seqint;
1975 jmp inb_next_wait;
1976 inb_next:
1977 mov NONE,SCSIDATL; /*dummy read from latch to ACK*/
1978 inb_next_wait:
1979 /*
1980 * If there is a parity error, wait for the kernel to
1981 * see the interrupt and prepare our message response
1982 * before continuing.
1983 */
1984 test SSTAT1, REQINIT jz inb_next_wait;
1985 test SSTAT1, SCSIPERR jnz inb_next_wait_perr;
1986 inb_next_check_phase:
1987 and LASTPHASE, PHASE_MASK, SCSISIGI;
1988 cmp LASTPHASE, P_MESGIN jne mesgin_phasemis;
1989 inb_first:
1990 mov DINDEX,SINDEX;
1991 mov DINDIR,SCSIBUSL ret; /*read byte directly from bus*/
1992 inb_last:
1993 mov NONE,SCSIDATL ret; /*dummy read from latch to ACK*/
1994 }
1995
1996 if ((ahc->flags & AHC_TARGETROLE) != 0) {
1997 /*
1998 * Change to a new phase. If we are changing the state of the I/O signal,
1999 * from out to in, wait an additional data release delay before continuing.
2000 */
2001 change_phase:
2002 /* Wait for preceding I/O session to complete. */
2003 test SCSISIGI, ACKI jnz .;
2004
2005 /* Change the phase */
2006 and DINDEX, IOI, SCSISIGI;
2007 mov SCSISIGO, SINDEX;
2008 and A, IOI, SINDEX;
2009
2010 /*
2011 * If the data direction has changed, from
2012 * out (initiator driving) to in (target driving),
2013 * we must wait at least a data release delay plus
2014 * the normal bus settle delay. [SCSI III SPI 10.11.0]
2015 */
2016 cmp DINDEX, A je change_phase_wait;
2017 test SINDEX, IOI jz change_phase_wait;
2018 call change_phase_wait;
2019 change_phase_wait:
2020 nop;
2021 nop;
2022 nop;
2023 nop ret;
2024
2025 /*
2026 * Send a byte to an initiator in Automatic PIO mode.
2027 */
2028 target_outb:
2029 or SXFRCTL0, SPIOEN;
2030 test SSTAT0, SPIORDY jz .;
2031 mov SCSIDATL, SINDEX;
2032 test SSTAT0, SPIORDY jz .;
2033 and SXFRCTL0, ~SPIOEN ret;
2034 }
2035
2036 /*
2037 * Locate a disconnected SCB by SCBID. Upon return, SCBPTR and SINDEX will
2038 * be set to the position of the SCB. If the SCB cannot be found locally,
2039 * it will be paged in from host memory. RETURN_2 stores the address of the
2040 * preceding SCB in the disconnected list which can be used to speed up
2041 * removal of the found SCB from the disconnected list.
2042 */
2043 if ((ahc->flags & AHC_PAGESCBS) != 0) {
2044 BEGIN_CRITICAL;
2045 findSCB:
2046 mov A, SINDEX; /* Tag passed in SINDEX */
2047 cmp DISCONNECTED_SCBH, SCB_LIST_NULL je findSCB_notFound;
2048 mov SCBPTR, DISCONNECTED_SCBH; /* Initialize SCBPTR */
2049 mvi ARG_2, SCB_LIST_NULL; /* Head of list */
2050 jmp findSCB_loop;
2051 findSCB_next:
2052 cmp SCB_NEXT, SCB_LIST_NULL je findSCB_notFound;
2053 mov ARG_2, SCBPTR;
2054 mov SCBPTR,SCB_NEXT;
2055 findSCB_loop:
2056 cmp SCB_TAG, A jne findSCB_next;
2057 rem_scb_from_disc_list:
2058 cmp ARG_2, SCB_LIST_NULL je rHead;
2059 mov DINDEX, SCB_NEXT;
2060 mov SINDEX, SCBPTR;
2061 mov SCBPTR, ARG_2;
2062 mov SCB_NEXT, DINDEX;
2063 mov SCBPTR, SINDEX ret;
2064 rHead:
2065 mov DISCONNECTED_SCBH,SCB_NEXT ret;
2066 END_CRITICAL;
2067 findSCB_notFound:
2068 /*
2069 * We didn't find it. Page in the SCB.
2070 */
2071 mov ARG_1, A; /* Save tag */
2072 mov ALLZEROS call get_free_or_disc_scb;
2073 mvi DMAPARAMS, HDMAEN|DIRECTION|FIFORESET;
2074 mov ARG_1 jmp dma_scb;
2075 }
2076
2077 /*
2078 * Prepare the hardware to post a byte to host memory given an
2079 * index of (A + (256 * SINDEX)) and a base address of SHARED_DATA_ADDR.
2080 */
2081 post_byte_setup:
2082 mov ARG_2, SINDEX;
2083 if ((ahc->features & AHC_CMD_CHAN) != 0) {
2084 mvi DINDEX, CCHADDR;
2085 mvi SHARED_DATA_ADDR call set_1byte_addr;
2086 mvi CCHCNT, 1;
2087 mvi CCSCBCTL, CCSCBRESET ret;
2088 } else {
2089 mvi DINDEX, HADDR;
2090 mvi SHARED_DATA_ADDR call set_1byte_addr;
2091 mvi 1 call set_hcnt;
2092 mvi DFCNTRL, FIFORESET ret;
2093 }
2094
2095 post_byte:
2096 if ((ahc->features & AHC_CMD_CHAN) != 0) {
2097 bmov CCSCBRAM, SINDEX, 1;
2098 or CCSCBCTL, CCSCBEN|CCSCBRESET;
2099 test CCSCBCTL, CCSCBDONE jz .;
2100 clr CCSCBCTL ret;
2101 } else {
2102 mov DFDAT, SINDEX;
2103 or DFCNTRL, HDMAEN|FIFOFLUSH;
2104 jmp dma_finish;
2105 }
2106
2107 phase_lock_perr:
2108 mvi PERR_DETECTED call set_seqint;
2109 phase_lock:
2110 /*
2111 * If there is a parity error, wait for the kernel to
2112 * see the interrupt and prepare our message response
2113 * before continuing.
2114 */
2115 test SSTAT1, REQINIT jz phase_lock;
2116 test SSTAT1, SCSIPERR jnz phase_lock_perr;
2117 phase_lock_latch_phase:
2118 if ((ahc->features & AHC_DT) == 0) {
2119 and SCSISIGO, PHASE_MASK, SCSISIGI;
2120 }
2121 and LASTPHASE, PHASE_MASK, SCSISIGI ret;
2122
2123 if ((ahc->features & AHC_CMD_CHAN) == 0) {
2124 set_hcnt:
2125 mov HCNT[0], SINDEX;
2126 clear_hcnt:
2127 clr HCNT[1];
2128 clr HCNT[2] ret;
2129
2130 set_stcnt_from_hcnt:
2131 mov STCNT[0], HCNT[0];
2132 mov STCNT[1], HCNT[1];
2133 mov STCNT[2], HCNT[2] ret;
2134
2135 bcopy_8:
2136 mov DINDIR, SINDIR;
2137 bcopy_7:
2138 mov DINDIR, SINDIR;
2139 mov DINDIR, SINDIR;
2140 bcopy_5:
2141 mov DINDIR, SINDIR;
2142 bcopy_4:
2143 mov DINDIR, SINDIR;
2144 bcopy_3:
2145 mov DINDIR, SINDIR;
2146 mov DINDIR, SINDIR;
2147 mov DINDIR, SINDIR ret;
2148 }
2149
2150 if ((ahc->flags & AHC_TARGETROLE) != 0) {
2151 /*
2152 * Setup addr assuming that A is an index into
2153 * an array of 32byte objects, SINDEX contains
2154 * the base address of that array, and DINDEX
2155 * contains the base address of the location
2156 * to store the indexed address.
2157 */
2158 set_32byte_addr:
2159 shr ARG_2, 3, A;
2160 shl A, 5;
2161 jmp set_1byte_addr;
2162 }
2163
2164 /*
2165 * Setup addr assuming that A is an index into
2166 * an array of 64byte objects, SINDEX contains
2167 * the base address of that array, and DINDEX
2168 * contains the base address of the location
2169 * to store the indexed address.
2170 */
2171 set_64byte_addr:
2172 shr ARG_2, 2, A;
2173 shl A, 6;
2174
2175 /*
2176 * Setup addr assuming that A + (ARG_2 * 256) is an
2177 * index into an array of 1byte objects, SINDEX contains
2178 * the base address of that array, and DINDEX contains
2179 * the base address of the location to store the computed
2180 * address.
2181 */
2182 set_1byte_addr:
2183 add DINDIR, A, SINDIR;
2184 mov A, ARG_2;
2185 adc DINDIR, A, SINDIR;
2186 clr A;
2187 adc DINDIR, A, SINDIR;
2188 adc DINDIR, A, SINDIR ret;
2189
2190 /*
2191 * Either post or fetch an SCB from host memory based on the
2192 * DIRECTION bit in DMAPARAMS. The host SCB index is in SINDEX.
2193 */
2194 dma_scb:
2195 mov A, SINDEX;
2196 if ((ahc->features & AHC_CMD_CHAN) != 0) {
2197 mvi DINDEX, CCHADDR;
2198 mvi HSCB_ADDR call set_64byte_addr;
2199 mov CCSCBPTR, SCBPTR;
2200 test DMAPARAMS, DIRECTION jz dma_scb_tohost;
2201 if ((ahc->flags & AHC_SCB_BTT) != 0) {
2202 mvi CCHCNT, SCB_DOWNLOAD_SIZE_64;
2203 } else {
2204 mvi CCHCNT, SCB_DOWNLOAD_SIZE;
2205 }
2206 mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBDIR|CCSCBRESET;
2207 cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN|CCSCBDIR jne .;
2208 jmp dma_scb_finish;
2209 dma_scb_tohost:
2210 mvi CCHCNT, SCB_UPLOAD_SIZE;
2211 if ((ahc->features & AHC_ULTRA2) == 0) {
2212 mvi CCSCBCTL, CCSCBRESET;
2213 bmov CCSCBRAM, SCB_BASE, SCB_UPLOAD_SIZE;
2214 or CCSCBCTL, CCSCBEN|CCSCBRESET;
2215 test CCSCBCTL, CCSCBDONE jz .;
2216 } else if ((ahc->bugs & AHC_SCBCHAN_UPLOAD_BUG) != 0) {
2217 mvi CCSCBCTL, CCARREN|CCSCBRESET;
2218 cmp CCSCBCTL, ARRDONE|CCARREN jne .;
2219 mvi CCHCNT, SCB_UPLOAD_SIZE;
2220 mvi CCSCBCTL, CCSCBEN|CCSCBRESET;
2221 cmp CCSCBCTL, CCSCBDONE|CCSCBEN jne .;
2222 } else {
2223 mvi CCSCBCTL, CCARREN|CCSCBEN|CCSCBRESET;
2224 cmp CCSCBCTL, CCSCBDONE|ARRDONE|CCARREN|CCSCBEN jne .;
2225 }
2226 dma_scb_finish:
2227 clr CCSCBCTL;
2228 test CCSCBCTL, CCARREN|CCSCBEN jnz .;
2229 ret;
2230 } else {
2231 mvi DINDEX, HADDR;
2232 mvi HSCB_ADDR call set_64byte_addr;
2233 mvi SCB_DOWNLOAD_SIZE call set_hcnt;
2234 mov DFCNTRL, DMAPARAMS;
2235 test DMAPARAMS, DIRECTION jnz dma_scb_fromhost;
2236 /* Fill it with the SCB data */
2237 copy_scb_tofifo:
2238 mvi SINDEX, SCB_BASE;
2239 add A, SCB_DOWNLOAD_SIZE, SINDEX;
2240 copy_scb_tofifo_loop:
2241 call copy_to_fifo_8;
2242 cmp SINDEX, A jne copy_scb_tofifo_loop;
2243 or DFCNTRL, HDMAEN|FIFOFLUSH;
2244 jmp dma_finish;
2245 dma_scb_fromhost:
2246 mvi DINDEX, SCB_BASE;
2247 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0) {
2248 /*
2249 * The PCI module will only issue a PCI
2250 * retry if the data FIFO is empty. If the
2251 * host disconnects in the middle of a
2252 * transfer, we must empty the fifo of all
2253 * available data to force the chip to
2254 * continue the transfer. This does not
2255 * happen for SCSI transfers as the SCSI module
2256 * will drain the FIFO as data are made available.
2257 * When the hang occurs, we know that a multiple
2258 * of 8 bytes is in the FIFO because the PCI
2259 * module has an 8 byte input latch that only
2260 * dumps to the FIFO when HCNT == 0 or the
2261 * latch is full.
2262 */
2263 clr A;
2264 /* Wait for at least 8 bytes of data to arrive. */
2265 dma_scb_hang_fifo:
2266 test DFSTATUS, FIFOQWDEMP jnz dma_scb_hang_fifo;
2267 dma_scb_hang_wait:
2268 test DFSTATUS, MREQPEND jnz dma_scb_hang_wait;
2269 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done;
2270 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done;
2271 test DFSTATUS, HDONE jnz dma_scb_hang_dma_done;
2272 /*
2273 * The PCI module no longer intends to perform
2274 * a PCI transaction. Drain the fifo.
2275 */
2276 dma_scb_hang_dma_drain_fifo:
2277 not A, HCNT;
2278 add A, SCB_DOWNLOAD_SIZE+SCB_BASE+1;
2279 and A, ~0x7;
2280 mov DINDIR,DFDAT;
2281 cmp DINDEX, A jne . - 1;
2282 cmp DINDEX, SCB_DOWNLOAD_SIZE+SCB_BASE
2283 je dma_finish_nowait;
2284 /* Restore A as the lines left to transfer. */
2285 add A, -SCB_BASE, DINDEX;
2286 shr A, 3;
2287 jmp dma_scb_hang_fifo;
2288 dma_scb_hang_dma_done:
2289 and DFCNTRL, ~HDMAEN;
2290 test DFCNTRL, HDMAEN jnz .;
2291 add SEQADDR0, A;
2292 } else {
2293 call dma_finish;
2294 }
2295 call dfdat_in_8;
2296 call dfdat_in_8;
2297 call dfdat_in_8;
2298 dfdat_in_8:
2299 mov DINDIR,DFDAT;
2300 dfdat_in_7:
2301 mov DINDIR,DFDAT;
2302 mov DINDIR,DFDAT;
2303 mov DINDIR,DFDAT;
2304 mov DINDIR,DFDAT;
2305 mov DINDIR,DFDAT;
2306 dfdat_in_2:
2307 mov DINDIR,DFDAT;
2308 mov DINDIR,DFDAT ret;
2309 }
2310
2311 copy_to_fifo_8:
2312 mov DFDAT,SINDIR;
2313 mov DFDAT,SINDIR;
2314 copy_to_fifo_6:
2315 mov DFDAT,SINDIR;
2316 copy_to_fifo_5:
2317 mov DFDAT,SINDIR;
2318 copy_to_fifo_4:
2319 mov DFDAT,SINDIR;
2320 mov DFDAT,SINDIR;
2321 mov DFDAT,SINDIR;
2322 mov DFDAT,SINDIR ret;
2323
2324 /*
2325 * Wait for DMA from host memory to data FIFO to complete, then disable
2326 * DMA and wait for it to acknowledge that it's off.
2327 */
2328 dma_finish:
2329 test DFSTATUS,HDONE jz dma_finish;
2330 dma_finish_nowait:
2331 /* Turn off DMA */
2332 and DFCNTRL, ~HDMAEN;
2333 test DFCNTRL, HDMAEN jnz .;
2334 ret;
2335
2336 /*
2337 * Restore an SCB that failed to match an incoming reselection
2338 * to the correct/safe state. If the SCB is for a disconnected
2339 * transaction, it must be returned to the disconnected list.
2340 * If it is not in the disconnected state, it must be free.
2341 */
2342 cleanup_scb:
2343 if ((ahc->flags & AHC_PAGESCBS) != 0) {
2344 test SCB_CONTROL,DISCONNECTED jnz add_scb_to_disc_list;
2345 }
2346 add_scb_to_free_list:
2347 if ((ahc->flags & AHC_PAGESCBS) != 0) {
2348 BEGIN_CRITICAL;
2349 mov SCB_NEXT, FREE_SCBH;
2350 mvi SCB_TAG, SCB_LIST_NULL;
2351 mov FREE_SCBH, SCBPTR ret;
2352 END_CRITICAL;
2353 } else {
2354 mvi SCB_TAG, SCB_LIST_NULL ret;
2355 }
2356
2357 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
2358 set_hhaddr:
2359 or DSCOMMAND1, HADDLDSEL0;
2360 and HADDR, SG_HIGH_ADDR_BITS, SINDEX;
2361 and DSCOMMAND1, ~HADDLDSEL0 ret;
2362 }
2363
2364 if ((ahc->flags & AHC_PAGESCBS) != 0) {
2365 get_free_or_disc_scb:
2366 BEGIN_CRITICAL;
2367 cmp FREE_SCBH, SCB_LIST_NULL jne dequeue_free_scb;
2368 cmp DISCONNECTED_SCBH, SCB_LIST_NULL jne dequeue_disc_scb;
2369 return_error:
2370 mvi NO_FREE_SCB call set_seqint;
2371 mvi SINDEX, SCB_LIST_NULL ret;
2372 dequeue_disc_scb:
2373 mov SCBPTR, DISCONNECTED_SCBH;
2374 mov DISCONNECTED_SCBH, SCB_NEXT;
2375 END_CRITICAL;
2376 mvi DMAPARAMS, FIFORESET;
2377 mov SCB_TAG jmp dma_scb;
2378 BEGIN_CRITICAL;
2379 dequeue_free_scb:
2380 mov SCBPTR, FREE_SCBH;
2381 mov FREE_SCBH, SCB_NEXT ret;
2382 END_CRITICAL;
2383
2384 add_scb_to_disc_list:
2385 /*
2386 * Link this SCB into the DISCONNECTED list. This list holds the
2387 * candidates for paging out an SCB if one is needed for a new command.
2388 * Modifying the disconnected list is a critical(pause dissabled) section.
2389 */
2390 BEGIN_CRITICAL;
2391 mov SCB_NEXT, DISCONNECTED_SCBH;
2392 mov DISCONNECTED_SCBH, SCBPTR ret;
2393 END_CRITICAL;
2394 }
2395 set_seqint:
2396 mov INTSTAT, SINDEX;
2397 nop;
2398 return:
2399 ret;
