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0001 /*
0002  * Core definitions and data structures shareable across OS platforms.
0003  *
0004  * Copyright (c) 1994-2001 Justin T. Gibbs.
0005  * Copyright (c) 2000-2001 Adaptec Inc.
0006  * All rights reserved.
0007  *
0008  * Redistribution and use in source and binary forms, with or without
0009  * modification, are permitted provided that the following conditions
0010  * are met:
0011  * 1. Redistributions of source code must retain the above copyright
0012  *    notice, this list of conditions, and the following disclaimer,
0013  *    without modification.
0014  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
0015  *    substantially similar to the "NO WARRANTY" disclaimer below
0016  *    ("Disclaimer") and any redistribution must be conditioned upon
0017  *    including a substantially similar Disclaimer requirement for further
0018  *    binary redistribution.
0019  * 3. Neither the names of the above-listed copyright holders nor the names
0020  *    of any contributors may be used to endorse or promote products derived
0021  *    from this software without specific prior written permission.
0022  *
0023  * Alternatively, this software may be distributed under the terms of the
0024  * GNU General Public License ("GPL") version 2 as published by the Free
0025  * Software Foundation.
0026  *
0027  * NO WARRANTY
0028  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0029  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0030  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
0031  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0032  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0033  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
0034  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
0035  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
0036  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
0037  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0038  * POSSIBILITY OF SUCH DAMAGES.
0039  *
0040  * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.h#85 $
0041  *
0042  * $FreeBSD$
0043  */
0044 
0045 #ifndef _AIC7XXX_H_
0046 #define _AIC7XXX_H_
0047 
0048 /* Register Definitions */
0049 #include "aic7xxx_reg.h"
0050 
0051 /************************* Forward Declarations *******************************/
0052 struct ahc_platform_data;
0053 struct scb_platform_data;
0054 struct seeprom_descriptor;
0055 
0056 /****************************** Useful Macros *********************************/
0057 #ifndef TRUE
0058 #define TRUE 1
0059 #endif
0060 #ifndef FALSE
0061 #define FALSE 0
0062 #endif
0063 
0064 #define ALL_CHANNELS '\0'
0065 #define ALL_TARGETS_MASK 0xFFFF
0066 #define INITIATOR_WILDCARD  (~0)
0067 
0068 #define SCSIID_TARGET(ahc, scsiid) \
0069     (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \
0070     >> TID_SHIFT)
0071 #define SCSIID_OUR_ID(scsiid) \
0072     ((scsiid) & OID)
0073 #define SCSIID_CHANNEL(ahc, scsiid) \
0074     ((((ahc)->features & AHC_TWIN) != 0) \
0075         ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \
0076        : 'A')
0077 #define SCB_IS_SCSIBUS_B(ahc, scb) \
0078     (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B')
0079 #define SCB_GET_OUR_ID(scb) \
0080     SCSIID_OUR_ID((scb)->hscb->scsiid)
0081 #define SCB_GET_TARGET(ahc, scb) \
0082     SCSIID_TARGET((ahc), (scb)->hscb->scsiid)
0083 #define SCB_GET_CHANNEL(ahc, scb) \
0084     SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid)
0085 #define SCB_GET_LUN(scb) \
0086     ((scb)->hscb->lun & LID)
0087 #define SCB_GET_TARGET_OFFSET(ahc, scb) \
0088     (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0))
0089 #define SCB_GET_TARGET_MASK(ahc, scb) \
0090     (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb)))
0091 #ifdef AHC_DEBUG
0092 #define SCB_IS_SILENT(scb)                  \
0093     ((ahc_debug & AHC_SHOW_MASKED_ERRORS) == 0      \
0094       && (((scb)->flags & SCB_SILENT) != 0))
0095 #else
0096 #define SCB_IS_SILENT(scb)                  \
0097     (((scb)->flags & SCB_SILENT) != 0)
0098 #endif
0099 #define TCL_TARGET_OFFSET(tcl) \
0100     ((((tcl) >> 4) & TID) >> 4)
0101 #define TCL_LUN(tcl) \
0102     (tcl & (AHC_NUM_LUNS - 1))
0103 #define BUILD_TCL(scsiid, lun) \
0104     ((lun) | (((scsiid) & TID) << 4))
0105 
0106 #ifndef AHC_TARGET_MODE
0107 #undef  AHC_TMODE_ENABLE
0108 #define AHC_TMODE_ENABLE 0
0109 #endif
0110 
0111 /**************************** Driver Constants ********************************/
0112 /*
0113  * The maximum number of supported targets.
0114  */
0115 #define AHC_NUM_TARGETS 16
0116 
0117 /*
0118  * The maximum number of supported luns.
0119  * The identify message only supports 64 luns in SPI3.
0120  * You can have 2^64 luns when information unit transfers are enabled,
0121  * but it is doubtful this driver will ever support IUTs.
0122  */
0123 #define AHC_NUM_LUNS 64
0124 
0125 /*
0126  * The maximum transfer per S/G segment.
0127  */
0128 #define AHC_MAXTRANSFER_SIZE     0x00ffffff /* limited by 24bit counter */
0129 
0130 /*
0131  * The maximum amount of SCB storage in hardware on a controller.
0132  * This value represents an upper bound.  Controllers vary in the number
0133  * they actually support.
0134  */
0135 #define AHC_SCB_MAX 255
0136 
0137 /*
0138  * The maximum number of concurrent transactions supported per driver instance.
0139  * Sequencer Control Blocks (SCBs) store per-transaction information.  Although
0140  * the space for SCBs on the host adapter varies by model, the driver will
0141  * page the SCBs between host and controller memory as needed.  We are limited
0142  * to 253 because:
0143  *  1) The 8bit nature of the RISC engine holds us to an 8bit value.
0144  *  2) We reserve one value, 255, to represent the invalid element.
0145  *  3) Our input queue scheme requires one SCB to always be reserved
0146  *     in advance of queuing any SCBs.  This takes us down to 254.
0147  *  4) To handle our output queue correctly on machines that only
0148  *     support 32bit stores, we must clear the array 4 bytes at a
0149  *     time.  To avoid colliding with a DMA write from the sequencer,
0150  *     we must be sure that 4 slots are empty when we write to clear
0151  *     the queue.  This reduces us to 253 SCBs: 1 that just completed
0152  *     and the known three additional empty slots in the queue that
0153  *     precede it.
0154  */
0155 #define AHC_MAX_QUEUE   253
0156 
0157 /*
0158  * The maximum amount of SCB storage we allocate in host memory.  This
0159  * number should reflect the 1 additional SCB we require to handle our
0160  * qinfifo mechanism.
0161  */
0162 #define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1)
0163 
0164 /*
0165  * Ring Buffer of incoming target commands.
0166  * We allocate 256 to simplify the logic in the sequencer
0167  * by using the natural wrap point of an 8bit counter.
0168  */
0169 #define AHC_TMODE_CMDS  256
0170 
0171 /* Reset line assertion time in us */
0172 #define AHC_BUSRESET_DELAY  25
0173 
0174 /******************* Chip Characteristics/Operating Settings  *****************/
0175 /*
0176  * Chip Type
0177  * The chip order is from least sophisticated to most sophisticated.
0178  */
0179 typedef enum {
0180     AHC_NONE    = 0x0000,
0181     AHC_CHIPID_MASK = 0x00FF,
0182     AHC_AIC7770 = 0x0001,
0183     AHC_AIC7850 = 0x0002,
0184     AHC_AIC7855 = 0x0003,
0185     AHC_AIC7859 = 0x0004,
0186     AHC_AIC7860 = 0x0005,
0187     AHC_AIC7870 = 0x0006,
0188     AHC_AIC7880 = 0x0007,
0189     AHC_AIC7895 = 0x0008,
0190     AHC_AIC7895C    = 0x0009,
0191     AHC_AIC7890 = 0x000a,
0192     AHC_AIC7896 = 0x000b,
0193     AHC_AIC7892 = 0x000c,
0194     AHC_AIC7899 = 0x000d,
0195     AHC_VL      = 0x0100,   /* Bus type VL */
0196     AHC_EISA    = 0x0200,   /* Bus type EISA */
0197     AHC_PCI     = 0x0400,   /* Bus type PCI */
0198     AHC_BUS_MASK    = 0x0F00
0199 } ahc_chip;
0200 
0201 /*
0202  * Features available in each chip type.
0203  */
0204 typedef enum {
0205     AHC_FENONE  = 0x00000,
0206     AHC_ULTRA   = 0x00001,  /* Supports 20MHz Transfers */
0207     AHC_ULTRA2  = 0x00002,  /* Supports 40MHz Transfers */
0208     AHC_WIDE    = 0x00004,  /* Wide Channel */
0209     AHC_TWIN    = 0x00008,  /* Twin Channel */
0210     AHC_MORE_SRAM   = 0x00010,  /* 80 bytes instead of 64 */
0211     AHC_CMD_CHAN    = 0x00020,  /* Has a Command DMA Channel */
0212     AHC_QUEUE_REGS  = 0x00040,  /* Has Queue management registers */
0213     AHC_SG_PRELOAD  = 0x00080,  /* Can perform auto-SG preload */
0214     AHC_SPIOCAP = 0x00100,  /* Has a Serial Port I/O Cap Register */
0215     AHC_MULTI_TID   = 0x00200,  /* Has bitmask of TIDs for select-in */
0216     AHC_HS_MAILBOX  = 0x00400,  /* Has HS_MAILBOX register */
0217     AHC_DT      = 0x00800,  /* Double Transition transfers */
0218     AHC_NEW_TERMCTL = 0x01000,  /* Newer termination scheme */
0219     AHC_MULTI_FUNC  = 0x02000,  /* Multi-Function Twin Channel Device */
0220     AHC_LARGE_SCBS  = 0x04000,  /* 64byte SCBs */
0221     AHC_AUTORATE    = 0x08000,  /* Automatic update of SCSIRATE/OFFSET*/
0222     AHC_AUTOPAUSE   = 0x10000,  /* Automatic pause on register access */
0223     AHC_TARGETMODE  = 0x20000,  /* Has tested target mode support */
0224     AHC_MULTIROLE   = 0x40000,  /* Space for two roles at a time */
0225     AHC_REMOVABLE   = 0x80000,  /* Hot-Swap supported */
0226     AHC_HVD     = 0x100000, /* HVD rather than SE */
0227     AHC_AIC7770_FE  = AHC_FENONE,
0228     /*
0229      * The real 7850 does not support Ultra modes, but there are
0230      * several cards that use the generic 7850 PCI ID even though
0231      * they are using an Ultra capable chip (7859/7860).  We start
0232      * out with the AHC_ULTRA feature set and then check the DEVSTATUS
0233      * register to determine if the capability is really present.
0234      */
0235     AHC_AIC7850_FE  = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA,
0236     AHC_AIC7860_FE  = AHC_AIC7850_FE,
0237     AHC_AIC7870_FE  = AHC_TARGETMODE|AHC_AUTOPAUSE,
0238     AHC_AIC7880_FE  = AHC_AIC7870_FE|AHC_ULTRA,
0239     /*
0240      * Although we have space for both the initiator and
0241      * target roles on ULTRA2 chips, we currently disable
0242      * the initiator role to allow multi-scsi-id target mode
0243      * configurations.  We can only respond on the same SCSI
0244      * ID as our initiator role if we allow initiator operation.
0245      * At some point, we should add a configuration knob to
0246      * allow both roles to be loaded.
0247      */
0248     AHC_AIC7890_FE  = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2
0249               |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID
0250               |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS
0251               |AHC_TARGETMODE,
0252     AHC_AIC7892_FE  = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE,
0253     AHC_AIC7895_FE  = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE
0254               |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS,
0255     AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID,
0256     AHC_AIC7896_FE  = AHC_AIC7890_FE|AHC_MULTI_FUNC,
0257     AHC_AIC7899_FE  = AHC_AIC7892_FE|AHC_MULTI_FUNC
0258 } ahc_feature;
0259 
0260 /*
0261  * Bugs in the silicon that we work around in software.
0262  */
0263 typedef enum {
0264     AHC_BUGNONE     = 0x00,
0265     /*
0266      * On all chips prior to the U2 product line,
0267      * the WIDEODD S/G segment feature does not
0268      * work during scsi->HostBus transfers.
0269      */
0270     AHC_TMODE_WIDEODD_BUG   = 0x01,
0271     /*
0272      * On the aic7890/91 Rev 0 chips, the autoflush
0273      * feature does not work.  A manual flush of
0274      * the DMA FIFO is required.
0275      */
0276     AHC_AUTOFLUSH_BUG   = 0x02,
0277     /*
0278      * On many chips, cacheline streaming does not work.
0279      */
0280     AHC_CACHETHEN_BUG   = 0x04,
0281     /*
0282      * On the aic7896/97 chips, cacheline
0283      * streaming must be enabled.
0284      */
0285     AHC_CACHETHEN_DIS_BUG   = 0x08,
0286     /*
0287      * PCI 2.1 Retry failure on non-empty data fifo.
0288      */
0289     AHC_PCI_2_1_RETRY_BUG   = 0x10,
0290     /*
0291      * Controller does not handle cacheline residuals
0292      * properly on S/G segments if PCI MWI instructions
0293      * are allowed.
0294      */
0295     AHC_PCI_MWI_BUG     = 0x20,
0296     /*
0297      * An SCB upload using the SCB channel's
0298      * auto array entry copy feature may 
0299      * corrupt data.  This appears to only
0300      * occur on 66MHz systems.
0301      */
0302     AHC_SCBCHAN_UPLOAD_BUG  = 0x40
0303 } ahc_bug;
0304 
0305 /*
0306  * Configuration specific settings.
0307  * The driver determines these settings by probing the
0308  * chip/controller's configuration.
0309  */
0310 typedef enum {
0311     AHC_FNONE         = 0x000,
0312     AHC_PRIMARY_CHANNEL   = 0x003,  /*
0313                      * The channel that should
0314                      * be probed first.
0315                      */
0316     AHC_USEDEFAULTS       = 0x004,  /*
0317                      * For cards without an seeprom
0318                      * or a BIOS to initialize the chip's
0319                      * SRAM, we use the default target
0320                      * settings.
0321                      */
0322     AHC_SEQUENCER_DEBUG   = 0x008,
0323     AHC_SHARED_SRAM       = 0x010,
0324     AHC_LARGE_SEEPROM     = 0x020,  /* Uses C56_66 not C46 */
0325     AHC_RESET_BUS_A       = 0x040,
0326     AHC_RESET_BUS_B       = 0x080,
0327     AHC_EXTENDED_TRANS_A  = 0x100,
0328     AHC_EXTENDED_TRANS_B  = 0x200,
0329     AHC_TERM_ENB_A        = 0x400,
0330     AHC_TERM_ENB_B        = 0x800,
0331     AHC_INITIATORROLE     = 0x1000,  /*
0332                       * Allow initiator operations on
0333                       * this controller.
0334                       */
0335     AHC_TARGETROLE        = 0x2000,  /*
0336                       * Allow target operations on this
0337                       * controller.
0338                       */
0339     AHC_NEWEEPROM_FMT     = 0x4000,
0340     AHC_TQINFIFO_BLOCKED  = 0x10000,  /* Blocked waiting for ATIOs */
0341     AHC_INT50_SPEEDFLEX   = 0x20000,  /*
0342                        * Internal 50pin connector
0343                        * sits behind an aic3860
0344                        */
0345     AHC_SCB_BTT       = 0x40000,  /*
0346                        * The busy targets table is
0347                        * stored in SCB space rather
0348                        * than SRAM.
0349                        */
0350     AHC_BIOS_ENABLED      = 0x80000,
0351     AHC_ALL_INTERRUPTS    = 0x100000,
0352     AHC_PAGESCBS          = 0x400000,  /* Enable SCB paging */
0353     AHC_EDGE_INTERRUPT    = 0x800000,  /* Device uses edge triggered ints */
0354     AHC_39BIT_ADDRESSING  = 0x1000000, /* Use 39 bit addressing scheme. */
0355     AHC_LSCBS_ENABLED     = 0x2000000, /* 64Byte SCBs enabled */
0356     AHC_SCB_CONFIG_USED   = 0x4000000, /* No SEEPROM but SCB2 had info. */
0357     AHC_NO_BIOS_INIT      = 0x8000000, /* No BIOS left over settings. */
0358     AHC_DISABLE_PCI_PERR  = 0x10000000,
0359     AHC_HAS_TERM_LOGIC    = 0x20000000
0360 } ahc_flag;
0361 
0362 /************************* Hardware  SCB Definition ***************************/
0363 
0364 /*
0365  * The driver keeps up to MAX_SCB scb structures per card in memory.  The SCB
0366  * consists of a "hardware SCB" mirroring the fields available on the card
0367  * and additional information the kernel stores for each transaction.
0368  *
0369  * To minimize space utilization, a portion of the hardware scb stores
0370  * different data during different portions of a SCSI transaction.
0371  * As initialized by the host driver for the initiator role, this area
0372  * contains the SCSI cdb (or a pointer to the  cdb) to be executed.  After
0373  * the cdb has been presented to the target, this area serves to store
0374  * residual transfer information and the SCSI status byte.
0375  * For the target role, the contents of this area do not change, but
0376  * still serve a different purpose than for the initiator role.  See
0377  * struct target_data for details.
0378  */
0379 
0380 /*
0381  * Status information embedded in the shared poriton of
0382  * an SCB after passing the cdb to the target.  The kernel
0383  * driver will only read this data for transactions that
0384  * complete abnormally (non-zero status byte).
0385  */
0386 struct status_pkt {
0387     uint32_t residual_datacnt;  /* Residual in the current S/G seg */
0388     uint32_t residual_sg_ptr;   /* The next S/G for this transfer */
0389     uint8_t  scsi_status;       /* Standard SCSI status byte */
0390 };
0391 
0392 /*
0393  * Target mode version of the shared data SCB segment.
0394  */
0395 struct target_data {
0396     uint32_t residual_datacnt;  /* Residual in the current S/G seg */
0397     uint32_t residual_sg_ptr;   /* The next S/G for this transfer */
0398     uint8_t  scsi_status;       /* SCSI status to give to initiator */
0399     uint8_t  target_phases;     /* Bitmap of phases to execute */
0400     uint8_t  data_phase;        /* Data-In or Data-Out */
0401     uint8_t  initiator_tag;     /* Initiator's transaction tag */
0402 };
0403 
0404 struct hardware_scb {
0405 /*0*/   union {
0406         /*
0407          * If the cdb is 12 bytes or less, we embed it directly
0408          * in the SCB.  For longer cdbs, we embed the address
0409          * of the cdb payload as seen by the chip and a DMA
0410          * is used to pull it in.
0411          */
0412         uint8_t  cdb[12];
0413         uint32_t cdb_ptr;
0414         struct   status_pkt status;
0415         struct   target_data tdata;
0416     } shared_data;
0417 /*
0418  * A word about residuals.
0419  * The scb is presented to the sequencer with the dataptr and datacnt
0420  * fields initialized to the contents of the first S/G element to
0421  * transfer.  The sgptr field is initialized to the bus address for
0422  * the S/G element that follows the first in the in core S/G array
0423  * or'ed with the SG_FULL_RESID flag.  Sgptr may point to an invalid
0424  * S/G entry for this transfer (single S/G element transfer with the
0425  * first elements address and length preloaded in the dataptr/datacnt
0426  * fields).  If no transfer is to occur, sgptr is set to SG_LIST_NULL.
0427  * The SG_FULL_RESID flag ensures that the residual will be correctly
0428  * noted even if no data transfers occur.  Once the data phase is entered,
0429  * the residual sgptr and datacnt are loaded from the sgptr and the
0430  * datacnt fields.  After each S/G element's dataptr and length are
0431  * loaded into the hardware, the residual sgptr is advanced.  After
0432  * each S/G element is expired, its datacnt field is checked to see
0433  * if the LAST_SEG flag is set.  If so, SG_LIST_NULL is set in the
0434  * residual sg ptr and the transfer is considered complete.  If the
0435  * sequencer determines that there is a residual in the tranfer, it
0436  * will set the SG_RESID_VALID flag in sgptr and dma the scb back into
0437  * host memory.  To sumarize:
0438  *
0439  * Sequencer:
0440  *  o A residual has occurred if SG_FULL_RESID is set in sgptr,
0441  *    or residual_sgptr does not have SG_LIST_NULL set.
0442  *
0443  *  o We are transferring the last segment if residual_datacnt has
0444  *    the SG_LAST_SEG flag set.
0445  *
0446  * Host:
0447  *  o A residual has occurred if a completed scb has the
0448  *    SG_RESID_VALID flag set.
0449  *
0450  *  o residual_sgptr and sgptr refer to the "next" sg entry
0451  *    and so may point beyond the last valid sg entry for the
0452  *    transfer.
0453  */ 
0454 /*12*/  uint32_t dataptr;
0455 /*16*/  uint32_t datacnt;       /*
0456                      * Byte 3 (numbered from 0) of
0457                      * the datacnt is really the
0458                      * 4th byte in that data address.
0459                      */
0460 /*20*/  uint32_t sgptr;
0461 #define SG_PTR_MASK 0xFFFFFFF8
0462 /*24*/  uint8_t  control;   /* See SCB_CONTROL in aic7xxx.reg for details */
0463 /*25*/  uint8_t  scsiid;    /* what to load in the SCSIID register */
0464 /*26*/  uint8_t  lun;
0465 /*27*/  uint8_t  tag;           /*
0466                      * Index into our kernel SCB array.
0467                      * Also used as the tag for tagged I/O
0468                      */
0469 /*28*/  uint8_t  cdb_len;
0470 /*29*/  uint8_t  scsirate;      /* Value for SCSIRATE register */
0471 /*30*/  uint8_t  scsioffset;        /* Value for SCSIOFFSET register */
0472 /*31*/  uint8_t  next;          /*
0473                      * Used for threading SCBs in the
0474                      * "Waiting for Selection" and
0475                      * "Disconnected SCB" lists down
0476                      * in the sequencer.
0477                      */
0478 /*32*/  uint8_t  cdb32[32];     /*
0479                      * CDB storage for cdbs of size
0480                      * 13->32.  We store them here
0481                      * because hardware scbs are
0482                      * allocated from DMA safe
0483                      * memory so we are guaranteed
0484                      * the controller can access
0485                      * this data.
0486                      */
0487 };
0488 
0489 /************************ Kernel SCB Definitions ******************************/
0490 /*
0491  * Some fields of the SCB are OS dependent.  Here we collect the
0492  * definitions for elements that all OS platforms need to include
0493  * in there SCB definition.
0494  */
0495 
0496 /*
0497  * Definition of a scatter/gather element as transferred to the controller.
0498  * The aic7xxx chips only support a 24bit length.  We use the top byte of
0499  * the length to store additional address bits and a flag to indicate
0500  * that a given segment terminates the transfer.  This gives us an
0501  * addressable range of 512GB on machines with 64bit PCI or with chips
0502  * that can support dual address cycles on 32bit PCI busses.
0503  */
0504 struct ahc_dma_seg {
0505     uint32_t    addr;
0506     uint32_t    len;
0507 #define AHC_DMA_LAST_SEG    0x80000000
0508 #define AHC_SG_HIGH_ADDR_MASK   0x7F000000
0509 #define AHC_SG_LEN_MASK     0x00FFFFFF
0510 };
0511 
0512 struct sg_map_node {
0513     bus_dmamap_t         sg_dmamap;
0514     dma_addr_t       sg_physaddr;
0515     struct ahc_dma_seg*  sg_vaddr;
0516     SLIST_ENTRY(sg_map_node) links;
0517 };
0518 
0519 /*
0520  * The current state of this SCB.
0521  */
0522 typedef enum {
0523     SCB_FREE        = 0x0000,
0524     SCB_OTHERTCL_TIMEOUT    = 0x0002,/*
0525                       * Another device was active
0526                       * during the first timeout for
0527                       * this SCB so we gave ourselves
0528                       * an additional timeout period
0529                       * in case it was hogging the
0530                       * bus.
0531                           */
0532     SCB_DEVICE_RESET    = 0x0004,
0533     SCB_SENSE       = 0x0008,
0534     SCB_CDB32_PTR       = 0x0010,
0535     SCB_RECOVERY_SCB    = 0x0020,
0536     SCB_AUTO_NEGOTIATE  = 0x0040,/* Negotiate to achieve goal. */
0537     SCB_NEGOTIATE       = 0x0080,/* Negotiation forced for command. */
0538     SCB_ABORT       = 0x0100,
0539     SCB_UNTAGGEDQ       = 0x0200,
0540     SCB_ACTIVE      = 0x0400,
0541     SCB_TARGET_IMMEDIATE    = 0x0800,
0542     SCB_TRANSMISSION_ERROR  = 0x1000,/*
0543                       * We detected a parity or CRC
0544                       * error that has effected the
0545                       * payload of the command.  This
0546                       * flag is checked when normal
0547                       * status is returned to catch
0548                       * the case of a target not
0549                       * responding to our attempt
0550                       * to report the error.
0551                       */
0552     SCB_TARGET_SCB      = 0x2000,
0553     SCB_SILENT      = 0x4000 /*
0554                       * Be quiet about transmission type
0555                       * errors.  They are expected and we
0556                       * don't want to upset the user.  This
0557                       * flag is typically used during DV.
0558                       */
0559 } scb_flag;
0560 
0561 struct scb {
0562     struct  hardware_scb     *hscb;
0563     union {
0564         SLIST_ENTRY(scb)  sle;
0565         TAILQ_ENTRY(scb)  tqe;
0566     } links;
0567     LIST_ENTRY(scb)       pending_links;
0568     ahc_io_ctx_t          io_ctx;
0569     struct ahc_softc     *ahc_softc;
0570     scb_flag          flags;
0571     struct scb_platform_data *platform_data;
0572     struct sg_map_node   *sg_map;
0573     struct ahc_dma_seg   *sg_list;
0574     dma_addr_t        sg_list_phys;
0575     u_int             sg_count;/* How full ahc_dma_seg is */
0576 };
0577 
0578 struct scb_data {
0579     SLIST_HEAD(, scb) free_scbs;    /*
0580                      * Pool of SCBs ready to be assigned
0581                      * commands to execute.
0582                      */
0583     struct  scb *scbindex[256]; /*
0584                      * Mapping from tag to SCB.
0585                      * As tag identifiers are an
0586                      * 8bit value, we provide space
0587                      * for all possible tag values.
0588                      * Any lookups to entries at or
0589                      * above AHC_SCB_MAX_ALLOC will
0590                      * always fail.
0591                      */
0592     struct  hardware_scb    *hscbs; /* Array of hardware SCBs */
0593     struct  scb *scbarray;      /* Array of kernel SCBs */
0594     struct  scsi_sense_data *sense; /* Per SCB sense data */
0595 
0596     /*
0597      * "Bus" addresses of our data structures.
0598      */
0599     bus_dma_tag_t    hscb_dmat; /* dmat for our hardware SCB array */
0600     bus_dmamap_t     hscb_dmamap;
0601     dma_addr_t   hscb_busaddr;
0602     bus_dma_tag_t    sense_dmat;
0603     bus_dmamap_t     sense_dmamap;
0604     dma_addr_t   sense_busaddr;
0605     bus_dma_tag_t    sg_dmat;   /* dmat for our sg segments */
0606     SLIST_HEAD(, sg_map_node) sg_maps;
0607     uint8_t numscbs;
0608     uint8_t maxhscbs;       /* Number of SCBs on the card */
0609     uint8_t init_level;     /*
0610                      * How far we've initialized
0611                      * this structure.
0612                      */
0613 };
0614 
0615 /************************ Target Mode Definitions *****************************/
0616 
0617 /*
0618  * Connection descriptor for select-in requests in target mode.
0619  */
0620 struct target_cmd {
0621     uint8_t scsiid;     /* Our ID and the initiator's ID */
0622     uint8_t identify;   /* Identify message */
0623     uint8_t bytes[22];  /* 
0624                  * Bytes contains any additional message
0625                  * bytes terminated by 0xFF.  The remainder
0626                  * is the cdb to execute.
0627                  */
0628     uint8_t cmd_valid;  /*
0629                  * When a command is complete, the firmware
0630                  * will set cmd_valid to all bits set.
0631                  * After the host has seen the command,
0632                  * the bits are cleared.  This allows us
0633                  * to just peek at host memory to determine
0634                  * if more work is complete. cmd_valid is on
0635                  * an 8 byte boundary to simplify setting
0636                  * it on aic7880 hardware which only has
0637                  * limited direct access to the DMA FIFO.
0638                  */
0639     uint8_t pad[7];
0640 };
0641 
0642 /*
0643  * Number of events we can buffer up if we run out
0644  * of immediate notify ccbs.
0645  */
0646 #define AHC_TMODE_EVENT_BUFFER_SIZE 8
0647 struct ahc_tmode_event {
0648     uint8_t initiator_id;
0649     uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
0650 #define EVENT_TYPE_BUS_RESET 0xFF
0651     uint8_t event_arg;
0652 };
0653 
0654 /*
0655  * Per enabled lun target mode state.
0656  * As this state is directly influenced by the host OS'es target mode
0657  * environment, we let the OS module define it.  Forward declare the
0658  * structure here so we can store arrays of them, etc. in OS neutral
0659  * data structures.
0660  */
0661 #ifdef AHC_TARGET_MODE 
0662 struct ahc_tmode_lstate {
0663     struct cam_path *path;
0664     struct ccb_hdr_slist accept_tios;
0665     struct ccb_hdr_slist immed_notifies;
0666     struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE];
0667     uint8_t event_r_idx;
0668     uint8_t event_w_idx;
0669 };
0670 #else
0671 struct ahc_tmode_lstate;
0672 #endif
0673 
0674 /******************** Transfer Negotiation Datastructures *********************/
0675 #define AHC_TRANS_CUR       0x01    /* Modify current neogtiation status */
0676 #define AHC_TRANS_ACTIVE    0x03    /* Assume this target is on the bus */
0677 #define AHC_TRANS_GOAL      0x04    /* Modify negotiation goal */
0678 #define AHC_TRANS_USER      0x08    /* Modify user negotiation settings */
0679 
0680 #define AHC_WIDTH_UNKNOWN   0xFF
0681 #define AHC_PERIOD_UNKNOWN  0xFF
0682 #define AHC_OFFSET_UNKNOWN  0xFF
0683 #define AHC_PPR_OPTS_UNKNOWN    0xFF
0684 
0685 /*
0686  * Transfer Negotiation Information.
0687  */
0688 struct ahc_transinfo {
0689     uint8_t protocol_version;   /* SCSI Revision level */
0690     uint8_t transport_version;  /* SPI Revision level */
0691     uint8_t width;          /* Bus width */
0692     uint8_t period;         /* Sync rate factor */
0693     uint8_t offset;         /* Sync offset */
0694     uint8_t ppr_options;        /* Parallel Protocol Request options */
0695 };
0696 
0697 /*
0698  * Per-initiator current, goal and user transfer negotiation information. */
0699 struct ahc_initiator_tinfo {
0700     uint8_t scsirate;       /* Computed value for SCSIRATE reg */
0701     struct ahc_transinfo curr;
0702     struct ahc_transinfo goal;
0703     struct ahc_transinfo user;
0704 };
0705 
0706 /*
0707  * Per enabled target ID state.
0708  * Pointers to lun target state as well as sync/wide negotiation information
0709  * for each initiator<->target mapping.  For the initiator role we pretend
0710  * that we are the target and the targets are the initiators since the
0711  * negotiation is the same regardless of role.
0712  */
0713 struct ahc_tmode_tstate {
0714     struct ahc_tmode_lstate*    enabled_luns[AHC_NUM_LUNS];
0715     struct ahc_initiator_tinfo  transinfo[AHC_NUM_TARGETS];
0716 
0717     /*
0718      * Per initiator state bitmasks.
0719      */
0720     uint16_t     auto_negotiate;/* Auto Negotiation Required */
0721     uint16_t     ultraenb;  /* Using ultra sync rate  */
0722     uint16_t     discenable;    /* Disconnection allowed  */
0723     uint16_t     tagenable; /* Tagged Queuing allowed */
0724 };
0725 
0726 /*
0727  * Data structure for our table of allowed synchronous transfer rates.
0728  */
0729 struct ahc_syncrate {
0730     u_int sxfr_u2;  /* Value of the SXFR parameter for Ultra2+ Chips */
0731     u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */
0732 #define     ULTRA_SXFR 0x100    /* Rate Requires Ultra Mode set */
0733 #define     ST_SXFR    0x010    /* Rate Single Transition Only */
0734 #define     DT_SXFR    0x040    /* Rate Double Transition Only */
0735     uint8_t period; /* Period to send to SCSI target */
0736     const char *rate;
0737 };
0738 
0739 /* Safe and valid period for async negotiations. */
0740 #define AHC_ASYNC_XFER_PERIOD 0x45
0741 #define AHC_ULTRA2_XFER_PERIOD 0x0a
0742 
0743 /*
0744  * Indexes into our table of syncronous transfer rates.
0745  */
0746 #define AHC_SYNCRATE_DT     0
0747 #define AHC_SYNCRATE_ULTRA2 1
0748 #define AHC_SYNCRATE_ULTRA  3
0749 #define AHC_SYNCRATE_FAST   6
0750 #define AHC_SYNCRATE_MAX    AHC_SYNCRATE_DT
0751 #define AHC_SYNCRATE_MIN    13
0752 
0753 /***************************** Lookup Tables **********************************/
0754 /*
0755  * Phase -> name and message out response
0756  * to parity errors in each phase table. 
0757  */
0758 struct ahc_phase_table_entry {
0759         uint8_t phase;
0760         uint8_t mesg_out; /* Message response to parity errors */
0761     char *phasemsg;
0762 };
0763 
0764 /************************** Serial EEPROM Format ******************************/
0765 
0766 struct seeprom_config {
0767 /*
0768  * Per SCSI ID Configuration Flags
0769  */
0770     uint16_t device_flags[16];  /* words 0-15 */
0771 #define     CFXFER      0x0007  /* synchronous transfer rate */
0772 #define     CFSYNCH     0x0008  /* enable synchronous transfer */
0773 #define     CFDISC      0x0010  /* enable disconnection */
0774 #define     CFWIDEB     0x0020  /* wide bus device */
0775 #define     CFSYNCHISULTRA  0x0040  /* CFSYNCH is an ultra offset (2940AU)*/
0776 #define     CFSYNCSINGLE    0x0080  /* Single-Transition signalling */
0777 #define     CFSTART     0x0100  /* send start unit SCSI command */
0778 #define     CFINCBIOS   0x0200  /* include in BIOS scan */
0779 #define     CFRNFOUND   0x0400  /* report even if not found */
0780 #define     CFMULTILUNDEV   0x0800  /* Probe multiple luns in BIOS scan */
0781 #define     CFWBCACHEENB    0x4000  /* Enable W-Behind Cache on disks */
0782 #define     CFWBCACHENOP    0xc000  /* Don't touch W-Behind Cache */
0783 
0784 /*
0785  * BIOS Control Bits
0786  */
0787     uint16_t bios_control;      /* word 16 */
0788 #define     CFSUPREM    0x0001  /* support all removeable drives */
0789 #define     CFSUPREMB   0x0002  /* support removeable boot drives */
0790 #define     CFBIOSEN    0x0004  /* BIOS enabled */
0791 #define     CFBIOS_BUSSCAN  0x0008  /* Have the BIOS Scan the Bus */
0792 #define     CFSM2DRV    0x0010  /* support more than two drives */
0793 #define     CFSTPWLEVEL 0x0010  /* Termination level control */
0794 #define     CF284XEXTEND    0x0020  /* extended translation (284x cards) */ 
0795 #define     CFCTRL_A    0x0020  /* BIOS displays Ctrl-A message */  
0796 #define     CFTERM_MENU 0x0040  /* BIOS displays termination menu */    
0797 #define     CFEXTEND    0x0080  /* extended translation enabled */
0798 #define     CFSCAMEN    0x0100  /* SCAM enable */
0799 #define     CFMSG_LEVEL 0x0600  /* BIOS Message Level */
0800 #define         CFMSG_VERBOSE   0x0000
0801 #define         CFMSG_SILENT    0x0200
0802 #define         CFMSG_DIAG  0x0400
0803 #define     CFBOOTCD    0x0800  /* Support Bootable CD-ROM */
0804 /*      UNUSED      0xff00  */
0805 
0806 /*
0807  * Host Adapter Control Bits
0808  */
0809     uint16_t adapter_control;   /* word 17 */   
0810 #define     CFAUTOTERM  0x0001  /* Perform Auto termination */
0811 #define     CFULTRAEN   0x0002  /* Ultra SCSI speed enable */
0812 #define     CF284XSELTO     0x0003  /* Selection timeout (284x cards) */
0813 #define     CF284XFIFO      0x000C  /* FIFO Threshold (284x cards) */
0814 #define     CFSTERM     0x0004  /* SCSI low byte termination */
0815 #define     CFWSTERM    0x0008  /* SCSI high byte termination */
0816 #define     CFSPARITY   0x0010  /* SCSI parity */
0817 #define     CF284XSTERM     0x0020  /* SCSI low byte term (284x cards) */   
0818 #define     CFMULTILUN  0x0020
0819 #define     CFRESETB    0x0040  /* reset SCSI bus at boot */
0820 #define     CFCLUSTERENB    0x0080  /* Cluster Enable */
0821 #define     CFBOOTCHAN  0x0300  /* probe this channel first */
0822 #define     CFBOOTCHANSHIFT 8
0823 #define     CFSEAUTOTERM    0x0400  /* Ultra2 Perform secondary Auto Term*/
0824 #define     CFSELOWTERM 0x0800  /* Ultra2 secondary low term */
0825 #define     CFSEHIGHTERM    0x1000  /* Ultra2 secondary high term */
0826 #define     CFENABLEDV  0x4000  /* Perform Domain Validation*/
0827 
0828 /*
0829  * Bus Release Time, Host Adapter ID
0830  */
0831     uint16_t brtime_id;     /* word 18 */
0832 #define     CFSCSIID    0x000f  /* host adapter SCSI ID */
0833 /*      UNUSED      0x00f0  */
0834 #define     CFBRTIME    0xff00  /* bus release time */
0835 
0836 /*
0837  * Maximum targets
0838  */
0839     uint16_t max_targets;       /* word 19 */   
0840 #define     CFMAXTARG   0x00ff  /* maximum targets */
0841 #define     CFBOOTLUN   0x0f00  /* Lun to boot from */
0842 #define     CFBOOTID    0xf000  /* Target to boot from */
0843     uint16_t res_1[10];     /* words 20-29 */
0844     uint16_t signature;     /* Signature == 0x250 */
0845 #define     CFSIGNATURE 0x250
0846 #define     CFSIGNATURE2    0x300
0847     uint16_t checksum;      /* word 31 */
0848 };
0849 
0850 /****************************  Message Buffer *********************************/
0851 typedef enum {
0852     MSG_TYPE_NONE           = 0x00,
0853     MSG_TYPE_INITIATOR_MSGOUT   = 0x01,
0854     MSG_TYPE_INITIATOR_MSGIN    = 0x02,
0855     MSG_TYPE_TARGET_MSGOUT      = 0x03,
0856     MSG_TYPE_TARGET_MSGIN       = 0x04
0857 } ahc_msg_type;
0858 
0859 typedef enum {
0860     MSGLOOP_IN_PROG,
0861     MSGLOOP_MSGCOMPLETE,
0862     MSGLOOP_TERMINATED
0863 } msg_loop_stat;
0864 
0865 /*********************** Software Configuration Structure *********************/
0866 TAILQ_HEAD(scb_tailq, scb);
0867 
0868 struct ahc_aic7770_softc {
0869     /*
0870      * Saved register state used for chip_init().
0871      */
0872     uint8_t busspd;
0873     uint8_t bustime;
0874 };
0875 
0876 struct ahc_pci_softc {
0877     /*
0878      * Saved register state used for chip_init().
0879      */
0880     uint32_t  devconfig;
0881     uint16_t  targcrccnt;
0882     uint8_t   command;
0883     uint8_t   csize_lattime;
0884     uint8_t   optionmode;
0885     uint8_t   crccontrol1;
0886     uint8_t   dscommand0;
0887     uint8_t   dspcistatus;
0888     uint8_t   scbbaddr;
0889     uint8_t   dff_thrsh;
0890 };
0891 
0892 union ahc_bus_softc {
0893     struct ahc_aic7770_softc aic7770_softc;
0894     struct ahc_pci_softc pci_softc;
0895 };
0896 
0897 typedef void (*ahc_bus_intr_t)(struct ahc_softc *);
0898 typedef int (*ahc_bus_chip_init_t)(struct ahc_softc *);
0899 typedef void ahc_callback_t (void *);
0900 
0901 struct ahc_softc {
0902     bus_space_tag_t           tag;
0903     bus_space_handle_t        bsh;
0904     struct scb_data      *scb_data;
0905 
0906     struct scb       *next_queued_scb;
0907 
0908     /*
0909      * SCBs that have been sent to the controller
0910      */
0911     BSD_LIST_HEAD(, scb)      pending_scbs;
0912 
0913     /*
0914      * Counting lock for deferring the release of additional
0915      * untagged transactions from the untagged_queues.  When
0916      * the lock is decremented to 0, all queues in the
0917      * untagged_queues array are run.
0918      */
0919     u_int             untagged_queue_lock;
0920 
0921     /*
0922      * Per-target queue of untagged-transactions.  The
0923      * transaction at the head of the queue is the
0924      * currently pending untagged transaction for the
0925      * target.  The driver only allows a single untagged
0926      * transaction per target.
0927      */
0928     struct scb_tailq      untagged_queues[AHC_NUM_TARGETS];
0929 
0930     /*
0931      * Bus attachment specific data.
0932      */
0933     union ahc_bus_softc   bus_softc;
0934 
0935     /*
0936      * Platform specific data.
0937      */
0938     struct ahc_platform_data *platform_data;
0939 
0940     /*
0941      * Platform specific device information.
0942      */
0943     ahc_dev_softc_t       dev_softc;
0944     struct device         *dev;
0945 
0946     /*
0947      * Bus specific device information.
0948      */
0949     ahc_bus_intr_t        bus_intr;
0950 
0951     /*
0952      * Bus specific initialization required
0953      * after a chip reset.
0954      */
0955     ahc_bus_chip_init_t   bus_chip_init;
0956 
0957     /*
0958      * Target mode related state kept on a per enabled lun basis.
0959      * Targets that are not enabled will have null entries.
0960      * As an initiator, we keep one target entry for our initiator
0961      * ID to store our sync/wide transfer settings.
0962      */
0963     struct ahc_tmode_tstate  *enabled_targets[AHC_NUM_TARGETS];
0964 
0965     /*
0966      * The black hole device responsible for handling requests for
0967      * disabled luns on enabled targets.
0968      */
0969     struct ahc_tmode_lstate  *black_hole;
0970 
0971     /*
0972      * Device instance currently on the bus awaiting a continue TIO
0973      * for a command that was not given the disconnect priveledge.
0974      */
0975     struct ahc_tmode_lstate  *pending_device;
0976 
0977     /*
0978      * Card characteristics
0979      */
0980     ahc_chip          chip;
0981     ahc_feature       features;
0982     ahc_bug           bugs;
0983     ahc_flag          flags;
0984     struct seeprom_config    *seep_config;
0985 
0986     /* Values to store in the SEQCTL register for pause and unpause */
0987     uint8_t           unpause;
0988     uint8_t           pause;
0989 
0990     /* Command Queues */
0991     uint8_t           qoutfifonext;
0992     uint8_t           qinfifonext;
0993     uint8_t          *qoutfifo;
0994     uint8_t          *qinfifo;
0995 
0996     /* Critical Section Data */
0997     struct cs        *critical_sections;
0998     u_int             num_critical_sections;
0999 
1000     /* Channel Names ('A', 'B', etc.) */
1001     char              channel;
1002     char              channel_b;
1003 
1004     /* Initiator Bus ID */
1005     uint8_t           our_id;
1006     uint8_t           our_id_b;
1007 
1008     /*
1009      * PCI error detection.
1010      */
1011     int           unsolicited_ints;
1012 
1013     /*
1014      * Target incoming command FIFO.
1015      */
1016     struct target_cmd    *targetcmds;
1017     uint8_t           tqinfifonext;
1018 
1019     /*
1020      * Cached copy of the sequencer control register.
1021      */
1022     uint8_t           seqctl;
1023 
1024     /*
1025      * Incoming and outgoing message handling.
1026      */
1027     uint8_t           send_msg_perror;
1028     ahc_msg_type          msg_type;
1029     uint8_t           msgout_buf[12];/* Message we are sending */
1030     uint8_t           msgin_buf[12];/* Message we are receiving */
1031     u_int             msgout_len;   /* Length of message to send */
1032     u_int             msgout_index; /* Current index in msgout */
1033     u_int             msgin_index;  /* Current index in msgin */
1034 
1035     /*
1036      * Mapping information for data structures shared
1037      * between the sequencer and kernel.
1038      */
1039     bus_dma_tag_t         parent_dmat;
1040     bus_dma_tag_t         shared_data_dmat;
1041     bus_dmamap_t          shared_data_dmamap;
1042     dma_addr_t        shared_data_busaddr;
1043 
1044     /*
1045      * Bus address of the one byte buffer used to
1046      * work-around a DMA bug for chips <= aic7880
1047      * in target mode.
1048      */
1049     dma_addr_t        dma_bug_buf;
1050 
1051     /* Number of enabled target mode device on this card */
1052     u_int             enabled_luns;
1053 
1054     /* Initialization level of this data structure */
1055     u_int             init_level;
1056 
1057     /* PCI cacheline size. */
1058     u_int             pci_cachesize;
1059 
1060     /*
1061      * Count of parity errors we have seen as a target.
1062      * We auto-disable parity error checking after seeing
1063      * AHC_PCI_TARGET_PERR_THRESH number of errors.
1064      */
1065     u_int             pci_target_perr_count;
1066 #define     AHC_PCI_TARGET_PERR_THRESH  10
1067 
1068     /* Maximum number of sequencer instructions supported. */
1069     u_int             instruction_ram_size;
1070 
1071     /* Per-Unit descriptive information */
1072     const char       *description;
1073     char             *name;
1074     int           unit;
1075 
1076     /* Selection Timer settings */
1077     int           seltime;
1078     int           seltime_b;
1079 
1080     uint16_t          user_discenable;/* Disconnection allowed  */
1081     uint16_t          user_tagenable;/* Tagged Queuing allowed */
1082 };
1083 
1084 /************************ Active Device Information ***************************/
1085 typedef enum {
1086     ROLE_UNKNOWN,
1087     ROLE_INITIATOR,
1088     ROLE_TARGET
1089 } role_t;
1090 
1091 struct ahc_devinfo {
1092     int  our_scsiid;
1093     int  target_offset;
1094     uint16_t target_mask;
1095     u_int    target;
1096     u_int    lun;
1097     char     channel;
1098     role_t   role;      /*
1099                  * Only guaranteed to be correct if not
1100                  * in the busfree state.
1101                  */
1102 };
1103 
1104 /****************************** PCI Structures ********************************/
1105 typedef int (ahc_device_setup_t)(struct ahc_softc *);
1106 
1107 struct ahc_pci_identity {
1108     uint64_t         full_id;
1109     uint64_t         id_mask;
1110     const char      *name;
1111     ahc_device_setup_t  *setup;
1112 };
1113 
1114 /***************************** VL/EISA Declarations ***************************/
1115 struct aic7770_identity {
1116     uint32_t         full_id;
1117     uint32_t         id_mask;
1118     const char      *name;
1119     ahc_device_setup_t  *setup;
1120 };
1121 extern struct aic7770_identity aic7770_ident_table[];
1122 extern const int ahc_num_aic7770_devs;
1123 
1124 #define AHC_EISA_SLOT_OFFSET    0xc00
1125 #define AHC_EISA_IOSIZE     0x100
1126 
1127 /*************************** Function Declarations ****************************/
1128 /******************************************************************************/
1129 
1130 /***************************** PCI Front End *********************************/
1131 const struct ahc_pci_identity   *ahc_find_pci_device(ahc_dev_softc_t);
1132 int          ahc_pci_config(struct ahc_softc *,
1133                     const struct ahc_pci_identity *);
1134 int          ahc_pci_test_register_access(struct ahc_softc *);
1135 void __maybe_unused  ahc_pci_resume(struct ahc_softc *ahc);
1136 
1137 /*************************** EISA/VL Front End ********************************/
1138 struct aic7770_identity *aic7770_find_device(uint32_t);
1139 int          aic7770_config(struct ahc_softc *ahc,
1140                     struct aic7770_identity *,
1141                     u_int port);
1142 
1143 /************************** SCB and SCB queue management **********************/
1144 int     ahc_probe_scbs(struct ahc_softc *);
1145 void        ahc_qinfifo_requeue_tail(struct ahc_softc *ahc,
1146                      struct scb *scb);
1147 int     ahc_match_scb(struct ahc_softc *ahc, struct scb *scb,
1148                   int target, char channel, int lun,
1149                   u_int tag, role_t role);
1150 
1151 /****************************** Initialization ********************************/
1152 struct ahc_softc    *ahc_alloc(void *platform_arg, char *name);
1153 int          ahc_softc_init(struct ahc_softc *);
1154 void             ahc_controller_info(struct ahc_softc *ahc, char *buf);
1155 int          ahc_chip_init(struct ahc_softc *ahc);
1156 int          ahc_init(struct ahc_softc *ahc);
1157 void             ahc_intr_enable(struct ahc_softc *ahc, int enable);
1158 void             ahc_pause_and_flushwork(struct ahc_softc *ahc);
1159 int __maybe_unused   ahc_suspend(struct ahc_softc *ahc);
1160 int __maybe_unused   ahc_resume(struct ahc_softc *ahc);
1161 void             ahc_set_unit(struct ahc_softc *, int);
1162 void             ahc_set_name(struct ahc_softc *, char *);
1163 void             ahc_free(struct ahc_softc *ahc);
1164 int          ahc_reset(struct ahc_softc *ahc, int reinit);
1165 
1166 /***************************** Error Recovery *********************************/
1167 typedef enum {
1168     SEARCH_COMPLETE,
1169     SEARCH_COUNT,
1170     SEARCH_REMOVE
1171 } ahc_search_action;
1172 int         ahc_search_qinfifo(struct ahc_softc *ahc, int target,
1173                        char channel, int lun, u_int tag,
1174                        role_t role, uint32_t status,
1175                        ahc_search_action action);
1176 int         ahc_search_untagged_queues(struct ahc_softc *ahc,
1177                            ahc_io_ctx_t ctx,
1178                            int target, char channel,
1179                            int lun, uint32_t status,
1180                            ahc_search_action action);
1181 int         ahc_search_disc_list(struct ahc_softc *ahc, int target,
1182                          char channel, int lun, u_int tag,
1183                          int stop_on_first, int remove,
1184                          int save_state);
1185 int         ahc_reset_channel(struct ahc_softc *ahc, char channel,
1186                       int initiate_reset);
1187 
1188 /*************************** Utility Functions ********************************/
1189 void            ahc_compile_devinfo(struct ahc_devinfo *devinfo,
1190                         u_int our_id, u_int target,
1191                         u_int lun, char channel,
1192                         role_t role);
1193 /************************** Transfer Negotiation ******************************/
1194 const struct ahc_syncrate*  ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1195                       u_int *ppr_options, u_int maxsync);
1196 u_int           ahc_find_period(struct ahc_softc *ahc,
1197                     u_int scsirate, u_int maxsync);
1198 /*
1199  * Negotiation types.  These are used to qualify if we should renegotiate
1200  * even if our goal and current transport parameters are identical.
1201  */
1202 typedef enum {
1203     AHC_NEG_TO_GOAL,    /* Renegotiate only if goal and curr differ. */
1204     AHC_NEG_IF_NON_ASYNC,   /* Renegotiate so long as goal is non-async. */
1205     AHC_NEG_ALWAYS      /* Renegotiat even if goal is async. */
1206 } ahc_neg_type;
1207 int         ahc_update_neg_request(struct ahc_softc*,
1208                            struct ahc_devinfo*,
1209                            struct ahc_tmode_tstate*,
1210                            struct ahc_initiator_tinfo*,
1211                            ahc_neg_type);
1212 void            ahc_set_width(struct ahc_softc *ahc,
1213                       struct ahc_devinfo *devinfo,
1214                       u_int width, u_int type, int paused);
1215 void            ahc_set_syncrate(struct ahc_softc *ahc,
1216                      struct ahc_devinfo *devinfo,
1217                      const struct ahc_syncrate *syncrate,
1218                      u_int period, u_int offset,
1219                      u_int ppr_options,
1220                      u_int type, int paused);
1221 typedef enum {
1222     AHC_QUEUE_NONE,
1223     AHC_QUEUE_BASIC,
1224     AHC_QUEUE_TAGGED
1225 } ahc_queue_alg;
1226 
1227 /**************************** Target Mode *************************************/
1228 #ifdef AHC_TARGET_MODE
1229 void        ahc_send_lstate_events(struct ahc_softc *,
1230                        struct ahc_tmode_lstate *);
1231 void        ahc_handle_en_lun(struct ahc_softc *ahc,
1232                   struct cam_sim *sim, union ccb *ccb);
1233 cam_status  ahc_find_tmode_devs(struct ahc_softc *ahc,
1234                     struct cam_sim *sim, union ccb *ccb,
1235                     struct ahc_tmode_tstate **tstate,
1236                     struct ahc_tmode_lstate **lstate,
1237                     int notfound_failure);
1238 #ifndef AHC_TMODE_ENABLE
1239 #define AHC_TMODE_ENABLE 0
1240 #endif
1241 #endif
1242 /******************************* Debug ***************************************/
1243 #ifdef AHC_DEBUG
1244 extern uint32_t ahc_debug;
1245 #define AHC_SHOW_MISC       0x0001
1246 #define AHC_SHOW_SENSE      0x0002
1247 #define AHC_DUMP_SEEPROM    0x0004
1248 #define AHC_SHOW_TERMCTL    0x0008
1249 #define AHC_SHOW_MEMORY     0x0010
1250 #define AHC_SHOW_MESSAGES   0x0020
1251 #define AHC_SHOW_DV     0x0040
1252 #define AHC_SHOW_SELTO      0x0080
1253 #define AHC_SHOW_QFULL      0x0200
1254 #define AHC_SHOW_QUEUE      0x0400
1255 #define AHC_SHOW_TQIN       0x0800
1256 #define AHC_SHOW_MASKED_ERRORS  0x1000
1257 #define AHC_DEBUG_SEQUENCER 0x2000
1258 #endif
1259 void            ahc_print_devinfo(struct ahc_softc *ahc,
1260                       struct ahc_devinfo *dev);
1261 void            ahc_dump_card_state(struct ahc_softc *ahc);
1262 int         ahc_print_register(const ahc_reg_parse_entry_t *table,
1263                        u_int num_entries,
1264                        const char *name,
1265                        u_int address,
1266                        u_int value,
1267                        u_int *cur_column,
1268                        u_int wrap_point);
1269 /******************************* SEEPROM *************************************/
1270 int     ahc_acquire_seeprom(struct ahc_softc *ahc,
1271                     struct seeprom_descriptor *sd);
1272 void        ahc_release_seeprom(struct seeprom_descriptor *sd);
1273 #endif /* _AIC7XXX_H_ */
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