0001 /*
0002 * DO NOT EDIT - This file is automatically generated
0003 * from the following source files:
0004 *
0005 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#120 $
0006 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#77 $
0007 */
0008
0009 #include "aic79xx_osm.h"
0010
0011 static const ahd_reg_parse_entry_t INTSTAT_parse_table[] = {
0012 { "SPLTINT", 0x01, 0x01 },
0013 { "CMDCMPLT", 0x02, 0x02 },
0014 { "SEQINT", 0x04, 0x04 },
0015 { "SCSIINT", 0x08, 0x08 },
0016 { "PCIINT", 0x10, 0x10 },
0017 { "SWTMINT", 0x20, 0x20 },
0018 { "BRKADRINT", 0x40, 0x40 },
0019 { "HWERRINT", 0x80, 0x80 },
0020 { "INT_PEND", 0xff, 0xff }
0021 };
0022
0023 int
0024 ahd_intstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
0025 {
0026 return (ahd_print_register(INTSTAT_parse_table, 9, "INTSTAT",
0027 0x01, regvalue, cur_col, wrap));
0028 }
0029
0030 static const ahd_reg_parse_entry_t HS_MAILBOX_parse_table[] = {
0031 { "ENINT_COALESCE", 0x40, 0x40 },
0032 { "HOST_TQINPOS", 0x80, 0x80 }
0033 };
0034
0035 int
0036 ahd_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap)
0037 {
0038 return (ahd_print_register(HS_MAILBOX_parse_table, 2, "HS_MAILBOX",
0039 0x0b, regvalue, cur_col, wrap));
0040 }
0041
0042 static const ahd_reg_parse_entry_t SEQINTSTAT_parse_table[] = {
0043 { "SEQ_SPLTINT", 0x01, 0x01 },
0044 { "SEQ_PCIINT", 0x02, 0x02 },
0045 { "SEQ_SCSIINT", 0x04, 0x04 },
0046 { "SEQ_SEQINT", 0x08, 0x08 },
0047 { "SEQ_SWTMRTO", 0x10, 0x10 }
0048 };
0049
0050 int
0051 ahd_seqintstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
0052 {
0053 return (ahd_print_register(SEQINTSTAT_parse_table, 5, "SEQINTSTAT",
0054 0x0c, regvalue, cur_col, wrap));
0055 }
0056
0057 static const ahd_reg_parse_entry_t INTCTL_parse_table[] = {
0058 { "SPLTINTEN", 0x01, 0x01 },
0059 { "SEQINTEN", 0x02, 0x02 },
0060 { "SCSIINTEN", 0x04, 0x04 },
0061 { "PCIINTEN", 0x08, 0x08 },
0062 { "AUTOCLRCMDINT", 0x10, 0x10 },
0063 { "SWTIMER_START", 0x20, 0x20 },
0064 { "SWTMINTEN", 0x40, 0x40 },
0065 { "SWTMINTMASK", 0x80, 0x80 }
0066 };
0067
0068 int
0069 ahd_intctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
0070 {
0071 return (ahd_print_register(INTCTL_parse_table, 8, "INTCTL",
0072 0x18, regvalue, cur_col, wrap));
0073 }
0074
0075 static const ahd_reg_parse_entry_t DFCNTRL_parse_table[] = {
0076 { "DIRECTIONEN", 0x01, 0x01 },
0077 { "FIFOFLUSH", 0x02, 0x02 },
0078 { "FIFOFLUSHACK", 0x02, 0x02 },
0079 { "DIRECTION", 0x04, 0x04 },
0080 { "DIRECTIONACK", 0x04, 0x04 },
0081 { "HDMAEN", 0x08, 0x08 },
0082 { "HDMAENACK", 0x08, 0x08 },
0083 { "SCSIEN", 0x20, 0x20 },
0084 { "SCSIENACK", 0x20, 0x20 },
0085 { "SCSIENWRDIS", 0x40, 0x40 },
0086 { "PRELOADEN", 0x80, 0x80 }
0087 };
0088
0089 int
0090 ahd_dfcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
0091 {
0092 return (ahd_print_register(DFCNTRL_parse_table, 11, "DFCNTRL",
0093 0x19, regvalue, cur_col, wrap));
0094 }
0095
0096 static const ahd_reg_parse_entry_t DFSTATUS_parse_table[] = {
0097 { "FIFOEMP", 0x01, 0x01 },
0098 { "FIFOFULL", 0x02, 0x02 },
0099 { "DFTHRESH", 0x04, 0x04 },
0100 { "HDONE", 0x08, 0x08 },
0101 { "MREQPEND", 0x10, 0x10 },
0102 { "PKT_PRELOAD_AVAIL", 0x40, 0x40 },
0103 { "PRELOAD_AVAIL", 0x80, 0x80 }
0104 };
0105
0106 int
0107 ahd_dfstatus_print(u_int regvalue, u_int *cur_col, u_int wrap)
0108 {
0109 return (ahd_print_register(DFSTATUS_parse_table, 7, "DFSTATUS",
0110 0x1a, regvalue, cur_col, wrap));
0111 }
0112
0113 static const ahd_reg_parse_entry_t SG_CACHE_SHADOW_parse_table[] = {
0114 { "LAST_SEG_DONE", 0x01, 0x01 },
0115 { "LAST_SEG", 0x02, 0x02 },
0116 { "ODD_SEG", 0x04, 0x04 },
0117 { "SG_ADDR_MASK", 0xf8, 0xf8 }
0118 };
0119
0120 int
0121 ahd_sg_cache_shadow_print(u_int regvalue, u_int *cur_col, u_int wrap)
0122 {
0123 return (ahd_print_register(SG_CACHE_SHADOW_parse_table, 4, "SG_CACHE_SHADOW",
0124 0x1b, regvalue, cur_col, wrap));
0125 }
0126
0127 static const ahd_reg_parse_entry_t SCSISEQ0_parse_table[] = {
0128 { "SCSIRSTO", 0x01, 0x01 },
0129 { "FORCEBUSFREE", 0x10, 0x10 },
0130 { "ENARBO", 0x20, 0x20 },
0131 { "ENSELO", 0x40, 0x40 },
0132 { "TEMODEO", 0x80, 0x80 }
0133 };
0134
0135 int
0136 ahd_scsiseq0_print(u_int regvalue, u_int *cur_col, u_int wrap)
0137 {
0138 return (ahd_print_register(SCSISEQ0_parse_table, 5, "SCSISEQ0",
0139 0x3a, regvalue, cur_col, wrap));
0140 }
0141
0142 static const ahd_reg_parse_entry_t SCSISEQ1_parse_table[] = {
0143 { "ALTSTIM", 0x01, 0x01 },
0144 { "ENAUTOATNP", 0x02, 0x02 },
0145 { "MANUALP", 0x0c, 0x0c },
0146 { "ENRSELI", 0x10, 0x10 },
0147 { "ENSELI", 0x20, 0x20 },
0148 { "MANUALCTL", 0x40, 0x40 }
0149 };
0150
0151 int
0152 ahd_scsiseq1_print(u_int regvalue, u_int *cur_col, u_int wrap)
0153 {
0154 return (ahd_print_register(SCSISEQ1_parse_table, 6, "SCSISEQ1",
0155 0x3b, regvalue, cur_col, wrap));
0156 }
0157
0158 static const ahd_reg_parse_entry_t DFFSTAT_parse_table[] = {
0159 { "CURRFIFO_0", 0x00, 0x03 },
0160 { "CURRFIFO_1", 0x01, 0x03 },
0161 { "CURRFIFO_NONE", 0x03, 0x03 },
0162 { "FIFO0FREE", 0x10, 0x10 },
0163 { "FIFO1FREE", 0x20, 0x20 },
0164 { "CURRFIFO", 0x03, 0x03 }
0165 };
0166
0167 int
0168 ahd_dffstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
0169 {
0170 return (ahd_print_register(DFFSTAT_parse_table, 6, "DFFSTAT",
0171 0x3f, regvalue, cur_col, wrap));
0172 }
0173
0174 static const ahd_reg_parse_entry_t SCSISIGI_parse_table[] = {
0175 { "P_DATAOUT", 0x00, 0xe0 },
0176 { "P_DATAOUT_DT", 0x20, 0xe0 },
0177 { "P_DATAIN", 0x40, 0xe0 },
0178 { "P_DATAIN_DT", 0x60, 0xe0 },
0179 { "P_COMMAND", 0x80, 0xe0 },
0180 { "P_MESGOUT", 0xa0, 0xe0 },
0181 { "P_STATUS", 0xc0, 0xe0 },
0182 { "P_MESGIN", 0xe0, 0xe0 },
0183 { "ACKI", 0x01, 0x01 },
0184 { "REQI", 0x02, 0x02 },
0185 { "BSYI", 0x04, 0x04 },
0186 { "SELI", 0x08, 0x08 },
0187 { "ATNI", 0x10, 0x10 },
0188 { "MSGI", 0x20, 0x20 },
0189 { "IOI", 0x40, 0x40 },
0190 { "CDI", 0x80, 0x80 },
0191 { "PHASE_MASK", 0xe0, 0xe0 }
0192 };
0193
0194 int
0195 ahd_scsisigi_print(u_int regvalue, u_int *cur_col, u_int wrap)
0196 {
0197 return (ahd_print_register(SCSISIGI_parse_table, 17, "SCSISIGI",
0198 0x41, regvalue, cur_col, wrap));
0199 }
0200
0201 static const ahd_reg_parse_entry_t SCSIPHASE_parse_table[] = {
0202 { "DATA_OUT_PHASE", 0x01, 0x03 },
0203 { "DATA_IN_PHASE", 0x02, 0x03 },
0204 { "DATA_PHASE_MASK", 0x03, 0x03 },
0205 { "MSG_OUT_PHASE", 0x04, 0x04 },
0206 { "MSG_IN_PHASE", 0x08, 0x08 },
0207 { "COMMAND_PHASE", 0x10, 0x10 },
0208 { "STATUS_PHASE", 0x20, 0x20 }
0209 };
0210
0211 int
0212 ahd_scsiphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
0213 {
0214 return (ahd_print_register(SCSIPHASE_parse_table, 7, "SCSIPHASE",
0215 0x42, regvalue, cur_col, wrap));
0216 }
0217
0218 int
0219 ahd_scsibus_print(u_int regvalue, u_int *cur_col, u_int wrap)
0220 {
0221 return (ahd_print_register(NULL, 0, "SCSIBUS",
0222 0x46, regvalue, cur_col, wrap));
0223 }
0224
0225 static const ahd_reg_parse_entry_t SELID_parse_table[] = {
0226 { "ONEBIT", 0x08, 0x08 },
0227 { "SELID_MASK", 0xf0, 0xf0 }
0228 };
0229
0230 int
0231 ahd_selid_print(u_int regvalue, u_int *cur_col, u_int wrap)
0232 {
0233 return (ahd_print_register(SELID_parse_table, 2, "SELID",
0234 0x49, regvalue, cur_col, wrap));
0235 }
0236
0237 static const ahd_reg_parse_entry_t SIMODE0_parse_table[] = {
0238 { "ENARBDO", 0x01, 0x01 },
0239 { "ENSPIORDY", 0x02, 0x02 },
0240 { "ENOVERRUN", 0x04, 0x04 },
0241 { "ENIOERR", 0x08, 0x08 },
0242 { "ENSELINGO", 0x10, 0x10 },
0243 { "ENSELDI", 0x20, 0x20 },
0244 { "ENSELDO", 0x40, 0x40 }
0245 };
0246
0247 int
0248 ahd_simode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
0249 {
0250 return (ahd_print_register(SIMODE0_parse_table, 7, "SIMODE0",
0251 0x4b, regvalue, cur_col, wrap));
0252 }
0253
0254 static const ahd_reg_parse_entry_t SSTAT0_parse_table[] = {
0255 { "ARBDO", 0x01, 0x01 },
0256 { "SPIORDY", 0x02, 0x02 },
0257 { "OVERRUN", 0x04, 0x04 },
0258 { "IOERR", 0x08, 0x08 },
0259 { "SELINGO", 0x10, 0x10 },
0260 { "SELDI", 0x20, 0x20 },
0261 { "SELDO", 0x40, 0x40 },
0262 { "TARGET", 0x80, 0x80 }
0263 };
0264
0265 int
0266 ahd_sstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
0267 {
0268 return (ahd_print_register(SSTAT0_parse_table, 8, "SSTAT0",
0269 0x4b, regvalue, cur_col, wrap));
0270 }
0271
0272 static const ahd_reg_parse_entry_t SSTAT1_parse_table[] = {
0273 { "REQINIT", 0x01, 0x01 },
0274 { "STRB2FAST", 0x02, 0x02 },
0275 { "SCSIPERR", 0x04, 0x04 },
0276 { "BUSFREE", 0x08, 0x08 },
0277 { "PHASEMIS", 0x10, 0x10 },
0278 { "SCSIRSTI", 0x20, 0x20 },
0279 { "ATNTARG", 0x40, 0x40 },
0280 { "SELTO", 0x80, 0x80 }
0281 };
0282
0283 int
0284 ahd_sstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
0285 {
0286 return (ahd_print_register(SSTAT1_parse_table, 8, "SSTAT1",
0287 0x4c, regvalue, cur_col, wrap));
0288 }
0289
0290 static const ahd_reg_parse_entry_t SSTAT2_parse_table[] = {
0291 { "BUSFREE_LQO", 0x40, 0xc0 },
0292 { "BUSFREE_DFF0", 0x80, 0xc0 },
0293 { "BUSFREE_DFF1", 0xc0, 0xc0 },
0294 { "DMADONE", 0x01, 0x01 },
0295 { "SDONE", 0x02, 0x02 },
0296 { "WIDE_RES", 0x04, 0x04 },
0297 { "BSYX", 0x08, 0x08 },
0298 { "EXP_ACTIVE", 0x10, 0x10 },
0299 { "NONPACKREQ", 0x20, 0x20 },
0300 { "BUSFREETIME", 0xc0, 0xc0 }
0301 };
0302
0303 int
0304 ahd_sstat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
0305 {
0306 return (ahd_print_register(SSTAT2_parse_table, 10, "SSTAT2",
0307 0x4d, regvalue, cur_col, wrap));
0308 }
0309
0310 static const ahd_reg_parse_entry_t PERRDIAG_parse_table[] = {
0311 { "DTERR", 0x01, 0x01 },
0312 { "DGFORMERR", 0x02, 0x02 },
0313 { "CRCERR", 0x04, 0x04 },
0314 { "AIPERR", 0x08, 0x08 },
0315 { "PARITYERR", 0x10, 0x10 },
0316 { "PREVPHASE", 0x20, 0x20 },
0317 { "HIPERR", 0x40, 0x40 },
0318 { "HIZERO", 0x80, 0x80 }
0319 };
0320
0321 int
0322 ahd_perrdiag_print(u_int regvalue, u_int *cur_col, u_int wrap)
0323 {
0324 return (ahd_print_register(PERRDIAG_parse_table, 8, "PERRDIAG",
0325 0x4e, regvalue, cur_col, wrap));
0326 }
0327
0328 int
0329 ahd_soffcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
0330 {
0331 return (ahd_print_register(NULL, 0, "SOFFCNT",
0332 0x4f, regvalue, cur_col, wrap));
0333 }
0334
0335 static const ahd_reg_parse_entry_t LQISTAT0_parse_table[] = {
0336 { "LQIATNCMD", 0x01, 0x01 },
0337 { "LQIATNLQ", 0x02, 0x02 },
0338 { "LQIBADLQT", 0x04, 0x04 },
0339 { "LQICRCT2", 0x08, 0x08 },
0340 { "LQICRCT1", 0x10, 0x10 },
0341 { "LQIATNQAS", 0x20, 0x20 }
0342 };
0343
0344 int
0345 ahd_lqistat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
0346 {
0347 return (ahd_print_register(LQISTAT0_parse_table, 6, "LQISTAT0",
0348 0x50, regvalue, cur_col, wrap));
0349 }
0350
0351 static const ahd_reg_parse_entry_t LQISTAT1_parse_table[] = {
0352 { "LQIOVERI_NLQ", 0x01, 0x01 },
0353 { "LQIOVERI_LQ", 0x02, 0x02 },
0354 { "LQIBADLQI", 0x04, 0x04 },
0355 { "LQICRCI_NLQ", 0x08, 0x08 },
0356 { "LQICRCI_LQ", 0x10, 0x10 },
0357 { "LQIABORT", 0x20, 0x20 },
0358 { "LQIPHASE_NLQ", 0x40, 0x40 },
0359 { "LQIPHASE_LQ", 0x80, 0x80 }
0360 };
0361
0362 int
0363 ahd_lqistat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
0364 {
0365 return (ahd_print_register(LQISTAT1_parse_table, 8, "LQISTAT1",
0366 0x51, regvalue, cur_col, wrap));
0367 }
0368
0369 static const ahd_reg_parse_entry_t LQISTAT2_parse_table[] = {
0370 { "LQIGSAVAIL", 0x01, 0x01 },
0371 { "LQISTOPCMD", 0x02, 0x02 },
0372 { "LQISTOPLQ", 0x04, 0x04 },
0373 { "LQISTOPPKT", 0x08, 0x08 },
0374 { "LQIWAITFIFO", 0x10, 0x10 },
0375 { "LQIWORKONLQ", 0x20, 0x20 },
0376 { "LQIPHASE_OUTPKT", 0x40, 0x40 },
0377 { "PACKETIZED", 0x80, 0x80 }
0378 };
0379
0380 int
0381 ahd_lqistat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
0382 {
0383 return (ahd_print_register(LQISTAT2_parse_table, 8, "LQISTAT2",
0384 0x52, regvalue, cur_col, wrap));
0385 }
0386
0387 static const ahd_reg_parse_entry_t SSTAT3_parse_table[] = {
0388 { "OSRAMPERR", 0x01, 0x01 },
0389 { "NTRAMPERR", 0x02, 0x02 }
0390 };
0391
0392 int
0393 ahd_sstat3_print(u_int regvalue, u_int *cur_col, u_int wrap)
0394 {
0395 return (ahd_print_register(SSTAT3_parse_table, 2, "SSTAT3",
0396 0x53, regvalue, cur_col, wrap));
0397 }
0398
0399 static const ahd_reg_parse_entry_t LQOSTAT0_parse_table[] = {
0400 { "LQOTCRC", 0x01, 0x01 },
0401 { "LQOATNPKT", 0x02, 0x02 },
0402 { "LQOATNLQ", 0x04, 0x04 },
0403 { "LQOSTOPT2", 0x08, 0x08 },
0404 { "LQOTARGSCBPERR", 0x10, 0x10 }
0405 };
0406
0407 int
0408 ahd_lqostat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
0409 {
0410 return (ahd_print_register(LQOSTAT0_parse_table, 5, "LQOSTAT0",
0411 0x54, regvalue, cur_col, wrap));
0412 }
0413
0414 static const ahd_reg_parse_entry_t LQOSTAT1_parse_table[] = {
0415 { "LQOPHACHGINPKT", 0x01, 0x01 },
0416 { "LQOBUSFREE", 0x02, 0x02 },
0417 { "LQOBADQAS", 0x04, 0x04 },
0418 { "LQOSTOPI2", 0x08, 0x08 },
0419 { "LQOINITSCBPERR", 0x10, 0x10 }
0420 };
0421
0422 int
0423 ahd_lqostat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
0424 {
0425 return (ahd_print_register(LQOSTAT1_parse_table, 5, "LQOSTAT1",
0426 0x55, regvalue, cur_col, wrap));
0427 }
0428
0429 static const ahd_reg_parse_entry_t LQOSTAT2_parse_table[] = {
0430 { "LQOSTOP0", 0x01, 0x01 },
0431 { "LQOPHACHGOUTPKT", 0x02, 0x02 },
0432 { "LQOWAITFIFO", 0x10, 0x10 },
0433 { "LQOPKT", 0xe0, 0xe0 }
0434 };
0435
0436 int
0437 ahd_lqostat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
0438 {
0439 return (ahd_print_register(LQOSTAT2_parse_table, 4, "LQOSTAT2",
0440 0x56, regvalue, cur_col, wrap));
0441 }
0442
0443 static const ahd_reg_parse_entry_t SIMODE1_parse_table[] = {
0444 { "ENREQINIT", 0x01, 0x01 },
0445 { "ENSTRB2FAST", 0x02, 0x02 },
0446 { "ENSCSIPERR", 0x04, 0x04 },
0447 { "ENBUSFREE", 0x08, 0x08 },
0448 { "ENPHASEMIS", 0x10, 0x10 },
0449 { "ENSCSIRST", 0x20, 0x20 },
0450 { "ENATNTARG", 0x40, 0x40 },
0451 { "ENSELTIMO", 0x80, 0x80 }
0452 };
0453
0454 int
0455 ahd_simode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
0456 {
0457 return (ahd_print_register(SIMODE1_parse_table, 8, "SIMODE1",
0458 0x57, regvalue, cur_col, wrap));
0459 }
0460
0461 static const ahd_reg_parse_entry_t DFFSXFRCTL_parse_table[] = {
0462 { "RSTCHN", 0x01, 0x01 },
0463 { "CLRCHN", 0x02, 0x02 },
0464 { "CLRSHCNT", 0x04, 0x04 },
0465 { "DFFBITBUCKET", 0x08, 0x08 }
0466 };
0467
0468 int
0469 ahd_dffsxfrctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
0470 {
0471 return (ahd_print_register(DFFSXFRCTL_parse_table, 4, "DFFSXFRCTL",
0472 0x5a, regvalue, cur_col, wrap));
0473 }
0474
0475 static const ahd_reg_parse_entry_t SEQINTSRC_parse_table[] = {
0476 { "CFG4TCMD", 0x01, 0x01 },
0477 { "CFG4ICMD", 0x02, 0x02 },
0478 { "CFG4TSTAT", 0x04, 0x04 },
0479 { "CFG4ISTAT", 0x08, 0x08 },
0480 { "CFG4DATA", 0x10, 0x10 },
0481 { "SAVEPTRS", 0x20, 0x20 },
0482 { "CTXTDONE", 0x40, 0x40 }
0483 };
0484
0485 int
0486 ahd_seqintsrc_print(u_int regvalue, u_int *cur_col, u_int wrap)
0487 {
0488 return (ahd_print_register(SEQINTSRC_parse_table, 7, "SEQINTSRC",
0489 0x5b, regvalue, cur_col, wrap));
0490 }
0491
0492 static const ahd_reg_parse_entry_t SEQIMODE_parse_table[] = {
0493 { "ENCFG4TCMD", 0x01, 0x01 },
0494 { "ENCFG4ICMD", 0x02, 0x02 },
0495 { "ENCFG4TSTAT", 0x04, 0x04 },
0496 { "ENCFG4ISTAT", 0x08, 0x08 },
0497 { "ENCFG4DATA", 0x10, 0x10 },
0498 { "ENSAVEPTRS", 0x20, 0x20 },
0499 { "ENCTXTDONE", 0x40, 0x40 }
0500 };
0501
0502 int
0503 ahd_seqimode_print(u_int regvalue, u_int *cur_col, u_int wrap)
0504 {
0505 return (ahd_print_register(SEQIMODE_parse_table, 7, "SEQIMODE",
0506 0x5c, regvalue, cur_col, wrap));
0507 }
0508
0509 static const ahd_reg_parse_entry_t MDFFSTAT_parse_table[] = {
0510 { "FIFOFREE", 0x01, 0x01 },
0511 { "DATAINFIFO", 0x02, 0x02 },
0512 { "DLZERO", 0x04, 0x04 },
0513 { "SHVALID", 0x08, 0x08 },
0514 { "LASTSDONE", 0x10, 0x10 },
0515 { "SHCNTMINUS1", 0x20, 0x20 },
0516 { "SHCNTNEGATIVE", 0x40, 0x40 }
0517 };
0518
0519 int
0520 ahd_mdffstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
0521 {
0522 return (ahd_print_register(MDFFSTAT_parse_table, 7, "MDFFSTAT",
0523 0x5d, regvalue, cur_col, wrap));
0524 }
0525
0526 int
0527 ahd_seloid_print(u_int regvalue, u_int *cur_col, u_int wrap)
0528 {
0529 return (ahd_print_register(NULL, 0, "SELOID",
0530 0x6b, regvalue, cur_col, wrap));
0531 }
0532
0533 static const ahd_reg_parse_entry_t SG_STATE_parse_table[] = {
0534 { "SEGS_AVAIL", 0x01, 0x01 },
0535 { "LOADING_NEEDED", 0x02, 0x02 },
0536 { "FETCH_INPROG", 0x04, 0x04 }
0537 };
0538
0539 int
0540 ahd_sg_state_print(u_int regvalue, u_int *cur_col, u_int wrap)
0541 {
0542 return (ahd_print_register(SG_STATE_parse_table, 3, "SG_STATE",
0543 0xa6, regvalue, cur_col, wrap));
0544 }
0545
0546 static const ahd_reg_parse_entry_t CCSCBCTL_parse_table[] = {
0547 { "CCSCBRESET", 0x01, 0x01 },
0548 { "CCSCBDIR", 0x04, 0x04 },
0549 { "CCSCBEN", 0x08, 0x08 },
0550 { "CCARREN", 0x10, 0x10 },
0551 { "ARRDONE", 0x40, 0x40 },
0552 { "CCSCBDONE", 0x80, 0x80 }
0553 };
0554
0555 int
0556 ahd_ccscbctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
0557 {
0558 return (ahd_print_register(CCSCBCTL_parse_table, 6, "CCSCBCTL",
0559 0xad, regvalue, cur_col, wrap));
0560 }
0561
0562 static const ahd_reg_parse_entry_t CCSGCTL_parse_table[] = {
0563 { "CCSGRESET", 0x01, 0x01 },
0564 { "SG_FETCH_REQ", 0x02, 0x02 },
0565 { "CCSGENACK", 0x08, 0x08 },
0566 { "SG_CACHE_AVAIL", 0x10, 0x10 },
0567 { "CCSGDONE", 0x80, 0x80 },
0568 { "CCSGEN", 0x0c, 0x0c }
0569 };
0570
0571 int
0572 ahd_ccsgctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
0573 {
0574 return (ahd_print_register(CCSGCTL_parse_table, 6, "CCSGCTL",
0575 0xad, regvalue, cur_col, wrap));
0576 }
0577
0578 static const ahd_reg_parse_entry_t SEQCTL0_parse_table[] = {
0579 { "LOADRAM", 0x01, 0x01 },
0580 { "SEQRESET", 0x02, 0x02 },
0581 { "STEP", 0x04, 0x04 },
0582 { "BRKADRINTEN", 0x08, 0x08 },
0583 { "FASTMODE", 0x10, 0x10 },
0584 { "FAILDIS", 0x20, 0x20 },
0585 { "PAUSEDIS", 0x40, 0x40 },
0586 { "PERRORDIS", 0x80, 0x80 }
0587 };
0588
0589 int
0590 ahd_seqctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
0591 {
0592 return (ahd_print_register(SEQCTL0_parse_table, 8, "SEQCTL0",
0593 0xd6, regvalue, cur_col, wrap));
0594 }
0595
0596 static const ahd_reg_parse_entry_t SEQINTCTL_parse_table[] = {
0597 { "IRET", 0x01, 0x01 },
0598 { "INTMASK1", 0x02, 0x02 },
0599 { "INTMASK2", 0x04, 0x04 },
0600 { "SCS_SEQ_INT1M0", 0x08, 0x08 },
0601 { "SCS_SEQ_INT1M1", 0x10, 0x10 },
0602 { "INT1_CONTEXT", 0x20, 0x20 },
0603 { "INTVEC1DSL", 0x80, 0x80 }
0604 };
0605
0606 int
0607 ahd_seqintctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
0608 {
0609 return (ahd_print_register(SEQINTCTL_parse_table, 7, "SEQINTCTL",
0610 0xd9, regvalue, cur_col, wrap));
0611 }
0612
0613 int
0614 ahd_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
0615 {
0616 return (ahd_print_register(NULL, 0, "SRAM_BASE",
0617 0x100, regvalue, cur_col, wrap));
0618 }
0619
0620 int
0621 ahd_qfreeze_count_print(u_int regvalue, u_int *cur_col, u_int wrap)
0622 {
0623 return (ahd_print_register(NULL, 0, "QFREEZE_COUNT",
0624 0x132, regvalue, cur_col, wrap));
0625 }
0626
0627 int
0628 ahd_kernel_qfreeze_count_print(u_int regvalue, u_int *cur_col, u_int wrap)
0629 {
0630 return (ahd_print_register(NULL, 0, "KERNEL_QFREEZE_COUNT",
0631 0x134, regvalue, cur_col, wrap));
0632 }
0633
0634 int
0635 ahd_saved_mode_print(u_int regvalue, u_int *cur_col, u_int wrap)
0636 {
0637 return (ahd_print_register(NULL, 0, "SAVED_MODE",
0638 0x136, regvalue, cur_col, wrap));
0639 }
0640
0641 static const ahd_reg_parse_entry_t SEQ_FLAGS_parse_table[] = {
0642 { "NO_DISCONNECT", 0x01, 0x01 },
0643 { "SPHASE_PENDING", 0x02, 0x02 },
0644 { "DPHASE_PENDING", 0x04, 0x04 },
0645 { "CMDPHASE_PENDING", 0x08, 0x08 },
0646 { "TARG_CMD_PENDING", 0x10, 0x10 },
0647 { "DPHASE", 0x20, 0x20 },
0648 { "NO_CDB_SENT", 0x40, 0x40 },
0649 { "TARGET_CMD_IS_TAGGED",0x40, 0x40 },
0650 { "NOT_IDENTIFIED", 0x80, 0x80 }
0651 };
0652
0653 int
0654 ahd_seq_flags_print(u_int regvalue, u_int *cur_col, u_int wrap)
0655 {
0656 return (ahd_print_register(SEQ_FLAGS_parse_table, 9, "SEQ_FLAGS",
0657 0x139, regvalue, cur_col, wrap));
0658 }
0659
0660 static const ahd_reg_parse_entry_t LASTPHASE_parse_table[] = {
0661 { "P_DATAOUT", 0x00, 0xe0 },
0662 { "P_DATAOUT_DT", 0x20, 0xe0 },
0663 { "P_DATAIN", 0x40, 0xe0 },
0664 { "P_DATAIN_DT", 0x60, 0xe0 },
0665 { "P_COMMAND", 0x80, 0xe0 },
0666 { "P_MESGOUT", 0xa0, 0xe0 },
0667 { "P_STATUS", 0xc0, 0xe0 },
0668 { "P_MESGIN", 0xe0, 0xe0 },
0669 { "P_BUSFREE", 0x01, 0x01 },
0670 { "MSGI", 0x20, 0x20 },
0671 { "IOI", 0x40, 0x40 },
0672 { "CDI", 0x80, 0x80 },
0673 { "PHASE_MASK", 0xe0, 0xe0 }
0674 };
0675
0676 int
0677 ahd_lastphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
0678 {
0679 return (ahd_print_register(LASTPHASE_parse_table, 13, "LASTPHASE",
0680 0x13c, regvalue, cur_col, wrap));
0681 }
0682
0683 static const ahd_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = {
0684 { "PENDING_MK_MESSAGE", 0x01, 0x01 },
0685 { "TARGET_MSG_PENDING", 0x02, 0x02 },
0686 { "SELECTOUT_QFROZEN", 0x04, 0x04 }
0687 };
0688
0689 int
0690 ahd_seq_flags2_print(u_int regvalue, u_int *cur_col, u_int wrap)
0691 {
0692 return (ahd_print_register(SEQ_FLAGS2_parse_table, 3, "SEQ_FLAGS2",
0693 0x14d, regvalue, cur_col, wrap));
0694 }
0695
0696 int
0697 ahd_mk_message_scb_print(u_int regvalue, u_int *cur_col, u_int wrap)
0698 {
0699 return (ahd_print_register(NULL, 0, "MK_MESSAGE_SCB",
0700 0x160, regvalue, cur_col, wrap));
0701 }
0702
0703 int
0704 ahd_mk_message_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
0705 {
0706 return (ahd_print_register(NULL, 0, "MK_MESSAGE_SCSIID",
0707 0x162, regvalue, cur_col, wrap));
0708 }
0709
0710 int
0711 ahd_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
0712 {
0713 return (ahd_print_register(NULL, 0, "SCB_BASE",
0714 0x180, regvalue, cur_col, wrap));
0715 }
0716
0717 static const ahd_reg_parse_entry_t SCB_CONTROL_parse_table[] = {
0718 { "SCB_TAG_TYPE", 0x03, 0x03 },
0719 { "DISCONNECTED", 0x04, 0x04 },
0720 { "STATUS_RCVD", 0x08, 0x08 },
0721 { "MK_MESSAGE", 0x10, 0x10 },
0722 { "TAG_ENB", 0x20, 0x20 },
0723 { "DISCENB", 0x40, 0x40 },
0724 { "TARGET_SCB", 0x80, 0x80 }
0725 };
0726
0727 int
0728 ahd_scb_control_print(u_int regvalue, u_int *cur_col, u_int wrap)
0729 {
0730 return (ahd_print_register(SCB_CONTROL_parse_table, 7, "SCB_CONTROL",
0731 0x192, regvalue, cur_col, wrap));
0732 }
0733
0734 static const ahd_reg_parse_entry_t SCB_SCSIID_parse_table[] = {
0735 { "OID", 0x0f, 0x0f },
0736 { "TID", 0xf0, 0xf0 }
0737 };
0738
0739 int
0740 ahd_scb_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
0741 {
0742 return (ahd_print_register(SCB_SCSIID_parse_table, 2, "SCB_SCSIID",
0743 0x193, regvalue, cur_col, wrap));
0744 }
0745
