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0001 /*
0002  * Core definitions and data structures shareable across OS platforms.
0003  *
0004  * Copyright (c) 1994-2002 Justin T. Gibbs.
0005  * Copyright (c) 2000-2002 Adaptec Inc.
0006  * All rights reserved.
0007  *
0008  * Redistribution and use in source and binary forms, with or without
0009  * modification, are permitted provided that the following conditions
0010  * are met:
0011  * 1. Redistributions of source code must retain the above copyright
0012  *    notice, this list of conditions, and the following disclaimer,
0013  *    without modification.
0014  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
0015  *    substantially similar to the "NO WARRANTY" disclaimer below
0016  *    ("Disclaimer") and any redistribution must be conditioned upon
0017  *    including a substantially similar Disclaimer requirement for further
0018  *    binary redistribution.
0019  * 3. Neither the names of the above-listed copyright holders nor the names
0020  *    of any contributors may be used to endorse or promote products derived
0021  *    from this software without specific prior written permission.
0022  *
0023  * Alternatively, this software may be distributed under the terms of the
0024  * GNU General Public License ("GPL") version 2 as published by the Free
0025  * Software Foundation.
0026  *
0027  * NO WARRANTY
0028  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0029  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0030  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
0031  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0032  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0033  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
0034  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
0035  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
0036  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
0037  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0038  * POSSIBILITY OF SUCH DAMAGES.
0039  *
0040  * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#109 $
0041  *
0042  * $FreeBSD$
0043  */
0044 
0045 #ifndef _AIC79XX_H_
0046 #define _AIC79XX_H_
0047 
0048 /* Register Definitions */
0049 #include "aic79xx_reg.h"
0050 
0051 /************************* Forward Declarations *******************************/
0052 struct ahd_platform_data;
0053 struct scb_platform_data;
0054 
0055 /****************************** Useful Macros *********************************/
0056 #ifndef TRUE
0057 #define TRUE 1
0058 #endif
0059 #ifndef FALSE
0060 #define FALSE 0
0061 #endif
0062 
0063 #define ALL_CHANNELS '\0'
0064 #define ALL_TARGETS_MASK 0xFFFF
0065 #define INITIATOR_WILDCARD  (~0)
0066 #define SCB_LIST_NULL       0xFF00
0067 #define SCB_LIST_NULL_LE    (ahd_htole16(SCB_LIST_NULL))
0068 #define QOUTFIFO_ENTRY_VALID 0x80
0069 #define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL)
0070 
0071 #define SCSIID_TARGET(ahd, scsiid)  \
0072     (((scsiid) & TID) >> TID_SHIFT)
0073 #define SCSIID_OUR_ID(scsiid)       \
0074     ((scsiid) & OID)
0075 #define SCSIID_CHANNEL(ahd, scsiid) ('A')
0076 #define SCB_IS_SCSIBUS_B(ahd, scb) (0)
0077 #define SCB_GET_OUR_ID(scb) \
0078     SCSIID_OUR_ID((scb)->hscb->scsiid)
0079 #define SCB_GET_TARGET(ahd, scb) \
0080     SCSIID_TARGET((ahd), (scb)->hscb->scsiid)
0081 #define SCB_GET_CHANNEL(ahd, scb) \
0082     SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid)
0083 #define SCB_GET_LUN(scb) \
0084     ((scb)->hscb->lun)
0085 #define SCB_GET_TARGET_OFFSET(ahd, scb) \
0086     SCB_GET_TARGET(ahd, scb)
0087 #define SCB_GET_TARGET_MASK(ahd, scb) \
0088     (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb)))
0089 #ifdef AHD_DEBUG
0090 #define SCB_IS_SILENT(scb)                  \
0091     ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0      \
0092       && (((scb)->flags & SCB_SILENT) != 0))
0093 #else
0094 #define SCB_IS_SILENT(scb)                  \
0095     (((scb)->flags & SCB_SILENT) != 0)
0096 #endif
0097 /*
0098  * TCLs have the following format: TTTTLLLLLLLL
0099  */
0100 #define TCL_TARGET_OFFSET(tcl) \
0101     ((((tcl) >> 4) & TID) >> 4)
0102 #define TCL_LUN(tcl) \
0103     (tcl & (AHD_NUM_LUNS - 1))
0104 #define BUILD_TCL(scsiid, lun) \
0105     ((lun) | (((scsiid) & TID) << 4))
0106 #define BUILD_TCL_RAW(target, channel, lun) \
0107     ((lun) | ((target) << 8))
0108 
0109 #define SCB_GET_TAG(scb) \
0110     ahd_le16toh(scb->hscb->tag)
0111 
0112 #ifndef AHD_TARGET_MODE
0113 #undef  AHD_TMODE_ENABLE
0114 #define AHD_TMODE_ENABLE 0
0115 #endif
0116 
0117 #define AHD_BUILD_COL_IDX(target, lun)              \
0118     ((((u8)lun) << 4) | target)
0119 
0120 #define AHD_GET_SCB_COL_IDX(ahd, scb)               \
0121     ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb))
0122 
0123 #define AHD_SET_SCB_COL_IDX(scb, col_idx)               \
0124 do {                                    \
0125     (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID;       \
0126     (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1);  \
0127 } while (0)
0128 
0129 #define AHD_COPY_SCB_COL_IDX(dst, src)              \
0130 do {                                \
0131     dst->hscb->scsiid = src->hscb->scsiid;          \
0132     dst->hscb->lun = src->hscb->lun;            \
0133 } while (0)
0134 
0135 #define AHD_NEVER_COL_IDX 0xFFFF
0136 
0137 /**************************** Driver Constants ********************************/
0138 /*
0139  * The maximum number of supported targets.
0140  */
0141 #define AHD_NUM_TARGETS 16
0142 
0143 /*
0144  * The maximum number of supported luns.
0145  * The identify message only supports 64 luns in non-packetized transfers.
0146  * You can have 2^64 luns when information unit transfers are enabled,
0147  * but until we see a need to support that many, we support 256.
0148  */
0149 #define AHD_NUM_LUNS_NONPKT 64
0150 #define AHD_NUM_LUNS 256
0151 
0152 /*
0153  * The maximum transfer per S/G segment.
0154  */
0155 #define AHD_MAXTRANSFER_SIZE     0x00ffffff /* limited by 24bit counter */
0156 
0157 /*
0158  * The maximum amount of SCB storage in hardware on a controller.
0159  * This value represents an upper bound.  Due to software design,
0160  * we may not be able to use this number.
0161  */
0162 #define AHD_SCB_MAX 512
0163 
0164 /*
0165  * The maximum number of concurrent transactions supported per driver instance.
0166  * Sequencer Control Blocks (SCBs) store per-transaction information.
0167  */
0168 #define AHD_MAX_QUEUE   AHD_SCB_MAX
0169 
0170 /*
0171  * Define the size of our QIN and QOUT FIFOs.  They must be a power of 2
0172  * in size and accommodate as many transactions as can be queued concurrently.
0173  */
0174 #define AHD_QIN_SIZE    AHD_MAX_QUEUE
0175 #define AHD_QOUT_SIZE   AHD_MAX_QUEUE
0176 
0177 #define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1))
0178 /*
0179  * The maximum amount of SCB storage we allocate in host memory.
0180  */
0181 #define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE
0182 
0183 /*
0184  * Ring Buffer of incoming target commands.
0185  * We allocate 256 to simplify the logic in the sequencer
0186  * by using the natural wrap point of an 8bit counter.
0187  */
0188 #define AHD_TMODE_CMDS  256
0189 
0190 /* Reset line assertion time in us */
0191 #define AHD_BUSRESET_DELAY  25
0192 
0193 /******************* Chip Characteristics/Operating Settings  *****************/
0194 /*
0195  * Chip Type
0196  * The chip order is from least sophisticated to most sophisticated.
0197  */
0198 typedef enum {
0199     AHD_NONE    = 0x0000,
0200     AHD_CHIPID_MASK = 0x00FF,
0201     AHD_AIC7901 = 0x0001,
0202     AHD_AIC7902 = 0x0002,
0203     AHD_AIC7901A    = 0x0003,
0204     AHD_PCI     = 0x0100,   /* Bus type PCI */
0205     AHD_PCIX    = 0x0200,   /* Bus type PCIX */
0206     AHD_BUS_MASK    = 0x0F00
0207 } ahd_chip;
0208 
0209 /*
0210  * Features available in each chip type.
0211  */
0212 typedef enum {
0213     AHD_FENONE      = 0x00000,
0214     AHD_WIDE        = 0x00001,/* Wide Channel */
0215     AHD_AIC79XXB_SLOWCRC    = 0x00002,/* SLOWCRC bit should be set */
0216     AHD_MULTI_FUNC      = 0x00100,/* Multi-Function/Channel Device */
0217     AHD_TARGETMODE      = 0x01000,/* Has tested target mode support */
0218     AHD_MULTIROLE       = 0x02000,/* Space for two roles at a time */
0219     AHD_RTI         = 0x04000,/* Retained Training Support */
0220     AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */
0221     AHD_NEW_DFCNTRL_OPTS    = 0x10000,/* SCSIENWRDIS bit */
0222     AHD_FAST_CDB_DELIVERY   = 0x20000,/* CDB acks released to Output Sync */
0223     AHD_REMOVABLE       = 0x00000,/* Hot-Swap supported - None so far*/
0224     AHD_AIC7901_FE      = AHD_FENONE,
0225     AHD_AIC7901A_FE     = AHD_FENONE,
0226     AHD_AIC7902_FE      = AHD_MULTI_FUNC
0227 } ahd_feature;
0228 
0229 /*
0230  * Bugs in the silicon that we work around in software.
0231  */
0232 typedef enum {
0233     AHD_BUGNONE     = 0x0000,
0234     /*
0235      * Rev A hardware fails to update LAST/CURR/NEXTSCB
0236      * correctly in certain packetized selection cases.
0237      */
0238     AHD_SENT_SCB_UPDATE_BUG = 0x0001,
0239     /* The wrong SCB is accessed to check the abort pending bit. */
0240     AHD_ABORT_LQI_BUG   = 0x0002,
0241     /* Packetized bitbucket crosses packet boundaries. */
0242     AHD_PKT_BITBUCKET_BUG   = 0x0004,
0243     /* The selection timer runs twice as long as its setting. */
0244     AHD_LONG_SETIMO_BUG = 0x0008,
0245     /* The Non-LQ CRC error status is delayed until phase change. */
0246     AHD_NLQICRC_DELAYED_BUG = 0x0010,
0247     /* The chip must be reset for all outgoing bus resets.  */
0248     AHD_SCSIRST_BUG     = 0x0020,
0249     /* Some PCIX fields must be saved and restored across chip reset. */
0250     AHD_PCIX_CHIPRST_BUG    = 0x0040,
0251     /* MMAPIO is not functional in PCI-X mode.  */
0252     AHD_PCIX_MMAPIO_BUG = 0x0080,
0253     /* Reads to SCBRAM fail to reset the discard timer. */
0254     AHD_PCIX_SCBRAM_RD_BUG  = 0x0100,
0255     /* Bug workarounds that can be disabled on non-PCIX busses. */
0256     AHD_PCIX_BUG_MASK   = AHD_PCIX_CHIPRST_BUG
0257                 | AHD_PCIX_MMAPIO_BUG
0258                 | AHD_PCIX_SCBRAM_RD_BUG,
0259     /*
0260      * LQOSTOP0 status set even for forced selections with ATN
0261      * to perform non-packetized message delivery.
0262      */
0263     AHD_LQO_ATNO_BUG    = 0x0200,
0264     /* FIFO auto-flush does not always trigger.  */
0265     AHD_AUTOFLUSH_BUG   = 0x0400,
0266     /* The CLRLQO registers are not self-clearing. */
0267     AHD_CLRLQO_AUTOCLR_BUG  = 0x0800,
0268     /* The PACKETIZED status bit refers to the previous connection. */
0269     AHD_PKTIZED_STATUS_BUG  = 0x1000,
0270     /* "Short Luns" are not placed into outgoing LQ packets correctly. */
0271     AHD_PKT_LUN_BUG     = 0x2000,
0272     /*
0273      * Only the FIFO allocated to the non-packetized connection may
0274      * be in use during a non-packetzied connection.
0275      */
0276     AHD_NONPACKFIFO_BUG = 0x4000,
0277     /*
0278      * Writing to a DFF SCBPTR register may fail if concurent with
0279      * a hardware write to the other DFF SCBPTR register.  This is
0280      * not currently a concern in our sequencer since all chips with
0281      * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern
0282      * occur in non-packetized connections.
0283      */
0284     AHD_MDFF_WSCBPTR_BUG    = 0x8000,
0285     /* SGHADDR updates are slow. */
0286     AHD_REG_SLOW_SETTLE_BUG = 0x10000,
0287     /*
0288      * Changing the MODE_PTR coincident with an interrupt that
0289      * switches to a different mode will cause the interrupt to
0290      * be in the mode written outside of interrupt context.
0291      */
0292     AHD_SET_MODE_BUG    = 0x20000,
0293     /* Non-packetized busfree revision does not work. */
0294     AHD_BUSFREEREV_BUG  = 0x40000,
0295     /*
0296      * Paced transfers are indicated with a non-standard PPR
0297      * option bit in the neg table, 160MHz is indicated by
0298      * sync factor 0x7, and the offset if off by a factor of 2.
0299      */
0300     AHD_PACED_NEGTABLE_BUG  = 0x80000,
0301     /* LQOOVERRUN false positives. */
0302     AHD_LQOOVERRUN_BUG  = 0x100000,
0303     /*
0304      * Controller write to INTSTAT will lose to a host
0305      * write to CLRINT.
0306      */
0307     AHD_INTCOLLISION_BUG    = 0x200000,
0308     /*
0309      * The GEM318 violates the SCSI spec by not waiting
0310      * the mandated bus settle delay between phase changes
0311      * in some situations.  Some aic79xx chip revs. are more
0312      * strict in this regard and will treat REQ assertions
0313      * that fall within the bus settle delay window as
0314      * glitches.  This flag tells the firmware to tolerate
0315      * early REQ assertions.
0316      */
0317     AHD_EARLY_REQ_BUG   = 0x400000,
0318     /*
0319      * The LED does not stay on long enough in packetized modes.
0320      */
0321     AHD_FAINT_LED_BUG   = 0x800000
0322 } ahd_bug;
0323 
0324 /*
0325  * Configuration specific settings.
0326  * The driver determines these settings by probing the
0327  * chip/controller's configuration.
0328  */
0329 typedef enum {
0330     AHD_FNONE         = 0x00000,
0331     AHD_BOOT_CHANNEL      = 0x00001,/* We were set as the boot channel. */
0332     AHD_USEDEFAULTS       = 0x00004,/*
0333                      * For cards without an seeprom
0334                      * or a BIOS to initialize the chip's
0335                      * SRAM, we use the default target
0336                      * settings.
0337                      */
0338     AHD_SEQUENCER_DEBUG   = 0x00008,
0339     AHD_RESET_BUS_A       = 0x00010,
0340     AHD_EXTENDED_TRANS_A  = 0x00020,
0341     AHD_TERM_ENB_A        = 0x00040,
0342     AHD_SPCHK_ENB_A       = 0x00080,
0343     AHD_STPWLEVEL_A       = 0x00100,
0344     AHD_INITIATORROLE     = 0x00200,/*
0345                      * Allow initiator operations on
0346                      * this controller.
0347                      */
0348     AHD_TARGETROLE        = 0x00400,/*
0349                      * Allow target operations on this
0350                      * controller.
0351                      */
0352     AHD_RESOURCE_SHORTAGE = 0x00800,
0353     AHD_TQINFIFO_BLOCKED  = 0x01000,/* Blocked waiting for ATIOs */
0354     AHD_INT50_SPEEDFLEX   = 0x02000,/*
0355                      * Internal 50pin connector
0356                      * sits behind an aic3860
0357                      */
0358     AHD_BIOS_ENABLED      = 0x04000,
0359     AHD_ALL_INTERRUPTS    = 0x08000,
0360     AHD_39BIT_ADDRESSING  = 0x10000,/* Use 39 bit addressing scheme. */
0361     AHD_64BIT_ADDRESSING  = 0x20000,/* Use 64 bit addressing scheme. */
0362     AHD_CURRENT_SENSING   = 0x40000,
0363     AHD_SCB_CONFIG_USED   = 0x80000,/* No SEEPROM but SCB had info. */
0364     AHD_HP_BOARD          = 0x100000,
0365     AHD_BUS_RESET_ACTIVE  = 0x200000,
0366     AHD_UPDATE_PEND_CMDS  = 0x400000,
0367     AHD_RUNNING_QOUTFIFO  = 0x800000,
0368     AHD_HAD_FIRST_SEL     = 0x1000000
0369 } ahd_flag;
0370 
0371 /************************* Hardware  SCB Definition ***************************/
0372 
0373 /*
0374  * The driver keeps up to MAX_SCB scb structures per card in memory.  The SCB
0375  * consists of a "hardware SCB" mirroring the fields available on the card
0376  * and additional information the kernel stores for each transaction.
0377  *
0378  * To minimize space utilization, a portion of the hardware scb stores
0379  * different data during different portions of a SCSI transaction.
0380  * As initialized by the host driver for the initiator role, this area
0381  * contains the SCSI cdb (or a pointer to the  cdb) to be executed.  After
0382  * the cdb has been presented to the target, this area serves to store
0383  * residual transfer information and the SCSI status byte.
0384  * For the target role, the contents of this area do not change, but
0385  * still serve a different purpose than for the initiator role.  See
0386  * struct target_data for details.
0387  */
0388 
0389 /*
0390  * Status information embedded in the shared poriton of
0391  * an SCB after passing the cdb to the target.  The kernel
0392  * driver will only read this data for transactions that
0393  * complete abnormally.
0394  */
0395 struct initiator_status {
0396     uint32_t residual_datacnt;  /* Residual in the current S/G seg */
0397     uint32_t residual_sgptr;    /* The next S/G for this transfer */
0398     uint8_t  scsi_status;       /* Standard SCSI status byte */
0399 };
0400 
0401 struct target_status {
0402     uint32_t residual_datacnt;  /* Residual in the current S/G seg */
0403     uint32_t residual_sgptr;    /* The next S/G for this transfer */
0404     uint8_t  scsi_status;       /* SCSI status to give to initiator */
0405     uint8_t  target_phases;     /* Bitmap of phases to execute */
0406     uint8_t  data_phase;        /* Data-In or Data-Out */
0407     uint8_t  initiator_tag;     /* Initiator's transaction tag */
0408 };
0409 
0410 /*
0411  * Initiator mode SCB shared data area.
0412  * If the embedded CDB is 12 bytes or less, we embed
0413  * the sense buffer address in the SCB.  This allows
0414  * us to retrieve sense information without interrupting
0415  * the host in packetized mode.
0416  */
0417 typedef uint32_t sense_addr_t;
0418 #define MAX_CDB_LEN 16
0419 #define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t))
0420 union initiator_data {
0421     struct {
0422         uint64_t cdbptr;
0423         uint8_t  cdblen;
0424     } cdb_from_host;
0425     uint8_t  cdb[MAX_CDB_LEN];
0426     struct {
0427         uint8_t  cdb[MAX_CDB_LEN_WITH_SENSE_ADDR];
0428         sense_addr_t sense_addr;
0429     } cdb_plus_saddr;
0430 };
0431 
0432 /*
0433  * Target mode version of the shared data SCB segment.
0434  */
0435 struct target_data {
0436     uint32_t spare[2];
0437     uint8_t  scsi_status;       /* SCSI status to give to initiator */
0438     uint8_t  target_phases;     /* Bitmap of phases to execute */
0439     uint8_t  data_phase;        /* Data-In or Data-Out */
0440     uint8_t  initiator_tag;     /* Initiator's transaction tag */
0441 };
0442 
0443 struct hardware_scb {
0444 /*0*/   union {
0445         union   initiator_data idata;
0446         struct  target_data tdata;
0447         struct  initiator_status istatus;
0448         struct  target_status tstatus;
0449     } shared_data;
0450 /*
0451  * A word about residuals.
0452  * The scb is presented to the sequencer with the dataptr and datacnt
0453  * fields initialized to the contents of the first S/G element to
0454  * transfer.  The sgptr field is initialized to the bus address for
0455  * the S/G element that follows the first in the in core S/G array
0456  * or'ed with the SG_FULL_RESID flag.  Sgptr may point to an invalid
0457  * S/G entry for this transfer (single S/G element transfer with the
0458  * first elements address and length preloaded in the dataptr/datacnt
0459  * fields).  If no transfer is to occur, sgptr is set to SG_LIST_NULL.
0460  * The SG_FULL_RESID flag ensures that the residual will be correctly
0461  * noted even if no data transfers occur.  Once the data phase is entered,
0462  * the residual sgptr and datacnt are loaded from the sgptr and the
0463  * datacnt fields.  After each S/G element's dataptr and length are
0464  * loaded into the hardware, the residual sgptr is advanced.  After
0465  * each S/G element is expired, its datacnt field is checked to see
0466  * if the LAST_SEG flag is set.  If so, SG_LIST_NULL is set in the
0467  * residual sg ptr and the transfer is considered complete.  If the
0468  * sequencer determines that there is a residual in the tranfer, or
0469  * there is non-zero status, it will set the SG_STATUS_VALID flag in
0470  * sgptr and dma the scb back into host memory.  To sumarize:
0471  *
0472  * Sequencer:
0473  *  o A residual has occurred if SG_FULL_RESID is set in sgptr,
0474  *    or residual_sgptr does not have SG_LIST_NULL set.
0475  *
0476  *  o We are transferring the last segment if residual_datacnt has
0477  *    the SG_LAST_SEG flag set.
0478  *
0479  * Host:
0480  *  o A residual can only have occurred if a completed scb has the
0481  *    SG_STATUS_VALID flag set.  Inspection of the SCSI status field,
0482  *    the residual_datacnt, and the residual_sgptr field will tell
0483  *    for sure.
0484  *
0485  *  o residual_sgptr and sgptr refer to the "next" sg entry
0486  *    and so may point beyond the last valid sg entry for the
0487  *    transfer.
0488  */ 
0489 #define SG_PTR_MASK 0xFFFFFFF8
0490 /*16*/  uint16_t tag;       /* Reused by Sequencer. */
0491 /*18*/  uint8_t  control;   /* See SCB_CONTROL in aic79xx.reg for details */
0492 /*19*/  uint8_t  scsiid;    /*
0493                  * Selection out Id
0494                  * Our Id (bits 0-3) Their ID (bits 4-7)
0495                  */
0496 /*20*/  uint8_t  lun;
0497 /*21*/  uint8_t  task_attribute;
0498 /*22*/  uint8_t  cdb_len;
0499 /*23*/  uint8_t  task_management;
0500 /*24*/  uint64_t dataptr;
0501 /*32*/  uint32_t datacnt;   /* Byte 3 is spare. */
0502 /*36*/  uint32_t sgptr;
0503 /*40*/  uint32_t hscb_busaddr;
0504 /*44*/  uint32_t next_hscb_busaddr;
0505 /********** Long lun field only downloaded for full 8 byte lun support ********/
0506 /*48*/  uint8_t  pkt_long_lun[8];
0507 /******* Fields below are not Downloaded (Sequencer may use for scratch) ******/
0508 /*56*/  uint8_t  spare[8];
0509 };
0510 
0511 /************************ Kernel SCB Definitions ******************************/
0512 /*
0513  * Some fields of the SCB are OS dependent.  Here we collect the
0514  * definitions for elements that all OS platforms need to include
0515  * in there SCB definition.
0516  */
0517 
0518 /*
0519  * Definition of a scatter/gather element as transferred to the controller.
0520  * The aic7xxx chips only support a 24bit length.  We use the top byte of
0521  * the length to store additional address bits and a flag to indicate
0522  * that a given segment terminates the transfer.  This gives us an
0523  * addressable range of 512GB on machines with 64bit PCI or with chips
0524  * that can support dual address cycles on 32bit PCI busses.
0525  */
0526 struct ahd_dma_seg {
0527     uint32_t    addr;
0528     uint32_t    len;
0529 #define AHD_DMA_LAST_SEG    0x80000000
0530 #define AHD_SG_HIGH_ADDR_MASK   0x7F000000
0531 #define AHD_SG_LEN_MASK     0x00FFFFFF
0532 };
0533 
0534 struct ahd_dma64_seg {
0535     uint64_t    addr;
0536     uint32_t    len;
0537     uint32_t    pad;
0538 };
0539 
0540 struct map_node {
0541     bus_dmamap_t         dmamap;
0542     dma_addr_t       physaddr;
0543     uint8_t         *vaddr;
0544     SLIST_ENTRY(map_node)    links;
0545 };
0546 
0547 /*
0548  * The current state of this SCB.
0549  */
0550 typedef enum {
0551     SCB_FLAG_NONE       = 0x00000,
0552     SCB_TRANSMISSION_ERROR  = 0x00001,/*
0553                        * We detected a parity or CRC
0554                        * error that has effected the
0555                        * payload of the command.  This
0556                        * flag is checked when normal
0557                        * status is returned to catch
0558                        * the case of a target not
0559                        * responding to our attempt
0560                        * to report the error.
0561                        */
0562     SCB_OTHERTCL_TIMEOUT    = 0x00002,/*
0563                        * Another device was active
0564                        * during the first timeout for
0565                        * this SCB so we gave ourselves
0566                        * an additional timeout period
0567                        * in case it was hogging the
0568                        * bus.
0569                            */
0570     SCB_DEVICE_RESET    = 0x00004,
0571     SCB_SENSE       = 0x00008,
0572     SCB_CDB32_PTR       = 0x00010,
0573     SCB_RECOVERY_SCB    = 0x00020,
0574     SCB_AUTO_NEGOTIATE  = 0x00040,/* Negotiate to achieve goal. */
0575     SCB_NEGOTIATE       = 0x00080,/* Negotiation forced for command. */
0576     SCB_ABORT       = 0x00100,
0577     SCB_ACTIVE      = 0x00200,
0578     SCB_TARGET_IMMEDIATE    = 0x00400,
0579     SCB_PACKETIZED      = 0x00800,
0580     SCB_EXPECT_PPR_BUSFREE  = 0x01000,
0581     SCB_PKT_SENSE       = 0x02000,
0582     SCB_EXTERNAL_RESET  = 0x04000,/* Device was reset externally */
0583     SCB_ON_COL_LIST     = 0x08000,
0584     SCB_SILENT      = 0x10000 /*
0585                        * Be quiet about transmission type
0586                        * errors.  They are expected and we
0587                        * don't want to upset the user.  This
0588                        * flag is typically used during DV.
0589                        */
0590 } scb_flag;
0591 
0592 struct scb {
0593     struct  hardware_scb     *hscb;
0594     union {
0595         SLIST_ENTRY(scb)  sle;
0596         LIST_ENTRY(scb)   le;
0597         TAILQ_ENTRY(scb)  tqe;
0598     } links;
0599     union {
0600         SLIST_ENTRY(scb)  sle;
0601         LIST_ENTRY(scb)   le;
0602         TAILQ_ENTRY(scb)  tqe;
0603     } links2;
0604 #define pending_links links2.le
0605 #define collision_links links2.le
0606     struct scb       *col_scb;
0607     ahd_io_ctx_t          io_ctx;
0608     struct ahd_softc     *ahd_softc;
0609     scb_flag          flags;
0610     struct scb_platform_data *platform_data;
0611     struct map_node      *hscb_map;
0612     struct map_node      *sg_map;
0613     struct map_node      *sense_map;
0614     void             *sg_list;
0615     uint8_t          *sense_data;
0616     dma_addr_t        sg_list_busaddr;
0617     dma_addr_t        sense_busaddr;
0618     u_int             sg_count;/* How full ahd_dma_seg is */
0619 #define AHD_MAX_LQ_CRC_ERRORS 5
0620     u_int             crc_retry_count;
0621 };
0622 
0623 TAILQ_HEAD(scb_tailq, scb);
0624 BSD_LIST_HEAD(scb_list, scb);
0625 
0626 struct scb_data {
0627     /*
0628      * TAILQ of lists of free SCBs grouped by device
0629      * collision domains.
0630      */
0631     struct scb_tailq free_scbs;
0632 
0633     /*
0634      * Per-device lists of SCBs whose tag ID would collide
0635      * with an already active tag on the device.
0636      */
0637     struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT];
0638 
0639     /*
0640      * SCBs that will not collide with any active device.
0641      */
0642     struct scb_list any_dev_free_scb_list;
0643 
0644     /*
0645      * Mapping from tag to SCB.
0646      */
0647     struct  scb *scbindex[AHD_SCB_MAX];
0648 
0649     /*
0650      * "Bus" addresses of our data structures.
0651      */
0652     bus_dma_tag_t    hscb_dmat; /* dmat for our hardware SCB array */
0653     bus_dma_tag_t    sg_dmat;   /* dmat for our sg segments */
0654     bus_dma_tag_t    sense_dmat;    /* dmat for our sense buffers */
0655     SLIST_HEAD(, map_node) hscb_maps;
0656     SLIST_HEAD(, map_node) sg_maps;
0657     SLIST_HEAD(, map_node) sense_maps;
0658     int      scbs_left; /* unallocated scbs in head map_node */
0659     int      sgs_left;  /* unallocated sgs in head map_node */
0660     int      sense_left;    /* unallocated sense in head map_node */
0661     uint16_t     numscbs;
0662     uint16_t     maxhscbs;  /* Number of SCBs on the card */
0663     uint8_t      init_level;    /*
0664                      * How far we've initialized
0665                      * this structure.
0666                      */
0667 };
0668 
0669 /************************ Target Mode Definitions *****************************/
0670 
0671 /*
0672  * Connection descriptor for select-in requests in target mode.
0673  */
0674 struct target_cmd {
0675     uint8_t scsiid;     /* Our ID and the initiator's ID */
0676     uint8_t identify;   /* Identify message */
0677     uint8_t bytes[22];  /*
0678                  * Bytes contains any additional message
0679                  * bytes terminated by 0xFF.  The remainder
0680                  * is the cdb to execute.
0681                  */
0682     uint8_t cmd_valid;  /*
0683                  * When a command is complete, the firmware
0684                  * will set cmd_valid to all bits set.
0685                  * After the host has seen the command,
0686                  * the bits are cleared.  This allows us
0687                  * to just peek at host memory to determine
0688                  * if more work is complete. cmd_valid is on
0689                  * an 8 byte boundary to simplify setting
0690                  * it on aic7880 hardware which only has
0691                  * limited direct access to the DMA FIFO.
0692                  */
0693     uint8_t pad[7];
0694 };
0695 
0696 /*
0697  * Number of events we can buffer up if we run out
0698  * of immediate notify ccbs.
0699  */
0700 #define AHD_TMODE_EVENT_BUFFER_SIZE 8
0701 struct ahd_tmode_event {
0702     uint8_t initiator_id;
0703     uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
0704 #define EVENT_TYPE_BUS_RESET 0xFF
0705     uint8_t event_arg;
0706 };
0707 
0708 /*
0709  * Per enabled lun target mode state.
0710  * As this state is directly influenced by the host OS'es target mode
0711  * environment, we let the OS module define it.  Forward declare the
0712  * structure here so we can store arrays of them, etc. in OS neutral
0713  * data structures.
0714  */
0715 #ifdef AHD_TARGET_MODE
0716 struct ahd_tmode_lstate {
0717     struct cam_path *path;
0718     struct ccb_hdr_slist accept_tios;
0719     struct ccb_hdr_slist immed_notifies;
0720     struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE];
0721     uint8_t event_r_idx;
0722     uint8_t event_w_idx;
0723 };
0724 #else
0725 struct ahd_tmode_lstate;
0726 #endif
0727 
0728 /******************** Transfer Negotiation Datastructures *********************/
0729 #define AHD_TRANS_CUR       0x01    /* Modify current neogtiation status */
0730 #define AHD_TRANS_ACTIVE    0x03    /* Assume this target is on the bus */
0731 #define AHD_TRANS_GOAL      0x04    /* Modify negotiation goal */
0732 #define AHD_TRANS_USER      0x08    /* Modify user negotiation settings */
0733 #define AHD_PERIOD_10MHz    0x19
0734 
0735 #define AHD_WIDTH_UNKNOWN   0xFF
0736 #define AHD_PERIOD_UNKNOWN  0xFF
0737 #define AHD_OFFSET_UNKNOWN  0xFF
0738 #define AHD_PPR_OPTS_UNKNOWN    0xFF
0739 
0740 /*
0741  * Transfer Negotiation Information.
0742  */
0743 struct ahd_transinfo {
0744     uint8_t protocol_version;   /* SCSI Revision level */
0745     uint8_t transport_version;  /* SPI Revision level */
0746     uint8_t width;          /* Bus width */
0747     uint8_t period;         /* Sync rate factor */
0748     uint8_t offset;         /* Sync offset */
0749     uint8_t ppr_options;        /* Parallel Protocol Request options */
0750 };
0751 
0752 /*
0753  * Per-initiator current, goal and user transfer negotiation information. */
0754 struct ahd_initiator_tinfo {
0755     struct ahd_transinfo curr;
0756     struct ahd_transinfo goal;
0757     struct ahd_transinfo user;
0758 };
0759 
0760 /*
0761  * Per enabled target ID state.
0762  * Pointers to lun target state as well as sync/wide negotiation information
0763  * for each initiator<->target mapping.  For the initiator role we pretend
0764  * that we are the target and the targets are the initiators since the
0765  * negotiation is the same regardless of role.
0766  */
0767 struct ahd_tmode_tstate {
0768     struct ahd_tmode_lstate*    enabled_luns[AHD_NUM_LUNS];
0769     struct ahd_initiator_tinfo  transinfo[AHD_NUM_TARGETS];
0770 
0771     /*
0772      * Per initiator state bitmasks.
0773      */
0774     uint16_t     auto_negotiate;/* Auto Negotiation Required */
0775     uint16_t     discenable;    /* Disconnection allowed  */
0776     uint16_t     tagenable; /* Tagged Queuing allowed */
0777 };
0778 
0779 /*
0780  * Points of interest along the negotiated transfer scale.
0781  */
0782 #define AHD_SYNCRATE_160    0x8
0783 #define AHD_SYNCRATE_PACED  0x8
0784 #define AHD_SYNCRATE_DT     0x9
0785 #define AHD_SYNCRATE_ULTRA2 0xa
0786 #define AHD_SYNCRATE_ULTRA  0xc
0787 #define AHD_SYNCRATE_FAST   0x19
0788 #define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST
0789 #define AHD_SYNCRATE_SYNC   0x32
0790 #define AHD_SYNCRATE_MIN    0x60
0791 #define AHD_SYNCRATE_ASYNC  0xFF
0792 #define AHD_SYNCRATE_MAX    AHD_SYNCRATE_160
0793 
0794 /* Safe and valid period for async negotiations. */
0795 #define AHD_ASYNC_XFER_PERIOD   0x44
0796 
0797 /*
0798  * In RevA, the synctable uses a 120MHz rate for the period
0799  * factor 8 and 160MHz for the period factor 7.  The 120MHz
0800  * rate never made it into the official SCSI spec, so we must
0801  * compensate when setting the negotiation table for Rev A
0802  * parts.
0803  */
0804 #define AHD_SYNCRATE_REVA_120   0x8
0805 #define AHD_SYNCRATE_REVA_160   0x7
0806 
0807 /***************************** Lookup Tables **********************************/
0808 /*
0809  * Phase -> name and message out response
0810  * to parity errors in each phase table.
0811  */
0812 struct ahd_phase_table_entry {
0813     uint8_t phase;
0814     uint8_t mesg_out; /* Message response to parity errors */
0815     const char *phasemsg;
0816 };
0817 
0818 /************************** Serial EEPROM Format ******************************/
0819 
0820 struct seeprom_config {
0821 /*
0822  * Per SCSI ID Configuration Flags
0823  */
0824     uint16_t device_flags[16];  /* words 0-15 */
0825 #define     CFXFER      0x003F  /* synchronous transfer rate */
0826 #define         CFXFER_ASYNC    0x3F
0827 #define     CFQAS       0x0040  /* Negotiate QAS */
0828 #define     CFPACKETIZED    0x0080  /* Negotiate Packetized Transfers */
0829 #define     CFSTART     0x0100  /* send start unit SCSI command */
0830 #define     CFINCBIOS   0x0200  /* include in BIOS scan */
0831 #define     CFDISC      0x0400  /* enable disconnection */
0832 #define     CFMULTILUNDEV   0x0800  /* Probe multiple luns in BIOS scan */
0833 #define     CFWIDEB     0x1000  /* wide bus device */
0834 #define     CFHOSTMANAGED   0x8000  /* Managed by a RAID controller */
0835 
0836 /*
0837  * BIOS Control Bits
0838  */
0839     uint16_t bios_control;      /* word 16 */
0840 #define     CFSUPREM    0x0001  /* support all removeable drives */
0841 #define     CFSUPREMB   0x0002  /* support removeable boot drives */
0842 #define     CFBIOSSTATE 0x000C  /* BIOS Action State */
0843 #define         CFBS_DISABLED   0x00
0844 #define         CFBS_ENABLED    0x04
0845 #define         CFBS_DISABLED_SCAN  0x08
0846 #define     CFENABLEDV  0x0010  /* Perform Domain Validation */
0847 #define     CFCTRL_A    0x0020  /* BIOS displays Ctrl-A message */
0848 #define     CFSPARITY   0x0040  /* SCSI parity */
0849 #define     CFEXTEND    0x0080  /* extended translation enabled */
0850 #define     CFBOOTCD    0x0100  /* Support Bootable CD-ROM */
0851 #define     CFMSG_LEVEL 0x0600  /* BIOS Message Level */
0852 #define         CFMSG_VERBOSE   0x0000
0853 #define         CFMSG_SILENT    0x0200
0854 #define         CFMSG_DIAG  0x0400
0855 #define     CFRESETB    0x0800  /* reset SCSI bus at boot */
0856 /*      UNUSED      0xf000  */
0857 
0858 /*
0859  * Host Adapter Control Bits
0860  */
0861     uint16_t adapter_control;   /* word 17 */
0862 #define     CFAUTOTERM  0x0001  /* Perform Auto termination */
0863 #define     CFSTERM     0x0002  /* SCSI low byte termination */
0864 #define     CFWSTERM    0x0004  /* SCSI high byte termination */
0865 #define     CFSEAUTOTERM    0x0008  /* Ultra2 Perform secondary Auto Term*/
0866 #define     CFSELOWTERM 0x0010  /* Ultra2 secondary low term */
0867 #define     CFSEHIGHTERM    0x0020  /* Ultra2 secondary high term */
0868 #define     CFSTPWLEVEL 0x0040  /* Termination level control */
0869 #define     CFBIOSAUTOTERM  0x0080  /* Perform Auto termination */
0870 #define     CFTERM_MENU 0x0100  /* BIOS displays termination menu */
0871 #define     CFCLUSTERENB    0x8000  /* Cluster Enable */
0872 
0873 /*
0874  * Bus Release Time, Host Adapter ID
0875  */
0876     uint16_t brtime_id;     /* word 18 */
0877 #define     CFSCSIID    0x000f  /* host adapter SCSI ID */
0878 /*      UNUSED      0x00f0  */
0879 #define     CFBRTIME    0xff00  /* bus release time/PCI Latency Time */
0880 
0881 /*
0882  * Maximum targets
0883  */
0884     uint16_t max_targets;       /* word 19 */
0885 #define     CFMAXTARG   0x00ff  /* maximum targets */
0886 #define     CFBOOTLUN   0x0f00  /* Lun to boot from */
0887 #define     CFBOOTID    0xf000  /* Target to boot from */
0888     uint16_t res_1[10];     /* words 20-29 */
0889     uint16_t signature;     /* BIOS Signature */
0890 #define     CFSIGNATURE 0x400
0891     uint16_t checksum;      /* word 31 */
0892 };
0893 
0894 /*
0895  * Vital Product Data used during POST and by the BIOS.
0896  */
0897 struct vpd_config {
0898     uint8_t  bios_flags;
0899 #define     VPDMASTERBIOS   0x0001
0900 #define     VPDBOOTHOST 0x0002
0901     uint8_t  reserved_1[21];
0902     uint8_t  resource_type;
0903     uint8_t  resource_len[2];
0904     uint8_t  resource_data[8];
0905     uint8_t  vpd_tag;
0906     uint16_t vpd_len;
0907     uint8_t  vpd_keyword[2];
0908     uint8_t  length;
0909     uint8_t  revision;
0910     uint8_t  device_flags;
0911     uint8_t  termination_menus[2];
0912     uint8_t  fifo_threshold;
0913     uint8_t  end_tag;
0914     uint8_t  vpd_checksum;
0915     uint16_t default_target_flags;
0916     uint16_t default_bios_flags;
0917     uint16_t default_ctrl_flags;
0918     uint8_t  default_irq;
0919     uint8_t  pci_lattime;
0920     uint8_t  max_target;
0921     uint8_t  boot_lun;
0922     uint16_t signature;
0923     uint8_t  reserved_2;
0924     uint8_t  checksum;
0925     uint8_t  reserved_3[4];
0926 };
0927 
0928 /****************************** Flexport Logic ********************************/
0929 #define FLXADDR_TERMCTL         0x0
0930 #define     FLX_TERMCTL_ENSECHIGH   0x8
0931 #define     FLX_TERMCTL_ENSECLOW    0x4
0932 #define     FLX_TERMCTL_ENPRIHIGH   0x2
0933 #define     FLX_TERMCTL_ENPRILOW    0x1
0934 #define FLXADDR_ROMSTAT_CURSENSECTL 0x1
0935 #define     FLX_ROMSTAT_SEECFG  0xF0
0936 #define     FLX_ROMSTAT_EECFG   0x0F
0937 #define     FLX_ROMSTAT_SEE_93C66   0x00
0938 #define     FLX_ROMSTAT_SEE_NONE    0xF0
0939 #define     FLX_ROMSTAT_EE_512x8    0x0
0940 #define     FLX_ROMSTAT_EE_1MBx8    0x1
0941 #define     FLX_ROMSTAT_EE_2MBx8    0x2
0942 #define     FLX_ROMSTAT_EE_4MBx8    0x3
0943 #define     FLX_ROMSTAT_EE_16MBx8   0x4
0944 #define         CURSENSE_ENB    0x1
0945 #define FLXADDR_FLEXSTAT        0x2
0946 #define     FLX_FSTAT_BUSY      0x1
0947 #define FLXADDR_CURRENT_STAT        0x4
0948 #define     FLX_CSTAT_SEC_HIGH  0xC0
0949 #define     FLX_CSTAT_SEC_LOW   0x30
0950 #define     FLX_CSTAT_PRI_HIGH  0x0C
0951 #define     FLX_CSTAT_PRI_LOW   0x03
0952 #define     FLX_CSTAT_MASK      0x03
0953 #define     FLX_CSTAT_SHIFT     2
0954 #define     FLX_CSTAT_OKAY      0x0
0955 #define     FLX_CSTAT_OVER      0x1
0956 #define     FLX_CSTAT_UNDER     0x2
0957 #define     FLX_CSTAT_INVALID   0x3
0958 
0959 int     ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf,
0960                  u_int start_addr, u_int count, int bstream);
0961 
0962 int     ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf,
0963                   u_int start_addr, u_int count);
0964 int     ahd_verify_cksum(struct seeprom_config *sc);
0965 int     ahd_acquire_seeprom(struct ahd_softc *ahd);
0966 void        ahd_release_seeprom(struct ahd_softc *ahd);
0967 
0968 /****************************  Message Buffer *********************************/
0969 typedef enum {
0970     MSG_FLAG_NONE           = 0x00,
0971     MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01,
0972     MSG_FLAG_IU_REQ_CHANGED     = 0x02,
0973     MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04,
0974     MSG_FLAG_EXPECT_QASREJ_BUSFREE  = 0x08,
0975     MSG_FLAG_PACKETIZED     = 0x10
0976 } ahd_msg_flags;
0977 
0978 typedef enum {
0979     MSG_TYPE_NONE           = 0x00,
0980     MSG_TYPE_INITIATOR_MSGOUT   = 0x01,
0981     MSG_TYPE_INITIATOR_MSGIN    = 0x02,
0982     MSG_TYPE_TARGET_MSGOUT      = 0x03,
0983     MSG_TYPE_TARGET_MSGIN       = 0x04
0984 } ahd_msg_type;
0985 
0986 typedef enum {
0987     MSGLOOP_IN_PROG,
0988     MSGLOOP_MSGCOMPLETE,
0989     MSGLOOP_TERMINATED
0990 } msg_loop_stat;
0991 
0992 /*********************** Software Configuration Structure *********************/
0993 struct ahd_suspend_channel_state {
0994     uint8_t scsiseq;
0995     uint8_t sxfrctl0;
0996     uint8_t sxfrctl1;
0997     uint8_t simode0;
0998     uint8_t simode1;
0999     uint8_t seltimer;
1000     uint8_t seqctl;
1001 };
1002 
1003 struct ahd_suspend_pci_state {
1004     uint32_t  devconfig;
1005     uint8_t   command;
1006     uint8_t   csize_lattime;
1007 };
1008 
1009 struct ahd_suspend_state {
1010     struct  ahd_suspend_channel_state channel[2];
1011     struct  ahd_suspend_pci_state pci_state;
1012     uint8_t optionmode;
1013     uint8_t dscommand0;
1014     uint8_t dspcistatus;
1015     /* hsmailbox */
1016     uint8_t crccontrol1;
1017     uint8_t scbbaddr;
1018     /* Host and sequencer SCB counts */
1019     uint8_t dff_thrsh;
1020     uint8_t *scratch_ram;
1021     uint8_t *btt;
1022 };
1023 
1024 typedef void (*ahd_bus_intr_t)(struct ahd_softc *);
1025 
1026 typedef enum {
1027     AHD_MODE_DFF0,
1028     AHD_MODE_DFF1,
1029     AHD_MODE_CCHAN,
1030     AHD_MODE_SCSI,
1031     AHD_MODE_CFG,
1032     AHD_MODE_UNKNOWN
1033 } ahd_mode;
1034 
1035 #define AHD_MK_MSK(x) (0x01 << (x))
1036 #define AHD_MODE_DFF0_MSK   AHD_MK_MSK(AHD_MODE_DFF0)
1037 #define AHD_MODE_DFF1_MSK   AHD_MK_MSK(AHD_MODE_DFF1)
1038 #define AHD_MODE_CCHAN_MSK  AHD_MK_MSK(AHD_MODE_CCHAN)
1039 #define AHD_MODE_SCSI_MSK   AHD_MK_MSK(AHD_MODE_SCSI)
1040 #define AHD_MODE_CFG_MSK    AHD_MK_MSK(AHD_MODE_CFG)
1041 #define AHD_MODE_UNKNOWN_MSK    AHD_MK_MSK(AHD_MODE_UNKNOWN)
1042 #define AHD_MODE_ANY_MSK (~0)
1043 
1044 typedef uint8_t ahd_mode_state;
1045 
1046 struct ahd_completion
1047 {
1048     uint16_t    tag;
1049     uint8_t     sg_status;
1050     uint8_t     valid_tag;
1051 };
1052 
1053 struct ahd_softc {
1054     bus_space_tag_t       tags[2];
1055     bus_space_handle_t    bshs[2];
1056     struct scb_data       scb_data;
1057 
1058     struct hardware_scb  *next_queued_hscb;
1059     struct map_node      *next_queued_hscb_map;
1060 
1061     /*
1062      * SCBs that have been sent to the controller
1063      */
1064     BSD_LIST_HEAD(, scb)      pending_scbs;
1065 
1066     /*
1067      * Current register window mode information.
1068      */
1069     ahd_mode          dst_mode;
1070     ahd_mode          src_mode;
1071 
1072     /*
1073      * Saved register window mode information
1074      * used for restore on next unpause.
1075      */
1076     ahd_mode          saved_dst_mode;
1077     ahd_mode          saved_src_mode;
1078 
1079     /*
1080      * Platform specific data.
1081      */
1082     struct ahd_platform_data *platform_data;
1083 
1084     /*
1085      * Platform specific device information.
1086      */
1087     ahd_dev_softc_t       dev_softc;
1088 
1089     /*
1090      * Bus specific device information.
1091      */
1092     ahd_bus_intr_t        bus_intr;
1093 
1094     /*
1095      * Target mode related state kept on a per enabled lun basis.
1096      * Targets that are not enabled will have null entries.
1097      * As an initiator, we keep one target entry for our initiator
1098      * ID to store our sync/wide transfer settings.
1099      */
1100     struct ahd_tmode_tstate  *enabled_targets[AHD_NUM_TARGETS];
1101 
1102     /*
1103      * The black hole device responsible for handling requests for
1104      * disabled luns on enabled targets.
1105      */
1106     struct ahd_tmode_lstate  *black_hole;
1107 
1108     /*
1109      * Device instance currently on the bus awaiting a continue TIO
1110      * for a command that was not given the disconnect priveledge.
1111      */
1112     struct ahd_tmode_lstate  *pending_device;
1113 
1114     /*
1115      * Timer handles for timer driven callbacks.
1116      */
1117     struct timer_list   stat_timer;
1118 
1119     /*
1120      * Statistics.
1121      */
1122 #define AHD_STAT_UPDATE_US  250000 /* 250ms */
1123 #define AHD_STAT_BUCKETS    4
1124     u_int             cmdcmplt_bucket;
1125     uint32_t          cmdcmplt_counts[AHD_STAT_BUCKETS];
1126     uint32_t          cmdcmplt_total;
1127 
1128     /*
1129      * Card characteristics
1130      */
1131     ahd_chip          chip;
1132     ahd_feature       features;
1133     ahd_bug           bugs;
1134     ahd_flag          flags;
1135     struct seeprom_config    *seep_config;
1136 
1137     /* Command Queues */
1138     struct ahd_completion     *qoutfifo;
1139     uint16_t          qoutfifonext;
1140     uint16_t          qoutfifonext_valid_tag;
1141     uint16_t          qinfifonext;
1142     uint16_t          qinfifo[AHD_SCB_MAX];
1143 
1144     /*
1145      * Our qfreeze count.  The sequencer compares
1146      * this value with its own counter to determine
1147      * whether to allow selections to occur.
1148      */
1149     uint16_t          qfreeze_cnt;
1150 
1151     /* Values to store in the SEQCTL register for pause and unpause */
1152     uint8_t           unpause;
1153     uint8_t           pause;
1154 
1155     /* Critical Section Data */
1156     struct cs        *critical_sections;
1157     u_int             num_critical_sections;
1158 
1159     /* Buffer for handling packetized bitbucket. */
1160     uint8_t          *overrun_buf;
1161 
1162     /* Links for chaining softcs */
1163     TAILQ_ENTRY(ahd_softc)    links;
1164 
1165     /* Channel Names ('A', 'B', etc.) */
1166     char              channel;
1167 
1168     /* Initiator Bus ID */
1169     uint8_t           our_id;
1170 
1171     /*
1172      * Target incoming command FIFO.
1173      */
1174     struct target_cmd    *targetcmds;
1175     uint8_t           tqinfifonext;
1176 
1177     /*
1178      * Cached version of the hs_mailbox so we can avoid
1179      * pausing the sequencer during mailbox updates.
1180      */
1181     uint8_t           hs_mailbox;
1182 
1183     /*
1184      * Incoming and outgoing message handling.
1185      */
1186     uint8_t           send_msg_perror;
1187     ahd_msg_flags         msg_flags;
1188     ahd_msg_type          msg_type;
1189     uint8_t           msgout_buf[12];/* Message we are sending */
1190     uint8_t           msgin_buf[12];/* Message we are receiving */
1191     u_int             msgout_len;   /* Length of message to send */
1192     u_int             msgout_index; /* Current index in msgout */
1193     u_int             msgin_index;  /* Current index in msgin */
1194 
1195     /*
1196      * Mapping information for data structures shared
1197      * between the sequencer and kernel.
1198      */
1199     bus_dma_tag_t         parent_dmat;
1200     bus_dma_tag_t         shared_data_dmat;
1201     struct map_node       shared_data_map;
1202 
1203     /* Information saved through suspend/resume cycles */
1204     struct ahd_suspend_state  suspend_state;
1205 
1206     /* Number of enabled target mode device on this card */
1207     u_int             enabled_luns;
1208 
1209     /* Initialization level of this data structure */
1210     u_int             init_level;
1211 
1212     /* PCI cacheline size. */
1213     u_int             pci_cachesize;
1214 
1215     /* IO Cell Parameters */
1216     uint8_t           iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS];
1217 
1218     u_int             stack_size;
1219     uint16_t         *saved_stack;
1220 
1221     /* Per-Unit descriptive information */
1222     const char       *description;
1223     const char       *bus_description;
1224     char             *name;
1225     int           unit;
1226 
1227     /* Selection Timer settings */
1228     int           seltime;
1229 
1230     /*
1231      * Interrupt coalescing settings.
1232      */
1233 #define AHD_INT_COALESCING_TIMER_DEFAULT        250 /*us*/
1234 #define AHD_INT_COALESCING_MAXCMDS_DEFAULT      10
1235 #define AHD_INT_COALESCING_MAXCMDS_MAX          127
1236 #define AHD_INT_COALESCING_MINCMDS_DEFAULT      5
1237 #define AHD_INT_COALESCING_MINCMDS_MAX          127
1238 #define AHD_INT_COALESCING_THRESHOLD_DEFAULT        2000
1239 #define AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT   1000
1240     u_int             int_coalescing_timer;
1241     u_int             int_coalescing_maxcmds;
1242     u_int             int_coalescing_mincmds;
1243     u_int             int_coalescing_threshold;
1244     u_int             int_coalescing_stop_threshold;
1245 
1246     uint16_t          user_discenable;/* Disconnection allowed  */
1247     uint16_t          user_tagenable;/* Tagged Queuing allowed */
1248 };
1249 
1250 /*************************** IO Cell Configuration ****************************/
1251 #define AHD_PRECOMP_SLEW_INDEX                      \
1252     (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0)
1253 
1254 #define AHD_AMPLITUDE_INDEX                     \
1255     (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0)
1256 
1257 #define AHD_SET_SLEWRATE(ahd, new_slew)                 \
1258 do {                                    \
1259     (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK;   \
1260     (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |=           \
1261     (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK);   \
1262 } while (0)
1263 
1264 #define AHD_SET_PRECOMP(ahd, new_pcomp)                 \
1265 do {                                    \
1266     (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK;    \
1267     (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |=           \
1268     (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK);    \
1269 } while (0)
1270 
1271 #define AHD_SET_AMPLITUDE(ahd, new_amp)                 \
1272 do {                                    \
1273     (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \
1274     (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |=              \
1275     (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK);  \
1276 } while (0)
1277 
1278 /************************ Active Device Information ***************************/
1279 typedef enum {
1280     ROLE_UNKNOWN,
1281     ROLE_INITIATOR,
1282     ROLE_TARGET
1283 } role_t;
1284 
1285 struct ahd_devinfo {
1286     int  our_scsiid;
1287     int  target_offset;
1288     uint16_t target_mask;
1289     u_int    target;
1290     u_int    lun;
1291     char     channel;
1292     role_t   role;      /*
1293                  * Only guaranteed to be correct if not
1294                  * in the busfree state.
1295                  */
1296 };
1297 
1298 /****************************** PCI Structures ********************************/
1299 #define AHD_PCI_IOADDR0 PCIR_BAR(0) /* I/O BAR*/
1300 #define AHD_PCI_MEMADDR PCIR_BAR(1) /* Memory BAR */
1301 #define AHD_PCI_IOADDR1 PCIR_BAR(3) /* Second I/O BAR */
1302 
1303 typedef int (ahd_device_setup_t)(struct ahd_softc *);
1304 
1305 struct ahd_pci_identity {
1306     uint64_t         full_id;
1307     uint64_t         id_mask;
1308     const char      *name;
1309     ahd_device_setup_t  *setup;
1310 };
1311 
1312 /***************************** VL/EISA Declarations ***************************/
1313 struct aic7770_identity {
1314     uint32_t         full_id;
1315     uint32_t         id_mask;
1316     const char      *name;
1317     ahd_device_setup_t  *setup;
1318 };
1319 extern struct aic7770_identity aic7770_ident_table [];
1320 extern const int ahd_num_aic7770_devs;
1321 
1322 #define AHD_EISA_SLOT_OFFSET    0xc00
1323 #define AHD_EISA_IOSIZE     0x100
1324 
1325 /*************************** Function Declarations ****************************/
1326 /******************************************************************************/
1327 
1328 /***************************** PCI Front End *********************************/
1329 const struct    ahd_pci_identity *ahd_find_pci_device(ahd_dev_softc_t);
1330 int           ahd_pci_config(struct ahd_softc *,
1331                      const struct ahd_pci_identity *);
1332 int ahd_pci_test_register_access(struct ahd_softc *);
1333 void __maybe_unused ahd_pci_suspend(struct ahd_softc *);
1334 void __maybe_unused ahd_pci_resume(struct ahd_softc *);
1335 
1336 /************************** SCB and SCB queue management **********************/
1337 void        ahd_qinfifo_requeue_tail(struct ahd_softc *ahd,
1338                      struct scb *scb);
1339 
1340 /****************************** Initialization ********************************/
1341 struct ahd_softc    *ahd_alloc(void *platform_arg, char *name);
1342 int          ahd_softc_init(struct ahd_softc *);
1343 void             ahd_controller_info(struct ahd_softc *ahd, char *buf);
1344 int          ahd_init(struct ahd_softc *ahd);
1345 int __maybe_unused   ahd_suspend(struct ahd_softc *ahd);
1346 void __maybe_unused  ahd_resume(struct ahd_softc *ahd);
1347 int          ahd_default_config(struct ahd_softc *ahd);
1348 int          ahd_parse_vpddata(struct ahd_softc *ahd,
1349                        struct vpd_config *vpd);
1350 int          ahd_parse_cfgdata(struct ahd_softc *ahd,
1351                        struct seeprom_config *sc);
1352 void             ahd_intr_enable(struct ahd_softc *ahd, int enable);
1353 void             ahd_pause_and_flushwork(struct ahd_softc *ahd);
1354 void             ahd_set_unit(struct ahd_softc *, int);
1355 void             ahd_set_name(struct ahd_softc *, char *);
1356 struct scb      *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx);
1357 void             ahd_free_scb(struct ahd_softc *ahd, struct scb *scb);
1358 void             ahd_free(struct ahd_softc *ahd);
1359 int          ahd_reset(struct ahd_softc *ahd, int reinit);
1360 int          ahd_write_flexport(struct ahd_softc *ahd,
1361                         u_int addr, u_int value);
1362 int          ahd_read_flexport(struct ahd_softc *ahd, u_int addr,
1363                        uint8_t *value);
1364 
1365 /***************************** Error Recovery *********************************/
1366 typedef enum {
1367     SEARCH_COMPLETE,
1368     SEARCH_COUNT,
1369     SEARCH_REMOVE,
1370     SEARCH_PRINT
1371 } ahd_search_action;
1372 int         ahd_search_qinfifo(struct ahd_softc *ahd, int target,
1373                        char channel, int lun, u_int tag,
1374                        role_t role, uint32_t status,
1375                        ahd_search_action action);
1376 int         ahd_search_disc_list(struct ahd_softc *ahd, int target,
1377                          char channel, int lun, u_int tag,
1378                          int stop_on_first, int remove,
1379                          int save_state);
1380 int         ahd_reset_channel(struct ahd_softc *ahd, char channel,
1381                       int initiate_reset);
1382 /*************************** Utility Functions ********************************/
1383 void            ahd_compile_devinfo(struct ahd_devinfo *devinfo,
1384                         u_int our_id, u_int target,
1385                         u_int lun, char channel,
1386                         role_t role);
1387 /************************** Transfer Negotiation ******************************/
1388 void            ahd_find_syncrate(struct ahd_softc *ahd, u_int *period,
1389                       u_int *ppr_options, u_int maxsync);
1390 /*
1391  * Negotiation types.  These are used to qualify if we should renegotiate
1392  * even if our goal and current transport parameters are identical.
1393  */
1394 typedef enum {
1395     AHD_NEG_TO_GOAL,    /* Renegotiate only if goal and curr differ. */
1396     AHD_NEG_IF_NON_ASYNC,   /* Renegotiate so long as goal is non-async. */
1397     AHD_NEG_ALWAYS      /* Renegotiat even if goal is async. */
1398 } ahd_neg_type;
1399 int         ahd_update_neg_request(struct ahd_softc*,
1400                            struct ahd_devinfo*,
1401                            struct ahd_tmode_tstate*,
1402                            struct ahd_initiator_tinfo*,
1403                            ahd_neg_type);
1404 void            ahd_set_width(struct ahd_softc *ahd,
1405                       struct ahd_devinfo *devinfo,
1406                       u_int width, u_int type, int paused);
1407 void            ahd_set_syncrate(struct ahd_softc *ahd,
1408                      struct ahd_devinfo *devinfo,
1409                      u_int period, u_int offset,
1410                      u_int ppr_options,
1411                      u_int type, int paused);
1412 typedef enum {
1413     AHD_QUEUE_NONE,
1414     AHD_QUEUE_BASIC,
1415     AHD_QUEUE_TAGGED
1416 } ahd_queue_alg;
1417 
1418 /**************************** Target Mode *************************************/
1419 #ifdef AHD_TARGET_MODE
1420 void        ahd_send_lstate_events(struct ahd_softc *,
1421                        struct ahd_tmode_lstate *);
1422 void        ahd_handle_en_lun(struct ahd_softc *ahd,
1423                   struct cam_sim *sim, union ccb *ccb);
1424 cam_status  ahd_find_tmode_devs(struct ahd_softc *ahd,
1425                     struct cam_sim *sim, union ccb *ccb,
1426                     struct ahd_tmode_tstate **tstate,
1427                     struct ahd_tmode_lstate **lstate,
1428                     int notfound_failure);
1429 #ifndef AHD_TMODE_ENABLE
1430 #define AHD_TMODE_ENABLE 0
1431 #endif
1432 #endif
1433 /******************************* Debug ***************************************/
1434 #ifdef AHD_DEBUG
1435 extern uint32_t ahd_debug;
1436 #define AHD_SHOW_MISC       0x00001
1437 #define AHD_SHOW_SENSE      0x00002
1438 #define AHD_SHOW_RECOVERY   0x00004
1439 #define AHD_DUMP_SEEPROM    0x00008
1440 #define AHD_SHOW_TERMCTL    0x00010
1441 #define AHD_SHOW_MEMORY     0x00020
1442 #define AHD_SHOW_MESSAGES   0x00040
1443 #define AHD_SHOW_MODEPTR    0x00080
1444 #define AHD_SHOW_SELTO      0x00100
1445 #define AHD_SHOW_FIFOS      0x00200
1446 #define AHD_SHOW_QFULL      0x00400
1447 #define AHD_SHOW_DV     0x00800
1448 #define AHD_SHOW_MASKED_ERRORS  0x01000
1449 #define AHD_SHOW_QUEUE      0x02000
1450 #define AHD_SHOW_TQIN       0x04000
1451 #define AHD_SHOW_SG     0x08000
1452 #define AHD_SHOW_INT_COALESCING 0x10000
1453 #define AHD_DEBUG_SEQUENCER 0x20000
1454 #endif
1455 void            ahd_print_devinfo(struct ahd_softc *ahd,
1456                       struct ahd_devinfo *devinfo);
1457 void            ahd_dump_card_state(struct ahd_softc *ahd);
1458 int         ahd_print_register(const ahd_reg_parse_entry_t *table,
1459                        u_int num_entries,
1460                        const char *name,
1461                        u_int address,
1462                        u_int value,
1463                        u_int *cur_column,
1464                        u_int wrap_point);
1465 #endif /* _AIC79XX_H_ */
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