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0001 /*
0002  * Initio A100 device driver for Linux.
0003  *
0004  * Copyright (c) 1994-1998 Initio Corporation
0005  * Copyright (c) 2003-2004 Christoph Hellwig
0006  * All rights reserved.
0007  *
0008  * This program is free software; you can redistribute it and/or modify
0009  * it under the terms of the GNU General Public License as published by
0010  * the Free Software Foundation; either version 2, or (at your option)
0011  * any later version.
0012  *
0013  * This program is distributed in the hope that it will be useful,
0014  * but WITHOUT ANY WARRANTY; without even the implied warranty of
0015  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
0016  * GNU General Public License for more details.
0017  *
0018  * You should have received a copy of the GNU General Public License
0019  * along with this program; see the file COPYING.  If not, write to
0020  * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
0021  *
0022  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
0023  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0024  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0025  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
0026  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0027  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
0028  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
0029  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
0030  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
0031  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
0032  * SUCH DAMAGE.
0033  */
0034 
0035 /*
0036  * Revision History:
0037  * 07/02/98 hl  - v.91n Initial drivers.
0038  * 09/14/98 hl - v1.01 Support new Kernel.
0039  * 09/22/98 hl - v1.01a Support reset.
0040  * 09/24/98 hl - v1.01b Fixed reset.
0041  * 10/05/98 hl - v1.02 split the source code and release.
0042  * 12/19/98 bv - v1.02a Use spinlocks for 2.1.95 and up
0043  * 01/31/99 bv - v1.02b Use mdelay instead of waitForPause
0044  * 08/08/99 bv - v1.02c Use waitForPause again.
0045  * 06/25/02 Doug Ledford <dledford@redhat.com> - v1.02d
0046  *          - Remove limit on number of controllers
0047  *          - Port to DMA mapping API
0048  *          - Clean up interrupt handler registration
0049  *          - Fix memory leaks
0050  *          - Fix allocation of scsi host structs and private data
0051  * 11/18/03 Christoph Hellwig <hch@lst.de>
0052  *      - Port to new probing API
0053  *      - Fix some more leaks in init failure cases
0054  * 9/28/04 Christoph Hellwig <hch@lst.de>
0055  *      - merge the two source files
0056  *      - remove internal queueing code
0057  * 14/06/07 Alan Cox <alan@lxorguk.ukuu.org.uk>
0058  *   - Grand cleanup and Linuxisation
0059  */
0060 
0061 #include <linux/module.h>
0062 #include <linux/errno.h>
0063 #include <linux/delay.h>
0064 #include <linux/interrupt.h>
0065 #include <linux/pci.h>
0066 #include <linux/init.h>
0067 #include <linux/blkdev.h>
0068 #include <linux/spinlock.h>
0069 #include <linux/kernel.h>
0070 #include <linux/string.h>
0071 #include <linux/ioport.h>
0072 #include <linux/dma-mapping.h>
0073 
0074 #include <asm/io.h>
0075 #include <asm/irq.h>
0076 
0077 #include <scsi/scsi.h>
0078 #include <scsi/scsi_cmnd.h>
0079 #include <scsi/scsi_device.h>
0080 #include <scsi/scsi_host.h>
0081 
0082 #include "a100u2w.h"
0083 
0084 
0085 static struct orc_scb *__orc_alloc_scb(struct orc_host * host);
0086 static void inia100_scb_handler(struct orc_host *host, struct orc_scb *scb);
0087 
0088 static struct orc_nvram nvram, *nvramp = &nvram;
0089 
0090 static u8 default_nvram[64] =
0091 {
0092 /*----------header -------------*/
0093     0x01,           /* 0x00: Sub System Vendor ID 0 */
0094     0x11,           /* 0x01: Sub System Vendor ID 1 */
0095     0x60,           /* 0x02: Sub System ID 0        */
0096     0x10,           /* 0x03: Sub System ID 1        */
0097     0x00,           /* 0x04: SubClass               */
0098     0x01,           /* 0x05: Vendor ID 0            */
0099     0x11,           /* 0x06: Vendor ID 1            */
0100     0x60,           /* 0x07: Device ID 0            */
0101     0x10,           /* 0x08: Device ID 1            */
0102     0x00,           /* 0x09: Reserved               */
0103     0x00,           /* 0x0A: Reserved               */
0104     0x01,           /* 0x0B: Revision of Data Structure     */
0105                 /* -- Host Adapter Structure --- */
0106     0x01,           /* 0x0C: Number Of SCSI Channel */
0107     0x01,           /* 0x0D: BIOS Configuration 1   */
0108     0x00,           /* 0x0E: BIOS Configuration 2   */
0109     0x00,           /* 0x0F: BIOS Configuration 3   */
0110                 /* --- SCSI Channel 0 Configuration --- */
0111     0x07,           /* 0x10: H/A ID                 */
0112     0x83,           /* 0x11: Channel Configuration  */
0113     0x20,           /* 0x12: MAX TAG per target     */
0114     0x0A,           /* 0x13: SCSI Reset Recovering time     */
0115     0x00,           /* 0x14: Channel Configuration4 */
0116     0x00,           /* 0x15: Channel Configuration5 */
0117                 /* SCSI Channel 0 Target Configuration  */
0118                 /* 0x16-0x25                    */
0119     0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
0120     0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
0121                 /* --- SCSI Channel 1 Configuration --- */
0122     0x07,           /* 0x26: H/A ID                 */
0123     0x83,           /* 0x27: Channel Configuration  */
0124     0x20,           /* 0x28: MAX TAG per target     */
0125     0x0A,           /* 0x29: SCSI Reset Recovering time     */
0126     0x00,           /* 0x2A: Channel Configuration4 */
0127     0x00,           /* 0x2B: Channel Configuration5 */
0128                 /* SCSI Channel 1 Target Configuration  */
0129                 /* 0x2C-0x3B                    */
0130     0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
0131     0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
0132     0x00,           /* 0x3C: Reserved               */
0133     0x00,           /* 0x3D: Reserved               */
0134     0x00,           /* 0x3E: Reserved               */
0135     0x00            /* 0x3F: Checksum               */
0136 };
0137 
0138 
0139 static u8 wait_chip_ready(struct orc_host * host)
0140 {
0141     int i;
0142 
0143     for (i = 0; i < 10; i++) {  /* Wait 1 second for report timeout     */
0144         if (inb(host->base + ORC_HCTRL) & HOSTSTOP) /* Wait HOSTSTOP set */
0145             return 1;
0146         msleep(100);
0147     }
0148     return 0;
0149 }
0150 
0151 static u8 wait_firmware_ready(struct orc_host * host)
0152 {
0153     int i;
0154 
0155     for (i = 0; i < 10; i++) {  /* Wait 1 second for report timeout     */
0156         if (inb(host->base + ORC_HSTUS) & RREADY)       /* Wait READY set */
0157             return 1;
0158         msleep(100);    /* wait 100ms before try again  */
0159     }
0160     return 0;
0161 }
0162 
0163 /***************************************************************************/
0164 static u8 wait_scsi_reset_done(struct orc_host * host)
0165 {
0166     int i;
0167 
0168     for (i = 0; i < 10; i++) {  /* Wait 1 second for report timeout     */
0169         if (!(inb(host->base + ORC_HCTRL) & SCSIRST))   /* Wait SCSIRST done */
0170             return 1;
0171         mdelay(100);    /* wait 100ms before try again  */
0172     }
0173     return 0;
0174 }
0175 
0176 /***************************************************************************/
0177 static u8 wait_HDO_off(struct orc_host * host)
0178 {
0179     int i;
0180 
0181     for (i = 0; i < 10; i++) {  /* Wait 1 second for report timeout     */
0182         if (!(inb(host->base + ORC_HCTRL) & HDO))       /* Wait HDO off */
0183             return 1;
0184         mdelay(100);    /* wait 100ms before try again  */
0185     }
0186     return 0;
0187 }
0188 
0189 /***************************************************************************/
0190 static u8 wait_hdi_set(struct orc_host * host, u8 * data)
0191 {
0192     int i;
0193 
0194     for (i = 0; i < 10; i++) {  /* Wait 1 second for report timeout     */
0195         if ((*data = inb(host->base + ORC_HSTUS)) & HDI)
0196             return 1;   /* Wait HDI set */
0197         mdelay(100);    /* wait 100ms before try again  */
0198     }
0199     return 0;
0200 }
0201 
0202 /***************************************************************************/
0203 static unsigned short orc_read_fwrev(struct orc_host * host)
0204 {
0205     u16 version;
0206     u8 data;
0207 
0208     outb(ORC_CMD_VERSION, host->base + ORC_HDATA);
0209     outb(HDO, host->base + ORC_HCTRL);
0210     if (wait_HDO_off(host) == 0)    /* Wait HDO off   */
0211         return 0;
0212 
0213     if (wait_hdi_set(host, &data) == 0) /* Wait HDI set   */
0214         return 0;
0215     version = inb(host->base + ORC_HDATA);
0216     outb(data, host->base + ORC_HSTUS); /* Clear HDI            */
0217 
0218     if (wait_hdi_set(host, &data) == 0) /* Wait HDI set   */
0219         return 0;
0220     version |= inb(host->base + ORC_HDATA) << 8;
0221     outb(data, host->base + ORC_HSTUS); /* Clear HDI            */
0222 
0223     return version;
0224 }
0225 
0226 /***************************************************************************/
0227 static u8 orc_nv_write(struct orc_host * host, unsigned char address, unsigned char value)
0228 {
0229     outb(ORC_CMD_SET_NVM, host->base + ORC_HDATA);  /* Write command */
0230     outb(HDO, host->base + ORC_HCTRL);
0231     if (wait_HDO_off(host) == 0)    /* Wait HDO off   */
0232         return 0;
0233 
0234     outb(address, host->base + ORC_HDATA);  /* Write address */
0235     outb(HDO, host->base + ORC_HCTRL);
0236     if (wait_HDO_off(host) == 0)    /* Wait HDO off   */
0237         return 0;
0238 
0239     outb(value, host->base + ORC_HDATA);    /* Write value  */
0240     outb(HDO, host->base + ORC_HCTRL);
0241     if (wait_HDO_off(host) == 0)    /* Wait HDO off   */
0242         return 0;
0243 
0244     return 1;
0245 }
0246 
0247 /***************************************************************************/
0248 static u8 orc_nv_read(struct orc_host * host, u8 address, u8 *ptr)
0249 {
0250     unsigned char data;
0251 
0252     outb(ORC_CMD_GET_NVM, host->base + ORC_HDATA);  /* Write command */
0253     outb(HDO, host->base + ORC_HCTRL);
0254     if (wait_HDO_off(host) == 0)    /* Wait HDO off   */
0255         return 0;
0256 
0257     outb(address, host->base + ORC_HDATA);  /* Write address */
0258     outb(HDO, host->base + ORC_HCTRL);
0259     if (wait_HDO_off(host) == 0)    /* Wait HDO off   */
0260         return 0;
0261 
0262     if (wait_hdi_set(host, &data) == 0) /* Wait HDI set   */
0263         return 0;
0264     *ptr = inb(host->base + ORC_HDATA);
0265     outb(data, host->base + ORC_HSTUS); /* Clear HDI    */
0266 
0267     return 1;
0268 
0269 }
0270 
0271 /**
0272  *  orc_exec_scb        -   Queue an SCB with the HA
0273  *  @host: host adapter the SCB belongs to
0274  *  @scb: SCB to queue for execution
0275  */
0276 
0277 static void orc_exec_scb(struct orc_host * host, struct orc_scb * scb)
0278 {
0279     scb->status = ORCSCB_POST;
0280     outb(scb->scbidx, host->base + ORC_PQUEUE);
0281 }
0282 
0283 
0284 /**
0285  *  se2_rd_all  -   read SCSI parameters from EEPROM
0286  *  @host: Host whose EEPROM is being loaded
0287  *
0288  *  Read SCSI H/A configuration parameters from serial EEPROM
0289  */
0290 
0291 static int se2_rd_all(struct orc_host * host)
0292 {
0293     int i;
0294     u8 *np, chksum = 0;
0295 
0296     np = (u8 *) nvramp;
0297     for (i = 0; i < 64; i++, np++) {    /* <01> */
0298         if (orc_nv_read(host, (u8) i, np) == 0)
0299             return -1;
0300     }
0301 
0302     /*------ Is ckecksum ok ? ------*/
0303     np = (u8 *) nvramp;
0304     for (i = 0; i < 63; i++)
0305         chksum += *np++;
0306 
0307     if (nvramp->CheckSum != (u8) chksum)
0308         return -1;
0309     return 1;
0310 }
0311 
0312 /**
0313  *  se2_update_all      -   update the EEPROM
0314  *  @host: Host whose EEPROM is being updated
0315  *
0316  *  Update changed bytes in the EEPROM image.
0317  */
0318 
0319 static void se2_update_all(struct orc_host * host)
0320 {               /* setup default pattern  */
0321     int i;
0322     u8 *np, *np1, chksum = 0;
0323 
0324     /* Calculate checksum first   */
0325     np = (u8 *) default_nvram;
0326     for (i = 0; i < 63; i++)
0327         chksum += *np++;
0328     *np = chksum;
0329 
0330     np = (u8 *) default_nvram;
0331     np1 = (u8 *) nvramp;
0332     for (i = 0; i < 64; i++, np++, np1++) {
0333         if (*np != *np1)
0334             orc_nv_write(host, (u8) i, *np);
0335     }
0336 }
0337 
0338 /**
0339  *  read_eeprom     -   load EEPROM
0340  *  @host: Host EEPROM to read
0341  *
0342  *  Read the EEPROM for a given host. If it is invalid or fails
0343  *  the restore the defaults and use them.
0344  */
0345 
0346 static void read_eeprom(struct orc_host * host)
0347 {
0348     if (se2_rd_all(host) != 1) {
0349         se2_update_all(host);   /* setup default pattern        */
0350         se2_rd_all(host);   /* load again                   */
0351     }
0352 }
0353 
0354 
0355 /**
0356  *  orc_load_firmware   -   initialise firmware
0357  *  @host: Host to set up
0358  *
0359  *  Load the firmware from the EEPROM into controller SRAM. This
0360  *  is basically a 4K block copy and then a 4K block read to check
0361  *  correctness. The rest is convulted by the indirect interfaces
0362  *  in the hardware
0363  */
0364 
0365 static u8 orc_load_firmware(struct orc_host * host)
0366 {
0367     u32 data32;
0368     u16 bios_addr;
0369     u16 i;
0370     u8 *data32_ptr, data;
0371 
0372 
0373     /* Set up the EEPROM for access */
0374 
0375     data = inb(host->base + ORC_GCFG);
0376     outb(data | EEPRG, host->base + ORC_GCFG);  /* Enable EEPROM programming */
0377     outb(0x00, host->base + ORC_EBIOSADR2);
0378     outw(0x0000, host->base + ORC_EBIOSADR0);
0379     if (inb(host->base + ORC_EBIOSDATA) != 0x55) {
0380         outb(data, host->base + ORC_GCFG);  /* Disable EEPROM programming */
0381         return 0;
0382     }
0383     outw(0x0001, host->base + ORC_EBIOSADR0);
0384     if (inb(host->base + ORC_EBIOSDATA) != 0xAA) {
0385         outb(data, host->base + ORC_GCFG);  /* Disable EEPROM programming */
0386         return 0;
0387     }
0388 
0389     outb(PRGMRST | DOWNLOAD, host->base + ORC_RISCCTL); /* Enable SRAM programming */
0390     data32_ptr = (u8 *) & data32;
0391     data32 = cpu_to_le32(0);        /* Initial FW address to 0 */
0392     outw(0x0010, host->base + ORC_EBIOSADR0);
0393     *data32_ptr = inb(host->base + ORC_EBIOSDATA);      /* Read from BIOS */
0394     outw(0x0011, host->base + ORC_EBIOSADR0);
0395     *(data32_ptr + 1) = inb(host->base + ORC_EBIOSDATA);    /* Read from BIOS */
0396     outw(0x0012, host->base + ORC_EBIOSADR0);
0397     *(data32_ptr + 2) = inb(host->base + ORC_EBIOSDATA);    /* Read from BIOS */
0398     outw(*(data32_ptr + 2), host->base + ORC_EBIOSADR2);
0399     outl(le32_to_cpu(data32), host->base + ORC_FWBASEADR);      /* Write FW address */
0400 
0401     /* Copy the code from the BIOS to the SRAM */
0402 
0403     udelay(500);    /* Required on Sun Ultra 5 ... 350 -> failures */
0404     bios_addr = (u16) le32_to_cpu(data32);  /* FW code locate at BIOS address + ? */
0405     for (i = 0, data32_ptr = (u8 *) & data32;   /* Download the code    */
0406          i < 0x1000;    /* Firmware code size = 4K      */
0407          i++, bios_addr++) {
0408         outw(bios_addr, host->base + ORC_EBIOSADR0);
0409         *data32_ptr++ = inb(host->base + ORC_EBIOSDATA);    /* Read from BIOS */
0410         if ((i % 4) == 3) {
0411             outl(le32_to_cpu(data32), host->base + ORC_RISCRAM);    /* Write every 4 bytes */
0412             data32_ptr = (u8 *) & data32;
0413         }
0414     }
0415 
0416     /* Go back and check they match */
0417 
0418     outb(PRGMRST | DOWNLOAD, host->base + ORC_RISCCTL); /* Reset program count 0 */
0419     bios_addr -= 0x1000;    /* Reset the BIOS address */
0420     for (i = 0, data32_ptr = (u8 *) & data32;   /* Check the code       */
0421          i < 0x1000;    /* Firmware code size = 4K      */
0422          i++, bios_addr++) {
0423         outw(bios_addr, host->base + ORC_EBIOSADR0);
0424         *data32_ptr++ = inb(host->base + ORC_EBIOSDATA);    /* Read from BIOS */
0425         if ((i % 4) == 3) {
0426             if (inl(host->base + ORC_RISCRAM) != le32_to_cpu(data32)) {
0427                 outb(PRGMRST, host->base + ORC_RISCCTL);    /* Reset program to 0 */
0428                 outb(data, host->base + ORC_GCFG);  /*Disable EEPROM programming */
0429                 return 0;
0430             }
0431             data32_ptr = (u8 *) & data32;
0432         }
0433     }
0434 
0435     /* Success */
0436     outb(PRGMRST, host->base + ORC_RISCCTL);    /* Reset program to 0   */
0437     outb(data, host->base + ORC_GCFG);  /* Disable EEPROM programming */
0438     return 1;
0439 }
0440 
0441 /***************************************************************************/
0442 static void setup_SCBs(struct orc_host * host)
0443 {
0444     struct orc_scb *scb;
0445     int i;
0446     struct orc_extended_scb *escb;
0447     dma_addr_t escb_phys;
0448 
0449     /* Setup SCB base and SCB Size registers */
0450     outb(ORC_MAXQUEUE, host->base + ORC_SCBSIZE);   /* Total number of SCBs */
0451     /* SCB base address 0      */
0452     outl(host->scb_phys, host->base + ORC_SCBBASE0);
0453     /* SCB base address 1      */
0454     outl(host->scb_phys, host->base + ORC_SCBBASE1);
0455 
0456     /* setup scatter list address with one buffer */
0457     scb = host->scb_virt;
0458     escb = host->escb_virt;
0459 
0460     for (i = 0; i < ORC_MAXQUEUE; i++) {
0461         escb_phys = (host->escb_phys + (sizeof(struct orc_extended_scb) * i));
0462         scb->sg_addr = cpu_to_le32((u32) escb_phys);
0463         scb->sense_addr = cpu_to_le32((u32) escb_phys);
0464         scb->escb = escb;
0465         scb->scbidx = i;
0466         scb++;
0467         escb++;
0468     }
0469 }
0470 
0471 /**
0472  *  init_alloc_map      -   initialise allocation map
0473  *  @host: host map to configure
0474  *
0475  *  Initialise the allocation maps for this device. If the device
0476  *  is not quiescent the caller must hold the allocation lock
0477  */
0478 
0479 static void init_alloc_map(struct orc_host * host)
0480 {
0481     u8 i, j;
0482 
0483     for (i = 0; i < MAX_CHANNELS; i++) {
0484         for (j = 0; j < 8; j++) {
0485             host->allocation_map[i][j] = 0xffffffff;
0486         }
0487     }
0488 }
0489 
0490 /**
0491  *  init_orchid     -   initialise the host adapter
0492  *  @host:host adapter to initialise
0493  *
0494  *  Initialise the controller and if necessary load the firmware.
0495  *
0496  *  Returns -1 if the initialisation fails.
0497  */
0498 
0499 static int init_orchid(struct orc_host * host)
0500 {
0501     u8 *ptr;
0502     u16 revision;
0503     u8 i;
0504 
0505     init_alloc_map(host);
0506     outb(0xFF, host->base + ORC_GIMSK); /* Disable all interrupts */
0507 
0508     if (inb(host->base + ORC_HSTUS) & RREADY) { /* Orchid is ready */
0509         revision = orc_read_fwrev(host);
0510         if (revision == 0xFFFF) {
0511             outb(DEVRST, host->base + ORC_HCTRL);   /* Reset Host Adapter   */
0512             if (wait_chip_ready(host) == 0)
0513                 return -1;
0514             orc_load_firmware(host);    /* Download FW                  */
0515             setup_SCBs(host);   /* Setup SCB base and SCB Size registers */
0516             outb(0x00, host->base + ORC_HCTRL); /* clear HOSTSTOP       */
0517             if (wait_firmware_ready(host) == 0)
0518                 return -1;
0519             /* Wait for firmware ready     */
0520         } else {
0521             setup_SCBs(host);   /* Setup SCB base and SCB Size registers */
0522         }
0523     } else {        /* Orchid is not Ready          */
0524         outb(DEVRST, host->base + ORC_HCTRL);   /* Reset Host Adapter   */
0525         if (wait_chip_ready(host) == 0)
0526             return -1;
0527         orc_load_firmware(host);    /* Download FW                  */
0528         setup_SCBs(host);   /* Setup SCB base and SCB Size registers */
0529         outb(HDO, host->base + ORC_HCTRL);  /* Do Hardware Reset &  */
0530 
0531         /*     clear HOSTSTOP  */
0532         if (wait_firmware_ready(host) == 0)     /* Wait for firmware ready      */
0533             return -1;
0534     }
0535 
0536     /* Load an EEProm copy into RAM */
0537     /* Assumes single threaded at this point */
0538     read_eeprom(host);
0539 
0540     if (nvramp->revision != 1)
0541         return -1;
0542 
0543     host->scsi_id = nvramp->scsi_id;
0544     host->BIOScfg = nvramp->BIOSConfig1;
0545     host->max_targets = MAX_TARGETS;
0546     ptr = (u8 *) & (nvramp->Target00Config);
0547     for (i = 0; i < 16; ptr++, i++) {
0548         host->target_flag[i] = *ptr;
0549         host->max_tags[i] = ORC_MAXTAGS;
0550     }
0551 
0552     if (nvramp->SCSI0Config & NCC_BUSRESET)
0553         host->flags |= HCF_SCSI_RESET;
0554     outb(0xFB, host->base + ORC_GIMSK); /* enable RP FIFO interrupt     */
0555     return 0;
0556 }
0557 
0558 /**
0559  *  orc_reset_scsi_bus      -   perform bus reset
0560  *  @host: host being reset
0561  *
0562  *  Perform a full bus reset on the adapter.
0563  */
0564 
0565 static int orc_reset_scsi_bus(struct orc_host * host)
0566 {               /* I need Host Control Block Information */
0567     unsigned long flags;
0568 
0569     spin_lock_irqsave(&host->allocation_lock, flags);
0570 
0571     init_alloc_map(host);
0572     /* reset scsi bus */
0573     outb(SCSIRST, host->base + ORC_HCTRL);
0574     /* FIXME: We can spend up to a second with the lock held and
0575        interrupts off here */
0576     if (wait_scsi_reset_done(host) == 0) {
0577         spin_unlock_irqrestore(&host->allocation_lock, flags);
0578         return FAILED;
0579     } else {
0580         spin_unlock_irqrestore(&host->allocation_lock, flags);
0581         return SUCCESS;
0582     }
0583 }
0584 
0585 /**
0586  *  orc_device_reset    -   device reset handler
0587  *  @host: host to reset
0588  *  @cmd: command causing the reset
0589  *  @target: target device
0590  *
0591  *  Reset registers, reset a hanging bus and kill active and disconnected
0592  *  commands for target w/o soft reset
0593  */
0594 
0595 static int orc_device_reset(struct orc_host * host, struct scsi_cmnd *cmd, unsigned int target)
0596 {               /* I need Host Control Block Information */
0597     struct orc_scb *scb;
0598     struct orc_extended_scb *escb;
0599     struct orc_scb *host_scb;
0600     u8 i;
0601     unsigned long flags;
0602 
0603     spin_lock_irqsave(&(host->allocation_lock), flags);
0604     scb = (struct orc_scb *) NULL;
0605     escb = (struct orc_extended_scb *) NULL;
0606 
0607     /* setup scatter list address with one buffer */
0608     host_scb = host->scb_virt;
0609 
0610     /* FIXME: is this safe if we then fail to issue the reset or race
0611        a completion ? */
0612     init_alloc_map(host);
0613 
0614     /* Find the scb corresponding to the command */
0615     for (i = 0; i < ORC_MAXQUEUE; i++) {
0616         escb = host_scb->escb;
0617         if (host_scb->status && escb->srb == cmd)
0618             break;
0619         host_scb++;
0620     }
0621 
0622     if (i == ORC_MAXQUEUE) {
0623         printk(KERN_ERR "Unable to Reset - No SCB Found\n");
0624         spin_unlock_irqrestore(&(host->allocation_lock), flags);
0625         return FAILED;
0626     }
0627 
0628     /* Allocate a new SCB for the reset command to the firmware */
0629     if ((scb = __orc_alloc_scb(host)) == NULL) {
0630         /* Can't happen.. */
0631         spin_unlock_irqrestore(&(host->allocation_lock), flags);
0632         return FAILED;
0633     }
0634 
0635     /* Reset device is handled by the firmware, we fill in an SCB and
0636        fire it at the controller, it does the rest */
0637     scb->opcode = ORC_BUSDEVRST;
0638     scb->target = target;
0639     scb->hastat = 0;
0640     scb->tastat = 0;
0641     scb->status = 0x0;
0642     scb->link = 0xFF;
0643     scb->reserved0 = 0;
0644     scb->reserved1 = 0;
0645     scb->xferlen = cpu_to_le32(0);
0646     scb->sg_len = cpu_to_le32(0);
0647 
0648     escb->srb = NULL;
0649     escb->srb = cmd;
0650     orc_exec_scb(host, scb);    /* Start execute SCB            */
0651     spin_unlock_irqrestore(&host->allocation_lock, flags);
0652     return SUCCESS;
0653 }
0654 
0655 /**
0656  *  __orc_alloc_scb     -       allocate an SCB
0657  *  @host: host to allocate from
0658  *
0659  *  Allocate an SCB and return a pointer to the SCB object. NULL
0660  *  is returned if no SCB is free. The caller must already hold
0661  *  the allocator lock at this point.
0662  */
0663 
0664 
0665 static struct orc_scb *__orc_alloc_scb(struct orc_host * host)
0666 {
0667     u8 channel;
0668     unsigned long idx;
0669     u8 index;
0670     u8 i;
0671 
0672     channel = host->index;
0673     for (i = 0; i < 8; i++) {
0674         for (index = 0; index < 32; index++) {
0675             if ((host->allocation_map[channel][i] >> index) & 0x01) {
0676                 host->allocation_map[channel][i] &= ~(1 << index);
0677                 idx = index + 32 * i;
0678                 /*
0679                  * Translate the index to a structure instance
0680                  */
0681                 return host->scb_virt + idx;
0682             }
0683         }
0684     }
0685     return NULL;
0686 }
0687 
0688 /**
0689  *  orc_alloc_scb       -       allocate an SCB
0690  *  @host: host to allocate from
0691  *
0692  *  Allocate an SCB and return a pointer to the SCB object. NULL
0693  *  is returned if no SCB is free.
0694  */
0695 
0696 static struct orc_scb *orc_alloc_scb(struct orc_host * host)
0697 {
0698     struct orc_scb *scb;
0699     unsigned long flags;
0700 
0701     spin_lock_irqsave(&host->allocation_lock, flags);
0702     scb = __orc_alloc_scb(host);
0703     spin_unlock_irqrestore(&host->allocation_lock, flags);
0704     return scb;
0705 }
0706 
0707 /**
0708  *  orc_release_scb         -   release an SCB
0709  *  @host: host owning the SCB
0710  *  @scb: SCB that is now free
0711  *
0712  *  Called to return a completed SCB to the allocation pool. Before
0713  *  calling the SCB must be out of use on both the host and the HA.
0714  */
0715 
0716 static void orc_release_scb(struct orc_host *host, struct orc_scb *scb)
0717 {
0718     unsigned long flags;
0719     u8 index, i, channel;
0720 
0721     spin_lock_irqsave(&(host->allocation_lock), flags);
0722     channel = host->index;  /* Channel */
0723     index = scb->scbidx;
0724     i = index / 32;
0725     index %= 32;
0726     host->allocation_map[channel][i] |= (1 << index);
0727     spin_unlock_irqrestore(&(host->allocation_lock), flags);
0728 }
0729 
0730 /*
0731  *  orchid_abort_scb    -   abort a command
0732  *
0733  *  Abort a queued command that has been passed to the firmware layer
0734  *  if possible. This is all handled by the firmware. We aks the firmware
0735  *  and it either aborts the command or fails
0736  */
0737 
0738 static int orchid_abort_scb(struct orc_host * host, struct orc_scb * scb)
0739 {
0740     unsigned char data, status;
0741 
0742     outb(ORC_CMD_ABORT_SCB, host->base + ORC_HDATA);    /* Write command */
0743     outb(HDO, host->base + ORC_HCTRL);
0744     if (wait_HDO_off(host) == 0)    /* Wait HDO off   */
0745         return 0;
0746 
0747     outb(scb->scbidx, host->base + ORC_HDATA);  /* Write address */
0748     outb(HDO, host->base + ORC_HCTRL);
0749     if (wait_HDO_off(host) == 0)    /* Wait HDO off   */
0750         return 0;
0751 
0752     if (wait_hdi_set(host, &data) == 0) /* Wait HDI set   */
0753         return 0;
0754     status = inb(host->base + ORC_HDATA);
0755     outb(data, host->base + ORC_HSTUS); /* Clear HDI    */
0756 
0757     if (status == 1)    /* 0 - Successfully               */
0758         return 0;   /* 1 - Fail                     */
0759     return 1;
0760 }
0761 
0762 static int inia100_abort_cmd(struct orc_host * host, struct scsi_cmnd *cmd)
0763 {
0764     struct orc_extended_scb *escb;
0765     struct orc_scb *scb;
0766     u8 i;
0767     unsigned long flags;
0768 
0769     spin_lock_irqsave(&(host->allocation_lock), flags);
0770 
0771     scb = host->scb_virt;
0772 
0773     /* Walk the queue until we find the SCB that belongs to the command
0774        block. This isn't a performance critical path so a walk in the park
0775        here does no harm */
0776 
0777     for (i = 0; i < ORC_MAXQUEUE; i++, scb++) {
0778         escb = scb->escb;
0779         if (scb->status && escb->srb == cmd) {
0780             if (scb->tag_msg == 0) {
0781                 goto out;
0782             } else {
0783                 /* Issue an ABORT to the firmware */
0784                 if (orchid_abort_scb(host, scb)) {
0785                     escb->srb = NULL;
0786                     spin_unlock_irqrestore(&host->allocation_lock, flags);
0787                     return SUCCESS;
0788                 } else
0789                     goto out;
0790             }
0791         }
0792     }
0793 out:
0794     spin_unlock_irqrestore(&host->allocation_lock, flags);
0795     return FAILED;
0796 }
0797 
0798 /**
0799  *  orc_interrupt       -   IRQ processing
0800  *  @host: Host causing the interrupt
0801  *
0802  *  This function is called from the IRQ handler and protected
0803  *  by the host lock. While the controller reports that there are
0804  *  scb's for processing we pull them off the controller, turn the
0805  *  index into a host address pointer to the scb and call the scb
0806  *  handler.
0807  *
0808  *  Returns IRQ_HANDLED if any SCBs were processed, IRQ_NONE otherwise
0809  */
0810 
0811 static irqreturn_t orc_interrupt(struct orc_host * host)
0812 {
0813     u8 scb_index;
0814     struct orc_scb *scb;
0815 
0816     /* Check if we have an SCB queued for servicing */
0817     if (inb(host->base + ORC_RQUEUECNT) == 0)
0818         return IRQ_NONE;
0819 
0820     do {
0821         /* Get the SCB index of the SCB to service */
0822         scb_index = inb(host->base + ORC_RQUEUE);
0823 
0824         /* Translate it back to a host pointer */
0825         scb = (struct orc_scb *) ((unsigned long) host->scb_virt + (unsigned long) (sizeof(struct orc_scb) * scb_index));
0826         scb->status = 0x0;
0827         /* Process the SCB */
0828         inia100_scb_handler(host, scb);
0829     } while (inb(host->base + ORC_RQUEUECNT));
0830     return IRQ_HANDLED;
0831 }               /* End of I1060Interrupt() */
0832 
0833 /**
0834  *  inia100_build_scb   -   build SCB
0835  *  @host: host owing the control block
0836  *  @scb: control block to use
0837  *  @cmd: Mid layer command
0838  *
0839  *  Build a host adapter control block from the SCSI mid layer command
0840  */
0841 
0842 static int inia100_build_scb(struct orc_host * host, struct orc_scb * scb, struct scsi_cmnd * cmd)
0843 {               /* Create corresponding SCB     */
0844     struct scatterlist *sg;
0845     struct orc_sgent *sgent;        /* Pointer to SG list           */
0846     int i, count_sg;
0847     struct orc_extended_scb *escb;
0848 
0849     /* Links between the escb, scb and Linux scsi midlayer cmd */
0850     escb = scb->escb;
0851     escb->srb = cmd;
0852     sgent = NULL;
0853 
0854     /* Set up the SCB to do a SCSI command block */
0855     scb->opcode = ORC_EXECSCSI;
0856     scb->flags = SCF_NO_DCHK;   /* Clear done bit               */
0857     scb->target = cmd->device->id;
0858     scb->lun = cmd->device->lun;
0859     scb->reserved0 = 0;
0860     scb->reserved1 = 0;
0861     scb->sg_len = cpu_to_le32(0);
0862 
0863     scb->xferlen = cpu_to_le32((u32) scsi_bufflen(cmd));
0864     sgent = (struct orc_sgent *) & escb->sglist[0];
0865 
0866     count_sg = scsi_dma_map(cmd);
0867     if (count_sg < 0)
0868         return count_sg;
0869     BUG_ON(count_sg > TOTAL_SG_ENTRY);
0870 
0871     /* Build the scatter gather lists */
0872     if (count_sg) {
0873         scb->sg_len = cpu_to_le32((u32) (count_sg * 8));
0874         scsi_for_each_sg(cmd, sg, count_sg, i) {
0875             sgent->base = cpu_to_le32((u32) sg_dma_address(sg));
0876             sgent->length = cpu_to_le32((u32) sg_dma_len(sg));
0877             sgent++;
0878         }
0879     } else {
0880         scb->sg_len = cpu_to_le32(0);
0881         sgent->base = cpu_to_le32(0);
0882         sgent->length = cpu_to_le32(0);
0883     }
0884     scb->sg_addr = (u32) scb->sense_addr;   /* sense_addr is already little endian */
0885     scb->hastat = 0;
0886     scb->tastat = 0;
0887     scb->link = 0xFF;
0888     scb->sense_len = SENSE_SIZE;
0889     scb->cdb_len = cmd->cmd_len;
0890     if (scb->cdb_len >= IMAX_CDB) {
0891         printk("max cdb length= %x\n", cmd->cmd_len);
0892         scb->cdb_len = IMAX_CDB;
0893     }
0894     scb->ident = (u8)(cmd->device->lun & 0xff) | DISC_ALLOW;
0895     if (cmd->device->tagged_supported) {    /* Tag Support                  */
0896         scb->tag_msg = SIMPLE_QUEUE_TAG;    /* Do simple tag only   */
0897     } else {
0898         scb->tag_msg = 0;   /* No tag support               */
0899     }
0900     memcpy(scb->cdb, cmd->cmnd, scb->cdb_len);
0901     return 0;
0902 }
0903 
0904 /**
0905  *  inia100_queue_lck       -   queue command with host
0906  *  @cmd: Command block
0907  *
0908  *  Called by the mid layer to queue a command. Process the command
0909  *  block, build the host specific scb structures and if there is room
0910  *  queue the command down to the controller
0911  */
0912 static int inia100_queue_lck(struct scsi_cmnd *cmd)
0913 {
0914     struct orc_scb *scb;
0915     struct orc_host *host;      /* Point to Host adapter control block */
0916 
0917     host = (struct orc_host *) cmd->device->host->hostdata;
0918     /* Get free SCSI control block  */
0919     if ((scb = orc_alloc_scb(host)) == NULL)
0920         return SCSI_MLQUEUE_HOST_BUSY;
0921 
0922     if (inia100_build_scb(host, scb, cmd)) {
0923         orc_release_scb(host, scb);
0924         return SCSI_MLQUEUE_HOST_BUSY;
0925     }
0926     orc_exec_scb(host, scb);    /* Start execute SCB            */
0927     return 0;
0928 }
0929 
0930 static DEF_SCSI_QCMD(inia100_queue)
0931 
0932 /*****************************************************************************
0933  Function name  : inia100_abort
0934  Description    : Abort a queued command.
0935                      (commands that are on the bus can't be aborted easily)
0936  Input          : host  -       Pointer to host adapter structure
0937  Output         : None.
0938  Return         : pSRB  -       Pointer to SCSI request block.
0939 *****************************************************************************/
0940 static int inia100_abort(struct scsi_cmnd * cmd)
0941 {
0942     struct orc_host *host;
0943 
0944     host = (struct orc_host *) cmd->device->host->hostdata;
0945     return inia100_abort_cmd(host, cmd);
0946 }
0947 
0948 /*****************************************************************************
0949  Function name  : inia100_reset
0950  Description    : Reset registers, reset a hanging bus and
0951                   kill active and disconnected commands for target w/o soft reset
0952  Input          : host  -       Pointer to host adapter structure
0953  Output         : None.
0954  Return         : pSRB  -       Pointer to SCSI request block.
0955 *****************************************************************************/
0956 static int inia100_bus_reset(struct scsi_cmnd * cmd)
0957 {               /* I need Host Control Block Information */
0958     struct orc_host *host;
0959     host = (struct orc_host *) cmd->device->host->hostdata;
0960     return orc_reset_scsi_bus(host);
0961 }
0962 
0963 /*****************************************************************************
0964  Function name  : inia100_device_reset
0965  Description    : Reset the device
0966  Input          : host  -       Pointer to host adapter structure
0967  Output         : None.
0968  Return         : pSRB  -       Pointer to SCSI request block.
0969 *****************************************************************************/
0970 static int inia100_device_reset(struct scsi_cmnd * cmd)
0971 {               /* I need Host Control Block Information */
0972     struct orc_host *host;
0973     host = (struct orc_host *) cmd->device->host->hostdata;
0974     return orc_device_reset(host, cmd, scmd_id(cmd));
0975 
0976 }
0977 
0978 /**
0979  *  inia100_scb_handler -   interrupt callback
0980  *  @host: Host causing the interrupt
0981  *  @scb: SCB the controller returned as needing processing
0982  *
0983  *  Perform completion processing on a control block. Do the conversions
0984  *  from host to SCSI midlayer error coding, save any sense data and
0985  *  the complete with the midlayer and recycle the scb.
0986  */
0987 
0988 static void inia100_scb_handler(struct orc_host *host, struct orc_scb *scb)
0989 {
0990     struct scsi_cmnd *cmd;  /* Pointer to SCSI request block */
0991     struct orc_extended_scb *escb;
0992 
0993     escb = scb->escb;
0994     if ((cmd = (struct scsi_cmnd *) escb->srb) == NULL) {
0995         printk(KERN_ERR "inia100_scb_handler: SRB pointer is empty\n");
0996         orc_release_scb(host, scb); /* Release SCB for current channel */
0997         return;
0998     }
0999     escb->srb = NULL;
1000 
1001     switch (scb->hastat) {
1002     case 0x0:
1003     case 0xa:       /* Linked command complete without error and linked normally */
1004     case 0xb:       /* Linked command complete without error interrupt generated */
1005         scb->hastat = 0;
1006         break;
1007 
1008     case 0x11:      /* Selection time out-The initiator selection or target
1009                    reselection was not complete within the SCSI Time out period */
1010         scb->hastat = DID_TIME_OUT;
1011         break;
1012 
1013     case 0x14:      /* Target bus phase sequence failure-An invalid bus phase or bus
1014                    phase sequence was requested by the target. The host adapter
1015                    will generate a SCSI Reset Condition, notifying the host with
1016                    a SCRD interrupt */
1017         scb->hastat = DID_RESET;
1018         break;
1019 
1020     case 0x1a:      /* SCB Aborted. 07/21/98 */
1021         scb->hastat = DID_ABORT;
1022         break;
1023 
1024     case 0x12:      /* Data overrun/underrun-The target attempted to transfer more data
1025                    than was allocated by the Data Length field or the sum of the
1026                    Scatter / Gather Data Length fields. */
1027     case 0x13:      /* Unexpected bus free-The target dropped the SCSI BSY at an unexpected time. */
1028     case 0x16:      /* Invalid CCB Operation Code-The first byte of the CCB was invalid. */
1029 
1030     default:
1031         printk(KERN_DEBUG "inia100: %x %x\n", scb->hastat, scb->tastat);
1032         scb->hastat = DID_ERROR;    /* Couldn't find any better */
1033         break;
1034     }
1035 
1036     if (scb->tastat == 2) { /* Check condition              */
1037         memcpy((unsigned char *) &cmd->sense_buffer[0],
1038            (unsigned char *) &escb->sglist[0], SENSE_SIZE);
1039     }
1040     cmd->result = scb->tastat | (scb->hastat << 16);
1041     scsi_dma_unmap(cmd);
1042     scsi_done(cmd);     /* Notify system DONE           */
1043     orc_release_scb(host, scb); /* Release SCB for current channel */
1044 }
1045 
1046 /**
1047  *  inia100_intr        -   interrupt handler
1048  *  @irqno: Interrupt value
1049  *  @devid: Host adapter
1050  *
1051  *  Entry point for IRQ handling. All the real work is performed
1052  *  by orc_interrupt.
1053  */
1054 static irqreturn_t inia100_intr(int irqno, void *devid)
1055 {
1056     struct Scsi_Host *shost = (struct Scsi_Host *)devid;
1057     struct orc_host *host = (struct orc_host *)shost->hostdata;
1058     unsigned long flags;
1059     irqreturn_t res;
1060 
1061     spin_lock_irqsave(shost->host_lock, flags);
1062     res = orc_interrupt(host);
1063     spin_unlock_irqrestore(shost->host_lock, flags);
1064 
1065     return res;
1066 }
1067 
1068 static struct scsi_host_template inia100_template = {
1069     .proc_name      = "inia100",
1070     .name           = inia100_REVID,
1071     .queuecommand       = inia100_queue,
1072     .eh_abort_handler   = inia100_abort,
1073     .eh_bus_reset_handler   = inia100_bus_reset,
1074     .eh_device_reset_handler = inia100_device_reset,
1075     .can_queue      = 1,
1076     .this_id        = 1,
1077     .sg_tablesize       = SG_ALL,
1078 };
1079 
1080 static int inia100_probe_one(struct pci_dev *pdev,
1081                  const struct pci_device_id *id)
1082 {
1083     struct Scsi_Host *shost;
1084     struct orc_host *host;
1085     unsigned long port, bios;
1086     int error = -ENODEV;
1087     u32 sz;
1088 
1089     if (pci_enable_device(pdev))
1090         goto out;
1091     if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
1092         printk(KERN_WARNING "Unable to set 32bit DMA "
1093                     "on inia100 adapter, ignoring.\n");
1094         goto out_disable_device;
1095     }
1096 
1097     pci_set_master(pdev);
1098 
1099     port = pci_resource_start(pdev, 0);
1100     if (!request_region(port, 256, "inia100")) {
1101         printk(KERN_WARNING "inia100: io port 0x%lx, is busy.\n", port);
1102         goto out_disable_device;
1103     }
1104 
1105     /* <02> read from base address + 0x50 offset to get the bios value. */
1106     bios = inw(port + 0x50);
1107 
1108 
1109     shost = scsi_host_alloc(&inia100_template, sizeof(struct orc_host));
1110     if (!shost)
1111         goto out_release_region;
1112 
1113     host = (struct orc_host *)shost->hostdata;
1114     host->pdev = pdev;
1115     host->base = port;
1116     host->BIOScfg = bios;
1117     spin_lock_init(&host->allocation_lock);
1118 
1119     /* Get total memory needed for SCB */
1120     sz = ORC_MAXQUEUE * sizeof(struct orc_scb);
1121     host->scb_virt = dma_alloc_coherent(&pdev->dev, sz, &host->scb_phys,
1122                         GFP_KERNEL);
1123     if (!host->scb_virt) {
1124         printk("inia100: SCB memory allocation error\n");
1125         goto out_host_put;
1126     }
1127 
1128     /* Get total memory needed for ESCB */
1129     sz = ORC_MAXQUEUE * sizeof(struct orc_extended_scb);
1130     host->escb_virt = dma_alloc_coherent(&pdev->dev, sz, &host->escb_phys,
1131                          GFP_KERNEL);
1132     if (!host->escb_virt) {
1133         printk("inia100: ESCB memory allocation error\n");
1134         goto out_free_scb_array;
1135     }
1136 
1137     if (init_orchid(host)) {    /* Initialize orchid chip */
1138         printk("inia100: initial orchid fail!!\n");
1139         goto out_free_escb_array;
1140     }
1141 
1142     shost->io_port = host->base;
1143     shost->n_io_port = 0xff;
1144     shost->can_queue = ORC_MAXQUEUE;
1145     shost->unique_id = shost->io_port;
1146     shost->max_id = host->max_targets;
1147     shost->max_lun = 16;
1148     shost->irq = pdev->irq;
1149     shost->this_id = host->scsi_id; /* Assign HCS index */
1150     shost->sg_tablesize = TOTAL_SG_ENTRY;
1151 
1152     /* Initial orc chip           */
1153     error = request_irq(pdev->irq, inia100_intr, IRQF_SHARED,
1154             "inia100", shost);
1155     if (error < 0) {
1156         printk(KERN_WARNING "inia100: unable to get irq %d\n",
1157                 pdev->irq);
1158         goto out_free_escb_array;
1159     }
1160 
1161     pci_set_drvdata(pdev, shost);
1162 
1163     error = scsi_add_host(shost, &pdev->dev);
1164     if (error)
1165         goto out_free_irq;
1166 
1167     scsi_scan_host(shost);
1168     return 0;
1169 
1170 out_free_irq:
1171         free_irq(shost->irq, shost);
1172 out_free_escb_array:
1173     dma_free_coherent(&pdev->dev,
1174             ORC_MAXQUEUE * sizeof(struct orc_extended_scb),
1175             host->escb_virt, host->escb_phys);
1176 out_free_scb_array:
1177     dma_free_coherent(&pdev->dev,
1178             ORC_MAXQUEUE * sizeof(struct orc_scb),
1179             host->scb_virt, host->scb_phys);
1180 out_host_put:
1181     scsi_host_put(shost);
1182 out_release_region:
1183         release_region(port, 256);
1184 out_disable_device:
1185     pci_disable_device(pdev);
1186 out:
1187     return error;
1188 }
1189 
1190 static void inia100_remove_one(struct pci_dev *pdev)
1191 {
1192     struct Scsi_Host *shost = pci_get_drvdata(pdev);
1193     struct orc_host *host = (struct orc_host *)shost->hostdata;
1194 
1195     scsi_remove_host(shost);
1196 
1197         free_irq(shost->irq, shost);
1198     dma_free_coherent(&pdev->dev,
1199             ORC_MAXQUEUE * sizeof(struct orc_extended_scb),
1200             host->escb_virt, host->escb_phys);
1201     dma_free_coherent(&pdev->dev,
1202             ORC_MAXQUEUE * sizeof(struct orc_scb),
1203             host->scb_virt, host->scb_phys);
1204         release_region(shost->io_port, 256);
1205 
1206     scsi_host_put(shost);
1207 } 
1208 
1209 static struct pci_device_id inia100_pci_tbl[] = {
1210     {PCI_VENDOR_ID_INIT, 0x1060, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1211     {0,}
1212 };
1213 MODULE_DEVICE_TABLE(pci, inia100_pci_tbl);
1214 
1215 static struct pci_driver inia100_pci_driver = {
1216     .name       = "inia100",
1217     .id_table   = inia100_pci_tbl,
1218     .probe      = inia100_probe_one,
1219     .remove     = inia100_remove_one,
1220 };
1221 
1222 module_pci_driver(inia100_pci_driver);
1223 
1224 MODULE_DESCRIPTION("Initio A100U2W SCSI driver");
1225 MODULE_AUTHOR("Initio Corporation");
1226 MODULE_LICENSE("Dual BSD/GPL");
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