drivers/scsi/NCR5380.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * NCR 5380 defines
0004  *
0005  * Copyright 1993, Drew Eckhardt
0006  *  Visionary Computing
0007  *  (Unix consulting and custom programming)
0008  *  drew@colorado.edu
0009  *      +1 (303) 666-5836
0010  *
0011  * For more information, please consult
0012  *
0013  * NCR 5380 Family
0014  * SCSI Protocol Controller
0015  * Databook
0016  * NCR Microelectronics
0017  * 1635 Aeroplaza Drive
0018  * Colorado Springs, CO 80916
0019  * 1+ (719) 578-3400
0020  * 1+ (800) 334-5454
0021  */
0022
0023 #ifndef NCR5380_H
0024 #define NCR5380_H
0025
0026 #include <linux/delay.h>
0027 #include <linux/interrupt.h>
0028 #include <linux/list.h>
0029 #include <linux/workqueue.h>
0030 #include <scsi/scsi_dbg.h>
0031 #include <scsi/scsi_eh.h>
0032 #include <scsi/scsi_transport_spi.h>
0033
0034 #define NDEBUG_ARBITRATION  0x1
0035 #define NDEBUG_AUTOSENSE    0x2
0036 #define NDEBUG_DMA      0x4
0037 #define NDEBUG_HANDSHAKE    0x8
0038 #define NDEBUG_INFORMATION  0x10
0039 #define NDEBUG_INIT     0x20
0040 #define NDEBUG_INTR     0x40
0041 #define NDEBUG_LINKED       0x80
0042 #define NDEBUG_MAIN     0x100
0043 #define NDEBUG_NO_DATAOUT   0x200
0044 #define NDEBUG_NO_WRITE     0x400
0045 #define NDEBUG_PIO      0x800
0046 #define NDEBUG_PSEUDO_DMA   0x1000
0047 #define NDEBUG_QUEUES       0x2000
0048 #define NDEBUG_RESELECTION  0x4000
0049 #define NDEBUG_SELECTION    0x8000
0050 #define NDEBUG_USLEEP       0x10000
0051 #define NDEBUG_LAST_BYTE_SENT   0x20000
0052 #define NDEBUG_RESTART_SELECT   0x40000
0053 #define NDEBUG_EXTENDED     0x80000
0054 #define NDEBUG_C400_PREAD   0x100000
0055 #define NDEBUG_C400_PWRITE  0x200000
0056 #define NDEBUG_LISTS        0x400000
0057 #define NDEBUG_ABORT        0x800000
0058 #define NDEBUG_TAGS     0x1000000
0059 #define NDEBUG_MERGING      0x2000000
0060
0061 #define NDEBUG_ANY      0xFFFFFFFFUL
0062
0063 /*
0064  * The contents of the OUTPUT DATA register are asserted on the bus when
0065  * either arbitration is occurring or the phase-indicating signals (
0066  * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
0067  * bit in the INITIATOR COMMAND register is set.
0068  */
0069
0070 #define OUTPUT_DATA_REG         0   /* wo DATA lines on SCSI bus */
0071 #define CURRENT_SCSI_DATA_REG   0   /* ro same */
0072
0073 #define INITIATOR_COMMAND_REG   1   /* rw */
0074 #define ICR_ASSERT_RST      0x80    /* rw Set to assert RST  */
0075 #define ICR_ARBITRATION_PROGRESS 0x40   /* ro Indicates arbitration complete */
0076 #define ICR_TRI_STATE       0x40    /* wo Set to tri-state drivers */
0077 #define ICR_ARBITRATION_LOST    0x20    /* ro Indicates arbitration lost */
0078 #define ICR_DIFF_ENABLE     0x20    /* wo Set to enable diff. drivers */
0079 #define ICR_ASSERT_ACK      0x10    /* rw ini Set to assert ACK */
0080 #define ICR_ASSERT_BSY      0x08    /* rw Set to assert BSY */
0081 #define ICR_ASSERT_SEL      0x04    /* rw Set to assert SEL */
0082 #define ICR_ASSERT_ATN      0x02    /* rw Set to assert ATN */
0083 #define ICR_ASSERT_DATA     0x01    /* rw SCSI_DATA_REG is asserted */
0084
0085 #define ICR_BASE        0
0086
0087 #define MODE_REG        2
0088 /*
0089  * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the
0090  * transfer, causing the chip to hog the bus.  You probably don't want
0091  * this.
0092  */
0093 #define MR_BLOCK_DMA_MODE   0x80    /* rw block mode DMA */
0094 #define MR_TARGET       0x40    /* rw target mode */
0095 #define MR_ENABLE_PAR_CHECK 0x20    /* rw enable parity checking */
0096 #define MR_ENABLE_PAR_INTR  0x10    /* rw enable bad parity interrupt */
0097 #define MR_ENABLE_EOP_INTR  0x08    /* rw enable eop interrupt */
0098 #define MR_MONITOR_BSY      0x04    /* rw enable int on unexpected bsy fail */
0099 #define MR_DMA_MODE     0x02    /* rw DMA / pseudo DMA mode */
0100 #define MR_ARBITRATE        0x01    /* rw start arbitration */
0101
0102 #define MR_BASE         0
0103
0104 #define TARGET_COMMAND_REG  3
0105 #define TCR_LAST_BYTE_SENT  0x80    /* ro DMA done */
0106 #define TCR_ASSERT_REQ      0x08    /* tgt rw assert REQ */
0107 #define TCR_ASSERT_MSG      0x04    /* tgt rw assert MSG */
0108 #define TCR_ASSERT_CD       0x02    /* tgt rw assert CD */
0109 #define TCR_ASSERT_IO       0x01    /* tgt rw assert IO */
0110
0111 #define STATUS_REG      4   /* ro */
0112 /*
0113  * Note : a set bit indicates an active signal, driven by us or another
0114  * device.
0115  */
0116 #define SR_RST          0x80
0117 #define SR_BSY          0x40
0118 #define SR_REQ          0x20
0119 #define SR_MSG          0x10
0120 #define SR_CD           0x08
0121 #define SR_IO           0x04
0122 #define SR_SEL          0x02
0123 #define SR_DBP          0x01
0124
0125 /*
0126  * Setting a bit in this register will cause an interrupt to be generated when
0127  * BSY is false and SEL true and this bit is asserted  on the bus.
0128  */
0129 #define SELECT_ENABLE_REG   4   /* wo */
0130
0131 #define BUS_AND_STATUS_REG  5   /* ro */
0132 #define BASR_END_DMA_TRANSFER   0x80    /* ro set on end of transfer */
0133 #define BASR_DRQ        0x40    /* ro mirror of DRQ pin */
0134 #define BASR_PARITY_ERROR   0x20    /* ro parity error detected */
0135 #define BASR_IRQ        0x10    /* ro mirror of IRQ pin */
0136 #define BASR_PHASE_MATCH    0x08    /* ro Set when MSG CD IO match TCR */
0137 #define BASR_BUSY_ERROR     0x04    /* ro Unexpected change to inactive state */
0138 #define BASR_ATN        0x02    /* ro BUS status */
0139 #define BASR_ACK        0x01    /* ro BUS status */
0140
0141 /* Write any value to this register to start a DMA send */
0142 #define START_DMA_SEND_REG  5   /* wo */
0143
0144 /*
0145  * Used in DMA transfer mode, data is latched from the SCSI bus on
0146  * the falling edge of REQ (ini) or ACK (tgt)
0147  */
0148 #define INPUT_DATA_REG          6   /* ro */
0149
0150 /* Write any value to this register to start a DMA receive */
0151 #define START_DMA_TARGET_RECEIVE_REG    6   /* wo */
0152
0153 /* Read this register to clear interrupt conditions */
0154 #define RESET_PARITY_INTERRUPT_REG  7   /* ro */
0155
0156 /* Write any value to this register to start an ini mode DMA receive */
0157 #define START_DMA_INITIATOR_RECEIVE_REG 7   /* wo */
0158
0159 /* NCR 53C400(A) Control Status Register bits: */
0160 #define CSR_RESET              0x80 /* wo  Resets 53c400 */
0161 #define CSR_53C80_REG          0x80 /* ro  5380 registers busy */
0162 #define CSR_TRANS_DIR          0x40 /* rw  Data transfer direction */
0163 #define CSR_SCSI_BUFF_INTR     0x20 /* rw  Enable int on transfer ready */
0164 #define CSR_53C80_INTR         0x10 /* rw  Enable 53c80 interrupts */
0165 #define CSR_SHARED_INTR        0x08 /* rw  Interrupt sharing */
0166 #define CSR_HOST_BUF_NOT_RDY   0x04 /* ro  Is Host buffer ready */
0167 #define CSR_SCSI_BUF_RDY       0x02 /* ro  SCSI buffer read */
0168 #define CSR_GATED_53C80_IRQ    0x01 /* ro  Last block xferred */
0169
0170 #define CSR_BASE CSR_53C80_INTR
0171
0172 /* Note : PHASE_* macros are based on the values of the STATUS register */
0173 #define PHASE_MASK  (SR_MSG | SR_CD | SR_IO)
0174
0175 #define PHASE_DATAOUT       0
0176 #define PHASE_DATAIN        SR_IO
0177 #define PHASE_CMDOUT        SR_CD
0178 #define PHASE_STATIN        (SR_CD | SR_IO)
0179 #define PHASE_MSGOUT        (SR_MSG | SR_CD)
0180 #define PHASE_MSGIN     (SR_MSG | SR_CD | SR_IO)
0181 #define PHASE_UNKNOWN       0xff
0182
0183 /*
0184  * Convert status register phase to something we can use to set phase in
0185  * the target register so we can get phase mismatch interrupts on DMA
0186  * transfers.
0187  */
0188
0189 #define PHASE_SR_TO_TCR(phase) ((phase) >> 2)
0190
0191 #ifndef NO_IRQ
0192 #define NO_IRQ      0
0193 #endif
0194
0195 #define FLAG_DMA_FIXUP          1   /* Use DMA errata workarounds */
0196 #define FLAG_NO_PSEUDO_DMA      8   /* Inhibit DMA */
0197 #define FLAG_LATE_DMA_SETUP     32  /* Setup NCR before DMA H/W */
0198 #define FLAG_TOSHIBA_DELAY      128 /* Allow for borken CD-ROMs */
0199
0200 struct NCR5380_hostdata {
0201     NCR5380_implementation_fields;      /* Board-specific data */
0202     u8 __iomem *io;             /* Remapped 5380 address */
0203     u8 __iomem *pdma_io;            /* Remapped PDMA address */
0204     unsigned long poll_loops;       /* Register polling limit */
0205     spinlock_t lock;            /* Protects this struct */
0206     struct scsi_cmnd *connected;        /* Currently connected cmnd */
0207     struct list_head disconnected;      /* Waiting for reconnect */
0208     struct Scsi_Host *host;         /* SCSI host backpointer */
0209     struct workqueue_struct *work_q;    /* SCSI host work queue */
0210     struct work_struct main_task;       /* Work item for main loop */
0211     int flags;              /* Board-specific quirks */
0212     int dma_len;                /* Requested length of DMA */
0213     int read_overruns;  /* Transfer size reduction for DMA erratum */
0214     unsigned long io_port;          /* Device IO port */
0215     unsigned long base;         /* Device base address */
0216     struct list_head unissued;      /* Waiting to be issued */
0217     struct scsi_cmnd *selecting;        /* Cmnd to be connected */
0218     struct list_head autosense;     /* Priority cmnd queue */
0219     struct scsi_cmnd *sensing;      /* Cmnd needing autosense */
0220     struct scsi_eh_save ses;        /* Cmnd state saved for EH */
0221     unsigned char busy[8];          /* Index = target, bit = lun */
0222     unsigned char id_mask;          /* 1 << Host ID */
0223     unsigned char id_higher_mask;       /* All bits above id_mask */
0224     unsigned char last_message;     /* Last Message Out */
0225     unsigned long region_size;      /* Size of address/port range */
0226     char info[168];             /* Host banner message */
0227 };
0228
0229 struct NCR5380_cmd {
0230     char *ptr;
0231     int this_residual;
0232     struct scatterlist *buffer;
0233     int status;
0234     int message;
0235     int phase;
0236     struct list_head list;
0237 };
0238
0239 #define NCR5380_PIO_CHUNK_SIZE      256
0240
0241 /* Time limit (ms) to poll registers when IRQs are disabled, e.g. during PDMA */
0242 #define NCR5380_REG_POLL_TIME       10
0243
0244 static inline struct scsi_cmnd *NCR5380_to_scmd(struct NCR5380_cmd *ncmd_ptr)
0245 {
0246     return ((struct scsi_cmnd *)ncmd_ptr) - 1;
0247 }
0248
0249 static inline struct NCR5380_cmd *NCR5380_to_ncmd(struct scsi_cmnd *cmd)
0250 {
0251     return scsi_cmd_priv(cmd);
0252 }
0253
0254 #ifndef NDEBUG
0255 #define NDEBUG (0)
0256 #endif
0257
0258 #define dprintk(flg, fmt, ...) \
0259     do { if ((NDEBUG) & (flg)) \
0260         printk(KERN_DEBUG fmt, ## __VA_ARGS__); } while (0)
0261
0262 #define dsprintk(flg, host, fmt, ...) \
0263     do { if ((NDEBUG) & (flg)) \
0264         shost_printk(KERN_DEBUG, host, fmt, ## __VA_ARGS__); \
0265     } while (0)
0266
0267 #if NDEBUG
0268 #define NCR5380_dprint(flg, arg) \
0269     do { if ((NDEBUG) & (flg)) NCR5380_print(arg); } while (0)
0270 #define NCR5380_dprint_phase(flg, arg) \
0271     do { if ((NDEBUG) & (flg)) NCR5380_print_phase(arg); } while (0)
0272 static void NCR5380_print_phase(struct Scsi_Host *instance);
0273 static void NCR5380_print(struct Scsi_Host *instance);
0274 #else
0275 #define NCR5380_dprint(flg, arg)       do {} while (0)
0276 #define NCR5380_dprint_phase(flg, arg) do {} while (0)
0277 #endif
0278
0279 static int NCR5380_init(struct Scsi_Host *instance, int flags);
0280 static int NCR5380_maybe_reset_bus(struct Scsi_Host *);
0281 static void NCR5380_exit(struct Scsi_Host *instance);
0282 static void NCR5380_information_transfer(struct Scsi_Host *instance);
0283 static irqreturn_t NCR5380_intr(int irq, void *dev_id);
0284 static void NCR5380_main(struct work_struct *work);
0285 static const char *NCR5380_info(struct Scsi_Host *instance);
0286 static void NCR5380_reselect(struct Scsi_Host *instance);
0287 static bool NCR5380_select(struct Scsi_Host *, struct scsi_cmnd *);
0288 static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
0289 static int NCR5380_transfer_pio(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data,
0290                 unsigned int can_sleep);
0291 static int NCR5380_poll_politely2(struct NCR5380_hostdata *,
0292                                   unsigned int, u8, u8,
0293                                   unsigned int, u8, u8, unsigned long);
0294
0295 static inline int NCR5380_poll_politely(struct NCR5380_hostdata *hostdata,
0296                                         unsigned int reg, u8 bit, u8 val,
0297                                         unsigned long wait)
0298 {
0299     if ((NCR5380_read(reg) & bit) == val)
0300         return 0;
0301
0302     return NCR5380_poll_politely2(hostdata, reg, bit, val,
0303                         reg, bit, val, wait);
0304 }
0305
0306 static int NCR5380_dma_xfer_len(struct NCR5380_hostdata *,
0307                                 struct scsi_cmnd *);
0308 static int NCR5380_dma_send_setup(struct NCR5380_hostdata *,
0309                                   unsigned char *, int);
0310 static int NCR5380_dma_recv_setup(struct NCR5380_hostdata *,
0311                                   unsigned char *, int);
0312 static int NCR5380_dma_residual(struct NCR5380_hostdata *);
0313
0314 static inline int NCR5380_dma_xfer_none(struct NCR5380_hostdata *hostdata,
0315                                         struct scsi_cmnd *cmd)
0316 {
0317     return 0;
0318 }
0319
0320 static inline int NCR5380_dma_setup_none(struct NCR5380_hostdata *hostdata,
0321                                          unsigned char *data, int count)
0322 {
0323     return 0;
0324 }
0325
0326 static inline int NCR5380_dma_residual_none(struct NCR5380_hostdata *hostdata)
0327 {
0328     return 0;
0329 }
0330
0331 #endif              /* NCR5380_H */