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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 
0003 /* Driver for 53c700 and 53c700-66 chips from NCR and Symbios
0004  *
0005  * Copyright (C) 2001 by James.Bottomley@HansenPartnership.com
0006  */
0007 
0008 #ifndef _53C700_H
0009 #define _53C700_H
0010 
0011 #include <linux/interrupt.h>
0012 #include <asm/io.h>
0013 
0014 #include <scsi/scsi_device.h>
0015 #include <scsi/scsi_cmnd.h>
0016 
0017 /* Turn on for general debugging---too verbose for normal use */
0018 #undef  NCR_700_DEBUG
0019 /* Debug the tag queues, checking hash queue allocation and deallocation
0020  * and search for duplicate tags */
0021 #undef NCR_700_TAG_DEBUG
0022 
0023 #ifdef NCR_700_DEBUG
0024 #define DEBUG(x)    printk x
0025 #define DDEBUG(prefix, sdev, fmt, a...) \
0026     sdev_printk(prefix, sdev, fmt, ##a)
0027 #define CDEBUG(prefix, scmd, fmt, a...) \
0028     scmd_printk(prefix, scmd, fmt, ##a)
0029 #else
0030 #define DEBUG(x)    do {} while (0)
0031 #define DDEBUG(prefix, scmd, fmt, a...) do {} while (0)
0032 #define CDEBUG(prefix, scmd, fmt, a...) do {} while (0)
0033 #endif
0034 
0035 /* The number of available command slots */
0036 #define NCR_700_COMMAND_SLOTS_PER_HOST  64
0037 /* The maximum number of Scatter Gathers we allow */
0038 #define NCR_700_SG_SEGMENTS     32
0039 /* The maximum number of luns (make this of the form 2^n) */
0040 #define NCR_700_MAX_LUNS        32
0041 #define NCR_700_LUN_MASK        (NCR_700_MAX_LUNS - 1)
0042 /* Maximum number of tags the driver ever allows per device */
0043 #define NCR_700_MAX_TAGS        16
0044 /* Tag depth the driver starts out with (can be altered in sysfs) */
0045 #define NCR_700_DEFAULT_TAGS        4
0046 /* This is the default number of commands per LUN in the untagged case.
0047  * two is a good value because it means we can have one command active and
0048  * one command fully prepared and waiting
0049  */
0050 #define NCR_700_CMD_PER_LUN     2
0051 /* magic byte identifying an internally generated REQUEST_SENSE command */
0052 #define NCR_700_INTERNAL_SENSE_MAGIC    0x42
0053 
0054 struct NCR_700_Host_Parameters;
0055 
0056 /* These are the externally used routines */
0057 struct Scsi_Host *NCR_700_detect(struct scsi_host_template *,
0058         struct NCR_700_Host_Parameters *, struct device *);
0059 int NCR_700_release(struct Scsi_Host *host);
0060 irqreturn_t NCR_700_intr(int, void *);
0061 
0062 
0063 enum NCR_700_Host_State {
0064     NCR_700_HOST_BUSY,
0065     NCR_700_HOST_FREE,
0066 };
0067 
0068 struct NCR_700_SG_List {
0069     /* The following is a script fragment to move the buffer onto the
0070      * bus and then link the next fragment or return */
0071     #define SCRIPT_MOVE_DATA_IN     0x09000000
0072     #define SCRIPT_MOVE_DATA_OUT        0x08000000
0073     __u32   ins;
0074     __u32   pAddr;
0075     #define SCRIPT_NOP          0x80000000
0076     #define SCRIPT_RETURN           0x90080000
0077 };
0078 
0079 struct NCR_700_Device_Parameters {
0080     /* space for creating a request sense command. Really, except
0081      * for the annoying SCSI-2 requirement for LUN information in
0082      * cmnd[1], this could be in static storage */
0083     unsigned char cmnd[MAX_COMMAND_SIZE];
0084     __u8    depth;
0085     struct scsi_cmnd *current_cmnd; /* currently active command */
0086 };
0087 
0088 
0089 /* The SYNC negotiation sequence looks like:
0090  * 
0091  * If DEV_NEGOTIATED_SYNC not set, tack and SDTR message on to the
0092  * initial identify for the device and set DEV_BEGIN_SYNC_NEGOTIATION
0093  * If we get an SDTR reply, work out the SXFER parameters, squirrel
0094  * them away here, clear DEV_BEGIN_SYNC_NEGOTIATION and set
0095  * DEV_NEGOTIATED_SYNC.  If we get a REJECT msg, squirrel
0096  *
0097  *
0098  * 0:7  SXFER_REG negotiated value for this device
0099  * 8:15 Current queue depth
0100  * 16   negotiated SYNC flag
0101  * 17 begin SYNC negotiation flag 
0102  * 18 device supports tag queueing */
0103 #define NCR_700_DEV_NEGOTIATED_SYNC (1<<16)
0104 #define NCR_700_DEV_BEGIN_SYNC_NEGOTIATION  (1<<17)
0105 #define NCR_700_DEV_PRINT_SYNC_NEGOTIATION (1<<19)
0106 
0107 static inline char *NCR_700_get_sense_cmnd(struct scsi_device *SDp)
0108 {
0109     struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
0110 
0111     return hostdata->cmnd;
0112 }
0113 
0114 static inline void
0115 NCR_700_set_depth(struct scsi_device *SDp, __u8 depth)
0116 {
0117     struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
0118 
0119     hostdata->depth = depth;
0120 }
0121 static inline __u8
0122 NCR_700_get_depth(struct scsi_device *SDp)
0123 {
0124     struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
0125 
0126     return hostdata->depth;
0127 }
0128 static inline int
0129 NCR_700_is_flag_set(struct scsi_device *SDp, __u32 flag)
0130 {
0131     return (spi_flags(SDp->sdev_target) & flag) == flag;
0132 }
0133 static inline int
0134 NCR_700_is_flag_clear(struct scsi_device *SDp, __u32 flag)
0135 {
0136     return (spi_flags(SDp->sdev_target) & flag) == 0;
0137 }
0138 static inline void
0139 NCR_700_set_flag(struct scsi_device *SDp, __u32 flag)
0140 {
0141     spi_flags(SDp->sdev_target) |= flag;
0142 }
0143 static inline void
0144 NCR_700_clear_flag(struct scsi_device *SDp, __u32 flag)
0145 {
0146     spi_flags(SDp->sdev_target) &= ~flag;
0147 }
0148 
0149 enum NCR_700_tag_neg_state {
0150     NCR_700_START_TAG_NEGOTIATION = 0,
0151     NCR_700_DURING_TAG_NEGOTIATION = 1,
0152     NCR_700_FINISHED_TAG_NEGOTIATION = 2,
0153 };
0154 
0155 static inline enum NCR_700_tag_neg_state
0156 NCR_700_get_tag_neg_state(struct scsi_device *SDp)
0157 {
0158     return (enum NCR_700_tag_neg_state)((spi_flags(SDp->sdev_target)>>20) & 0x3);
0159 }
0160 
0161 static inline void
0162 NCR_700_set_tag_neg_state(struct scsi_device *SDp,
0163               enum NCR_700_tag_neg_state state)
0164 {
0165     /* clear the slot */
0166     spi_flags(SDp->sdev_target) &= ~(0x3 << 20);
0167     spi_flags(SDp->sdev_target) |= ((__u32)state) << 20;
0168 }
0169 
0170 struct NCR_700_command_slot {
0171     struct NCR_700_SG_List  SG[NCR_700_SG_SEGMENTS+1];
0172     struct NCR_700_SG_List  *pSG;
0173     #define NCR_700_SLOT_MASK 0xFC
0174     #define NCR_700_SLOT_MAGIC 0xb8
0175     #define NCR_700_SLOT_FREE (0|NCR_700_SLOT_MAGIC) /* slot may be used */
0176     #define NCR_700_SLOT_BUSY (1|NCR_700_SLOT_MAGIC) /* slot has command active on HA */
0177     #define NCR_700_SLOT_QUEUED (2|NCR_700_SLOT_MAGIC) /* slot has command to be made active on HA */
0178     __u8    state;
0179     #define NCR_700_FLAG_AUTOSENSE  0x01
0180     __u8    flags;
0181     __u8    pad1[2];    /* Needed for m68k where min alignment is 2 bytes */
0182     int tag;
0183     __u32   resume_offset;
0184     struct scsi_cmnd *cmnd;
0185     /* The pci_mapped address of the actual command in cmnd */
0186     dma_addr_t  pCmd;
0187     __u32       temp;
0188     /* if this command is a pci_single mapping, holds the dma address
0189      * for later unmapping in the done routine */
0190     dma_addr_t  dma_handle;
0191     /* historical remnant, now used to link free commands */
0192     struct NCR_700_command_slot *ITL_forw;
0193 };
0194 
0195 struct NCR_700_Host_Parameters {
0196     /* These must be filled in by the calling driver */
0197     int clock;          /* board clock speed in MHz */
0198     void __iomem    *base;      /* the base for the port (copied to host) */
0199     struct device   *dev;
0200     __u32   dmode_extra;    /* adjustable bus settings */
0201     __u32   dcntl_extra;    /* adjustable bus settings */
0202     __u32   ctest7_extra;   /* adjustable bus settings */
0203     __u32   differential:1; /* if we are differential */
0204 #ifdef CONFIG_53C700_LE_ON_BE
0205     /* This option is for HP only.  Set it if your chip is wired for
0206      * little endian on this platform (which is big endian) */
0207     __u32   force_le_on_be:1;
0208 #endif
0209     __u32   chip710:1;  /* set if really a 710 not 700 */
0210     __u32   burst_length:4; /* set to 0 to disable 710 bursting */
0211     __u32   noncoherent:1;  /* needs to use non-coherent DMA */
0212 
0213     /* NOTHING BELOW HERE NEEDS ALTERING */
0214     __u32   fast:1;     /* if we can alter the SCSI bus clock
0215                                    speed (so can negiotiate sync) */
0216     int sync_clock; /* The speed of the SYNC core */
0217 
0218     __u32   *script;        /* pointer to script location */
0219     __u32   pScript;        /* physical mem addr of script */
0220 
0221     enum NCR_700_Host_State state; /* protected by state lock */
0222     struct scsi_cmnd *cmd;
0223     /* Note: pScript contains the single consistent block of
0224      * memory.  All the msgin, msgout and status are allocated in
0225      * this memory too (at separate cache lines).  TOTAL_MEM_SIZE
0226      * represents the total size of this area */
0227 #define MSG_ARRAY_SIZE  8
0228 #define MSGOUT_OFFSET   (L1_CACHE_ALIGN(sizeof(SCRIPT)))
0229     __u8    *msgout;
0230 #define MSGIN_OFFSET    (MSGOUT_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
0231     __u8    *msgin;
0232 #define STATUS_OFFSET   (MSGIN_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
0233     __u8    *status;
0234 #define SLOTS_OFFSET    (STATUS_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
0235     struct NCR_700_command_slot *slots;
0236 #define TOTAL_MEM_SIZE  (SLOTS_OFFSET + L1_CACHE_ALIGN(sizeof(struct NCR_700_command_slot) * NCR_700_COMMAND_SLOTS_PER_HOST))
0237     int saved_slot_position;
0238     int command_slot_count; /* protected by state lock */
0239     __u8    tag_negotiated;
0240     __u8    rev;
0241     __u8    reselection_id;
0242     __u8    min_period;
0243 
0244     /* Free list, singly linked by ITL_forw elements */
0245     struct NCR_700_command_slot *free_list;
0246     /* Completion for waited for ops, like reset, abort or
0247      * device reset.
0248      *
0249      * NOTE: relies on single threading in the error handler to
0250      * have only one outstanding at once */
0251     struct completion *eh_complete;
0252 };
0253 
0254 /*
0255  *  53C700 Register Interface - the offset from the Selected base
0256  *  I/O address */
0257 #ifdef CONFIG_53C700_LE_ON_BE
0258 #define bE  (hostdata->force_le_on_be ? 0 : 3)
0259 #define bSWAP   (hostdata->force_le_on_be)
0260 #define bEBus   (!hostdata->force_le_on_be)
0261 #elif defined(__BIG_ENDIAN)
0262 #define bE  3
0263 #define bSWAP   0
0264 #elif defined(__LITTLE_ENDIAN)
0265 #define bE  0
0266 #define bSWAP   0
0267 #else
0268 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined, did you include byteorder.h?"
0269 #endif
0270 #ifndef bEBus
0271 #ifdef CONFIG_53C700_BE_BUS
0272 #define bEBus   1
0273 #else
0274 #define bEBus   0
0275 #endif
0276 #endif
0277 #define bS_to_cpu(x)    (bSWAP ? le32_to_cpu(x) : (x))
0278 #define bS_to_host(x)   (bSWAP ? cpu_to_le32(x) : (x))
0279 
0280 /* NOTE: These registers are in the LE register space only, the required byte
0281  * swapping is done by the NCR_700_{read|write}[b] functions */
0282 #define SCNTL0_REG          0x00
0283 #define     FULL_ARBITRATION    0xc0
0284 #define     PARITY          0x08
0285 #define     ENABLE_PARITY       0x04
0286 #define     AUTO_ATN        0x02
0287 #define SCNTL1_REG          0x01
0288 #define     SLOW_BUS        0x80
0289 #define     ENABLE_SELECT       0x20
0290 #define     ASSERT_RST      0x08
0291 #define     ASSERT_EVEN_PARITY  0x04
0292 #define SDID_REG            0x02
0293 #define SIEN_REG            0x03
0294 #define     PHASE_MM_INT        0x80
0295 #define     FUNC_COMP_INT       0x40
0296 #define     SEL_TIMEOUT_INT     0x20
0297 #define     SELECT_INT      0x10
0298 #define     GROSS_ERR_INT       0x08
0299 #define     UX_DISC_INT     0x04
0300 #define     RST_INT         0x02
0301 #define     PAR_ERR_INT     0x01
0302 #define SCID_REG            0x04
0303 #define SXFER_REG           0x05
0304 #define     ASYNC_OPERATION     0x00
0305 #define SODL_REG                        0x06
0306 #define SOCL_REG            0x07
0307 #define SFBR_REG            0x08
0308 #define SIDL_REG            0x09
0309 #define SBDL_REG            0x0A
0310 #define SBCL_REG            0x0B
0311 /* read bits */
0312 #define     SBCL_IO         0x01
0313 /*write bits */
0314 #define     SYNC_DIV_AS_ASYNC   0x00
0315 #define     SYNC_DIV_1_0        0x01
0316 #define     SYNC_DIV_1_5        0x02
0317 #define     SYNC_DIV_2_0        0x03
0318 #define DSTAT_REG           0x0C
0319 #define     ILGL_INST_DETECTED  0x01
0320 #define     WATCH_DOG_INTERRUPT 0x02
0321 #define     SCRIPT_INT_RECEIVED 0x04
0322 #define     ABORTED         0x10
0323 #define SSTAT0_REG          0x0D
0324 #define     PARITY_ERROR        0x01
0325 #define     SCSI_RESET_DETECTED 0x02
0326 #define     UNEXPECTED_DISCONNECT   0x04
0327 #define     SCSI_GROSS_ERROR    0x08
0328 #define     SELECTED        0x10
0329 #define     SELECTION_TIMEOUT   0x20
0330 #define     FUNCTION_COMPLETE   0x40
0331 #define     PHASE_MISMATCH      0x80
0332 #define SSTAT1_REG          0x0E
0333 #define     SIDL_REG_FULL       0x80
0334 #define     SODR_REG_FULL       0x40
0335 #define     SODL_REG_FULL       0x20
0336 #define SSTAT2_REG                      0x0F
0337 #define CTEST0_REG                      0x14
0338 #define     BTB_TIMER_DISABLE   0x40
0339 #define CTEST1_REG                      0x15
0340 #define CTEST2_REG                      0x16
0341 #define CTEST3_REG                      0x17
0342 #define CTEST4_REG                      0x18
0343 #define         DISABLE_FIFO            0x00
0344 #define         SLBE                    0x10
0345 #define         SFWR                    0x08
0346 #define         BYTE_LANE0              0x04
0347 #define         BYTE_LANE1              0x05
0348 #define         BYTE_LANE2              0x06
0349 #define         BYTE_LANE3              0x07
0350 #define         SCSI_ZMODE              0x20
0351 #define         ZMODE                   0x40
0352 #define CTEST5_REG                      0x19
0353 #define         MASTER_CONTROL          0x10
0354 #define         DMA_DIRECTION           0x08
0355 #define CTEST7_REG                      0x1B
0356 #define     BURST_DISABLE       0x80 /* 710 only */
0357 #define     SEL_TIMEOUT_DISABLE 0x10 /* 710 only */
0358 #define         DFP                     0x08
0359 #define         EVP                     0x04
0360 #define         CTEST7_TT1              0x02
0361 #define     DIFF            0x01
0362 #define CTEST6_REG                      0x1A
0363 #define TEMP_REG            0x1C
0364 #define DFIFO_REG           0x20
0365 #define     FLUSH_DMA_FIFO      0x80
0366 #define     CLR_FIFO        0x40
0367 #define ISTAT_REG           0x21
0368 #define     ABORT_OPERATION     0x80
0369 #define     SOFTWARE_RESET_710  0x40
0370 #define     DMA_INT_PENDING     0x01
0371 #define     SCSI_INT_PENDING    0x02
0372 #define     CONNECTED       0x08
0373 #define CTEST8_REG                      0x22
0374 #define         LAST_DIS_ENBL           0x01
0375 #define     SHORTEN_FILTERING   0x04
0376 #define     ENABLE_ACTIVE_NEGATION  0x10
0377 #define     GENERATE_RECEIVE_PARITY 0x20
0378 #define     CLR_FIFO_710        0x04
0379 #define     FLUSH_DMA_FIFO_710  0x08
0380 #define CTEST9_REG                      0x23
0381 #define DBC_REG             0x24
0382 #define DCMD_REG            0x27
0383 #define DNAD_REG            0x28
0384 #define DIEN_REG            0x39
0385 #define     BUS_FAULT       0x20
0386 #define     ABORT_INT       0x10
0387 #define     INT_INST_INT        0x04
0388 #define     WD_INT          0x02
0389 #define     ILGL_INST_INT       0x01
0390 #define DCNTL_REG           0x3B
0391 #define     SOFTWARE_RESET      0x01
0392 #define     COMPAT_700_MODE     0x01
0393 #define     SCRPTS_16BITS       0x20
0394 #define     EA_710          0x20
0395 #define     ASYNC_DIV_2_0       0x00
0396 #define     ASYNC_DIV_1_5       0x40
0397 #define     ASYNC_DIV_1_0       0x80
0398 #define     ASYNC_DIV_3_0       0xc0
0399 #define DMODE_710_REG           0x38
0400 #define DMODE_700_REG           0x34
0401 #define     BURST_LENGTH_1      0x00
0402 #define     BURST_LENGTH_2      0x40
0403 #define     BURST_LENGTH_4      0x80
0404 #define     BURST_LENGTH_8      0xC0
0405 #define     DMODE_FC1       0x10
0406 #define     DMODE_FC2       0x20
0407 #define     BW16            32 
0408 #define     MODE_286        16
0409 #define     IO_XFER         8
0410 #define     FIXED_ADDR      4
0411 
0412 #define DSP_REG                         0x2C
0413 #define DSPS_REG                        0x30
0414 
0415 /* Parameters to begin SDTR negotiations.  Empirically, I find that
0416  * the 53c700-66 cannot handle an offset >8, so don't change this  */
0417 #define NCR_700_MAX_OFFSET  8
0418 /* Was hoping the max offset would be greater for the 710, but
0419  * empirically it seems to be 8 also */
0420 #define NCR_710_MAX_OFFSET  8
0421 #define NCR_700_MIN_XFERP   1
0422 #define NCR_710_MIN_XFERP   0
0423 #define NCR_700_MIN_PERIOD  25 /* for SDTR message, 100ns */
0424 
0425 #define script_patch_32(h, script, symbol, value) \
0426 { \
0427     int i; \
0428     dma_addr_t da = value; \
0429     for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
0430         __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]) + da; \
0431         (script)[A_##symbol##_used[i]] = bS_to_host(val); \
0432         dma_sync_to_dev((h), &(script)[A_##symbol##_used[i]], 4); \
0433         DEBUG((" script, patching %s at %d to %pad\n", \
0434                #symbol, A_##symbol##_used[i], &da)); \
0435     } \
0436 }
0437 
0438 #define script_patch_32_abs(h, script, symbol, value) \
0439 { \
0440     int i; \
0441     dma_addr_t da = value; \
0442     for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
0443         (script)[A_##symbol##_used[i]] = bS_to_host(da); \
0444         dma_sync_to_dev((h), &(script)[A_##symbol##_used[i]], 4); \
0445         DEBUG((" script, patching %s at %d to %pad\n", \
0446                #symbol, A_##symbol##_used[i], &da)); \
0447     } \
0448 }
0449 
0450 /* Used for patching the SCSI ID in the SELECT instruction */
0451 #define script_patch_ID(h, script, symbol, value) \
0452 { \
0453     int i; \
0454     for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
0455         __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
0456         val &= 0xff00ffff; \
0457         val |= ((value) & 0xff) << 16; \
0458         (script)[A_##symbol##_used[i]] = bS_to_host(val); \
0459         dma_sync_to_dev((h), &(script)[A_##symbol##_used[i]], 4); \
0460         DEBUG((" script, patching ID field %s at %d to 0x%x\n", \
0461                #symbol, A_##symbol##_used[i], val)); \
0462     } \
0463 }
0464 
0465 #define script_patch_16(h, script, symbol, value) \
0466 { \
0467     int i; \
0468     for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
0469         __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
0470         val &= 0xffff0000; \
0471         val |= ((value) & 0xffff); \
0472         (script)[A_##symbol##_used[i]] = bS_to_host(val); \
0473         dma_sync_to_dev((h), &(script)[A_##symbol##_used[i]], 4); \
0474         DEBUG((" script, patching short field %s at %d to 0x%x\n", \
0475                #symbol, A_##symbol##_used[i], val)); \
0476     } \
0477 }
0478 
0479 
0480 static inline __u8
0481 NCR_700_readb(struct Scsi_Host *host, __u32 reg)
0482 {
0483     const struct NCR_700_Host_Parameters *hostdata
0484         = (struct NCR_700_Host_Parameters *)host->hostdata[0];
0485 
0486     return ioread8(hostdata->base + (reg^bE));
0487 }
0488 
0489 static inline __u32
0490 NCR_700_readl(struct Scsi_Host *host, __u32 reg)
0491 {
0492     const struct NCR_700_Host_Parameters *hostdata
0493         = (struct NCR_700_Host_Parameters *)host->hostdata[0];
0494     __u32 value = bEBus ? ioread32be(hostdata->base + reg) :
0495         ioread32(hostdata->base + reg);
0496 #if 1
0497     /* sanity check the register */
0498     BUG_ON((reg & 0x3) != 0);
0499 #endif
0500 
0501     return value;
0502 }
0503 
0504 static inline void
0505 NCR_700_writeb(__u8 value, struct Scsi_Host *host, __u32 reg)
0506 {
0507     const struct NCR_700_Host_Parameters *hostdata
0508         = (struct NCR_700_Host_Parameters *)host->hostdata[0];
0509 
0510     iowrite8(value, hostdata->base + (reg^bE));
0511 }
0512 
0513 static inline void
0514 NCR_700_writel(__u32 value, struct Scsi_Host *host, __u32 reg)
0515 {
0516     const struct NCR_700_Host_Parameters *hostdata
0517         = (struct NCR_700_Host_Parameters *)host->hostdata[0];
0518 
0519 #if 1
0520     /* sanity check the register */
0521     BUG_ON((reg & 0x3) != 0);
0522 #endif
0523 
0524     bEBus ? iowrite32be(value, hostdata->base + reg): 
0525         iowrite32(value, hostdata->base + reg);
0526 }
0527 
0528 #endif
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