drivers/scsi/3w-xxxx.h

0001 /*
0002    3w-xxxx.h -- 3ware Storage Controller device driver for Linux.
0003
0004    Written By: Adam Radford <aradford@gmail.com>
0005    Modifications By: Joel Jacobson <linux@3ware.com>
0006                      Arnaldo Carvalho de Melo <acme@conectiva.com.br>
0007                      Brad Strand <linux@3ware.com>
0008
0009    Copyright (C) 1999-2010 3ware Inc.
0010
0011    Kernel compatibility By: Andre Hedrick <andre@suse.com>
0012    Non-Copyright (C) 2000   Andre Hedrick <andre@suse.com>
0013
0014    This program is free software; you can redistribute it and/or modify
0015    it under the terms of the GNU General Public License as published by
0016    the Free Software Foundation; version 2 of the License.
0017
0018    This program is distributed in the hope that it will be useful,
0019    but WITHOUT ANY WARRANTY; without even the implied warranty of
0020    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
0021    GNU General Public License for more details.
0022
0023    NO WARRANTY
0024    THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
0025    CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
0026    LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
0027    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
0028    solely responsible for determining the appropriateness of using and
0029    distributing the Program and assumes all risks associated with its
0030    exercise of rights under this Agreement, including but not limited to
0031    the risks and costs of program errors, damage to or loss of data,
0032    programs or equipment, and unavailability or interruption of operations.
0033
0034    DISCLAIMER OF LIABILITY
0035    NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
0036    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0037    DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
0038    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
0039    TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
0040    USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
0041    HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
0042
0043    You should have received a copy of the GNU General Public License
0044    along with this program; if not, write to the Free Software
0045    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
0046
0047    Bugs/Comments/Suggestions should be mailed to:
0048
0049    aradford@gmail.com
0050
0051    For more information, goto:
0052    http://www.lsi.com
0053 */
0054
0055 #ifndef _3W_XXXX_H
0056 #define _3W_XXXX_H
0057
0058 #include <linux/types.h>
0059
0060 /* AEN strings */
0061 static char *tw_aen_string[] = {
0062     [0x000] = "INFO: AEN queue empty",
0063     [0x001] = "INFO: Soft reset occurred",
0064     [0x002] = "ERROR: Unit degraded: Unit #",
0065     [0x003] = "ERROR: Controller error",
0066     [0x004] = "ERROR: Rebuild failed: Unit #",
0067     [0x005] = "INFO: Rebuild complete: Unit #",
0068     [0x006] = "ERROR: Incomplete unit detected: Unit #",
0069     [0x007] = "INFO: Initialization complete: Unit #",
0070     [0x008] = "WARNING: Unclean shutdown detected: Unit #",
0071     [0x009] = "WARNING: ATA port timeout: Port #",
0072     [0x00A] = "ERROR: Drive error: Port #",
0073     [0x00B] = "INFO: Rebuild started: Unit #",
0074     [0x00C] = "INFO: Initialization started: Unit #",
0075     [0x00D] = "ERROR: Logical unit deleted: Unit #",
0076     [0x00F] = "WARNING: SMART threshold exceeded: Port #",
0077     [0x021] = "WARNING: ATA UDMA downgrade: Port #",
0078     [0x022] = "WARNING: ATA UDMA upgrade: Port #",
0079     [0x023] = "WARNING: Sector repair occurred: Port #",
0080     [0x024] = "ERROR: SBUF integrity check failure",
0081     [0x025] = "ERROR: Lost cached write: Port #",
0082     [0x026] = "ERROR: Drive ECC error detected: Port #",
0083     [0x027] = "ERROR: DCB checksum error: Port #",
0084     [0x028] = "ERROR: DCB unsupported version: Port #",
0085     [0x029] = "INFO: Verify started: Unit #",
0086     [0x02A] = "ERROR: Verify failed: Port #",
0087     [0x02B] = "INFO: Verify complete: Unit #",
0088     [0x02C] = "WARNING: Overwrote bad sector during rebuild: Port #",
0089     [0x02D] = "ERROR: Encountered bad sector during rebuild: Port #",
0090     [0x02E] = "ERROR: Replacement drive is too small: Port #",
0091     [0x02F] = "WARNING: Verify error: Unit not previously initialized: Unit #",
0092     [0x030] = "ERROR: Drive not supported: Port #"
0093 };
0094
0095 /*
0096    Sense key lookup table
0097    Format: ESDC/flags,SenseKey,AdditionalSenseCode,AdditionalSenseCodeQualifier
0098 */
0099 static unsigned char tw_sense_table[][4] =
0100 {
0101   /* Codes for newer firmware */
0102     // ATA Error                    SCSI Error
0103     {0x01, 0x03, 0x13, 0x00}, // Address mark not found       Address mark not found for data field
0104     {0x04, 0x0b, 0x00, 0x00}, // Aborted command              Aborted command
0105     {0x10, 0x0b, 0x14, 0x00}, // ID not found                 Recorded entity not found
0106     {0x40, 0x03, 0x11, 0x00}, // Uncorrectable ECC error      Unrecovered read error
0107     {0x61, 0x04, 0x00, 0x00}, // Device fault                 Hardware error
0108     {0x84, 0x0b, 0x47, 0x00}, // Data CRC error               SCSI parity error
0109     {0xd0, 0x0b, 0x00, 0x00}, // Device busy                  Aborted command
0110     {0xd1, 0x0b, 0x00, 0x00}, // Device busy                  Aborted command
0111     {0x37, 0x02, 0x04, 0x00}, // Unit offline                 Not ready
0112     {0x09, 0x02, 0x04, 0x00}, // Unrecovered disk error       Not ready
0113
0114     /* Codes for older firmware */
0115     // 3ware Error                  SCSI Error
0116     {0x51, 0x0b, 0x00, 0x00}  // Unspecified                  Aborted command
0117 };
0118
0119 /* Control register bit definitions */
0120 #define TW_CONTROL_CLEAR_HOST_INTERRUPT        0x00080000
0121 #define TW_CONTROL_CLEAR_ATTENTION_INTERRUPT   0x00040000
0122 #define TW_CONTROL_MASK_COMMAND_INTERRUPT      0x00020000
0123 #define TW_CONTROL_MASK_RESPONSE_INTERRUPT     0x00010000
0124 #define TW_CONTROL_UNMASK_COMMAND_INTERRUPT    0x00008000
0125 #define TW_CONTROL_UNMASK_RESPONSE_INTERRUPT   0x00004000
0126 #define TW_CONTROL_CLEAR_ERROR_STATUS          0x00000200
0127 #define TW_CONTROL_ISSUE_SOFT_RESET        0x00000100
0128 #define TW_CONTROL_ENABLE_INTERRUPTS           0x00000080
0129 #define TW_CONTROL_DISABLE_INTERRUPTS          0x00000040
0130 #define TW_CONTROL_ISSUE_HOST_INTERRUPT        0x00000020
0131 #define TW_CONTROL_CLEAR_PARITY_ERROR          0x00800000
0132 #define TW_CONTROL_CLEAR_QUEUE_ERROR           0x00400000
0133 #define TW_CONTROL_CLEAR_PCI_ABORT         0x00100000
0134 #define TW_CONTROL_CLEAR_SBUF_WRITE_ERROR      0x00000008
0135
0136 /* Status register bit definitions */
0137 #define TW_STATUS_MAJOR_VERSION_MASK           0xF0000000
0138 #define TW_STATUS_MINOR_VERSION_MASK           0x0F000000
0139 #define TW_STATUS_PCI_PARITY_ERROR         0x00800000
0140 #define TW_STATUS_QUEUE_ERROR              0x00400000
0141 #define TW_STATUS_MICROCONTROLLER_ERROR        0x00200000
0142 #define TW_STATUS_PCI_ABORT            0x00100000
0143 #define TW_STATUS_HOST_INTERRUPT           0x00080000
0144 #define TW_STATUS_ATTENTION_INTERRUPT          0x00040000
0145 #define TW_STATUS_COMMAND_INTERRUPT        0x00020000
0146 #define TW_STATUS_RESPONSE_INTERRUPT           0x00010000
0147 #define TW_STATUS_COMMAND_QUEUE_FULL           0x00008000
0148 #define TW_STATUS_RESPONSE_QUEUE_EMPTY         0x00004000
0149 #define TW_STATUS_MICROCONTROLLER_READY        0x00002000
0150 #define TW_STATUS_COMMAND_QUEUE_EMPTY          0x00001000
0151 #define TW_STATUS_ALL_INTERRUPTS           0x000F0000
0152 #define TW_STATUS_CLEARABLE_BITS           0x00D00000
0153 #define TW_STATUS_EXPECTED_BITS            0x00002000
0154 #define TW_STATUS_UNEXPECTED_BITS          0x00F00008
0155 #define TW_STATUS_SBUF_WRITE_ERROR         0x00000008
0156 #define TW_STATUS_VALID_INTERRUPT          0x00DF0008
0157
0158 /* RESPONSE QUEUE BIT DEFINITIONS */
0159 #define TW_RESPONSE_ID_MASK            0x00000FF0
0160
0161 /* PCI related defines */
0162 #define TW_IO_ADDRESS_RANGE            0x10
0163 #define TW_DEVICE_NAME                 "3ware Storage Controller"
0164 #define TW_VENDOR_ID (0x13C1)   /* 3ware */
0165 #define TW_DEVICE_ID (0x1000)   /* Storage Controller */
0166 #define TW_DEVICE_ID2 (0x1001)  /* 7000 series controller */
0167 #define TW_NUMDEVICES 2
0168 #define TW_PCI_CLEAR_PARITY_ERRORS 0xc100
0169 #define TW_PCI_CLEAR_PCI_ABORT     0x2000
0170
0171 /* Command packet opcodes */
0172 #define TW_OP_NOP         0x0
0173 #define TW_OP_INIT_CONNECTION 0x1
0174 #define TW_OP_READ        0x2
0175 #define TW_OP_WRITE       0x3
0176 #define TW_OP_VERIFY          0x4
0177 #define TW_OP_GET_PARAM       0x12
0178 #define TW_OP_SET_PARAM       0x13
0179 #define TW_OP_SECTOR_INFO     0x1a
0180 #define TW_OP_AEN_LISTEN      0x1c
0181 #define TW_OP_FLUSH_CACHE     0x0e
0182 #define TW_CMD_PACKET         0x1d
0183 #define TW_CMD_PACKET_WITH_DATA 0x1f
0184
0185 /* Asynchronous Event Notification (AEN) Codes */
0186 #define TW_AEN_QUEUE_EMPTY       0x0000
0187 #define TW_AEN_SOFT_RESET    0x0001
0188 #define TW_AEN_DEGRADED_MIRROR   0x0002
0189 #define TW_AEN_CONTROLLER_ERROR  0x0003
0190 #define TW_AEN_REBUILD_FAIL      0x0004
0191 #define TW_AEN_REBUILD_DONE      0x0005
0192 #define TW_AEN_QUEUE_FULL    0x00ff
0193 #define TW_AEN_TABLE_UNDEFINED   0x15
0194 #define TW_AEN_APORT_TIMEOUT     0x0009
0195 #define TW_AEN_DRIVE_ERROR       0x000A
0196 #define TW_AEN_SMART_FAIL    0x000F
0197 #define TW_AEN_SBUF_FAIL     0x0024
0198
0199 /* Misc defines */
0200 #define TW_ALIGNMENT_6000             64 /* 64 bytes */
0201 #define TW_ALIGNMENT_7000             4  /* 4 bytes */
0202 #define TW_MAX_UNITS                  16
0203 #define TW_COMMAND_ALIGNMENT_MASK         0x1ff
0204 #define TW_INIT_MESSAGE_CREDITS           0x100
0205 #define TW_INIT_COMMAND_PACKET_SIZE       0x3
0206 #define TW_POLL_MAX_RETRIES           20000
0207 #define TW_MAX_SGL_LENGTH             62
0208 #define TW_ATA_PASS_SGL_MAX           60
0209 #define TW_Q_LENGTH               256
0210 #define TW_Q_START                0
0211 #define TW_MAX_SLOT               32
0212 #define TW_MAX_PCI_BUSES              255
0213 #define TW_MAX_RESET_TRIES            3
0214 #define TW_UNIT_INFORMATION_TABLE_BASE        0x300
0215 #define TW_MAX_CMDS_PER_LUN           254 /* 254 for io, 1 for
0216                                                      chrdev ioctl, one for
0217                                                      internal aen post */
0218 #define TW_BLOCK_SIZE                 0x200 /* 512-byte blocks */
0219 #define TW_IOCTL                  0x80
0220 #define TW_UNIT_ONLINE                1
0221 #define TW_IN_INTR                1
0222 #define TW_IN_RESET               2
0223 #define TW_IN_CHRDEV_IOCTL            3
0224 #define TW_MAX_SECTORS                256
0225 #define TW_MAX_IOCTL_SECTORS              512
0226 #define TW_AEN_WAIT_TIME              1000
0227 #define TW_IOCTL_WAIT_TIME            (1 * HZ) /* 1 second */
0228 #define TW_ISR_DONT_COMPLETE              2
0229 #define TW_ISR_DONT_RESULT            3
0230 #define TW_IOCTL_TIMEOUT              25 /* 25 seconds */
0231 #define TW_IOCTL_CHRDEV_TIMEOUT           60 /* 60 seconds */
0232 #define TW_IOCTL_CHRDEV_FREE              -1
0233 #define TW_MAX_CDB_LEN                16
0234
0235 /* Bitmask macros to eliminate bitfields */
0236
0237 /* opcode: 5, sgloffset: 3 */
0238 #define TW_OPSGL_IN(x,y) ((x << 5) | (y & 0x1f))
0239 #define TW_SGL_OUT(x) ((x >> 5) & 0x7)
0240
0241 /* reserved_1: 4, response_id: 8, reserved_2: 20 */
0242 #define TW_RESID_OUT(x) ((x >> 4) & 0xff)
0243
0244 /* unit: 4, host_id: 4 */
0245 #define TW_UNITHOST_IN(x,y) ((x << 4) | ( y & 0xf))
0246 #define TW_UNIT_OUT(x) (x & 0xf)
0247
0248 /* Macros */
0249 #define TW_CONTROL_REG_ADDR(x) (x->base_addr)
0250 #define TW_STATUS_REG_ADDR(x) (x->base_addr + 0x4)
0251 #define TW_COMMAND_QUEUE_REG_ADDR(x) (x->base_addr + 0x8)
0252 #define TW_RESPONSE_QUEUE_REG_ADDR(x) (x->base_addr + 0xC)
0253 #define TW_CLEAR_ALL_INTERRUPTS(x)                  \
0254     (outl(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
0255 #define TW_CLEAR_ATTENTION_INTERRUPT(x)                 \
0256     (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
0257 #define TW_CLEAR_HOST_INTERRUPT(x)                  \
0258     (outl(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
0259 #define TW_DISABLE_INTERRUPTS(x)                    \
0260     (outl(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
0261 #define TW_ENABLE_AND_CLEAR_INTERRUPTS(x)               \
0262     (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT |            \
0263           TW_CONTROL_UNMASK_RESPONSE_INTERRUPT |            \
0264           TW_CONTROL_ENABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
0265 #define TW_MASK_COMMAND_INTERRUPT(x)                    \
0266     (outl(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
0267 #define TW_UNMASK_COMMAND_INTERRUPT(x)                  \
0268     (outl(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
0269 #define TW_SOFT_RESET(x) (outl(TW_CONTROL_ISSUE_SOFT_RESET |        \
0270                    TW_CONTROL_CLEAR_HOST_INTERRUPT |    \
0271                    TW_CONTROL_CLEAR_ATTENTION_INTERRUPT |   \
0272                    TW_CONTROL_MASK_COMMAND_INTERRUPT |  \
0273                    TW_CONTROL_MASK_RESPONSE_INTERRUPT | \
0274                    TW_CONTROL_CLEAR_ERROR_STATUS |      \
0275                    TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
0276 #define TW_STATUS_ERRORS(x)             \
0277     (((x & TW_STATUS_PCI_ABORT) ||          \
0278       (x & TW_STATUS_PCI_PARITY_ERROR) ||       \
0279       (x & TW_STATUS_QUEUE_ERROR) ||        \
0280       (x & TW_STATUS_MICROCONTROLLER_ERROR)) && \
0281      (x & TW_STATUS_MICROCONTROLLER_READY))
0282
0283 #ifdef TW_DEBUG
0284 #define dprintk(msg...) printk(msg)
0285 #else
0286 #define dprintk(msg...) do { } while(0)
0287 #endif
0288
0289 #pragma pack(1)
0290
0291 /* Scatter Gather List Entry */
0292 typedef struct TAG_TW_SG_Entry {
0293     u32 address;
0294     u32 length;
0295 } TW_SG_Entry;
0296
0297 typedef unsigned char TW_Sector[512];
0298
0299 /* Command Packet */
0300 typedef struct TW_Command {
0301     unsigned char opcode__sgloffset;
0302     unsigned char size;
0303     unsigned char request_id;
0304     unsigned char unit__hostid;
0305     /* Second DWORD */
0306     unsigned char status;
0307     unsigned char flags;
0308     union {
0309         unsigned short block_count;
0310         unsigned short parameter_count;
0311         unsigned short message_credits;
0312     } byte6;
0313     union {
0314         struct {
0315             u32 lba;
0316             TW_SG_Entry sgl[TW_MAX_SGL_LENGTH];
0317             u32 padding;    /* pad to 512 bytes */
0318         } io;
0319         struct {
0320             TW_SG_Entry sgl[TW_MAX_SGL_LENGTH];
0321             u32 padding[2];
0322         } param;
0323         struct {
0324             u32 response_queue_pointer;
0325             u32 padding[125];
0326         } init_connection;
0327         struct {
0328             char version[504];
0329         } ioctl_miniport_version;
0330     } byte8;
0331 } TW_Command;
0332
0333 #pragma pack()
0334
0335 typedef struct TAG_TW_Ioctl {
0336     unsigned char opcode;
0337     unsigned short table_id;
0338     unsigned char parameter_id;
0339     unsigned char parameter_size_bytes;
0340     unsigned char unit_index;
0341     unsigned char data[1];
0342 } TW_Ioctl;
0343
0344 #pragma pack(1)
0345
0346 /* Structure for new chardev ioctls */
0347 typedef struct TAG_TW_New_Ioctl {
0348     unsigned int data_buffer_length;
0349     unsigned char padding [508];
0350     TW_Command firmware_command;
0351     char data_buffer[1];
0352 } TW_New_Ioctl;
0353
0354 /* GetParam descriptor */
0355 typedef struct {
0356     unsigned short  table_id;
0357     unsigned char   parameter_id;
0358     unsigned char   parameter_size_bytes;
0359     unsigned char   data[1];
0360 } TW_Param, *PTW_Param;
0361
0362 /* Response queue */
0363 typedef union TAG_TW_Response_Queue {
0364     u32 response_id;
0365     u32 value;
0366 } TW_Response_Queue;
0367
0368 typedef int TW_Cmd_State;
0369
0370 #define TW_S_INITIAL   0x1  /* Initial state */
0371 #define TW_S_STARTED   0x2  /* Id in use */
0372 #define TW_S_POSTED    0x4  /* Posted to the controller */
0373 #define TW_S_PENDING   0x8  /* Waiting to be posted in isr */
0374 #define TW_S_COMPLETED 0x10 /* Completed by isr */
0375 #define TW_S_FINISHED  0x20 /* I/O completely done */
0376 #define TW_START_MASK (TW_S_STARTED | TW_S_POSTED | TW_S_PENDING | TW_S_COMPLETED)
0377
0378 /* Command header for ATA pass-thru */
0379 typedef struct TAG_TW_Passthru
0380 {
0381     unsigned char opcode__sgloffset;
0382     unsigned char size;
0383     unsigned char request_id;
0384     unsigned char aport__hostid;
0385     unsigned char status;
0386     unsigned char flags;
0387     unsigned short param;
0388     unsigned short features;
0389     unsigned short sector_count;
0390     unsigned short sector_num;
0391     unsigned short cylinder_lo;
0392     unsigned short cylinder_hi;
0393     unsigned char drive_head;
0394     unsigned char command;
0395     TW_SG_Entry sg_list[TW_ATA_PASS_SGL_MAX];
0396     unsigned char padding[12];
0397 } TW_Passthru;
0398
0399 #pragma pack()
0400
0401 typedef struct TAG_TW_Device_Extension {
0402     u32         base_addr;
0403     unsigned long       *alignment_virtual_address[TW_Q_LENGTH];
0404     unsigned long       alignment_physical_address[TW_Q_LENGTH];
0405     int         is_unit_present[TW_MAX_UNITS];
0406     unsigned long       *command_packet_virtual_address[TW_Q_LENGTH];
0407     unsigned long       command_packet_physical_address[TW_Q_LENGTH];
0408     struct pci_dev      *tw_pci_dev;
0409     struct scsi_cmnd    *srb[TW_Q_LENGTH];
0410     unsigned char       free_queue[TW_Q_LENGTH];
0411     unsigned char       free_head;
0412     unsigned char       free_tail;
0413     unsigned char       pending_queue[TW_Q_LENGTH];
0414     unsigned char       pending_head;
0415     unsigned char       pending_tail;
0416     TW_Cmd_State        state[TW_Q_LENGTH];
0417     u32         posted_request_count;
0418     u32         max_posted_request_count;
0419     u32         request_count_marked_pending;
0420     u32         pending_request_count;
0421     u32         max_pending_request_count;
0422     u32         max_sgl_entries;
0423     u32         sgl_entries;
0424     u32         num_resets;
0425     u32         sector_count;
0426     u32         max_sector_count;
0427     u32         aen_count;
0428     struct Scsi_Host    *host;
0429     struct mutex        ioctl_lock;
0430     unsigned short      aen_queue[TW_Q_LENGTH];
0431     unsigned char       aen_head;
0432     unsigned char       aen_tail;
0433     volatile long       flags; /* long req'd for set_bit --RR */
0434     int         reset_print;
0435     volatile int        chrdev_request_id;
0436     wait_queue_head_t   ioctl_wqueue;
0437 } TW_Device_Extension;
0438
0439 #endif /* _3W_XXXX_H */