0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011 #undef DEBUG
0012 #undef DEBUGDATA
0013 #undef DEBUGCCW
0014
0015 #define KMSG_COMPONENT "ctcm"
0016 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
0017
0018 #include <linux/module.h>
0019 #include <linux/init.h>
0020 #include <linux/kernel.h>
0021 #include <linux/slab.h>
0022 #include <linux/errno.h>
0023 #include <linux/types.h>
0024 #include <linux/interrupt.h>
0025 #include <linux/timer.h>
0026 #include <linux/bitops.h>
0027
0028 #include <linux/signal.h>
0029 #include <linux/string.h>
0030
0031 #include <linux/ip.h>
0032 #include <linux/if_arp.h>
0033 #include <linux/tcp.h>
0034 #include <linux/skbuff.h>
0035 #include <linux/ctype.h>
0036 #include <net/dst.h>
0037
0038 #include <linux/io.h>
0039 #include <asm/ccwdev.h>
0040 #include <asm/ccwgroup.h>
0041 #include <linux/uaccess.h>
0042
0043 #include <asm/idals.h>
0044
0045 #include "fsm.h"
0046
0047 #include "ctcm_dbug.h"
0048 #include "ctcm_main.h"
0049 #include "ctcm_fsms.h"
0050
0051 const char *dev_state_names[] = {
0052 [DEV_STATE_STOPPED] = "Stopped",
0053 [DEV_STATE_STARTWAIT_RXTX] = "StartWait RXTX",
0054 [DEV_STATE_STARTWAIT_RX] = "StartWait RX",
0055 [DEV_STATE_STARTWAIT_TX] = "StartWait TX",
0056 [DEV_STATE_STOPWAIT_RXTX] = "StopWait RXTX",
0057 [DEV_STATE_STOPWAIT_RX] = "StopWait RX",
0058 [DEV_STATE_STOPWAIT_TX] = "StopWait TX",
0059 [DEV_STATE_RUNNING] = "Running",
0060 };
0061
0062 const char *dev_event_names[] = {
0063 [DEV_EVENT_START] = "Start",
0064 [DEV_EVENT_STOP] = "Stop",
0065 [DEV_EVENT_RXUP] = "RX up",
0066 [DEV_EVENT_TXUP] = "TX up",
0067 [DEV_EVENT_RXDOWN] = "RX down",
0068 [DEV_EVENT_TXDOWN] = "TX down",
0069 [DEV_EVENT_RESTART] = "Restart",
0070 };
0071
0072 const char *ctc_ch_event_names[] = {
0073 [CTC_EVENT_IO_SUCCESS] = "ccw_device success",
0074 [CTC_EVENT_IO_EBUSY] = "ccw_device busy",
0075 [CTC_EVENT_IO_ENODEV] = "ccw_device enodev",
0076 [CTC_EVENT_IO_UNKNOWN] = "ccw_device unknown",
0077 [CTC_EVENT_ATTNBUSY] = "Status ATTN & BUSY",
0078 [CTC_EVENT_ATTN] = "Status ATTN",
0079 [CTC_EVENT_BUSY] = "Status BUSY",
0080 [CTC_EVENT_UC_RCRESET] = "Unit check remote reset",
0081 [CTC_EVENT_UC_RSRESET] = "Unit check remote system reset",
0082 [CTC_EVENT_UC_TXTIMEOUT] = "Unit check TX timeout",
0083 [CTC_EVENT_UC_TXPARITY] = "Unit check TX parity",
0084 [CTC_EVENT_UC_HWFAIL] = "Unit check Hardware failure",
0085 [CTC_EVENT_UC_RXPARITY] = "Unit check RX parity",
0086 [CTC_EVENT_UC_ZERO] = "Unit check ZERO",
0087 [CTC_EVENT_UC_UNKNOWN] = "Unit check Unknown",
0088 [CTC_EVENT_SC_UNKNOWN] = "SubChannel check Unknown",
0089 [CTC_EVENT_MC_FAIL] = "Machine check failure",
0090 [CTC_EVENT_MC_GOOD] = "Machine check operational",
0091 [CTC_EVENT_IRQ] = "IRQ normal",
0092 [CTC_EVENT_FINSTAT] = "IRQ final",
0093 [CTC_EVENT_TIMER] = "Timer",
0094 [CTC_EVENT_START] = "Start",
0095 [CTC_EVENT_STOP] = "Stop",
0096
0097
0098
0099 [CTC_EVENT_SEND_XID] = "XID Exchange",
0100 [CTC_EVENT_RSWEEP_TIMER] = "MPC Group Sweep Timer",
0101 };
0102
0103 const char *ctc_ch_state_names[] = {
0104 [CTC_STATE_IDLE] = "Idle",
0105 [CTC_STATE_STOPPED] = "Stopped",
0106 [CTC_STATE_STARTWAIT] = "StartWait",
0107 [CTC_STATE_STARTRETRY] = "StartRetry",
0108 [CTC_STATE_SETUPWAIT] = "SetupWait",
0109 [CTC_STATE_RXINIT] = "RX init",
0110 [CTC_STATE_TXINIT] = "TX init",
0111 [CTC_STATE_RX] = "RX",
0112 [CTC_STATE_TX] = "TX",
0113 [CTC_STATE_RXIDLE] = "RX idle",
0114 [CTC_STATE_TXIDLE] = "TX idle",
0115 [CTC_STATE_RXERR] = "RX error",
0116 [CTC_STATE_TXERR] = "TX error",
0117 [CTC_STATE_TERM] = "Terminating",
0118 [CTC_STATE_DTERM] = "Restarting",
0119 [CTC_STATE_NOTOP] = "Not operational",
0120
0121
0122
0123 [CH_XID0_PENDING] = "Pending XID0 Start",
0124 [CH_XID0_INPROGRESS] = "In XID0 Negotiations ",
0125 [CH_XID7_PENDING] = "Pending XID7 P1 Start",
0126 [CH_XID7_PENDING1] = "Active XID7 P1 Exchange ",
0127 [CH_XID7_PENDING2] = "Pending XID7 P2 Start ",
0128 [CH_XID7_PENDING3] = "Active XID7 P2 Exchange ",
0129 [CH_XID7_PENDING4] = "XID7 Complete - Pending READY ",
0130 };
0131
0132 static void ctcm_action_nop(fsm_instance *fi, int event, void *arg);
0133
0134
0135
0136
0137
0138 static void chx_txdone(fsm_instance *fi, int event, void *arg);
0139 static void chx_rx(fsm_instance *fi, int event, void *arg);
0140 static void chx_rxidle(fsm_instance *fi, int event, void *arg);
0141 static void chx_firstio(fsm_instance *fi, int event, void *arg);
0142 static void ctcm_chx_setmode(fsm_instance *fi, int event, void *arg);
0143 static void ctcm_chx_start(fsm_instance *fi, int event, void *arg);
0144 static void ctcm_chx_haltio(fsm_instance *fi, int event, void *arg);
0145 static void ctcm_chx_stopped(fsm_instance *fi, int event, void *arg);
0146 static void ctcm_chx_stop(fsm_instance *fi, int event, void *arg);
0147 static void ctcm_chx_fail(fsm_instance *fi, int event, void *arg);
0148 static void ctcm_chx_setuperr(fsm_instance *fi, int event, void *arg);
0149 static void ctcm_chx_restart(fsm_instance *fi, int event, void *arg);
0150 static void ctcm_chx_rxiniterr(fsm_instance *fi, int event, void *arg);
0151 static void ctcm_chx_rxinitfail(fsm_instance *fi, int event, void *arg);
0152 static void ctcm_chx_rxdisc(fsm_instance *fi, int event, void *arg);
0153 static void ctcm_chx_txiniterr(fsm_instance *fi, int event, void *arg);
0154 static void ctcm_chx_txretry(fsm_instance *fi, int event, void *arg);
0155 static void ctcm_chx_iofatal(fsm_instance *fi, int event, void *arg);
0156
0157
0158
0159
0160
0161 static void ctcmpc_chx_txdone(fsm_instance *fi, int event, void *arg);
0162 static void ctcmpc_chx_rx(fsm_instance *fi, int event, void *arg);
0163 static void ctcmpc_chx_firstio(fsm_instance *fi, int event, void *arg);
0164
0165
0166
0167
0168
0169
0170
0171
0172
0173
0174
0175
0176
0177
0178
0179
0180 static void ctcmpc_chx_attn(fsm_instance *fsm, int event, void *arg);
0181 static void ctcmpc_chx_attnbusy(fsm_instance *, int, void *);
0182 static void ctcmpc_chx_resend(fsm_instance *, int, void *);
0183 static void ctcmpc_chx_send_sweep(fsm_instance *fsm, int event, void *arg);
0184
0185
0186
0187
0188
0189
0190
0191 void ctcm_ccw_check_rc(struct channel *ch, int rc, char *msg)
0192 {
0193 CTCM_DBF_TEXT_(ERROR, CTC_DBF_ERROR,
0194 "%s(%s): %s: %04x\n",
0195 CTCM_FUNTAIL, ch->id, msg, rc);
0196 switch (rc) {
0197 case -EBUSY:
0198 pr_info("%s: The communication peer is busy\n",
0199 ch->id);
0200 fsm_event(ch->fsm, CTC_EVENT_IO_EBUSY, ch);
0201 break;
0202 case -ENODEV:
0203 pr_err("%s: The specified target device is not valid\n",
0204 ch->id);
0205 fsm_event(ch->fsm, CTC_EVENT_IO_ENODEV, ch);
0206 break;
0207 default:
0208 pr_err("An I/O operation resulted in error %04x\n",
0209 rc);
0210 fsm_event(ch->fsm, CTC_EVENT_IO_UNKNOWN, ch);
0211 }
0212 }
0213
0214 void ctcm_purge_skb_queue(struct sk_buff_head *q)
0215 {
0216 struct sk_buff *skb;
0217
0218 CTCM_DBF_TEXT(TRACE, CTC_DBF_DEBUG, __func__);
0219
0220 while ((skb = skb_dequeue(q))) {
0221 refcount_dec(&skb->users);
0222 dev_kfree_skb_any(skb);
0223 }
0224 }
0225
0226
0227
0228
0229 static void ctcm_action_nop(fsm_instance *fi, int event, void *arg)
0230 {
0231 }
0232
0233
0234
0235
0236
0237
0238
0239
0240
0241
0242
0243
0244
0245
0246 static void chx_txdone(fsm_instance *fi, int event, void *arg)
0247 {
0248 struct channel *ch = arg;
0249 struct net_device *dev = ch->netdev;
0250 struct ctcm_priv *priv = dev->ml_priv;
0251 struct sk_buff *skb;
0252 int first = 1;
0253 int i;
0254 unsigned long duration;
0255 unsigned long done_stamp = jiffies;
0256
0257 CTCM_PR_DEBUG("%s(%s): %s\n", __func__, ch->id, dev->name);
0258
0259 duration = done_stamp - ch->prof.send_stamp;
0260 if (duration > ch->prof.tx_time)
0261 ch->prof.tx_time = duration;
0262
0263 if (ch->irb->scsw.cmd.count != 0)
0264 CTCM_DBF_TEXT_(TRACE, CTC_DBF_DEBUG,
0265 "%s(%s): TX not complete, remaining %d bytes",
0266 CTCM_FUNTAIL, dev->name, ch->irb->scsw.cmd.count);
0267 fsm_deltimer(&ch->timer);
0268 while ((skb = skb_dequeue(&ch->io_queue))) {
0269 priv->stats.tx_packets++;
0270 priv->stats.tx_bytes += skb->len - LL_HEADER_LENGTH;
0271 if (first) {
0272 priv->stats.tx_bytes += 2;
0273 first = 0;
0274 }
0275 refcount_dec(&skb->users);
0276 dev_kfree_skb_irq(skb);
0277 }
0278 spin_lock(&ch->collect_lock);
0279 clear_normalized_cda(&ch->ccw[4]);
0280 if (ch->collect_len > 0) {
0281 int rc;
0282
0283 if (ctcm_checkalloc_buffer(ch)) {
0284 spin_unlock(&ch->collect_lock);
0285 return;
0286 }
0287 ch->trans_skb->data = ch->trans_skb_data;
0288 skb_reset_tail_pointer(ch->trans_skb);
0289 ch->trans_skb->len = 0;
0290 if (ch->prof.maxmulti < (ch->collect_len + 2))
0291 ch->prof.maxmulti = ch->collect_len + 2;
0292 if (ch->prof.maxcqueue < skb_queue_len(&ch->collect_queue))
0293 ch->prof.maxcqueue = skb_queue_len(&ch->collect_queue);
0294 *((__u16 *)skb_put(ch->trans_skb, 2)) = ch->collect_len + 2;
0295 i = 0;
0296 while ((skb = skb_dequeue(&ch->collect_queue))) {
0297 skb_copy_from_linear_data(skb,
0298 skb_put(ch->trans_skb, skb->len), skb->len);
0299 priv->stats.tx_packets++;
0300 priv->stats.tx_bytes += skb->len - LL_HEADER_LENGTH;
0301 refcount_dec(&skb->users);
0302 dev_kfree_skb_irq(skb);
0303 i++;
0304 }
0305 ch->collect_len = 0;
0306 spin_unlock(&ch->collect_lock);
0307 ch->ccw[1].count = ch->trans_skb->len;
0308 fsm_addtimer(&ch->timer, CTCM_TIME_5_SEC, CTC_EVENT_TIMER, ch);
0309 ch->prof.send_stamp = jiffies;
0310 rc = ccw_device_start(ch->cdev, &ch->ccw[0], 0, 0xff, 0);
0311 ch->prof.doios_multi++;
0312 if (rc != 0) {
0313 priv->stats.tx_dropped += i;
0314 priv->stats.tx_errors += i;
0315 fsm_deltimer(&ch->timer);
0316 ctcm_ccw_check_rc(ch, rc, "chained TX");
0317 }
0318 } else {
0319 spin_unlock(&ch->collect_lock);
0320 fsm_newstate(fi, CTC_STATE_TXIDLE);
0321 }
0322 ctcm_clear_busy_do(dev);
0323 }
0324
0325
0326
0327
0328
0329
0330
0331
0332
0333
0334 void ctcm_chx_txidle(fsm_instance *fi, int event, void *arg)
0335 {
0336 struct channel *ch = arg;
0337 struct net_device *dev = ch->netdev;
0338 struct ctcm_priv *priv = dev->ml_priv;
0339
0340 CTCM_PR_DEBUG("%s(%s): %s\n", __func__, ch->id, dev->name);
0341
0342 fsm_deltimer(&ch->timer);
0343 fsm_newstate(fi, CTC_STATE_TXIDLE);
0344 fsm_event(priv->fsm, DEV_EVENT_TXUP, ch->netdev);
0345 }
0346
0347
0348
0349
0350
0351
0352
0353
0354
0355 static void chx_rx(fsm_instance *fi, int event, void *arg)
0356 {
0357 struct channel *ch = arg;
0358 struct net_device *dev = ch->netdev;
0359 struct ctcm_priv *priv = dev->ml_priv;
0360 int len = ch->max_bufsize - ch->irb->scsw.cmd.count;
0361 struct sk_buff *skb = ch->trans_skb;
0362 __u16 block_len = *((__u16 *)skb->data);
0363 int check_len;
0364 int rc;
0365
0366 fsm_deltimer(&ch->timer);
0367 if (len < 8) {
0368 CTCM_DBF_TEXT_(TRACE, CTC_DBF_NOTICE,
0369 "%s(%s): got packet with length %d < 8\n",
0370 CTCM_FUNTAIL, dev->name, len);
0371 priv->stats.rx_dropped++;
0372 priv->stats.rx_length_errors++;
0373 goto again;
0374 }
0375 if (len > ch->max_bufsize) {
0376 CTCM_DBF_TEXT_(TRACE, CTC_DBF_NOTICE,
0377 "%s(%s): got packet with length %d > %d\n",
0378 CTCM_FUNTAIL, dev->name, len, ch->max_bufsize);
0379 priv->stats.rx_dropped++;
0380 priv->stats.rx_length_errors++;
0381 goto again;
0382 }
0383
0384
0385
0386
0387 switch (ch->protocol) {
0388 case CTCM_PROTO_S390:
0389 case CTCM_PROTO_OS390:
0390 check_len = block_len + 2;
0391 break;
0392 default:
0393 check_len = block_len;
0394 break;
0395 }
0396 if ((len < block_len) || (len > check_len)) {
0397 CTCM_DBF_TEXT_(TRACE, CTC_DBF_NOTICE,
0398 "%s(%s): got block length %d != rx length %d\n",
0399 CTCM_FUNTAIL, dev->name, block_len, len);
0400 if (do_debug)
0401 ctcmpc_dump_skb(skb, 0);
0402
0403 *((__u16 *)skb->data) = len;
0404 priv->stats.rx_dropped++;
0405 priv->stats.rx_length_errors++;
0406 goto again;
0407 }
0408 if (block_len > 2) {
0409 *((__u16 *)skb->data) = block_len - 2;
0410 ctcm_unpack_skb(ch, skb);
0411 }
0412 again:
0413 skb->data = ch->trans_skb_data;
0414 skb_reset_tail_pointer(skb);
0415 skb->len = 0;
0416 if (ctcm_checkalloc_buffer(ch))
0417 return;
0418 ch->ccw[1].count = ch->max_bufsize;
0419 rc = ccw_device_start(ch->cdev, &ch->ccw[0], 0, 0xff, 0);
0420 if (rc != 0)
0421 ctcm_ccw_check_rc(ch, rc, "normal RX");
0422 }
0423
0424
0425
0426
0427
0428
0429
0430
0431 static void chx_firstio(fsm_instance *fi, int event, void *arg)
0432 {
0433 int rc;
0434 struct channel *ch = arg;
0435 int fsmstate = fsm_getstate(fi);
0436
0437 CTCM_DBF_TEXT_(TRACE, CTC_DBF_NOTICE,
0438 "%s(%s) : %02x",
0439 CTCM_FUNTAIL, ch->id, fsmstate);
0440
0441 ch->sense_rc = 0;
0442 if (fsmstate == CTC_STATE_TXIDLE)
0443 CTCM_DBF_TEXT_(TRACE, CTC_DBF_DEBUG,
0444 "%s(%s): remote side issued READ?, init.\n",
0445 CTCM_FUNTAIL, ch->id);
0446 fsm_deltimer(&ch->timer);
0447 if (ctcm_checkalloc_buffer(ch))
0448 return;
0449 if ((fsmstate == CTC_STATE_SETUPWAIT) &&
0450 (ch->protocol == CTCM_PROTO_OS390)) {
0451
0452 if (CHANNEL_DIRECTION(ch->flags) == CTCM_READ) {
0453 *((__u16 *)ch->trans_skb->data) = CTCM_INITIAL_BLOCKLEN;
0454 fsm_addtimer(&ch->timer, CTCM_TIME_5_SEC,
0455 CTC_EVENT_TIMER, ch);
0456 chx_rxidle(fi, event, arg);
0457 } else {
0458 struct net_device *dev = ch->netdev;
0459 struct ctcm_priv *priv = dev->ml_priv;
0460 fsm_newstate(fi, CTC_STATE_TXIDLE);
0461 fsm_event(priv->fsm, DEV_EVENT_TXUP, dev);
0462 }
0463 return;
0464 }
0465
0466
0467
0468
0469
0470 if ((CHANNEL_DIRECTION(ch->flags) == CTCM_WRITE) ||
0471 (ch->protocol != CTCM_PROTO_S390))
0472 fsm_addtimer(&ch->timer, CTCM_TIME_5_SEC, CTC_EVENT_TIMER, ch);
0473
0474 *((__u16 *)ch->trans_skb->data) = CTCM_INITIAL_BLOCKLEN;
0475 ch->ccw[1].count = 2;
0476
0477 fsm_newstate(fi, (CHANNEL_DIRECTION(ch->flags) == CTCM_READ)
0478 ? CTC_STATE_RXINIT : CTC_STATE_TXINIT);
0479 rc = ccw_device_start(ch->cdev, &ch->ccw[0], 0, 0xff, 0);
0480 if (rc != 0) {
0481 fsm_deltimer(&ch->timer);
0482 fsm_newstate(fi, CTC_STATE_SETUPWAIT);
0483 ctcm_ccw_check_rc(ch, rc, "init IO");
0484 }
0485
0486
0487
0488
0489
0490
0491
0492 if ((CHANNEL_DIRECTION(ch->flags) == CTCM_READ) &&
0493 (ch->protocol == CTCM_PROTO_S390)) {
0494 struct net_device *dev = ch->netdev;
0495 struct ctcm_priv *priv = dev->ml_priv;
0496 fsm_event(priv->fsm, DEV_EVENT_RXUP, dev);
0497 }
0498 }
0499
0500
0501
0502
0503
0504
0505
0506
0507
0508
0509 static void chx_rxidle(fsm_instance *fi, int event, void *arg)
0510 {
0511 struct channel *ch = arg;
0512 struct net_device *dev = ch->netdev;
0513 struct ctcm_priv *priv = dev->ml_priv;
0514 __u16 buflen;
0515 int rc;
0516
0517 fsm_deltimer(&ch->timer);
0518 buflen = *((__u16 *)ch->trans_skb->data);
0519 CTCM_PR_DEBUG("%s: %s: Initial RX count = %d\n",
0520 __func__, dev->name, buflen);
0521
0522 if (buflen >= CTCM_INITIAL_BLOCKLEN) {
0523 if (ctcm_checkalloc_buffer(ch))
0524 return;
0525 ch->ccw[1].count = ch->max_bufsize;
0526 fsm_newstate(fi, CTC_STATE_RXIDLE);
0527 rc = ccw_device_start(ch->cdev, &ch->ccw[0], 0, 0xff, 0);
0528 if (rc != 0) {
0529 fsm_newstate(fi, CTC_STATE_RXINIT);
0530 ctcm_ccw_check_rc(ch, rc, "initial RX");
0531 } else
0532 fsm_event(priv->fsm, DEV_EVENT_RXUP, dev);
0533 } else {
0534 CTCM_PR_DEBUG("%s: %s: Initial RX count %d not %d\n",
0535 __func__, dev->name,
0536 buflen, CTCM_INITIAL_BLOCKLEN);
0537 chx_firstio(fi, event, arg);
0538 }
0539 }
0540
0541
0542
0543
0544
0545
0546
0547
0548 static void ctcm_chx_setmode(fsm_instance *fi, int event, void *arg)
0549 {
0550 struct channel *ch = arg;
0551 int rc;
0552 unsigned long saveflags = 0;
0553 int timeout = CTCM_TIME_5_SEC;
0554
0555 fsm_deltimer(&ch->timer);
0556 if (IS_MPC(ch)) {
0557 timeout = 1500;
0558 CTCM_PR_DEBUG("enter %s: cp=%i ch=0x%p id=%s\n",
0559 __func__, smp_processor_id(), ch, ch->id);
0560 }
0561 fsm_addtimer(&ch->timer, timeout, CTC_EVENT_TIMER, ch);
0562 fsm_newstate(fi, CTC_STATE_SETUPWAIT);
0563 CTCM_CCW_DUMP((char *)&ch->ccw[6], sizeof(struct ccw1) * 2);
0564
0565 if (event == CTC_EVENT_TIMER)
0566 spin_lock_irqsave(get_ccwdev_lock(ch->cdev), saveflags);
0567
0568
0569
0570 rc = ccw_device_start(ch->cdev, &ch->ccw[6], 0, 0xff, 0);
0571 if (event == CTC_EVENT_TIMER)
0572 spin_unlock_irqrestore(get_ccwdev_lock(ch->cdev), saveflags);
0573 if (rc != 0) {
0574 fsm_deltimer(&ch->timer);
0575 fsm_newstate(fi, CTC_STATE_STARTWAIT);
0576 ctcm_ccw_check_rc(ch, rc, "set Mode");
0577 } else
0578 ch->retry = 0;
0579 }
0580
0581
0582
0583
0584
0585
0586
0587
0588 static void ctcm_chx_start(fsm_instance *fi, int event, void *arg)
0589 {
0590 struct channel *ch = arg;
0591 unsigned long saveflags;
0592 int rc;
0593
0594 CTCM_DBF_TEXT_(SETUP, CTC_DBF_INFO, "%s(%s): %s",
0595 CTCM_FUNTAIL, ch->id,
0596 (CHANNEL_DIRECTION(ch->flags) == CTCM_READ) ? "RX" : "TX");
0597
0598 if (ch->trans_skb != NULL) {
0599 clear_normalized_cda(&ch->ccw[1]);
0600 dev_kfree_skb(ch->trans_skb);
0601 ch->trans_skb = NULL;
0602 }
0603 if (CHANNEL_DIRECTION(ch->flags) == CTCM_READ) {
0604 ch->ccw[1].cmd_code = CCW_CMD_READ;
0605 ch->ccw[1].flags = CCW_FLAG_SLI;
0606 ch->ccw[1].count = 0;
0607 } else {
0608 ch->ccw[1].cmd_code = CCW_CMD_WRITE;
0609 ch->ccw[1].flags = CCW_FLAG_SLI | CCW_FLAG_CC;
0610 ch->ccw[1].count = 0;
0611 }
0612 if (ctcm_checkalloc_buffer(ch)) {
0613 CTCM_DBF_TEXT_(TRACE, CTC_DBF_DEBUG,
0614 "%s(%s): %s trans_skb alloc delayed "
0615 "until first transfer",
0616 CTCM_FUNTAIL, ch->id,
0617 (CHANNEL_DIRECTION(ch->flags) == CTCM_READ) ?
0618 "RX" : "TX");
0619 }
0620 ch->ccw[0].cmd_code = CCW_CMD_PREPARE;
0621 ch->ccw[0].flags = CCW_FLAG_SLI | CCW_FLAG_CC;
0622 ch->ccw[0].count = 0;
0623 ch->ccw[0].cda = 0;
0624 ch->ccw[2].cmd_code = CCW_CMD_NOOP;
0625 ch->ccw[2].flags = CCW_FLAG_SLI;
0626 ch->ccw[2].count = 0;
0627 ch->ccw[2].cda = 0;
0628 memcpy(&ch->ccw[3], &ch->ccw[0], sizeof(struct ccw1) * 3);
0629 ch->ccw[4].cda = 0;
0630 ch->ccw[4].flags &= ~CCW_FLAG_IDA;
0631
0632 fsm_newstate(fi, CTC_STATE_STARTWAIT);
0633 fsm_addtimer(&ch->timer, 1000, CTC_EVENT_TIMER, ch);
0634 spin_lock_irqsave(get_ccwdev_lock(ch->cdev), saveflags);
0635 rc = ccw_device_halt(ch->cdev, 0);
0636 spin_unlock_irqrestore(get_ccwdev_lock(ch->cdev), saveflags);
0637 if (rc != 0) {
0638 if (rc != -EBUSY)
0639 fsm_deltimer(&ch->timer);
0640 ctcm_ccw_check_rc(ch, rc, "initial HaltIO");
0641 }
0642 }
0643
0644
0645
0646
0647
0648
0649
0650
0651 static void ctcm_chx_haltio(fsm_instance *fi, int event, void *arg)
0652 {
0653 struct channel *ch = arg;
0654 unsigned long saveflags = 0;
0655 int rc;
0656 int oldstate;
0657
0658 fsm_deltimer(&ch->timer);
0659 if (IS_MPC(ch))
0660 fsm_deltimer(&ch->sweep_timer);
0661
0662 fsm_addtimer(&ch->timer, CTCM_TIME_5_SEC, CTC_EVENT_TIMER, ch);
0663
0664 if (event == CTC_EVENT_STOP)
0665 spin_lock_irqsave(get_ccwdev_lock(ch->cdev), saveflags);
0666
0667
0668 oldstate = fsm_getstate(fi);
0669 fsm_newstate(fi, CTC_STATE_TERM);
0670 rc = ccw_device_halt(ch->cdev, 0);
0671
0672 if (event == CTC_EVENT_STOP)
0673 spin_unlock_irqrestore(get_ccwdev_lock(ch->cdev), saveflags);
0674
0675
0676 if (rc != 0 && rc != -EBUSY) {
0677 fsm_deltimer(&ch->timer);
0678 if (event != CTC_EVENT_STOP) {
0679 fsm_newstate(fi, oldstate);
0680 ctcm_ccw_check_rc(ch, rc, (char *)__func__);
0681 }
0682 }
0683 }
0684
0685
0686
0687
0688
0689
0690
0691
0692
0693 static void ctcm_chx_cleanup(fsm_instance *fi, int state,
0694 struct channel *ch)
0695 {
0696 struct net_device *dev = ch->netdev;
0697 struct ctcm_priv *priv = dev->ml_priv;
0698
0699 CTCM_DBF_TEXT_(SETUP, CTC_DBF_NOTICE,
0700 "%s(%s): %s[%d]\n",
0701 CTCM_FUNTAIL, dev->name, ch->id, state);
0702
0703 fsm_deltimer(&ch->timer);
0704 if (IS_MPC(ch))
0705 fsm_deltimer(&ch->sweep_timer);
0706
0707 fsm_newstate(fi, state);
0708 if (state == CTC_STATE_STOPPED && ch->trans_skb != NULL) {
0709 clear_normalized_cda(&ch->ccw[1]);
0710 dev_kfree_skb_any(ch->trans_skb);
0711 ch->trans_skb = NULL;
0712 }
0713
0714 ch->th_seg = 0x00;
0715 ch->th_seq_num = 0x00;
0716 if (CHANNEL_DIRECTION(ch->flags) == CTCM_READ) {
0717 skb_queue_purge(&ch->io_queue);
0718 fsm_event(priv->fsm, DEV_EVENT_RXDOWN, dev);
0719 } else {
0720 ctcm_purge_skb_queue(&ch->io_queue);
0721 if (IS_MPC(ch))
0722 ctcm_purge_skb_queue(&ch->sweep_queue);
0723 spin_lock(&ch->collect_lock);
0724 ctcm_purge_skb_queue(&ch->collect_queue);
0725 ch->collect_len = 0;
0726 spin_unlock(&ch->collect_lock);
0727 fsm_event(priv->fsm, DEV_EVENT_TXDOWN, dev);
0728 }
0729 }
0730
0731
0732
0733
0734
0735
0736
0737
0738
0739 static void ctcm_chx_stopped(fsm_instance *fi, int event, void *arg)
0740 {
0741 ctcm_chx_cleanup(fi, CTC_STATE_STOPPED, arg);
0742 }
0743
0744
0745
0746
0747
0748
0749
0750
0751
0752 static void ctcm_chx_stop(fsm_instance *fi, int event, void *arg)
0753 {
0754 fsm_newstate(fi, CTC_STATE_STOPPED);
0755 }
0756
0757
0758
0759
0760
0761
0762
0763
0764
0765
0766 static void ctcm_chx_fail(fsm_instance *fi, int event, void *arg)
0767 {
0768 ctcm_chx_cleanup(fi, CTC_STATE_NOTOP, arg);
0769 }
0770
0771
0772
0773
0774
0775
0776
0777
0778 static void ctcm_chx_setuperr(fsm_instance *fi, int event, void *arg)
0779 {
0780 struct channel *ch = arg;
0781 struct net_device *dev = ch->netdev;
0782 struct ctcm_priv *priv = dev->ml_priv;
0783
0784
0785
0786
0787
0788
0789 if ((fsm_getstate(fi) == CTC_STATE_SETUPWAIT) &&
0790 ((event == CTC_EVENT_UC_RCRESET) ||
0791 (event == CTC_EVENT_UC_RSRESET))) {
0792 fsm_newstate(fi, CTC_STATE_STARTRETRY);
0793 fsm_deltimer(&ch->timer);
0794 fsm_addtimer(&ch->timer, CTCM_TIME_5_SEC, CTC_EVENT_TIMER, ch);
0795 if (!IS_MPC(ch) &&
0796 (CHANNEL_DIRECTION(ch->flags) == CTCM_READ)) {
0797 int rc = ccw_device_halt(ch->cdev, 0);
0798 if (rc != 0)
0799 ctcm_ccw_check_rc(ch, rc,
0800 "HaltIO in chx_setuperr");
0801 }
0802 return;
0803 }
0804
0805 CTCM_DBF_TEXT_(ERROR, CTC_DBF_CRIT,
0806 "%s(%s) : %s error during %s channel setup state=%s\n",
0807 CTCM_FUNTAIL, dev->name, ctc_ch_event_names[event],
0808 (CHANNEL_DIRECTION(ch->flags) == CTCM_READ) ? "RX" : "TX",
0809 fsm_getstate_str(fi));
0810
0811 if (CHANNEL_DIRECTION(ch->flags) == CTCM_READ) {
0812 fsm_newstate(fi, CTC_STATE_RXERR);
0813 fsm_event(priv->fsm, DEV_EVENT_RXDOWN, dev);
0814 } else {
0815 fsm_newstate(fi, CTC_STATE_TXERR);
0816 fsm_event(priv->fsm, DEV_EVENT_TXDOWN, dev);
0817 }
0818 }
0819
0820
0821
0822
0823
0824
0825
0826
0827 static void ctcm_chx_restart(fsm_instance *fi, int event, void *arg)
0828 {
0829 struct channel *ch = arg;
0830 struct net_device *dev = ch->netdev;
0831 unsigned long saveflags = 0;
0832 int oldstate;
0833 int rc;
0834
0835 CTCM_DBF_TEXT_(TRACE, CTC_DBF_NOTICE,
0836 "%s: %s[%d] of %s\n",
0837 CTCM_FUNTAIL, ch->id, event, dev->name);
0838
0839 fsm_deltimer(&ch->timer);
0840
0841 fsm_addtimer(&ch->timer, CTCM_TIME_5_SEC, CTC_EVENT_TIMER, ch);
0842 oldstate = fsm_getstate(fi);
0843 fsm_newstate(fi, CTC_STATE_STARTWAIT);
0844 if (event == CTC_EVENT_TIMER)
0845 spin_lock_irqsave(get_ccwdev_lock(ch->cdev), saveflags);
0846
0847
0848
0849 rc = ccw_device_halt(ch->cdev, 0);
0850 if (event == CTC_EVENT_TIMER)
0851 spin_unlock_irqrestore(get_ccwdev_lock(ch->cdev), saveflags);
0852 if (rc != 0) {
0853 if (rc != -EBUSY) {
0854 fsm_deltimer(&ch->timer);
0855 fsm_newstate(fi, oldstate);
0856 }
0857 ctcm_ccw_check_rc(ch, rc, "HaltIO in ctcm_chx_restart");
0858 }
0859 }
0860
0861
0862
0863
0864
0865
0866
0867
0868
0869 static void ctcm_chx_rxiniterr(fsm_instance *fi, int event, void *arg)
0870 {
0871 struct channel *ch = arg;
0872 struct net_device *dev = ch->netdev;
0873 struct ctcm_priv *priv = dev->ml_priv;
0874
0875 if (event == CTC_EVENT_TIMER) {
0876 if (!IS_MPCDEV(dev))
0877
0878 fsm_deltimer(&ch->timer);
0879 if (ch->retry++ < 3)
0880 ctcm_chx_restart(fi, event, arg);
0881 else {
0882 fsm_newstate(fi, CTC_STATE_RXERR);
0883 fsm_event(priv->fsm, DEV_EVENT_RXDOWN, dev);
0884 }
0885 } else {
0886 CTCM_DBF_TEXT_(ERROR, CTC_DBF_ERROR,
0887 "%s(%s): %s in %s", CTCM_FUNTAIL, ch->id,
0888 ctc_ch_event_names[event], fsm_getstate_str(fi));
0889
0890 dev_warn(&dev->dev,
0891 "Initialization failed with RX/TX init handshake "
0892 "error %s\n", ctc_ch_event_names[event]);
0893 }
0894 }
0895
0896
0897
0898
0899
0900
0901
0902
0903
0904 static void ctcm_chx_rxinitfail(fsm_instance *fi, int event, void *arg)
0905 {
0906 struct channel *ch = arg;
0907 struct net_device *dev = ch->netdev;
0908 struct ctcm_priv *priv = dev->ml_priv;
0909
0910 CTCM_DBF_TEXT_(ERROR, CTC_DBF_ERROR,
0911 "%s(%s): RX %s busy, init. fail",
0912 CTCM_FUNTAIL, dev->name, ch->id);
0913 fsm_newstate(fi, CTC_STATE_RXERR);
0914 fsm_event(priv->fsm, DEV_EVENT_RXDOWN, dev);
0915 }
0916
0917
0918
0919
0920
0921
0922
0923
0924 static void ctcm_chx_rxdisc(fsm_instance *fi, int event, void *arg)
0925 {
0926 struct channel *ch = arg;
0927 struct channel *ch2;
0928 struct net_device *dev = ch->netdev;
0929 struct ctcm_priv *priv = dev->ml_priv;
0930
0931 CTCM_DBF_TEXT_(TRACE, CTC_DBF_NOTICE,
0932 "%s: %s: remote disconnect - re-init ...",
0933 CTCM_FUNTAIL, dev->name);
0934 fsm_deltimer(&ch->timer);
0935
0936
0937
0938 fsm_event(priv->fsm, DEV_EVENT_RXDOWN, dev);
0939 fsm_event(priv->fsm, DEV_EVENT_TXDOWN, dev);
0940
0941 fsm_newstate(fi, CTC_STATE_DTERM);
0942 ch2 = priv->channel[CTCM_WRITE];
0943 fsm_newstate(ch2->fsm, CTC_STATE_DTERM);
0944
0945 ccw_device_halt(ch->cdev, 0);
0946 ccw_device_halt(ch2->cdev, 0);
0947 }
0948
0949
0950
0951
0952
0953
0954
0955
0956 static void ctcm_chx_txiniterr(fsm_instance *fi, int event, void *arg)
0957 {
0958 struct channel *ch = arg;
0959 struct net_device *dev = ch->netdev;
0960 struct ctcm_priv *priv = dev->ml_priv;
0961
0962 if (event == CTC_EVENT_TIMER) {
0963 fsm_deltimer(&ch->timer);
0964 if (ch->retry++ < 3)
0965 ctcm_chx_restart(fi, event, arg);
0966 else {
0967 fsm_newstate(fi, CTC_STATE_TXERR);
0968 fsm_event(priv->fsm, DEV_EVENT_TXDOWN, dev);
0969 }
0970 } else {
0971 CTCM_DBF_TEXT_(ERROR, CTC_DBF_ERROR,
0972 "%s(%s): %s in %s", CTCM_FUNTAIL, ch->id,
0973 ctc_ch_event_names[event], fsm_getstate_str(fi));
0974
0975 dev_warn(&dev->dev,
0976 "Initialization failed with RX/TX init handshake "
0977 "error %s\n", ctc_ch_event_names[event]);
0978 }
0979 }
0980
0981
0982
0983
0984
0985
0986
0987
0988 static void ctcm_chx_txretry(fsm_instance *fi, int event, void *arg)
0989 {
0990 struct channel *ch = arg;
0991 struct net_device *dev = ch->netdev;
0992 struct ctcm_priv *priv = dev->ml_priv;
0993 struct sk_buff *skb;
0994
0995 CTCM_PR_DEBUG("Enter: %s: cp=%i ch=0x%p id=%s\n",
0996 __func__, smp_processor_id(), ch, ch->id);
0997
0998 fsm_deltimer(&ch->timer);
0999 if (ch->retry++ > 3) {
1000 struct mpc_group *gptr = priv->mpcg;
1001 CTCM_DBF_TEXT_(TRACE, CTC_DBF_INFO,
1002 "%s: %s: retries exceeded",
1003 CTCM_FUNTAIL, ch->id);
1004 fsm_event(priv->fsm, DEV_EVENT_TXDOWN, dev);
1005
1006
1007 if (!(gptr && (fsm_getstate(gptr->fsm) != MPCG_STATE_READY)))
1008 ctcm_chx_restart(fi, event, arg);
1009 goto done;
1010 }
1011
1012 CTCM_DBF_TEXT_(TRACE, CTC_DBF_DEBUG,
1013 "%s : %s: retry %d",
1014 CTCM_FUNTAIL, ch->id, ch->retry);
1015 skb = skb_peek(&ch->io_queue);
1016 if (skb) {
1017 int rc = 0;
1018 unsigned long saveflags = 0;
1019 clear_normalized_cda(&ch->ccw[4]);
1020 ch->ccw[4].count = skb->len;
1021 if (set_normalized_cda(&ch->ccw[4], skb->data)) {
1022 CTCM_DBF_TEXT_(TRACE, CTC_DBF_INFO,
1023 "%s: %s: IDAL alloc failed",
1024 CTCM_FUNTAIL, ch->id);
1025 fsm_event(priv->fsm, DEV_EVENT_TXDOWN, dev);
1026 ctcm_chx_restart(fi, event, arg);
1027 goto done;
1028 }
1029 fsm_addtimer(&ch->timer, 1000, CTC_EVENT_TIMER, ch);
1030 if (event == CTC_EVENT_TIMER)
1031 spin_lock_irqsave(get_ccwdev_lock(ch->cdev), saveflags);
1032
1033
1034
1035 if (do_debug_ccw)
1036 ctcmpc_dumpit((char *)&ch->ccw[3],
1037 sizeof(struct ccw1) * 3);
1038
1039 rc = ccw_device_start(ch->cdev, &ch->ccw[3], 0, 0xff, 0);
1040 if (event == CTC_EVENT_TIMER)
1041 spin_unlock_irqrestore(get_ccwdev_lock(ch->cdev),
1042 saveflags);
1043 if (rc != 0) {
1044 fsm_deltimer(&ch->timer);
1045 ctcm_ccw_check_rc(ch, rc, "TX in chx_txretry");
1046 ctcm_purge_skb_queue(&ch->io_queue);
1047 }
1048 }
1049 done:
1050 return;
1051 }
1052
1053
1054
1055
1056
1057
1058
1059
1060 static void ctcm_chx_iofatal(fsm_instance *fi, int event, void *arg)
1061 {
1062 struct channel *ch = arg;
1063 struct net_device *dev = ch->netdev;
1064 struct ctcm_priv *priv = dev->ml_priv;
1065 int rd = CHANNEL_DIRECTION(ch->flags);
1066
1067 fsm_deltimer(&ch->timer);
1068 CTCM_DBF_TEXT_(ERROR, CTC_DBF_ERROR,
1069 "%s: %s: %s unrecoverable channel error",
1070 CTCM_FUNTAIL, ch->id, rd == CTCM_READ ? "RX" : "TX");
1071
1072 if (IS_MPC(ch)) {
1073 priv->stats.tx_dropped++;
1074 priv->stats.tx_errors++;
1075 }
1076 if (rd == CTCM_READ) {
1077 fsm_newstate(fi, CTC_STATE_RXERR);
1078 fsm_event(priv->fsm, DEV_EVENT_RXDOWN, dev);
1079 } else {
1080 fsm_newstate(fi, CTC_STATE_TXERR);
1081 fsm_event(priv->fsm, DEV_EVENT_TXDOWN, dev);
1082 }
1083 }
1084
1085
1086
1087
1088 const fsm_node ch_fsm[] = {
1089 { CTC_STATE_STOPPED, CTC_EVENT_STOP, ctcm_action_nop },
1090 { CTC_STATE_STOPPED, CTC_EVENT_START, ctcm_chx_start },
1091 { CTC_STATE_STOPPED, CTC_EVENT_FINSTAT, ctcm_action_nop },
1092 { CTC_STATE_STOPPED, CTC_EVENT_MC_FAIL, ctcm_action_nop },
1093
1094 { CTC_STATE_NOTOP, CTC_EVENT_STOP, ctcm_chx_stop },
1095 { CTC_STATE_NOTOP, CTC_EVENT_START, ctcm_action_nop },
1096 { CTC_STATE_NOTOP, CTC_EVENT_FINSTAT, ctcm_action_nop },
1097 { CTC_STATE_NOTOP, CTC_EVENT_MC_FAIL, ctcm_action_nop },
1098 { CTC_STATE_NOTOP, CTC_EVENT_MC_GOOD, ctcm_chx_start },
1099
1100 { CTC_STATE_STARTWAIT, CTC_EVENT_STOP, ctcm_chx_haltio },
1101 { CTC_STATE_STARTWAIT, CTC_EVENT_START, ctcm_action_nop },
1102 { CTC_STATE_STARTWAIT, CTC_EVENT_FINSTAT, ctcm_chx_setmode },
1103 { CTC_STATE_STARTWAIT, CTC_EVENT_TIMER, ctcm_chx_setuperr },
1104 { CTC_STATE_STARTWAIT, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1105 { CTC_STATE_STARTWAIT, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1106
1107 { CTC_STATE_STARTRETRY, CTC_EVENT_STOP, ctcm_chx_haltio },
1108 { CTC_STATE_STARTRETRY, CTC_EVENT_TIMER, ctcm_chx_setmode },
1109 { CTC_STATE_STARTRETRY, CTC_EVENT_FINSTAT, ctcm_action_nop },
1110 { CTC_STATE_STARTRETRY, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1111
1112 { CTC_STATE_SETUPWAIT, CTC_EVENT_STOP, ctcm_chx_haltio },
1113 { CTC_STATE_SETUPWAIT, CTC_EVENT_START, ctcm_action_nop },
1114 { CTC_STATE_SETUPWAIT, CTC_EVENT_FINSTAT, chx_firstio },
1115 { CTC_STATE_SETUPWAIT, CTC_EVENT_UC_RCRESET, ctcm_chx_setuperr },
1116 { CTC_STATE_SETUPWAIT, CTC_EVENT_UC_RSRESET, ctcm_chx_setuperr },
1117 { CTC_STATE_SETUPWAIT, CTC_EVENT_TIMER, ctcm_chx_setmode },
1118 { CTC_STATE_SETUPWAIT, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1119 { CTC_STATE_SETUPWAIT, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1120
1121 { CTC_STATE_RXINIT, CTC_EVENT_STOP, ctcm_chx_haltio },
1122 { CTC_STATE_RXINIT, CTC_EVENT_START, ctcm_action_nop },
1123 { CTC_STATE_RXINIT, CTC_EVENT_FINSTAT, chx_rxidle },
1124 { CTC_STATE_RXINIT, CTC_EVENT_UC_RCRESET, ctcm_chx_rxiniterr },
1125 { CTC_STATE_RXINIT, CTC_EVENT_UC_RSRESET, ctcm_chx_rxiniterr },
1126 { CTC_STATE_RXINIT, CTC_EVENT_TIMER, ctcm_chx_rxiniterr },
1127 { CTC_STATE_RXINIT, CTC_EVENT_ATTNBUSY, ctcm_chx_rxinitfail },
1128 { CTC_STATE_RXINIT, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1129 { CTC_STATE_RXINIT, CTC_EVENT_UC_ZERO, chx_firstio },
1130 { CTC_STATE_RXINIT, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1131
1132 { CTC_STATE_RXIDLE, CTC_EVENT_STOP, ctcm_chx_haltio },
1133 { CTC_STATE_RXIDLE, CTC_EVENT_START, ctcm_action_nop },
1134 { CTC_STATE_RXIDLE, CTC_EVENT_FINSTAT, chx_rx },
1135 { CTC_STATE_RXIDLE, CTC_EVENT_UC_RCRESET, ctcm_chx_rxdisc },
1136 { CTC_STATE_RXIDLE, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1137 { CTC_STATE_RXIDLE, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1138 { CTC_STATE_RXIDLE, CTC_EVENT_UC_ZERO, chx_rx },
1139
1140 { CTC_STATE_TXINIT, CTC_EVENT_STOP, ctcm_chx_haltio },
1141 { CTC_STATE_TXINIT, CTC_EVENT_START, ctcm_action_nop },
1142 { CTC_STATE_TXINIT, CTC_EVENT_FINSTAT, ctcm_chx_txidle },
1143 { CTC_STATE_TXINIT, CTC_EVENT_UC_RCRESET, ctcm_chx_txiniterr },
1144 { CTC_STATE_TXINIT, CTC_EVENT_UC_RSRESET, ctcm_chx_txiniterr },
1145 { CTC_STATE_TXINIT, CTC_EVENT_TIMER, ctcm_chx_txiniterr },
1146 { CTC_STATE_TXINIT, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1147 { CTC_STATE_TXINIT, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1148
1149 { CTC_STATE_TXIDLE, CTC_EVENT_STOP, ctcm_chx_haltio },
1150 { CTC_STATE_TXIDLE, CTC_EVENT_START, ctcm_action_nop },
1151 { CTC_STATE_TXIDLE, CTC_EVENT_FINSTAT, chx_firstio },
1152 { CTC_STATE_TXIDLE, CTC_EVENT_UC_RCRESET, ctcm_action_nop },
1153 { CTC_STATE_TXIDLE, CTC_EVENT_UC_RSRESET, ctcm_action_nop },
1154 { CTC_STATE_TXIDLE, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1155 { CTC_STATE_TXIDLE, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1156
1157 { CTC_STATE_TERM, CTC_EVENT_STOP, ctcm_action_nop },
1158 { CTC_STATE_TERM, CTC_EVENT_START, ctcm_chx_restart },
1159 { CTC_STATE_TERM, CTC_EVENT_FINSTAT, ctcm_chx_stopped },
1160 { CTC_STATE_TERM, CTC_EVENT_UC_RCRESET, ctcm_action_nop },
1161 { CTC_STATE_TERM, CTC_EVENT_UC_RSRESET, ctcm_action_nop },
1162 { CTC_STATE_TERM, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1163
1164 { CTC_STATE_DTERM, CTC_EVENT_STOP, ctcm_chx_haltio },
1165 { CTC_STATE_DTERM, CTC_EVENT_START, ctcm_chx_restart },
1166 { CTC_STATE_DTERM, CTC_EVENT_FINSTAT, ctcm_chx_setmode },
1167 { CTC_STATE_DTERM, CTC_EVENT_UC_RCRESET, ctcm_action_nop },
1168 { CTC_STATE_DTERM, CTC_EVENT_UC_RSRESET, ctcm_action_nop },
1169 { CTC_STATE_DTERM, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1170
1171 { CTC_STATE_TX, CTC_EVENT_STOP, ctcm_chx_haltio },
1172 { CTC_STATE_TX, CTC_EVENT_START, ctcm_action_nop },
1173 { CTC_STATE_TX, CTC_EVENT_FINSTAT, chx_txdone },
1174 { CTC_STATE_TX, CTC_EVENT_UC_RCRESET, ctcm_chx_txretry },
1175 { CTC_STATE_TX, CTC_EVENT_UC_RSRESET, ctcm_chx_txretry },
1176 { CTC_STATE_TX, CTC_EVENT_TIMER, ctcm_chx_txretry },
1177 { CTC_STATE_TX, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1178 { CTC_STATE_TX, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1179
1180 { CTC_STATE_RXERR, CTC_EVENT_STOP, ctcm_chx_haltio },
1181 { CTC_STATE_TXERR, CTC_EVENT_STOP, ctcm_chx_haltio },
1182 { CTC_STATE_TXERR, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1183 { CTC_STATE_RXERR, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1184 };
1185
1186 int ch_fsm_len = ARRAY_SIZE(ch_fsm);
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210 static void ctcmpc_chx_txdone(fsm_instance *fi, int event, void *arg)
1211 {
1212 struct channel *ch = arg;
1213 struct net_device *dev = ch->netdev;
1214 struct ctcm_priv *priv = dev->ml_priv;
1215 struct mpc_group *grp = priv->mpcg;
1216 struct sk_buff *skb;
1217 int first = 1;
1218 int i;
1219 __u32 data_space;
1220 unsigned long duration;
1221 struct sk_buff *peekskb;
1222 int rc;
1223 struct th_header *header;
1224 struct pdu *p_header;
1225 unsigned long done_stamp = jiffies;
1226
1227 CTCM_PR_DEBUG("Enter %s: %s cp:%i\n",
1228 __func__, dev->name, smp_processor_id());
1229
1230 duration = done_stamp - ch->prof.send_stamp;
1231 if (duration > ch->prof.tx_time)
1232 ch->prof.tx_time = duration;
1233
1234 if (ch->irb->scsw.cmd.count != 0)
1235 CTCM_DBF_TEXT_(MPC_TRACE, CTC_DBF_DEBUG,
1236 "%s(%s): TX not complete, remaining %d bytes",
1237 CTCM_FUNTAIL, dev->name, ch->irb->scsw.cmd.count);
1238 fsm_deltimer(&ch->timer);
1239 while ((skb = skb_dequeue(&ch->io_queue))) {
1240 priv->stats.tx_packets++;
1241 priv->stats.tx_bytes += skb->len - TH_HEADER_LENGTH;
1242 if (first) {
1243 priv->stats.tx_bytes += 2;
1244 first = 0;
1245 }
1246 refcount_dec(&skb->users);
1247 dev_kfree_skb_irq(skb);
1248 }
1249 spin_lock(&ch->collect_lock);
1250 clear_normalized_cda(&ch->ccw[4]);
1251 if ((ch->collect_len <= 0) || (grp->in_sweep != 0)) {
1252 spin_unlock(&ch->collect_lock);
1253 fsm_newstate(fi, CTC_STATE_TXIDLE);
1254 goto done;
1255 }
1256
1257 if (ctcm_checkalloc_buffer(ch)) {
1258 spin_unlock(&ch->collect_lock);
1259 goto done;
1260 }
1261 ch->trans_skb->data = ch->trans_skb_data;
1262 skb_reset_tail_pointer(ch->trans_skb);
1263 ch->trans_skb->len = 0;
1264 if (ch->prof.maxmulti < (ch->collect_len + TH_HEADER_LENGTH))
1265 ch->prof.maxmulti = ch->collect_len + TH_HEADER_LENGTH;
1266 if (ch->prof.maxcqueue < skb_queue_len(&ch->collect_queue))
1267 ch->prof.maxcqueue = skb_queue_len(&ch->collect_queue);
1268 i = 0;
1269 p_header = NULL;
1270 data_space = grp->group_max_buflen - TH_HEADER_LENGTH;
1271
1272 CTCM_PR_DBGDATA("%s: building trans_skb from collect_q"
1273 " data_space:%04x\n",
1274 __func__, data_space);
1275
1276 while ((skb = skb_dequeue(&ch->collect_queue))) {
1277 skb_put_data(ch->trans_skb, skb->data, skb->len);
1278 p_header = (struct pdu *)
1279 (skb_tail_pointer(ch->trans_skb) - skb->len);
1280 p_header->pdu_flag = 0x00;
1281 if (be16_to_cpu(skb->protocol) == ETH_P_SNAP)
1282 p_header->pdu_flag |= 0x60;
1283 else
1284 p_header->pdu_flag |= 0x20;
1285
1286 CTCM_PR_DBGDATA("%s: trans_skb len:%04x \n",
1287 __func__, ch->trans_skb->len);
1288 CTCM_PR_DBGDATA("%s: pdu header and data for up"
1289 " to 32 bytes sent to vtam\n", __func__);
1290 CTCM_D3_DUMP((char *)p_header, min_t(int, skb->len, 32));
1291
1292 ch->collect_len -= skb->len;
1293 data_space -= skb->len;
1294 priv->stats.tx_packets++;
1295 priv->stats.tx_bytes += skb->len;
1296 refcount_dec(&skb->users);
1297 dev_kfree_skb_any(skb);
1298 peekskb = skb_peek(&ch->collect_queue);
1299 if (peekskb->len > data_space)
1300 break;
1301 i++;
1302 }
1303
1304 if (p_header)
1305 p_header->pdu_flag |= PDU_LAST;
1306
1307 header = skb_push(ch->trans_skb, TH_HEADER_LENGTH);
1308 memset(header, 0, TH_HEADER_LENGTH);
1309
1310 header->th_ch_flag = TH_HAS_PDU;
1311 ch->th_seq_num++;
1312 header->th_seq_num = ch->th_seq_num;
1313
1314 CTCM_PR_DBGDATA("%s: ToVTAM_th_seq= %08x\n" ,
1315 __func__, ch->th_seq_num);
1316
1317 CTCM_PR_DBGDATA("%s: trans_skb len:%04x \n",
1318 __func__, ch->trans_skb->len);
1319 CTCM_PR_DBGDATA("%s: up-to-50 bytes of trans_skb "
1320 "data to vtam from collect_q\n", __func__);
1321 CTCM_D3_DUMP((char *)ch->trans_skb->data,
1322 min_t(int, ch->trans_skb->len, 50));
1323
1324 spin_unlock(&ch->collect_lock);
1325 clear_normalized_cda(&ch->ccw[1]);
1326
1327 CTCM_PR_DBGDATA("ccwcda=0x%p data=0x%p\n",
1328 (void *)(unsigned long)ch->ccw[1].cda,
1329 ch->trans_skb->data);
1330 ch->ccw[1].count = ch->max_bufsize;
1331
1332 if (set_normalized_cda(&ch->ccw[1], ch->trans_skb->data)) {
1333 dev_kfree_skb_any(ch->trans_skb);
1334 ch->trans_skb = NULL;
1335 CTCM_DBF_TEXT_(MPC_TRACE, CTC_DBF_ERROR,
1336 "%s: %s: IDAL alloc failed",
1337 CTCM_FUNTAIL, ch->id);
1338 fsm_event(priv->mpcg->fsm, MPCG_EVENT_INOP, dev);
1339 return;
1340 }
1341
1342 CTCM_PR_DBGDATA("ccwcda=0x%p data=0x%p\n",
1343 (void *)(unsigned long)ch->ccw[1].cda,
1344 ch->trans_skb->data);
1345
1346 ch->ccw[1].count = ch->trans_skb->len;
1347 fsm_addtimer(&ch->timer, CTCM_TIME_5_SEC, CTC_EVENT_TIMER, ch);
1348 ch->prof.send_stamp = jiffies;
1349 if (do_debug_ccw)
1350 ctcmpc_dumpit((char *)&ch->ccw[0], sizeof(struct ccw1) * 3);
1351 rc = ccw_device_start(ch->cdev, &ch->ccw[0], 0, 0xff, 0);
1352 ch->prof.doios_multi++;
1353 if (rc != 0) {
1354 priv->stats.tx_dropped += i;
1355 priv->stats.tx_errors += i;
1356 fsm_deltimer(&ch->timer);
1357 ctcm_ccw_check_rc(ch, rc, "chained TX");
1358 }
1359 done:
1360 ctcm_clear_busy(dev);
1361 return;
1362 }
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372 static void ctcmpc_chx_rx(fsm_instance *fi, int event, void *arg)
1373 {
1374 struct channel *ch = arg;
1375 struct net_device *dev = ch->netdev;
1376 struct ctcm_priv *priv = dev->ml_priv;
1377 struct mpc_group *grp = priv->mpcg;
1378 struct sk_buff *skb = ch->trans_skb;
1379 struct sk_buff *new_skb;
1380 unsigned long saveflags = 0;
1381 int len = ch->max_bufsize - ch->irb->scsw.cmd.count;
1382
1383 CTCM_PR_DEBUG("%s: %s: cp:%i %s maxbuf : %04x, len: %04x\n",
1384 CTCM_FUNTAIL, dev->name, smp_processor_id(),
1385 ch->id, ch->max_bufsize, len);
1386 fsm_deltimer(&ch->timer);
1387
1388 if (skb == NULL) {
1389 CTCM_DBF_TEXT_(MPC_ERROR, CTC_DBF_ERROR,
1390 "%s(%s): TRANS_SKB = NULL",
1391 CTCM_FUNTAIL, dev->name);
1392 goto again;
1393 }
1394
1395 if (len < TH_HEADER_LENGTH) {
1396 CTCM_DBF_TEXT_(MPC_ERROR, CTC_DBF_ERROR,
1397 "%s(%s): packet length %d too short",
1398 CTCM_FUNTAIL, dev->name, len);
1399 priv->stats.rx_dropped++;
1400 priv->stats.rx_length_errors++;
1401 } else {
1402
1403 __u32 block_len = len;
1404 len = TH_HEADER_LENGTH + XID2_LENGTH + 4;
1405 new_skb = __dev_alloc_skb(ch->max_bufsize, GFP_ATOMIC);
1406
1407 if (new_skb == NULL) {
1408 CTCM_DBF_TEXT_(MPC_ERROR, CTC_DBF_ERROR,
1409 "%s(%s): skb allocation failed",
1410 CTCM_FUNTAIL, dev->name);
1411 fsm_event(priv->mpcg->fsm, MPCG_EVENT_INOP, dev);
1412 goto again;
1413 }
1414 switch (fsm_getstate(grp->fsm)) {
1415 case MPCG_STATE_RESET:
1416 case MPCG_STATE_INOP:
1417 dev_kfree_skb_any(new_skb);
1418 break;
1419 case MPCG_STATE_FLOWC:
1420 case MPCG_STATE_READY:
1421 skb_put_data(new_skb, skb->data, block_len);
1422 skb_queue_tail(&ch->io_queue, new_skb);
1423 tasklet_schedule(&ch->ch_tasklet);
1424 break;
1425 default:
1426 skb_put_data(new_skb, skb->data, len);
1427 skb_queue_tail(&ch->io_queue, new_skb);
1428 tasklet_hi_schedule(&ch->ch_tasklet);
1429 break;
1430 }
1431 }
1432
1433 again:
1434 switch (fsm_getstate(grp->fsm)) {
1435 int rc, dolock;
1436 case MPCG_STATE_FLOWC:
1437 case MPCG_STATE_READY:
1438 if (ctcm_checkalloc_buffer(ch))
1439 break;
1440 ch->trans_skb->data = ch->trans_skb_data;
1441 skb_reset_tail_pointer(ch->trans_skb);
1442 ch->trans_skb->len = 0;
1443 ch->ccw[1].count = ch->max_bufsize;
1444 if (do_debug_ccw)
1445 ctcmpc_dumpit((char *)&ch->ccw[0],
1446 sizeof(struct ccw1) * 3);
1447 dolock = !in_hardirq();
1448 if (dolock)
1449 spin_lock_irqsave(
1450 get_ccwdev_lock(ch->cdev), saveflags);
1451 rc = ccw_device_start(ch->cdev, &ch->ccw[0], 0, 0xff, 0);
1452 if (dolock)
1453 spin_unlock_irqrestore(
1454 get_ccwdev_lock(ch->cdev), saveflags);
1455 if (rc != 0)
1456 ctcm_ccw_check_rc(ch, rc, "normal RX");
1457 break;
1458 default:
1459 break;
1460 }
1461
1462 CTCM_PR_DEBUG("Exit %s: %s, ch=0x%p, id=%s\n",
1463 __func__, dev->name, ch, ch->id);
1464
1465 }
1466
1467
1468
1469
1470
1471
1472
1473
1474 static void ctcmpc_chx_firstio(fsm_instance *fi, int event, void *arg)
1475 {
1476 struct channel *ch = arg;
1477 struct net_device *dev = ch->netdev;
1478 struct ctcm_priv *priv = dev->ml_priv;
1479 struct mpc_group *gptr = priv->mpcg;
1480
1481 CTCM_PR_DEBUG("Enter %s: id=%s, ch=0x%p\n",
1482 __func__, ch->id, ch);
1483
1484 CTCM_DBF_TEXT_(MPC_TRACE, CTC_DBF_INFO,
1485 "%s: %s: chstate:%i, grpstate:%i, prot:%i\n",
1486 CTCM_FUNTAIL, ch->id, fsm_getstate(fi),
1487 fsm_getstate(gptr->fsm), ch->protocol);
1488
1489 if (fsm_getstate(fi) == CTC_STATE_TXIDLE)
1490 MPC_DBF_DEV_NAME(TRACE, dev, "remote side issued READ? ");
1491
1492 fsm_deltimer(&ch->timer);
1493 if (ctcm_checkalloc_buffer(ch))
1494 goto done;
1495
1496 switch (fsm_getstate(fi)) {
1497 case CTC_STATE_STARTRETRY:
1498 case CTC_STATE_SETUPWAIT:
1499 if (CHANNEL_DIRECTION(ch->flags) == CTCM_READ) {
1500 ctcmpc_chx_rxidle(fi, event, arg);
1501 } else {
1502 fsm_newstate(fi, CTC_STATE_TXIDLE);
1503 fsm_event(priv->fsm, DEV_EVENT_TXUP, dev);
1504 }
1505 goto done;
1506 default:
1507 break;
1508 }
1509
1510 fsm_newstate(fi, (CHANNEL_DIRECTION(ch->flags) == CTCM_READ)
1511 ? CTC_STATE_RXINIT : CTC_STATE_TXINIT);
1512
1513 done:
1514 CTCM_PR_DEBUG("Exit %s: id=%s, ch=0x%p\n",
1515 __func__, ch->id, ch);
1516 return;
1517 }
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528 void ctcmpc_chx_rxidle(fsm_instance *fi, int event, void *arg)
1529 {
1530 struct channel *ch = arg;
1531 struct net_device *dev = ch->netdev;
1532 struct ctcm_priv *priv = dev->ml_priv;
1533 struct mpc_group *grp = priv->mpcg;
1534 int rc;
1535 unsigned long saveflags = 0;
1536
1537 fsm_deltimer(&ch->timer);
1538 CTCM_PR_DEBUG("%s: %s: %s: cp:%i, chstate:%i grpstate:%i\n",
1539 __func__, ch->id, dev->name, smp_processor_id(),
1540 fsm_getstate(fi), fsm_getstate(grp->fsm));
1541
1542 fsm_newstate(fi, CTC_STATE_RXIDLE);
1543
1544
1545 switch (fsm_getstate(grp->fsm)) {
1546 case MPCG_STATE_FLOWC:
1547 case MPCG_STATE_READY:
1548 if (ctcm_checkalloc_buffer(ch))
1549 goto done;
1550 ch->trans_skb->data = ch->trans_skb_data;
1551 skb_reset_tail_pointer(ch->trans_skb);
1552 ch->trans_skb->len = 0;
1553 ch->ccw[1].count = ch->max_bufsize;
1554 CTCM_CCW_DUMP((char *)&ch->ccw[0], sizeof(struct ccw1) * 3);
1555 if (event == CTC_EVENT_START)
1556
1557 spin_lock_irqsave(get_ccwdev_lock(ch->cdev), saveflags);
1558 rc = ccw_device_start(ch->cdev, &ch->ccw[0], 0, 0xff, 0);
1559 if (event == CTC_EVENT_START)
1560 spin_unlock_irqrestore(
1561 get_ccwdev_lock(ch->cdev), saveflags);
1562 if (rc != 0) {
1563 fsm_newstate(fi, CTC_STATE_RXINIT);
1564 ctcm_ccw_check_rc(ch, rc, "initial RX");
1565 goto done;
1566 }
1567 break;
1568 default:
1569 break;
1570 }
1571
1572 fsm_event(priv->fsm, DEV_EVENT_RXUP, dev);
1573 done:
1574 return;
1575 }
1576
1577
1578
1579
1580
1581
1582 static void ctcmpc_chx_attn(fsm_instance *fsm, int event, void *arg)
1583 {
1584 struct channel *ch = arg;
1585 struct net_device *dev = ch->netdev;
1586 struct ctcm_priv *priv = dev->ml_priv;
1587 struct mpc_group *grp = priv->mpcg;
1588
1589 CTCM_PR_DEBUG("%s(%s): %s(ch=0x%p), cp=%i, ChStat:%s, GrpStat:%s\n",
1590 __func__, dev->name, ch->id, ch, smp_processor_id(),
1591 fsm_getstate_str(ch->fsm), fsm_getstate_str(grp->fsm));
1592
1593 switch (fsm_getstate(grp->fsm)) {
1594 case MPCG_STATE_XID2INITW:
1595
1596 if (!ch->in_mpcgroup)
1597 break;
1598 if (fsm_getstate(ch->fsm) == CH_XID0_PENDING) {
1599 fsm_deltimer(&grp->timer);
1600 fsm_addtimer(&grp->timer,
1601 MPC_XID_TIMEOUT_VALUE,
1602 MPCG_EVENT_TIMER, dev);
1603 fsm_event(grp->fsm, MPCG_EVENT_XID0DO, ch);
1604
1605 } else if (fsm_getstate(ch->fsm) < CH_XID7_PENDING1)
1606
1607 fsm_newstate(ch->fsm, CH_XID7_PENDING1);
1608 break;
1609 case MPCG_STATE_XID2INITX:
1610 case MPCG_STATE_XID0IOWAIT:
1611 case MPCG_STATE_XID0IOWAIX:
1612
1613
1614 if (fsm_getstate(ch->fsm) < CH_XID7_PENDING1)
1615 fsm_newstate(ch->fsm, CH_XID7_PENDING1);
1616 break;
1617 case MPCG_STATE_XID7INITW:
1618 case MPCG_STATE_XID7INITX:
1619 case MPCG_STATE_XID7INITI:
1620 case MPCG_STATE_XID7INITZ:
1621 switch (fsm_getstate(ch->fsm)) {
1622 case CH_XID7_PENDING:
1623 fsm_newstate(ch->fsm, CH_XID7_PENDING1);
1624 break;
1625 case CH_XID7_PENDING2:
1626 fsm_newstate(ch->fsm, CH_XID7_PENDING3);
1627 break;
1628 }
1629 fsm_event(grp->fsm, MPCG_EVENT_XID7DONE, dev);
1630 break;
1631 }
1632
1633 return;
1634 }
1635
1636
1637
1638
1639
1640
1641 static void ctcmpc_chx_attnbusy(fsm_instance *fsm, int event, void *arg)
1642 {
1643 struct channel *ch = arg;
1644 struct net_device *dev = ch->netdev;
1645 struct ctcm_priv *priv = dev->ml_priv;
1646 struct mpc_group *grp = priv->mpcg;
1647
1648 CTCM_PR_DEBUG("%s(%s): %s\n ChState:%s GrpState:%s\n",
1649 __func__, dev->name, ch->id,
1650 fsm_getstate_str(ch->fsm), fsm_getstate_str(grp->fsm));
1651
1652 fsm_deltimer(&ch->timer);
1653
1654 switch (fsm_getstate(grp->fsm)) {
1655 case MPCG_STATE_XID0IOWAIT:
1656
1657
1658
1659 grp->changed_side = 1;
1660 fsm_newstate(grp->fsm, MPCG_STATE_XID2INITW);
1661 break;
1662 case MPCG_STATE_XID2INITW:
1663 if (grp->changed_side == 1) {
1664 grp->changed_side = 2;
1665 break;
1666 }
1667
1668
1669
1670 if (grp->estconnfunc)
1671 goto done;
1672
1673
1674
1675
1676
1677 if (fsm_getstate(ch->fsm) == CH_XID0_INPROGRESS) {
1678 fsm_newstate(ch->fsm, CH_XID0_PENDING) ;
1679 fsm_deltimer(&grp->timer);
1680 goto done;
1681 }
1682 fsm_event(grp->fsm, MPCG_EVENT_INOP, dev);
1683 goto done;
1684 case MPCG_STATE_XID2INITX:
1685
1686
1687
1688 if (grp->changed_side == 1) {
1689 grp->changed_side = 2;
1690 break;
1691 }
1692 fallthrough;
1693 case MPCG_STATE_XID0IOWAIX:
1694 case MPCG_STATE_XID7INITW:
1695 case MPCG_STATE_XID7INITX:
1696 case MPCG_STATE_XID7INITI:
1697 case MPCG_STATE_XID7INITZ:
1698 default:
1699
1700
1701
1702 fsm_event(grp->fsm, MPCG_EVENT_INOP, dev);
1703 goto done;
1704 }
1705
1706 if (grp->changed_side == 1) {
1707 fsm_deltimer(&grp->timer);
1708 fsm_addtimer(&grp->timer, MPC_XID_TIMEOUT_VALUE,
1709 MPCG_EVENT_TIMER, dev);
1710 }
1711 if (ch->in_mpcgroup)
1712 fsm_event(grp->fsm, MPCG_EVENT_XID0DO, ch);
1713 else
1714 CTCM_DBF_TEXT_(MPC_ERROR, CTC_DBF_ERROR,
1715 "%s(%s): channel %s not added to group",
1716 CTCM_FUNTAIL, dev->name, ch->id);
1717
1718 done:
1719 return;
1720 }
1721
1722
1723
1724
1725
1726
1727 static void ctcmpc_chx_resend(fsm_instance *fsm, int event, void *arg)
1728 {
1729 struct channel *ch = arg;
1730 struct net_device *dev = ch->netdev;
1731 struct ctcm_priv *priv = dev->ml_priv;
1732 struct mpc_group *grp = priv->mpcg;
1733
1734 fsm_event(grp->fsm, MPCG_EVENT_XID0DO, ch);
1735 return;
1736 }
1737
1738
1739
1740
1741
1742
1743 static void ctcmpc_chx_send_sweep(fsm_instance *fsm, int event, void *arg)
1744 {
1745 struct channel *ach = arg;
1746 struct net_device *dev = ach->netdev;
1747 struct ctcm_priv *priv = dev->ml_priv;
1748 struct mpc_group *grp = priv->mpcg;
1749 struct channel *wch = priv->channel[CTCM_WRITE];
1750 struct channel *rch = priv->channel[CTCM_READ];
1751 struct sk_buff *skb;
1752 struct th_sweep *header;
1753 int rc = 0;
1754 unsigned long saveflags = 0;
1755
1756 CTCM_PR_DEBUG("ctcmpc enter: %s(): cp=%i ch=0x%p id=%s\n",
1757 __func__, smp_processor_id(), ach, ach->id);
1758
1759 if (grp->in_sweep == 0)
1760 goto done;
1761
1762 CTCM_PR_DBGDATA("%s: 1: ToVTAM_th_seq= %08x\n" ,
1763 __func__, wch->th_seq_num);
1764 CTCM_PR_DBGDATA("%s: 1: FromVTAM_th_seq= %08x\n" ,
1765 __func__, rch->th_seq_num);
1766
1767 if (fsm_getstate(wch->fsm) != CTC_STATE_TXIDLE) {
1768
1769 fsm_addtimer(&wch->sweep_timer,
1770 200, CTC_EVENT_RSWEEP_TIMER, wch);
1771 goto done;
1772 }
1773
1774 skb = skb_dequeue(&wch->sweep_queue);
1775 if (!skb)
1776 goto done;
1777
1778 if (set_normalized_cda(&wch->ccw[4], skb->data)) {
1779 grp->in_sweep = 0;
1780 ctcm_clear_busy_do(dev);
1781 dev_kfree_skb_any(skb);
1782 fsm_event(grp->fsm, MPCG_EVENT_INOP, dev);
1783 goto done;
1784 } else {
1785 refcount_inc(&skb->users);
1786 skb_queue_tail(&wch->io_queue, skb);
1787 }
1788
1789
1790 wch->ccw[4].count = skb->len;
1791
1792 header = (struct th_sweep *)skb->data;
1793 switch (header->th.th_ch_flag) {
1794 case TH_SWEEP_REQ:
1795 grp->sweep_req_pend_num--;
1796 break;
1797 case TH_SWEEP_RESP:
1798 grp->sweep_rsp_pend_num--;
1799 break;
1800 }
1801
1802 header->sw.th_last_seq = wch->th_seq_num;
1803
1804 CTCM_CCW_DUMP((char *)&wch->ccw[3], sizeof(struct ccw1) * 3);
1805 CTCM_PR_DBGDATA("%s: sweep packet\n", __func__);
1806 CTCM_D3_DUMP((char *)header, TH_SWEEP_LENGTH);
1807
1808 fsm_addtimer(&wch->timer, CTCM_TIME_5_SEC, CTC_EVENT_TIMER, wch);
1809 fsm_newstate(wch->fsm, CTC_STATE_TX);
1810
1811 spin_lock_irqsave(get_ccwdev_lock(wch->cdev), saveflags);
1812 wch->prof.send_stamp = jiffies;
1813 rc = ccw_device_start(wch->cdev, &wch->ccw[3], 0, 0xff, 0);
1814 spin_unlock_irqrestore(get_ccwdev_lock(wch->cdev), saveflags);
1815
1816 if ((grp->sweep_req_pend_num == 0) &&
1817 (grp->sweep_rsp_pend_num == 0)) {
1818 grp->in_sweep = 0;
1819 rch->th_seq_num = 0x00;
1820 wch->th_seq_num = 0x00;
1821 ctcm_clear_busy_do(dev);
1822 }
1823
1824 CTCM_PR_DBGDATA("%s: To-/From-VTAM_th_seq = %08x/%08x\n" ,
1825 __func__, wch->th_seq_num, rch->th_seq_num);
1826
1827 if (rc != 0)
1828 ctcm_ccw_check_rc(wch, rc, "send sweep");
1829
1830 done:
1831 return;
1832 }
1833
1834
1835
1836
1837
1838
1839 const fsm_node ctcmpc_ch_fsm[] = {
1840 { CTC_STATE_STOPPED, CTC_EVENT_STOP, ctcm_action_nop },
1841 { CTC_STATE_STOPPED, CTC_EVENT_START, ctcm_chx_start },
1842 { CTC_STATE_STOPPED, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1843 { CTC_STATE_STOPPED, CTC_EVENT_FINSTAT, ctcm_action_nop },
1844 { CTC_STATE_STOPPED, CTC_EVENT_MC_FAIL, ctcm_action_nop },
1845
1846 { CTC_STATE_NOTOP, CTC_EVENT_STOP, ctcm_chx_stop },
1847 { CTC_STATE_NOTOP, CTC_EVENT_START, ctcm_action_nop },
1848 { CTC_STATE_NOTOP, CTC_EVENT_FINSTAT, ctcm_action_nop },
1849 { CTC_STATE_NOTOP, CTC_EVENT_MC_FAIL, ctcm_action_nop },
1850 { CTC_STATE_NOTOP, CTC_EVENT_MC_GOOD, ctcm_chx_start },
1851 { CTC_STATE_NOTOP, CTC_EVENT_UC_RCRESET, ctcm_chx_stop },
1852 { CTC_STATE_NOTOP, CTC_EVENT_UC_RSRESET, ctcm_chx_stop },
1853 { CTC_STATE_NOTOP, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1854
1855 { CTC_STATE_STARTWAIT, CTC_EVENT_STOP, ctcm_chx_haltio },
1856 { CTC_STATE_STARTWAIT, CTC_EVENT_START, ctcm_action_nop },
1857 { CTC_STATE_STARTWAIT, CTC_EVENT_FINSTAT, ctcm_chx_setmode },
1858 { CTC_STATE_STARTWAIT, CTC_EVENT_TIMER, ctcm_chx_setuperr },
1859 { CTC_STATE_STARTWAIT, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1860 { CTC_STATE_STARTWAIT, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1861
1862 { CTC_STATE_STARTRETRY, CTC_EVENT_STOP, ctcm_chx_haltio },
1863 { CTC_STATE_STARTRETRY, CTC_EVENT_TIMER, ctcm_chx_setmode },
1864 { CTC_STATE_STARTRETRY, CTC_EVENT_FINSTAT, ctcm_chx_setmode },
1865 { CTC_STATE_STARTRETRY, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1866 { CTC_STATE_STARTRETRY, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1867
1868 { CTC_STATE_SETUPWAIT, CTC_EVENT_STOP, ctcm_chx_haltio },
1869 { CTC_STATE_SETUPWAIT, CTC_EVENT_START, ctcm_action_nop },
1870 { CTC_STATE_SETUPWAIT, CTC_EVENT_FINSTAT, ctcmpc_chx_firstio },
1871 { CTC_STATE_SETUPWAIT, CTC_EVENT_UC_RCRESET, ctcm_chx_setuperr },
1872 { CTC_STATE_SETUPWAIT, CTC_EVENT_UC_RSRESET, ctcm_chx_setuperr },
1873 { CTC_STATE_SETUPWAIT, CTC_EVENT_TIMER, ctcm_chx_setmode },
1874 { CTC_STATE_SETUPWAIT, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1875 { CTC_STATE_SETUPWAIT, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1876
1877 { CTC_STATE_RXINIT, CTC_EVENT_STOP, ctcm_chx_haltio },
1878 { CTC_STATE_RXINIT, CTC_EVENT_START, ctcm_action_nop },
1879 { CTC_STATE_RXINIT, CTC_EVENT_FINSTAT, ctcmpc_chx_rxidle },
1880 { CTC_STATE_RXINIT, CTC_EVENT_UC_RCRESET, ctcm_chx_rxiniterr },
1881 { CTC_STATE_RXINIT, CTC_EVENT_UC_RSRESET, ctcm_chx_rxiniterr },
1882 { CTC_STATE_RXINIT, CTC_EVENT_TIMER, ctcm_chx_rxiniterr },
1883 { CTC_STATE_RXINIT, CTC_EVENT_ATTNBUSY, ctcm_chx_rxinitfail },
1884 { CTC_STATE_RXINIT, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1885 { CTC_STATE_RXINIT, CTC_EVENT_UC_ZERO, ctcmpc_chx_firstio },
1886 { CTC_STATE_RXINIT, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1887
1888 { CH_XID0_PENDING, CTC_EVENT_FINSTAT, ctcm_action_nop },
1889 { CH_XID0_PENDING, CTC_EVENT_ATTN, ctcmpc_chx_attn },
1890 { CH_XID0_PENDING, CTC_EVENT_STOP, ctcm_chx_haltio },
1891 { CH_XID0_PENDING, CTC_EVENT_START, ctcm_action_nop },
1892 { CH_XID0_PENDING, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1893 { CH_XID0_PENDING, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1894 { CH_XID0_PENDING, CTC_EVENT_UC_RCRESET, ctcm_chx_setuperr },
1895 { CH_XID0_PENDING, CTC_EVENT_UC_RSRESET, ctcm_chx_setuperr },
1896 { CH_XID0_PENDING, CTC_EVENT_UC_RSRESET, ctcm_chx_setuperr },
1897 { CH_XID0_PENDING, CTC_EVENT_ATTNBUSY, ctcm_chx_iofatal },
1898
1899 { CH_XID0_INPROGRESS, CTC_EVENT_FINSTAT, ctcmpc_chx_rx },
1900 { CH_XID0_INPROGRESS, CTC_EVENT_ATTN, ctcmpc_chx_attn },
1901 { CH_XID0_INPROGRESS, CTC_EVENT_STOP, ctcm_chx_haltio },
1902 { CH_XID0_INPROGRESS, CTC_EVENT_START, ctcm_action_nop },
1903 { CH_XID0_INPROGRESS, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1904 { CH_XID0_INPROGRESS, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1905 { CH_XID0_INPROGRESS, CTC_EVENT_UC_ZERO, ctcmpc_chx_rx },
1906 { CH_XID0_INPROGRESS, CTC_EVENT_UC_RCRESET, ctcm_chx_setuperr },
1907 { CH_XID0_INPROGRESS, CTC_EVENT_ATTNBUSY, ctcmpc_chx_attnbusy },
1908 { CH_XID0_INPROGRESS, CTC_EVENT_TIMER, ctcmpc_chx_resend },
1909 { CH_XID0_INPROGRESS, CTC_EVENT_IO_EBUSY, ctcm_chx_fail },
1910
1911 { CH_XID7_PENDING, CTC_EVENT_FINSTAT, ctcmpc_chx_rx },
1912 { CH_XID7_PENDING, CTC_EVENT_ATTN, ctcmpc_chx_attn },
1913 { CH_XID7_PENDING, CTC_EVENT_STOP, ctcm_chx_haltio },
1914 { CH_XID7_PENDING, CTC_EVENT_START, ctcm_action_nop },
1915 { CH_XID7_PENDING, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1916 { CH_XID7_PENDING, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1917 { CH_XID7_PENDING, CTC_EVENT_UC_ZERO, ctcmpc_chx_rx },
1918 { CH_XID7_PENDING, CTC_EVENT_UC_RCRESET, ctcm_chx_setuperr },
1919 { CH_XID7_PENDING, CTC_EVENT_UC_RSRESET, ctcm_chx_setuperr },
1920 { CH_XID7_PENDING, CTC_EVENT_UC_RSRESET, ctcm_chx_setuperr },
1921 { CH_XID7_PENDING, CTC_EVENT_ATTNBUSY, ctcm_chx_iofatal },
1922 { CH_XID7_PENDING, CTC_EVENT_TIMER, ctcmpc_chx_resend },
1923 { CH_XID7_PENDING, CTC_EVENT_IO_EBUSY, ctcm_chx_fail },
1924
1925 { CH_XID7_PENDING1, CTC_EVENT_FINSTAT, ctcmpc_chx_rx },
1926 { CH_XID7_PENDING1, CTC_EVENT_ATTN, ctcmpc_chx_attn },
1927 { CH_XID7_PENDING1, CTC_EVENT_STOP, ctcm_chx_haltio },
1928 { CH_XID7_PENDING1, CTC_EVENT_START, ctcm_action_nop },
1929 { CH_XID7_PENDING1, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1930 { CH_XID7_PENDING1, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1931 { CH_XID7_PENDING1, CTC_EVENT_UC_ZERO, ctcmpc_chx_rx },
1932 { CH_XID7_PENDING1, CTC_EVENT_UC_RCRESET, ctcm_chx_setuperr },
1933 { CH_XID7_PENDING1, CTC_EVENT_UC_RSRESET, ctcm_chx_setuperr },
1934 { CH_XID7_PENDING1, CTC_EVENT_ATTNBUSY, ctcm_chx_iofatal },
1935 { CH_XID7_PENDING1, CTC_EVENT_TIMER, ctcmpc_chx_resend },
1936 { CH_XID7_PENDING1, CTC_EVENT_IO_EBUSY, ctcm_chx_fail },
1937
1938 { CH_XID7_PENDING2, CTC_EVENT_FINSTAT, ctcmpc_chx_rx },
1939 { CH_XID7_PENDING2, CTC_EVENT_ATTN, ctcmpc_chx_attn },
1940 { CH_XID7_PENDING2, CTC_EVENT_STOP, ctcm_chx_haltio },
1941 { CH_XID7_PENDING2, CTC_EVENT_START, ctcm_action_nop },
1942 { CH_XID7_PENDING2, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1943 { CH_XID7_PENDING2, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1944 { CH_XID7_PENDING2, CTC_EVENT_UC_ZERO, ctcmpc_chx_rx },
1945 { CH_XID7_PENDING2, CTC_EVENT_UC_RCRESET, ctcm_chx_setuperr },
1946 { CH_XID7_PENDING2, CTC_EVENT_UC_RSRESET, ctcm_chx_setuperr },
1947 { CH_XID7_PENDING2, CTC_EVENT_ATTNBUSY, ctcm_chx_iofatal },
1948 { CH_XID7_PENDING2, CTC_EVENT_TIMER, ctcmpc_chx_resend },
1949 { CH_XID7_PENDING2, CTC_EVENT_IO_EBUSY, ctcm_chx_fail },
1950
1951 { CH_XID7_PENDING3, CTC_EVENT_FINSTAT, ctcmpc_chx_rx },
1952 { CH_XID7_PENDING3, CTC_EVENT_ATTN, ctcmpc_chx_attn },
1953 { CH_XID7_PENDING3, CTC_EVENT_STOP, ctcm_chx_haltio },
1954 { CH_XID7_PENDING3, CTC_EVENT_START, ctcm_action_nop },
1955 { CH_XID7_PENDING3, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1956 { CH_XID7_PENDING3, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1957 { CH_XID7_PENDING3, CTC_EVENT_UC_ZERO, ctcmpc_chx_rx },
1958 { CH_XID7_PENDING3, CTC_EVENT_UC_RCRESET, ctcm_chx_setuperr },
1959 { CH_XID7_PENDING3, CTC_EVENT_UC_RSRESET, ctcm_chx_setuperr },
1960 { CH_XID7_PENDING3, CTC_EVENT_ATTNBUSY, ctcm_chx_iofatal },
1961 { CH_XID7_PENDING3, CTC_EVENT_TIMER, ctcmpc_chx_resend },
1962 { CH_XID7_PENDING3, CTC_EVENT_IO_EBUSY, ctcm_chx_fail },
1963
1964 { CH_XID7_PENDING4, CTC_EVENT_FINSTAT, ctcmpc_chx_rx },
1965 { CH_XID7_PENDING4, CTC_EVENT_ATTN, ctcmpc_chx_attn },
1966 { CH_XID7_PENDING4, CTC_EVENT_STOP, ctcm_chx_haltio },
1967 { CH_XID7_PENDING4, CTC_EVENT_START, ctcm_action_nop },
1968 { CH_XID7_PENDING4, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1969 { CH_XID7_PENDING4, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1970 { CH_XID7_PENDING4, CTC_EVENT_UC_ZERO, ctcmpc_chx_rx },
1971 { CH_XID7_PENDING4, CTC_EVENT_UC_RCRESET, ctcm_chx_setuperr },
1972 { CH_XID7_PENDING4, CTC_EVENT_UC_RSRESET, ctcm_chx_setuperr },
1973 { CH_XID7_PENDING4, CTC_EVENT_ATTNBUSY, ctcm_chx_iofatal },
1974 { CH_XID7_PENDING4, CTC_EVENT_TIMER, ctcmpc_chx_resend },
1975 { CH_XID7_PENDING4, CTC_EVENT_IO_EBUSY, ctcm_chx_fail },
1976
1977 { CTC_STATE_RXIDLE, CTC_EVENT_STOP, ctcm_chx_haltio },
1978 { CTC_STATE_RXIDLE, CTC_EVENT_START, ctcm_action_nop },
1979 { CTC_STATE_RXIDLE, CTC_EVENT_FINSTAT, ctcmpc_chx_rx },
1980 { CTC_STATE_RXIDLE, CTC_EVENT_UC_RCRESET, ctcm_chx_rxdisc },
1981 { CTC_STATE_RXIDLE, CTC_EVENT_UC_RSRESET, ctcm_chx_fail },
1982 { CTC_STATE_RXIDLE, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1983 { CTC_STATE_RXIDLE, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1984 { CTC_STATE_RXIDLE, CTC_EVENT_UC_ZERO, ctcmpc_chx_rx },
1985
1986 { CTC_STATE_TXINIT, CTC_EVENT_STOP, ctcm_chx_haltio },
1987 { CTC_STATE_TXINIT, CTC_EVENT_START, ctcm_action_nop },
1988 { CTC_STATE_TXINIT, CTC_EVENT_FINSTAT, ctcm_chx_txidle },
1989 { CTC_STATE_TXINIT, CTC_EVENT_UC_RCRESET, ctcm_chx_txiniterr },
1990 { CTC_STATE_TXINIT, CTC_EVENT_UC_RSRESET, ctcm_chx_txiniterr },
1991 { CTC_STATE_TXINIT, CTC_EVENT_TIMER, ctcm_chx_txiniterr },
1992 { CTC_STATE_TXINIT, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
1993 { CTC_STATE_TXINIT, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
1994 { CTC_STATE_TXINIT, CTC_EVENT_RSWEEP_TIMER, ctcmpc_chx_send_sweep },
1995
1996 { CTC_STATE_TXIDLE, CTC_EVENT_STOP, ctcm_chx_haltio },
1997 { CTC_STATE_TXIDLE, CTC_EVENT_START, ctcm_action_nop },
1998 { CTC_STATE_TXIDLE, CTC_EVENT_FINSTAT, ctcmpc_chx_firstio },
1999 { CTC_STATE_TXIDLE, CTC_EVENT_UC_RCRESET, ctcm_chx_fail },
2000 { CTC_STATE_TXIDLE, CTC_EVENT_UC_RSRESET, ctcm_chx_fail },
2001 { CTC_STATE_TXIDLE, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
2002 { CTC_STATE_TXIDLE, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
2003 { CTC_STATE_TXIDLE, CTC_EVENT_RSWEEP_TIMER, ctcmpc_chx_send_sweep },
2004
2005 { CTC_STATE_TERM, CTC_EVENT_STOP, ctcm_action_nop },
2006 { CTC_STATE_TERM, CTC_EVENT_START, ctcm_chx_restart },
2007 { CTC_STATE_TERM, CTC_EVENT_FINSTAT, ctcm_chx_stopped },
2008 { CTC_STATE_TERM, CTC_EVENT_UC_RCRESET, ctcm_action_nop },
2009 { CTC_STATE_TERM, CTC_EVENT_UC_RSRESET, ctcm_action_nop },
2010 { CTC_STATE_TERM, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
2011 { CTC_STATE_TERM, CTC_EVENT_IO_EBUSY, ctcm_chx_fail },
2012 { CTC_STATE_TERM, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
2013
2014 { CTC_STATE_DTERM, CTC_EVENT_STOP, ctcm_chx_haltio },
2015 { CTC_STATE_DTERM, CTC_EVENT_START, ctcm_chx_restart },
2016 { CTC_STATE_DTERM, CTC_EVENT_FINSTAT, ctcm_chx_setmode },
2017 { CTC_STATE_DTERM, CTC_EVENT_UC_RCRESET, ctcm_action_nop },
2018 { CTC_STATE_DTERM, CTC_EVENT_UC_RSRESET, ctcm_action_nop },
2019 { CTC_STATE_DTERM, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
2020 { CTC_STATE_DTERM, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
2021
2022 { CTC_STATE_TX, CTC_EVENT_STOP, ctcm_chx_haltio },
2023 { CTC_STATE_TX, CTC_EVENT_START, ctcm_action_nop },
2024 { CTC_STATE_TX, CTC_EVENT_FINSTAT, ctcmpc_chx_txdone },
2025 { CTC_STATE_TX, CTC_EVENT_UC_RCRESET, ctcm_chx_fail },
2026 { CTC_STATE_TX, CTC_EVENT_UC_RSRESET, ctcm_chx_fail },
2027 { CTC_STATE_TX, CTC_EVENT_TIMER, ctcm_chx_txretry },
2028 { CTC_STATE_TX, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
2029 { CTC_STATE_TX, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
2030 { CTC_STATE_TX, CTC_EVENT_RSWEEP_TIMER, ctcmpc_chx_send_sweep },
2031 { CTC_STATE_TX, CTC_EVENT_IO_EBUSY, ctcm_chx_fail },
2032
2033 { CTC_STATE_RXERR, CTC_EVENT_STOP, ctcm_chx_haltio },
2034 { CTC_STATE_TXERR, CTC_EVENT_STOP, ctcm_chx_haltio },
2035 { CTC_STATE_TXERR, CTC_EVENT_IO_ENODEV, ctcm_chx_iofatal },
2036 { CTC_STATE_TXERR, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
2037 { CTC_STATE_RXERR, CTC_EVENT_MC_FAIL, ctcm_chx_fail },
2038 };
2039
2040 int mpc_ch_fsm_len = ARRAY_SIZE(ctcmpc_ch_fsm);
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053 static void dev_action_start(fsm_instance *fi, int event, void *arg)
2054 {
2055 struct net_device *dev = arg;
2056 struct ctcm_priv *priv = dev->ml_priv;
2057 int direction;
2058
2059 CTCMY_DBF_DEV_NAME(SETUP, dev, "");
2060
2061 fsm_deltimer(&priv->restart_timer);
2062 fsm_newstate(fi, DEV_STATE_STARTWAIT_RXTX);
2063 if (IS_MPC(priv))
2064 priv->mpcg->channels_terminating = 0;
2065 for (direction = CTCM_READ; direction <= CTCM_WRITE; direction++) {
2066 struct channel *ch = priv->channel[direction];
2067 fsm_event(ch->fsm, CTC_EVENT_START, ch);
2068 }
2069 }
2070
2071
2072
2073
2074
2075
2076
2077
2078 static void dev_action_stop(fsm_instance *fi, int event, void *arg)
2079 {
2080 int direction;
2081 struct net_device *dev = arg;
2082 struct ctcm_priv *priv = dev->ml_priv;
2083
2084 CTCMY_DBF_DEV_NAME(SETUP, dev, "");
2085
2086 fsm_newstate(fi, DEV_STATE_STOPWAIT_RXTX);
2087 for (direction = CTCM_READ; direction <= CTCM_WRITE; direction++) {
2088 struct channel *ch = priv->channel[direction];
2089 fsm_event(ch->fsm, CTC_EVENT_STOP, ch);
2090 ch->th_seq_num = 0x00;
2091 CTCM_PR_DEBUG("%s: CH_th_seq= %08x\n",
2092 __func__, ch->th_seq_num);
2093 }
2094 if (IS_MPC(priv))
2095 fsm_newstate(priv->mpcg->fsm, MPCG_STATE_RESET);
2096 }
2097
2098 static void dev_action_restart(fsm_instance *fi, int event, void *arg)
2099 {
2100 int restart_timer;
2101 struct net_device *dev = arg;
2102 struct ctcm_priv *priv = dev->ml_priv;
2103
2104 CTCMY_DBF_DEV_NAME(TRACE, dev, "");
2105
2106 if (IS_MPC(priv)) {
2107 restart_timer = CTCM_TIME_1_SEC;
2108 } else {
2109 restart_timer = CTCM_TIME_5_SEC;
2110 }
2111 dev_info(&dev->dev, "Restarting device\n");
2112
2113 dev_action_stop(fi, event, arg);
2114 fsm_event(priv->fsm, DEV_EVENT_STOP, dev);
2115 if (IS_MPC(priv))
2116 fsm_newstate(priv->mpcg->fsm, MPCG_STATE_RESET);
2117
2118
2119
2120
2121 fsm_addtimer(&priv->restart_timer, restart_timer,
2122 DEV_EVENT_START, dev);
2123 }
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133 static void dev_action_chup(fsm_instance *fi, int event, void *arg)
2134 {
2135 struct net_device *dev = arg;
2136 struct ctcm_priv *priv = dev->ml_priv;
2137 int dev_stat = fsm_getstate(fi);
2138
2139 CTCM_DBF_TEXT_(SETUP, CTC_DBF_NOTICE,
2140 "%s(%s): priv = %p [%d,%d]\n ", CTCM_FUNTAIL,
2141 dev->name, dev->ml_priv, dev_stat, event);
2142
2143 switch (fsm_getstate(fi)) {
2144 case DEV_STATE_STARTWAIT_RXTX:
2145 if (event == DEV_EVENT_RXUP)
2146 fsm_newstate(fi, DEV_STATE_STARTWAIT_TX);
2147 else
2148 fsm_newstate(fi, DEV_STATE_STARTWAIT_RX);
2149 break;
2150 case DEV_STATE_STARTWAIT_RX:
2151 if (event == DEV_EVENT_RXUP) {
2152 fsm_newstate(fi, DEV_STATE_RUNNING);
2153 dev_info(&dev->dev,
2154 "Connected with remote side\n");
2155 ctcm_clear_busy(dev);
2156 }
2157 break;
2158 case DEV_STATE_STARTWAIT_TX:
2159 if (event == DEV_EVENT_TXUP) {
2160 fsm_newstate(fi, DEV_STATE_RUNNING);
2161 dev_info(&dev->dev,
2162 "Connected with remote side\n");
2163 ctcm_clear_busy(dev);
2164 }
2165 break;
2166 case DEV_STATE_STOPWAIT_TX:
2167 if (event == DEV_EVENT_RXUP)
2168 fsm_newstate(fi, DEV_STATE_STOPWAIT_RXTX);
2169 break;
2170 case DEV_STATE_STOPWAIT_RX:
2171 if (event == DEV_EVENT_TXUP)
2172 fsm_newstate(fi, DEV_STATE_STOPWAIT_RXTX);
2173 break;
2174 }
2175
2176 if (IS_MPC(priv)) {
2177 if (event == DEV_EVENT_RXUP)
2178 mpc_channel_action(priv->channel[CTCM_READ],
2179 CTCM_READ, MPC_CHANNEL_ADD);
2180 else
2181 mpc_channel_action(priv->channel[CTCM_WRITE],
2182 CTCM_WRITE, MPC_CHANNEL_ADD);
2183 }
2184 }
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194 static void dev_action_chdown(fsm_instance *fi, int event, void *arg)
2195 {
2196
2197 struct net_device *dev = arg;
2198 struct ctcm_priv *priv = dev->ml_priv;
2199
2200 CTCMY_DBF_DEV_NAME(SETUP, dev, "");
2201
2202 switch (fsm_getstate(fi)) {
2203 case DEV_STATE_RUNNING:
2204 if (event == DEV_EVENT_TXDOWN)
2205 fsm_newstate(fi, DEV_STATE_STARTWAIT_TX);
2206 else
2207 fsm_newstate(fi, DEV_STATE_STARTWAIT_RX);
2208 break;
2209 case DEV_STATE_STARTWAIT_RX:
2210 if (event == DEV_EVENT_TXDOWN)
2211 fsm_newstate(fi, DEV_STATE_STARTWAIT_RXTX);
2212 break;
2213 case DEV_STATE_STARTWAIT_TX:
2214 if (event == DEV_EVENT_RXDOWN)
2215 fsm_newstate(fi, DEV_STATE_STARTWAIT_RXTX);
2216 break;
2217 case DEV_STATE_STOPWAIT_RXTX:
2218 if (event == DEV_EVENT_TXDOWN)
2219 fsm_newstate(fi, DEV_STATE_STOPWAIT_RX);
2220 else
2221 fsm_newstate(fi, DEV_STATE_STOPWAIT_TX);
2222 break;
2223 case DEV_STATE_STOPWAIT_RX:
2224 if (event == DEV_EVENT_RXDOWN)
2225 fsm_newstate(fi, DEV_STATE_STOPPED);
2226 break;
2227 case DEV_STATE_STOPWAIT_TX:
2228 if (event == DEV_EVENT_TXDOWN)
2229 fsm_newstate(fi, DEV_STATE_STOPPED);
2230 break;
2231 }
2232 if (IS_MPC(priv)) {
2233 if (event == DEV_EVENT_RXDOWN)
2234 mpc_channel_action(priv->channel[CTCM_READ],
2235 CTCM_READ, MPC_CHANNEL_REMOVE);
2236 else
2237 mpc_channel_action(priv->channel[CTCM_WRITE],
2238 CTCM_WRITE, MPC_CHANNEL_REMOVE);
2239 }
2240 }
2241
2242 const fsm_node dev_fsm[] = {
2243 { DEV_STATE_STOPPED, DEV_EVENT_START, dev_action_start },
2244 { DEV_STATE_STOPWAIT_RXTX, DEV_EVENT_START, dev_action_start },
2245 { DEV_STATE_STOPWAIT_RXTX, DEV_EVENT_RXDOWN, dev_action_chdown },
2246 { DEV_STATE_STOPWAIT_RXTX, DEV_EVENT_TXDOWN, dev_action_chdown },
2247 { DEV_STATE_STOPWAIT_RXTX, DEV_EVENT_RESTART, dev_action_restart },
2248 { DEV_STATE_STOPWAIT_RX, DEV_EVENT_START, dev_action_start },
2249 { DEV_STATE_STOPWAIT_RX, DEV_EVENT_RXUP, dev_action_chup },
2250 { DEV_STATE_STOPWAIT_RX, DEV_EVENT_TXUP, dev_action_chup },
2251 { DEV_STATE_STOPWAIT_RX, DEV_EVENT_RXDOWN, dev_action_chdown },
2252 { DEV_STATE_STOPWAIT_RX, DEV_EVENT_RESTART, dev_action_restart },
2253 { DEV_STATE_STOPWAIT_TX, DEV_EVENT_START, dev_action_start },
2254 { DEV_STATE_STOPWAIT_TX, DEV_EVENT_RXUP, dev_action_chup },
2255 { DEV_STATE_STOPWAIT_TX, DEV_EVENT_TXUP, dev_action_chup },
2256 { DEV_STATE_STOPWAIT_TX, DEV_EVENT_TXDOWN, dev_action_chdown },
2257 { DEV_STATE_STOPWAIT_TX, DEV_EVENT_RESTART, dev_action_restart },
2258 { DEV_STATE_STARTWAIT_RXTX, DEV_EVENT_STOP, dev_action_stop },
2259 { DEV_STATE_STARTWAIT_RXTX, DEV_EVENT_RXUP, dev_action_chup },
2260 { DEV_STATE_STARTWAIT_RXTX, DEV_EVENT_TXUP, dev_action_chup },
2261 { DEV_STATE_STARTWAIT_RXTX, DEV_EVENT_RXDOWN, dev_action_chdown },
2262 { DEV_STATE_STARTWAIT_RXTX, DEV_EVENT_TXDOWN, dev_action_chdown },
2263 { DEV_STATE_STARTWAIT_RXTX, DEV_EVENT_RESTART, dev_action_restart },
2264 { DEV_STATE_STARTWAIT_TX, DEV_EVENT_STOP, dev_action_stop },
2265 { DEV_STATE_STARTWAIT_TX, DEV_EVENT_RXUP, dev_action_chup },
2266 { DEV_STATE_STARTWAIT_TX, DEV_EVENT_TXUP, dev_action_chup },
2267 { DEV_STATE_STARTWAIT_TX, DEV_EVENT_RXDOWN, dev_action_chdown },
2268 { DEV_STATE_STARTWAIT_TX, DEV_EVENT_RESTART, dev_action_restart },
2269 { DEV_STATE_STARTWAIT_RX, DEV_EVENT_STOP, dev_action_stop },
2270 { DEV_STATE_STARTWAIT_RX, DEV_EVENT_RXUP, dev_action_chup },
2271 { DEV_STATE_STARTWAIT_RX, DEV_EVENT_TXUP, dev_action_chup },
2272 { DEV_STATE_STARTWAIT_RX, DEV_EVENT_TXDOWN, dev_action_chdown },
2273 { DEV_STATE_STARTWAIT_RX, DEV_EVENT_RESTART, dev_action_restart },
2274 { DEV_STATE_RUNNING, DEV_EVENT_STOP, dev_action_stop },
2275 { DEV_STATE_RUNNING, DEV_EVENT_RXDOWN, dev_action_chdown },
2276 { DEV_STATE_RUNNING, DEV_EVENT_TXDOWN, dev_action_chdown },
2277 { DEV_STATE_RUNNING, DEV_EVENT_TXUP, ctcm_action_nop },
2278 { DEV_STATE_RUNNING, DEV_EVENT_RXUP, ctcm_action_nop },
2279 { DEV_STATE_RUNNING, DEV_EVENT_RESTART, dev_action_restart },
2280 };
2281
2282 int dev_fsm_len = ARRAY_SIZE(dev_fsm);
2283
2284
2285