drivers/rtc/rtc-zynqmp.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver
0004  *
0005  * Copyright (C) 2015 Xilinx, Inc.
0006  *
0007  */
0008
0009 #include <linux/clk.h>
0010 #include <linux/delay.h>
0011 #include <linux/init.h>
0012 #include <linux/io.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/rtc.h>
0017
0018 /* RTC Registers */
0019 #define RTC_SET_TM_WR       0x00
0020 #define RTC_SET_TM_RD       0x04
0021 #define RTC_CALIB_WR        0x08
0022 #define RTC_CALIB_RD        0x0C
0023 #define RTC_CUR_TM      0x10
0024 #define RTC_CUR_TICK        0x14
0025 #define RTC_ALRM        0x18
0026 #define RTC_INT_STS     0x20
0027 #define RTC_INT_MASK        0x24
0028 #define RTC_INT_EN      0x28
0029 #define RTC_INT_DIS     0x2C
0030 #define RTC_CTRL        0x40
0031
0032 #define RTC_FR_EN       BIT(20)
0033 #define RTC_FR_DATSHIFT     16
0034 #define RTC_TICK_MASK       0xFFFF
0035 #define RTC_INT_SEC     BIT(0)
0036 #define RTC_INT_ALRM        BIT(1)
0037 #define RTC_OSC_EN      BIT(24)
0038 #define RTC_BATT_EN     BIT(31)
0039
0040 #define RTC_CALIB_DEF       0x7FFF
0041 #define RTC_CALIB_MASK      0x1FFFFF
0042 #define RTC_ALRM_MASK          BIT(1)
0043 #define RTC_MSEC               1000
0044 #define RTC_FR_MASK     0xF0000
0045 #define RTC_FR_MAX_TICKS    16
0046 #define RTC_PPB         1000000000LL
0047 #define RTC_MIN_OFFSET      -32768000
0048 #define RTC_MAX_OFFSET      32767000
0049
0050 struct xlnx_rtc_dev {
0051     struct rtc_device   *rtc;
0052     void __iomem        *reg_base;
0053     int         alarm_irq;
0054     int         sec_irq;
0055     struct clk      *rtc_clk;
0056     unsigned int        freq;
0057 };
0058
0059 static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm)
0060 {
0061     struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
0062     unsigned long new_time;
0063
0064     /*
0065      * The value written will be updated after 1 sec into the
0066      * seconds read register, so we need to program time +1 sec
0067      * to get the correct time on read.
0068      */
0069     new_time = rtc_tm_to_time64(tm) + 1;
0070
0071     writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR);
0072
0073     /*
0074      * Clear the rtc interrupt status register after setting the
0075      * time. During a read_time function, the code should read the
0076      * RTC_INT_STATUS register and if bit 0 is still 0, it means
0077      * that one second has not elapsed yet since RTC was set and
0078      * the current time should be read from SET_TIME_READ register;
0079      * otherwise, CURRENT_TIME register is read to report the time
0080      */
0081     writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS);
0082
0083     return 0;
0084 }
0085
0086 static int xlnx_rtc_read_time(struct device *dev, struct rtc_time *tm)
0087 {
0088     u32 status;
0089     unsigned long read_time;
0090     struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
0091
0092     status = readl(xrtcdev->reg_base + RTC_INT_STS);
0093
0094     if (status & RTC_INT_SEC) {
0095         /*
0096          * RTC has updated the CURRENT_TIME with the time written into
0097          * SET_TIME_WRITE register.
0098          */
0099         read_time = readl(xrtcdev->reg_base + RTC_CUR_TM);
0100     } else {
0101         /*
0102          * Time written in SET_TIME_WRITE has not yet updated into
0103          * the seconds read register, so read the time from the
0104          * SET_TIME_WRITE instead of CURRENT_TIME register.
0105          * Since we add +1 sec while writing, we need to -1 sec while
0106          * reading.
0107          */
0108         read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1;
0109     }
0110     rtc_time64_to_tm(read_time, tm);
0111
0112     return 0;
0113 }
0114
0115 static int xlnx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0116 {
0117     struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
0118
0119     rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time);
0120     alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM;
0121
0122     return 0;
0123 }
0124
0125 static int xlnx_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
0126 {
0127     struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
0128     unsigned int status;
0129     ulong timeout;
0130
0131     timeout = jiffies + msecs_to_jiffies(RTC_MSEC);
0132
0133     if (enabled) {
0134         while (1) {
0135             status = readl(xrtcdev->reg_base + RTC_INT_STS);
0136             if (!((status & RTC_ALRM_MASK) == RTC_ALRM_MASK))
0137                 break;
0138
0139             if (time_after_eq(jiffies, timeout)) {
0140                 dev_err(dev, "Time out occur, while clearing alarm status bit\n");
0141                 return -ETIMEDOUT;
0142             }
0143             writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_STS);
0144         }
0145
0146         writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN);
0147     } else {
0148         writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
0149     }
0150
0151     return 0;
0152 }
0153
0154 static int xlnx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0155 {
0156     struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
0157     unsigned long alarm_time;
0158
0159     alarm_time = rtc_tm_to_time64(&alrm->time);
0160
0161     writel((u32)alarm_time, (xrtcdev->reg_base + RTC_ALRM));
0162
0163     xlnx_rtc_alarm_irq_enable(dev, alrm->enabled);
0164
0165     return 0;
0166 }
0167
0168 static void xlnx_init_rtc(struct xlnx_rtc_dev *xrtcdev)
0169 {
0170     u32 rtc_ctrl;
0171
0172     /* Enable RTC switch to battery when VCC_PSAUX is not available */
0173     rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL);
0174     rtc_ctrl |= RTC_BATT_EN;
0175     writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL);
0176 }
0177
0178 static int xlnx_rtc_read_offset(struct device *dev, long *offset)
0179 {
0180     struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
0181     unsigned long long rtc_ppb = RTC_PPB;
0182     unsigned int tick_mult = do_div(rtc_ppb, xrtcdev->freq);
0183     unsigned int calibval;
0184     long offset_val;
0185
0186     calibval = readl(xrtcdev->reg_base + RTC_CALIB_RD);
0187     /* Offset with seconds ticks */
0188     offset_val = calibval & RTC_TICK_MASK;
0189     offset_val = offset_val - RTC_CALIB_DEF;
0190     offset_val = offset_val * tick_mult;
0191
0192     /* Offset with fractional ticks */
0193     if (calibval & RTC_FR_EN)
0194         offset_val += ((calibval & RTC_FR_MASK) >> RTC_FR_DATSHIFT)
0195             * (tick_mult / RTC_FR_MAX_TICKS);
0196     *offset = offset_val;
0197
0198     return 0;
0199 }
0200
0201 static int xlnx_rtc_set_offset(struct device *dev, long offset)
0202 {
0203     struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
0204     unsigned long long rtc_ppb = RTC_PPB;
0205     unsigned int tick_mult = do_div(rtc_ppb, xrtcdev->freq);
0206     unsigned char fract_tick = 0;
0207     unsigned int calibval;
0208     short int  max_tick;
0209     int fract_offset;
0210
0211     if (offset < RTC_MIN_OFFSET || offset > RTC_MAX_OFFSET)
0212         return -ERANGE;
0213
0214     /* Number ticks for given offset */
0215     max_tick = div_s64_rem(offset, tick_mult, &fract_offset);
0216
0217     /* Number fractional ticks for given offset */
0218     if (fract_offset) {
0219         if (fract_offset < 0) {
0220             fract_offset = fract_offset + tick_mult;
0221             max_tick--;
0222         }
0223         if (fract_offset > (tick_mult / RTC_FR_MAX_TICKS)) {
0224             for (fract_tick = 1; fract_tick < 16; fract_tick++) {
0225                 if (fract_offset <=
0226                     (fract_tick *
0227                      (tick_mult / RTC_FR_MAX_TICKS)))
0228                     break;
0229             }
0230         }
0231     }
0232
0233     /* Zynqmp RTC uses second and fractional tick
0234      * counters for compensation
0235      */
0236     calibval = max_tick + RTC_CALIB_DEF;
0237
0238     if (fract_tick)
0239         calibval |= RTC_FR_EN;
0240
0241     calibval |= (fract_tick << RTC_FR_DATSHIFT);
0242
0243     writel(calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
0244
0245     return 0;
0246 }
0247
0248 static const struct rtc_class_ops xlnx_rtc_ops = {
0249     .set_time     = xlnx_rtc_set_time,
0250     .read_time    = xlnx_rtc_read_time,
0251     .read_alarm   = xlnx_rtc_read_alarm,
0252     .set_alarm    = xlnx_rtc_set_alarm,
0253     .alarm_irq_enable = xlnx_rtc_alarm_irq_enable,
0254     .read_offset      = xlnx_rtc_read_offset,
0255     .set_offset   = xlnx_rtc_set_offset,
0256 };
0257
0258 static irqreturn_t xlnx_rtc_interrupt(int irq, void *id)
0259 {
0260     struct xlnx_rtc_dev *xrtcdev = (struct xlnx_rtc_dev *)id;
0261     unsigned int status;
0262
0263     status = readl(xrtcdev->reg_base + RTC_INT_STS);
0264     /* Check if interrupt asserted */
0265     if (!(status & (RTC_INT_SEC | RTC_INT_ALRM)))
0266         return IRQ_NONE;
0267
0268     /* Disable RTC_INT_ALRM interrupt only */
0269     writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
0270
0271     if (status & RTC_INT_ALRM)
0272         rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_AF);
0273
0274     return IRQ_HANDLED;
0275 }
0276
0277 static int xlnx_rtc_probe(struct platform_device *pdev)
0278 {
0279     struct xlnx_rtc_dev *xrtcdev;
0280     int ret;
0281
0282     xrtcdev = devm_kzalloc(&pdev->dev, sizeof(*xrtcdev), GFP_KERNEL);
0283     if (!xrtcdev)
0284         return -ENOMEM;
0285
0286     platform_set_drvdata(pdev, xrtcdev);
0287
0288     xrtcdev->rtc = devm_rtc_allocate_device(&pdev->dev);
0289     if (IS_ERR(xrtcdev->rtc))
0290         return PTR_ERR(xrtcdev->rtc);
0291
0292     xrtcdev->rtc->ops = &xlnx_rtc_ops;
0293     xrtcdev->rtc->range_max = U32_MAX;
0294
0295     xrtcdev->reg_base = devm_platform_ioremap_resource(pdev, 0);
0296     if (IS_ERR(xrtcdev->reg_base))
0297         return PTR_ERR(xrtcdev->reg_base);
0298
0299     xrtcdev->alarm_irq = platform_get_irq_byname(pdev, "alarm");
0300     if (xrtcdev->alarm_irq < 0)
0301         return xrtcdev->alarm_irq;
0302     ret = devm_request_irq(&pdev->dev, xrtcdev->alarm_irq,
0303                    xlnx_rtc_interrupt, 0,
0304                    dev_name(&pdev->dev), xrtcdev);
0305     if (ret) {
0306         dev_err(&pdev->dev, "request irq failed\n");
0307         return ret;
0308     }
0309
0310     xrtcdev->sec_irq = platform_get_irq_byname(pdev, "sec");
0311     if (xrtcdev->sec_irq < 0)
0312         return xrtcdev->sec_irq;
0313     ret = devm_request_irq(&pdev->dev, xrtcdev->sec_irq,
0314                    xlnx_rtc_interrupt, 0,
0315                    dev_name(&pdev->dev), xrtcdev);
0316     if (ret) {
0317         dev_err(&pdev->dev, "request irq failed\n");
0318         return ret;
0319     }
0320
0321     /* Getting the rtc_clk info */
0322     xrtcdev->rtc_clk = devm_clk_get_optional(&pdev->dev, "rtc_clk");
0323     if (IS_ERR(xrtcdev->rtc_clk)) {
0324         if (PTR_ERR(xrtcdev->rtc_clk) != -EPROBE_DEFER)
0325             dev_warn(&pdev->dev, "Device clock not found.\n");
0326     }
0327     xrtcdev->freq = clk_get_rate(xrtcdev->rtc_clk);
0328     if (!xrtcdev->freq) {
0329         ret = of_property_read_u32(pdev->dev.of_node, "calibration",
0330                        &xrtcdev->freq);
0331         if (ret)
0332             xrtcdev->freq = RTC_CALIB_DEF;
0333     }
0334     ret = readl(xrtcdev->reg_base + RTC_CALIB_RD);
0335     if (!ret)
0336         writel(xrtcdev->freq, (xrtcdev->reg_base + RTC_CALIB_WR));
0337
0338     xlnx_init_rtc(xrtcdev);
0339
0340     device_init_wakeup(&pdev->dev, 1);
0341
0342     return devm_rtc_register_device(xrtcdev->rtc);
0343 }
0344
0345 static int xlnx_rtc_remove(struct platform_device *pdev)
0346 {
0347     xlnx_rtc_alarm_irq_enable(&pdev->dev, 0);
0348     device_init_wakeup(&pdev->dev, 0);
0349
0350     return 0;
0351 }
0352
0353 static int __maybe_unused xlnx_rtc_suspend(struct device *dev)
0354 {
0355     struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
0356
0357     if (device_may_wakeup(dev))
0358         enable_irq_wake(xrtcdev->alarm_irq);
0359     else
0360         xlnx_rtc_alarm_irq_enable(dev, 0);
0361
0362     return 0;
0363 }
0364
0365 static int __maybe_unused xlnx_rtc_resume(struct device *dev)
0366 {
0367     struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
0368
0369     if (device_may_wakeup(dev))
0370         disable_irq_wake(xrtcdev->alarm_irq);
0371     else
0372         xlnx_rtc_alarm_irq_enable(dev, 1);
0373
0374     return 0;
0375 }
0376
0377 static SIMPLE_DEV_PM_OPS(xlnx_rtc_pm_ops, xlnx_rtc_suspend, xlnx_rtc_resume);
0378
0379 static const struct of_device_id xlnx_rtc_of_match[] = {
0380     {.compatible = "xlnx,zynqmp-rtc" },
0381     { }
0382 };
0383 MODULE_DEVICE_TABLE(of, xlnx_rtc_of_match);
0384
0385 static struct platform_driver xlnx_rtc_driver = {
0386     .probe      = xlnx_rtc_probe,
0387     .remove     = xlnx_rtc_remove,
0388     .driver     = {
0389         .name   = KBUILD_MODNAME,
0390         .pm = &xlnx_rtc_pm_ops,
0391         .of_match_table = xlnx_rtc_of_match,
0392     },
0393 };
0394
0395 module_platform_driver(xlnx_rtc_driver);
0396
0397 MODULE_DESCRIPTION("Xilinx Zynq MPSoC RTC driver");
0398 MODULE_AUTHOR("Xilinx Inc.");
0399 MODULE_LICENSE("GPL v2");