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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * rtc-twl.c -- TWL Real Time Clock interface
0004  *
0005  * Copyright (C) 2007 MontaVista Software, Inc
0006  * Author: Alexandre Rusev <source@mvista.com>
0007  *
0008  * Based on original TI driver twl4030-rtc.c
0009  *   Copyright (C) 2006 Texas Instruments, Inc.
0010  *
0011  * Based on rtc-omap.c
0012  *   Copyright (C) 2003 MontaVista Software, Inc.
0013  *   Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
0014  *   Copyright (C) 2006 David Brownell
0015  */
0016 
0017 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0018 
0019 #include <linux/kernel.h>
0020 #include <linux/errno.h>
0021 #include <linux/init.h>
0022 #include <linux/module.h>
0023 #include <linux/types.h>
0024 #include <linux/rtc.h>
0025 #include <linux/bcd.h>
0026 #include <linux/platform_device.h>
0027 #include <linux/interrupt.h>
0028 #include <linux/of.h>
0029 
0030 #include <linux/mfd/twl.h>
0031 
0032 enum twl_class {
0033     TWL_4030 = 0,
0034     TWL_6030,
0035 };
0036 
0037 /*
0038  * RTC block register offsets (use TWL_MODULE_RTC)
0039  */
0040 enum {
0041     REG_SECONDS_REG = 0,
0042     REG_MINUTES_REG,
0043     REG_HOURS_REG,
0044     REG_DAYS_REG,
0045     REG_MONTHS_REG,
0046     REG_YEARS_REG,
0047     REG_WEEKS_REG,
0048 
0049     REG_ALARM_SECONDS_REG,
0050     REG_ALARM_MINUTES_REG,
0051     REG_ALARM_HOURS_REG,
0052     REG_ALARM_DAYS_REG,
0053     REG_ALARM_MONTHS_REG,
0054     REG_ALARM_YEARS_REG,
0055 
0056     REG_RTC_CTRL_REG,
0057     REG_RTC_STATUS_REG,
0058     REG_RTC_INTERRUPTS_REG,
0059 
0060     REG_RTC_COMP_LSB_REG,
0061     REG_RTC_COMP_MSB_REG,
0062 };
0063 static const u8 twl4030_rtc_reg_map[] = {
0064     [REG_SECONDS_REG] = 0x00,
0065     [REG_MINUTES_REG] = 0x01,
0066     [REG_HOURS_REG] = 0x02,
0067     [REG_DAYS_REG] = 0x03,
0068     [REG_MONTHS_REG] = 0x04,
0069     [REG_YEARS_REG] = 0x05,
0070     [REG_WEEKS_REG] = 0x06,
0071 
0072     [REG_ALARM_SECONDS_REG] = 0x07,
0073     [REG_ALARM_MINUTES_REG] = 0x08,
0074     [REG_ALARM_HOURS_REG] = 0x09,
0075     [REG_ALARM_DAYS_REG] = 0x0A,
0076     [REG_ALARM_MONTHS_REG] = 0x0B,
0077     [REG_ALARM_YEARS_REG] = 0x0C,
0078 
0079     [REG_RTC_CTRL_REG] = 0x0D,
0080     [REG_RTC_STATUS_REG] = 0x0E,
0081     [REG_RTC_INTERRUPTS_REG] = 0x0F,
0082 
0083     [REG_RTC_COMP_LSB_REG] = 0x10,
0084     [REG_RTC_COMP_MSB_REG] = 0x11,
0085 };
0086 static const u8 twl6030_rtc_reg_map[] = {
0087     [REG_SECONDS_REG] = 0x00,
0088     [REG_MINUTES_REG] = 0x01,
0089     [REG_HOURS_REG] = 0x02,
0090     [REG_DAYS_REG] = 0x03,
0091     [REG_MONTHS_REG] = 0x04,
0092     [REG_YEARS_REG] = 0x05,
0093     [REG_WEEKS_REG] = 0x06,
0094 
0095     [REG_ALARM_SECONDS_REG] = 0x08,
0096     [REG_ALARM_MINUTES_REG] = 0x09,
0097     [REG_ALARM_HOURS_REG] = 0x0A,
0098     [REG_ALARM_DAYS_REG] = 0x0B,
0099     [REG_ALARM_MONTHS_REG] = 0x0C,
0100     [REG_ALARM_YEARS_REG] = 0x0D,
0101 
0102     [REG_RTC_CTRL_REG] = 0x10,
0103     [REG_RTC_STATUS_REG] = 0x11,
0104     [REG_RTC_INTERRUPTS_REG] = 0x12,
0105 
0106     [REG_RTC_COMP_LSB_REG] = 0x13,
0107     [REG_RTC_COMP_MSB_REG] = 0x14,
0108 };
0109 
0110 /* RTC_CTRL_REG bitfields */
0111 #define BIT_RTC_CTRL_REG_STOP_RTC_M              0x01
0112 #define BIT_RTC_CTRL_REG_ROUND_30S_M             0x02
0113 #define BIT_RTC_CTRL_REG_AUTO_COMP_M             0x04
0114 #define BIT_RTC_CTRL_REG_MODE_12_24_M            0x08
0115 #define BIT_RTC_CTRL_REG_TEST_MODE_M             0x10
0116 #define BIT_RTC_CTRL_REG_SET_32_COUNTER_M        0x20
0117 #define BIT_RTC_CTRL_REG_GET_TIME_M              0x40
0118 #define BIT_RTC_CTRL_REG_RTC_V_OPT               0x80
0119 
0120 /* RTC_STATUS_REG bitfields */
0121 #define BIT_RTC_STATUS_REG_RUN_M                 0x02
0122 #define BIT_RTC_STATUS_REG_1S_EVENT_M            0x04
0123 #define BIT_RTC_STATUS_REG_1M_EVENT_M            0x08
0124 #define BIT_RTC_STATUS_REG_1H_EVENT_M            0x10
0125 #define BIT_RTC_STATUS_REG_1D_EVENT_M            0x20
0126 #define BIT_RTC_STATUS_REG_ALARM_M               0x40
0127 #define BIT_RTC_STATUS_REG_POWER_UP_M            0x80
0128 
0129 /* RTC_INTERRUPTS_REG bitfields */
0130 #define BIT_RTC_INTERRUPTS_REG_EVERY_M           0x03
0131 #define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M        0x04
0132 #define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M        0x08
0133 
0134 
0135 /* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */
0136 #define ALL_TIME_REGS       6
0137 
0138 /*----------------------------------------------------------------------*/
0139 struct twl_rtc {
0140     struct device *dev;
0141     struct rtc_device *rtc;
0142     u8 *reg_map;
0143     /*
0144      * Cache the value for timer/alarm interrupts register; this is
0145      * only changed by callers holding rtc ops lock (or resume).
0146      */
0147     unsigned char rtc_irq_bits;
0148     bool wake_enabled;
0149 #ifdef CONFIG_PM_SLEEP
0150     unsigned char irqstat;
0151 #endif
0152     enum twl_class class;
0153 };
0154 
0155 /*
0156  * Supports 1 byte read from TWL RTC register.
0157  */
0158 static int twl_rtc_read_u8(struct twl_rtc *twl_rtc, u8 *data, u8 reg)
0159 {
0160     int ret;
0161 
0162     ret = twl_i2c_read_u8(TWL_MODULE_RTC, data, (twl_rtc->reg_map[reg]));
0163     if (ret < 0)
0164         pr_err("Could not read TWL register %X - error %d\n", reg, ret);
0165     return ret;
0166 }
0167 
0168 /*
0169  * Supports 1 byte write to TWL RTC registers.
0170  */
0171 static int twl_rtc_write_u8(struct twl_rtc *twl_rtc, u8 data, u8 reg)
0172 {
0173     int ret;
0174 
0175     ret = twl_i2c_write_u8(TWL_MODULE_RTC, data, (twl_rtc->reg_map[reg]));
0176     if (ret < 0)
0177         pr_err("Could not write TWL register %X - error %d\n",
0178                reg, ret);
0179     return ret;
0180 }
0181 
0182 /*
0183  * Enable 1/second update and/or alarm interrupts.
0184  */
0185 static int set_rtc_irq_bit(struct twl_rtc *twl_rtc, unsigned char bit)
0186 {
0187     unsigned char val;
0188     int ret;
0189 
0190     /* if the bit is set, return from here */
0191     if (twl_rtc->rtc_irq_bits & bit)
0192         return 0;
0193 
0194     val = twl_rtc->rtc_irq_bits | bit;
0195     val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M;
0196     ret = twl_rtc_write_u8(twl_rtc, val, REG_RTC_INTERRUPTS_REG);
0197     if (ret == 0)
0198         twl_rtc->rtc_irq_bits = val;
0199 
0200     return ret;
0201 }
0202 
0203 /*
0204  * Disable update and/or alarm interrupts.
0205  */
0206 static int mask_rtc_irq_bit(struct twl_rtc *twl_rtc, unsigned char bit)
0207 {
0208     unsigned char val;
0209     int ret;
0210 
0211     /* if the bit is clear, return from here */
0212     if (!(twl_rtc->rtc_irq_bits & bit))
0213         return 0;
0214 
0215     val = twl_rtc->rtc_irq_bits & ~bit;
0216     ret = twl_rtc_write_u8(twl_rtc, val, REG_RTC_INTERRUPTS_REG);
0217     if (ret == 0)
0218         twl_rtc->rtc_irq_bits = val;
0219 
0220     return ret;
0221 }
0222 
0223 static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
0224 {
0225     struct platform_device *pdev = to_platform_device(dev);
0226     struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
0227     int irq = platform_get_irq(pdev, 0);
0228     int ret;
0229 
0230     if (enabled) {
0231         ret = set_rtc_irq_bit(twl_rtc,
0232                       BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
0233         if (device_can_wakeup(dev) && !twl_rtc->wake_enabled) {
0234             enable_irq_wake(irq);
0235             twl_rtc->wake_enabled = true;
0236         }
0237     } else {
0238         ret = mask_rtc_irq_bit(twl_rtc,
0239                        BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
0240         if (twl_rtc->wake_enabled) {
0241             disable_irq_wake(irq);
0242             twl_rtc->wake_enabled = false;
0243         }
0244     }
0245 
0246     return ret;
0247 }
0248 
0249 /*
0250  * Gets current TWL RTC time and date parameters.
0251  *
0252  * The RTC's time/alarm representation is not what gmtime(3) requires
0253  * Linux to use:
0254  *
0255  *  - Months are 1..12 vs Linux 0-11
0256  *  - Years are 0..99 vs Linux 1900..N (we assume 21st century)
0257  */
0258 static int twl_rtc_read_time(struct device *dev, struct rtc_time *tm)
0259 {
0260     struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
0261     unsigned char rtc_data[ALL_TIME_REGS];
0262     int ret;
0263     u8 save_control;
0264     u8 rtc_control;
0265 
0266     ret = twl_rtc_read_u8(twl_rtc, &save_control, REG_RTC_CTRL_REG);
0267     if (ret < 0) {
0268         dev_err(dev, "%s: reading CTRL_REG, error %d\n", __func__, ret);
0269         return ret;
0270     }
0271     /* for twl6030/32 make sure BIT_RTC_CTRL_REG_GET_TIME_M is clear */
0272     if (twl_rtc->class == TWL_6030) {
0273         if (save_control & BIT_RTC_CTRL_REG_GET_TIME_M) {
0274             save_control &= ~BIT_RTC_CTRL_REG_GET_TIME_M;
0275             ret = twl_rtc_write_u8(twl_rtc, save_control,
0276                            REG_RTC_CTRL_REG);
0277             if (ret < 0) {
0278                 dev_err(dev, "%s clr GET_TIME, error %d\n",
0279                     __func__, ret);
0280                 return ret;
0281             }
0282         }
0283     }
0284 
0285     /* Copy RTC counting registers to static registers or latches */
0286     rtc_control = save_control | BIT_RTC_CTRL_REG_GET_TIME_M;
0287 
0288     /* for twl6030/32 enable read access to static shadowed registers */
0289     if (twl_rtc->class == TWL_6030)
0290         rtc_control |= BIT_RTC_CTRL_REG_RTC_V_OPT;
0291 
0292     ret = twl_rtc_write_u8(twl_rtc, rtc_control, REG_RTC_CTRL_REG);
0293     if (ret < 0) {
0294         dev_err(dev, "%s: writing CTRL_REG, error %d\n", __func__, ret);
0295         return ret;
0296     }
0297 
0298     ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
0299             (twl_rtc->reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
0300 
0301     if (ret < 0) {
0302         dev_err(dev, "%s: reading data, error %d\n", __func__, ret);
0303         return ret;
0304     }
0305 
0306     /* for twl6030 restore original state of rtc control register */
0307     if (twl_rtc->class == TWL_6030) {
0308         ret = twl_rtc_write_u8(twl_rtc, save_control, REG_RTC_CTRL_REG);
0309         if (ret < 0) {
0310             dev_err(dev, "%s: restore CTRL_REG, error %d\n",
0311                 __func__, ret);
0312             return ret;
0313         }
0314     }
0315 
0316     tm->tm_sec = bcd2bin(rtc_data[0]);
0317     tm->tm_min = bcd2bin(rtc_data[1]);
0318     tm->tm_hour = bcd2bin(rtc_data[2]);
0319     tm->tm_mday = bcd2bin(rtc_data[3]);
0320     tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
0321     tm->tm_year = bcd2bin(rtc_data[5]) + 100;
0322 
0323     return ret;
0324 }
0325 
0326 static int twl_rtc_set_time(struct device *dev, struct rtc_time *tm)
0327 {
0328     struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
0329     unsigned char save_control;
0330     unsigned char rtc_data[ALL_TIME_REGS];
0331     int ret;
0332 
0333     rtc_data[0] = bin2bcd(tm->tm_sec);
0334     rtc_data[1] = bin2bcd(tm->tm_min);
0335     rtc_data[2] = bin2bcd(tm->tm_hour);
0336     rtc_data[3] = bin2bcd(tm->tm_mday);
0337     rtc_data[4] = bin2bcd(tm->tm_mon + 1);
0338     rtc_data[5] = bin2bcd(tm->tm_year - 100);
0339 
0340     /* Stop RTC while updating the TC registers */
0341     ret = twl_rtc_read_u8(twl_rtc, &save_control, REG_RTC_CTRL_REG);
0342     if (ret < 0)
0343         goto out;
0344 
0345     save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M;
0346     ret = twl_rtc_write_u8(twl_rtc, save_control, REG_RTC_CTRL_REG);
0347     if (ret < 0)
0348         goto out;
0349 
0350     /* update all the time registers in one shot */
0351     ret = twl_i2c_write(TWL_MODULE_RTC, rtc_data,
0352         (twl_rtc->reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
0353     if (ret < 0) {
0354         dev_err(dev, "rtc_set_time error %d\n", ret);
0355         goto out;
0356     }
0357 
0358     /* Start back RTC */
0359     save_control |= BIT_RTC_CTRL_REG_STOP_RTC_M;
0360     ret = twl_rtc_write_u8(twl_rtc, save_control, REG_RTC_CTRL_REG);
0361 
0362 out:
0363     return ret;
0364 }
0365 
0366 /*
0367  * Gets current TWL RTC alarm time.
0368  */
0369 static int twl_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
0370 {
0371     struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
0372     unsigned char rtc_data[ALL_TIME_REGS];
0373     int ret;
0374 
0375     ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
0376             twl_rtc->reg_map[REG_ALARM_SECONDS_REG], ALL_TIME_REGS);
0377     if (ret < 0) {
0378         dev_err(dev, "rtc_read_alarm error %d\n", ret);
0379         return ret;
0380     }
0381 
0382     /* some of these fields may be wildcard/"match all" */
0383     alm->time.tm_sec = bcd2bin(rtc_data[0]);
0384     alm->time.tm_min = bcd2bin(rtc_data[1]);
0385     alm->time.tm_hour = bcd2bin(rtc_data[2]);
0386     alm->time.tm_mday = bcd2bin(rtc_data[3]);
0387     alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1;
0388     alm->time.tm_year = bcd2bin(rtc_data[5]) + 100;
0389 
0390     /* report cached alarm enable state */
0391     if (twl_rtc->rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M)
0392         alm->enabled = 1;
0393 
0394     return ret;
0395 }
0396 
0397 static int twl_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
0398 {
0399     struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
0400 
0401     unsigned char alarm_data[ALL_TIME_REGS];
0402     int ret;
0403 
0404     ret = twl_rtc_alarm_irq_enable(dev, 0);
0405     if (ret)
0406         goto out;
0407 
0408     alarm_data[0] = bin2bcd(alm->time.tm_sec);
0409     alarm_data[1] = bin2bcd(alm->time.tm_min);
0410     alarm_data[2] = bin2bcd(alm->time.tm_hour);
0411     alarm_data[3] = bin2bcd(alm->time.tm_mday);
0412     alarm_data[4] = bin2bcd(alm->time.tm_mon + 1);
0413     alarm_data[5] = bin2bcd(alm->time.tm_year - 100);
0414 
0415     /* update all the alarm registers in one shot */
0416     ret = twl_i2c_write(TWL_MODULE_RTC, alarm_data,
0417             twl_rtc->reg_map[REG_ALARM_SECONDS_REG], ALL_TIME_REGS);
0418     if (ret) {
0419         dev_err(dev, "rtc_set_alarm error %d\n", ret);
0420         goto out;
0421     }
0422 
0423     if (alm->enabled)
0424         ret = twl_rtc_alarm_irq_enable(dev, 1);
0425 out:
0426     return ret;
0427 }
0428 
0429 static irqreturn_t twl_rtc_interrupt(int irq, void *data)
0430 {
0431     struct twl_rtc *twl_rtc = data;
0432     unsigned long events;
0433     int ret = IRQ_NONE;
0434     int res;
0435     u8 rd_reg;
0436 
0437     res = twl_rtc_read_u8(twl_rtc, &rd_reg, REG_RTC_STATUS_REG);
0438     if (res)
0439         goto out;
0440     /*
0441      * Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG.
0442      * only one (ALARM or RTC) interrupt source may be enabled
0443      * at time, we also could check our results
0444      * by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM]
0445      */
0446     if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
0447         events = RTC_IRQF | RTC_AF;
0448     else
0449         events = RTC_IRQF | RTC_PF;
0450 
0451     res = twl_rtc_write_u8(twl_rtc, BIT_RTC_STATUS_REG_ALARM_M,
0452                    REG_RTC_STATUS_REG);
0453     if (res)
0454         goto out;
0455 
0456     if (twl_rtc->class == TWL_4030) {
0457         /* Clear on Read enabled. RTC_IT bit of TWL4030_INT_PWR_ISR1
0458          * needs 2 reads to clear the interrupt. One read is done in
0459          * do_twl_pwrirq(). Doing the second read, to clear
0460          * the bit.
0461          *
0462          * FIXME the reason PWR_ISR1 needs an extra read is that
0463          * RTC_IF retriggered until we cleared REG_ALARM_M above.
0464          * But re-reading like this is a bad hack; by doing so we
0465          * risk wrongly clearing status for some other IRQ (losing
0466          * the interrupt).  Be smarter about handling RTC_UF ...
0467          */
0468         res = twl_i2c_read_u8(TWL4030_MODULE_INT,
0469             &rd_reg, TWL4030_INT_PWR_ISR1);
0470         if (res)
0471             goto out;
0472     }
0473 
0474     /* Notify RTC core on event */
0475     rtc_update_irq(twl_rtc->rtc, 1, events);
0476 
0477     ret = IRQ_HANDLED;
0478 out:
0479     return ret;
0480 }
0481 
0482 static const struct rtc_class_ops twl_rtc_ops = {
0483     .read_time  = twl_rtc_read_time,
0484     .set_time   = twl_rtc_set_time,
0485     .read_alarm = twl_rtc_read_alarm,
0486     .set_alarm  = twl_rtc_set_alarm,
0487     .alarm_irq_enable = twl_rtc_alarm_irq_enable,
0488 };
0489 
0490 /*----------------------------------------------------------------------*/
0491 
0492 static int twl_rtc_probe(struct platform_device *pdev)
0493 {
0494     struct twl_rtc *twl_rtc;
0495     struct device_node *np = pdev->dev.of_node;
0496     int ret = -EINVAL;
0497     int irq = platform_get_irq(pdev, 0);
0498     u8 rd_reg;
0499 
0500     if (!np) {
0501         dev_err(&pdev->dev, "no DT info\n");
0502         return -EINVAL;
0503     }
0504 
0505     if (irq <= 0)
0506         return ret;
0507 
0508     twl_rtc = devm_kzalloc(&pdev->dev, sizeof(*twl_rtc), GFP_KERNEL);
0509     if (!twl_rtc)
0510         return -ENOMEM;
0511 
0512     if (twl_class_is_4030()) {
0513         twl_rtc->class = TWL_4030;
0514         twl_rtc->reg_map = (u8 *)twl4030_rtc_reg_map;
0515     } else if (twl_class_is_6030()) {
0516         twl_rtc->class = TWL_6030;
0517         twl_rtc->reg_map = (u8 *)twl6030_rtc_reg_map;
0518     } else {
0519         dev_err(&pdev->dev, "TWL Class not supported.\n");
0520         return -EINVAL;
0521     }
0522 
0523     ret = twl_rtc_read_u8(twl_rtc, &rd_reg, REG_RTC_STATUS_REG);
0524     if (ret < 0)
0525         return ret;
0526 
0527     if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M)
0528         dev_warn(&pdev->dev, "Power up reset detected.\n");
0529 
0530     if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
0531         dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n");
0532 
0533     /* Clear RTC Power up reset and pending alarm interrupts */
0534     ret = twl_rtc_write_u8(twl_rtc, rd_reg, REG_RTC_STATUS_REG);
0535     if (ret < 0)
0536         return ret;
0537 
0538     if (twl_rtc->class == TWL_6030) {
0539         twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
0540             REG_INT_MSK_LINE_A);
0541         twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
0542             REG_INT_MSK_STS_A);
0543     }
0544 
0545     dev_info(&pdev->dev, "Enabling TWL-RTC\n");
0546     ret = twl_rtc_write_u8(twl_rtc, BIT_RTC_CTRL_REG_STOP_RTC_M,
0547                    REG_RTC_CTRL_REG);
0548     if (ret < 0)
0549         return ret;
0550 
0551     /* ensure interrupts are disabled, bootloaders can be strange */
0552     ret = twl_rtc_write_u8(twl_rtc, 0, REG_RTC_INTERRUPTS_REG);
0553     if (ret < 0)
0554         dev_warn(&pdev->dev, "unable to disable interrupt\n");
0555 
0556     /* init cached IRQ enable bits */
0557     ret = twl_rtc_read_u8(twl_rtc, &twl_rtc->rtc_irq_bits,
0558                   REG_RTC_INTERRUPTS_REG);
0559     if (ret < 0)
0560         return ret;
0561 
0562     platform_set_drvdata(pdev, twl_rtc);
0563     device_init_wakeup(&pdev->dev, 1);
0564 
0565     twl_rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
0566                     &twl_rtc_ops, THIS_MODULE);
0567     if (IS_ERR(twl_rtc->rtc)) {
0568         dev_err(&pdev->dev, "can't register RTC device, err %ld\n",
0569             PTR_ERR(twl_rtc->rtc));
0570         return PTR_ERR(twl_rtc->rtc);
0571     }
0572 
0573     ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
0574                     twl_rtc_interrupt,
0575                     IRQF_TRIGGER_RISING | IRQF_ONESHOT,
0576                     dev_name(&twl_rtc->rtc->dev), twl_rtc);
0577     if (ret < 0) {
0578         dev_err(&pdev->dev, "IRQ is not free.\n");
0579         return ret;
0580     }
0581 
0582     return 0;
0583 }
0584 
0585 /*
0586  * Disable all TWL RTC module interrupts.
0587  * Sets status flag to free.
0588  */
0589 static int twl_rtc_remove(struct platform_device *pdev)
0590 {
0591     struct twl_rtc *twl_rtc = platform_get_drvdata(pdev);
0592 
0593     /* leave rtc running, but disable irqs */
0594     mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
0595     mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
0596     if (twl_rtc->class == TWL_6030) {
0597         twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
0598             REG_INT_MSK_LINE_A);
0599         twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
0600             REG_INT_MSK_STS_A);
0601     }
0602 
0603     return 0;
0604 }
0605 
0606 static void twl_rtc_shutdown(struct platform_device *pdev)
0607 {
0608     struct twl_rtc *twl_rtc = platform_get_drvdata(pdev);
0609 
0610     /* mask timer interrupts, but leave alarm interrupts on to enable
0611        power-on when alarm is triggered */
0612     mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
0613 }
0614 
0615 #ifdef CONFIG_PM_SLEEP
0616 static int twl_rtc_suspend(struct device *dev)
0617 {
0618     struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
0619 
0620     twl_rtc->irqstat = twl_rtc->rtc_irq_bits;
0621 
0622     mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
0623     return 0;
0624 }
0625 
0626 static int twl_rtc_resume(struct device *dev)
0627 {
0628     struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
0629 
0630     set_rtc_irq_bit(twl_rtc, twl_rtc->irqstat);
0631     return 0;
0632 }
0633 #endif
0634 
0635 static SIMPLE_DEV_PM_OPS(twl_rtc_pm_ops, twl_rtc_suspend, twl_rtc_resume);
0636 
0637 static const struct of_device_id twl_rtc_of_match[] = {
0638     {.compatible = "ti,twl4030-rtc", },
0639     { },
0640 };
0641 MODULE_DEVICE_TABLE(of, twl_rtc_of_match);
0642 
0643 static struct platform_driver twl4030rtc_driver = {
0644     .probe      = twl_rtc_probe,
0645     .remove     = twl_rtc_remove,
0646     .shutdown   = twl_rtc_shutdown,
0647     .driver     = {
0648         .name       = "twl_rtc",
0649         .pm     = &twl_rtc_pm_ops,
0650         .of_match_table = twl_rtc_of_match,
0651     },
0652 };
0653 
0654 module_platform_driver(twl4030rtc_driver);
0655 
0656 MODULE_AUTHOR("Texas Instruments, MontaVista Software");
0657 MODULE_LICENSE("GPL");
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