drivers/rtc/rtc-ti-k3.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Texas Instruments K3 RTC driver
0004  *
0005  * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
0006  */
0007
0008 #include <linux/clk.h>
0009 #include <linux/delay.h>
0010 #include <linux/mod_devicetable.h>
0011 #include <linux/module.h>
0012 #include <linux/of_device.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/property.h>
0015 #include <linux/regmap.h>
0016 #include <linux/rtc.h>
0017
0018 /* Registers */
0019 #define REG_K3RTC_S_CNT_LSW     0x08
0020 #define REG_K3RTC_S_CNT_MSW     0x0c
0021 #define REG_K3RTC_COMP          0x10
0022 #define REG_K3RTC_ON_OFF_S_CNT_LSW  0x20
0023 #define REG_K3RTC_ON_OFF_S_CNT_MSW  0x24
0024 #define REG_K3RTC_SCRATCH0      0x30
0025 #define REG_K3RTC_SCRATCH7      0x4c
0026 #define REG_K3RTC_GENERAL_CTL       0x50
0027 #define REG_K3RTC_IRQSTATUS_RAW_SYS 0x54
0028 #define REG_K3RTC_IRQSTATUS_SYS     0x58
0029 #define REG_K3RTC_IRQENABLE_SET_SYS 0x5c
0030 #define REG_K3RTC_IRQENABLE_CLR_SYS 0x60
0031 #define REG_K3RTC_SYNCPEND      0x68
0032 #define REG_K3RTC_KICK0         0x70
0033 #define REG_K3RTC_KICK1         0x74
0034
0035 /* Freeze when lsw is read and unfreeze when msw is read */
0036 #define K3RTC_CNT_FMODE_S_CNT_VALUE (0x2 << 24)
0037
0038 /* Magic values for lock/unlock */
0039 #define K3RTC_KICK0_UNLOCK_VALUE    0x83e70b13
0040 #define K3RTC_KICK1_UNLOCK_VALUE    0x95a4f1e0
0041
0042 /* Multiplier for ppb conversions */
0043 #define K3RTC_PPB_MULT          (1000000000LL)
0044 /* Min and max values supported with 'offset' interface (swapped sign) */
0045 #define K3RTC_MIN_OFFSET        (-277761)
0046 #define K3RTC_MAX_OFFSET        (277778)
0047
0048 /**
0049  * struct ti_k3_rtc_soc_data - Private of compatible data for ti-k3-rtc
0050  * @unlock_irq_erratum: Has erratum for unlock infinite IRQs (erratum i2327)
0051  */
0052 struct ti_k3_rtc_soc_data {
0053     const bool unlock_irq_erratum;
0054 };
0055
0056 static const struct regmap_config ti_k3_rtc_regmap_config = {
0057     .name = "peripheral-registers",
0058     .reg_bits = 32,
0059     .val_bits = 32,
0060     .reg_stride = 4,
0061     .max_register = REG_K3RTC_KICK1,
0062 };
0063
0064 enum ti_k3_rtc_fields {
0065     K3RTC_KICK0,
0066     K3RTC_KICK1,
0067     K3RTC_S_CNT_LSW,
0068     K3RTC_S_CNT_MSW,
0069     K3RTC_O32K_OSC_DEP_EN,
0070     K3RTC_UNLOCK,
0071     K3RTC_CNT_FMODE,
0072     K3RTC_PEND,
0073     K3RTC_RELOAD_FROM_BBD,
0074     K3RTC_COMP,
0075
0076     K3RTC_ALM_S_CNT_LSW,
0077     K3RTC_ALM_S_CNT_MSW,
0078     K3RTC_IRQ_STATUS_RAW,
0079     K3RTC_IRQ_STATUS,
0080     K3RTC_IRQ_ENABLE_SET,
0081     K3RTC_IRQ_ENABLE_CLR,
0082
0083     K3RTC_IRQ_STATUS_ALT,
0084     K3RTC_IRQ_ENABLE_CLR_ALT,
0085
0086     K3_RTC_MAX_FIELDS
0087 };
0088
0089 static const struct reg_field ti_rtc_reg_fields[] = {
0090     [K3RTC_KICK0] = REG_FIELD(REG_K3RTC_KICK0, 0, 31),
0091     [K3RTC_KICK1] = REG_FIELD(REG_K3RTC_KICK1, 0, 31),
0092     [K3RTC_S_CNT_LSW] = REG_FIELD(REG_K3RTC_S_CNT_LSW, 0, 31),
0093     [K3RTC_S_CNT_MSW] = REG_FIELD(REG_K3RTC_S_CNT_MSW, 0, 15),
0094     [K3RTC_O32K_OSC_DEP_EN] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 21, 21),
0095     [K3RTC_UNLOCK] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 23, 23),
0096     [K3RTC_CNT_FMODE] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 24, 25),
0097     [K3RTC_PEND] = REG_FIELD(REG_K3RTC_SYNCPEND, 0, 1),
0098     [K3RTC_RELOAD_FROM_BBD] = REG_FIELD(REG_K3RTC_SYNCPEND, 31, 31),
0099     [K3RTC_COMP] = REG_FIELD(REG_K3RTC_COMP, 0, 31),
0100
0101     /* We use on to off as alarm trigger */
0102     [K3RTC_ALM_S_CNT_LSW] = REG_FIELD(REG_K3RTC_ON_OFF_S_CNT_LSW, 0, 31),
0103     [K3RTC_ALM_S_CNT_MSW] = REG_FIELD(REG_K3RTC_ON_OFF_S_CNT_MSW, 0, 15),
0104     [K3RTC_IRQ_STATUS_RAW] = REG_FIELD(REG_K3RTC_IRQSTATUS_RAW_SYS, 0, 0),
0105     [K3RTC_IRQ_STATUS] = REG_FIELD(REG_K3RTC_IRQSTATUS_SYS, 0, 0),
0106     [K3RTC_IRQ_ENABLE_SET] = REG_FIELD(REG_K3RTC_IRQENABLE_SET_SYS, 0, 0),
0107     [K3RTC_IRQ_ENABLE_CLR] = REG_FIELD(REG_K3RTC_IRQENABLE_CLR_SYS, 0, 0),
0108     /* Off to on is alternate */
0109     [K3RTC_IRQ_STATUS_ALT] = REG_FIELD(REG_K3RTC_IRQSTATUS_SYS, 1, 1),
0110     [K3RTC_IRQ_ENABLE_CLR_ALT] = REG_FIELD(REG_K3RTC_IRQENABLE_CLR_SYS, 1, 1),
0111 };
0112
0113 /**
0114  * struct ti_k3_rtc - Private data for ti-k3-rtc
0115  * @irq:        IRQ
0116  * @sync_timeout_us:    data sync timeout period in uSec
0117  * @rate_32k:       32k clock rate in Hz
0118  * @rtc_dev:        rtc device
0119  * @regmap:     rtc mmio regmap
0120  * @r_fields:       rtc register fields
0121  * @soc:        SoC compatible match data
0122  */
0123 struct ti_k3_rtc {
0124     unsigned int irq;
0125     u32 sync_timeout_us;
0126     unsigned long rate_32k;
0127     struct rtc_device *rtc_dev;
0128     struct regmap *regmap;
0129     struct regmap_field *r_fields[K3_RTC_MAX_FIELDS];
0130     const struct ti_k3_rtc_soc_data *soc;
0131 };
0132
0133 static int k3rtc_field_read(struct ti_k3_rtc *priv, enum ti_k3_rtc_fields f)
0134 {
0135     int ret;
0136     int val;
0137
0138     ret = regmap_field_read(priv->r_fields[f], &val);
0139     /*
0140      * We shouldn't be seeing regmap fail on us for mmio reads
0141      * This is possible if clock context fails, but that isn't the case for us
0142      */
0143     if (WARN_ON_ONCE(ret))
0144         return ret;
0145     return val;
0146 }
0147
0148 static void k3rtc_field_write(struct ti_k3_rtc *priv, enum ti_k3_rtc_fields f, u32 val)
0149 {
0150     regmap_field_write(priv->r_fields[f], val);
0151 }
0152
0153 /**
0154  * k3rtc_fence  - Ensure a register sync took place between the two domains
0155  * @priv:      pointer to priv data
0156  *
0157  * Return: 0 if the sync took place, else returns -ETIMEDOUT
0158  */
0159 static int k3rtc_fence(struct ti_k3_rtc *priv)
0160 {
0161     int ret;
0162
0163     ret = regmap_field_read_poll_timeout(priv->r_fields[K3RTC_PEND], ret,
0164                          !ret, 2, priv->sync_timeout_us);
0165
0166     return ret;
0167 }
0168
0169 static inline int k3rtc_check_unlocked(struct ti_k3_rtc *priv)
0170 {
0171     int ret;
0172
0173     ret = k3rtc_field_read(priv, K3RTC_UNLOCK);
0174     if (ret < 0)
0175         return ret;
0176
0177     return (ret) ? 0 : 1;
0178 }
0179
0180 static int k3rtc_unlock_rtc(struct ti_k3_rtc *priv)
0181 {
0182     int ret;
0183
0184     ret = k3rtc_check_unlocked(priv);
0185     if (!ret)
0186         return ret;
0187
0188     k3rtc_field_write(priv, K3RTC_KICK0, K3RTC_KICK0_UNLOCK_VALUE);
0189     k3rtc_field_write(priv, K3RTC_KICK1, K3RTC_KICK1_UNLOCK_VALUE);
0190
0191     /* Skip fence since we are going to check the unlock bit as fence */
0192     ret = regmap_field_read_poll_timeout(priv->r_fields[K3RTC_UNLOCK], ret,
0193                          !ret, 2, priv->sync_timeout_us);
0194
0195     return ret;
0196 }
0197
0198 static int k3rtc_configure(struct device *dev)
0199 {
0200     int ret;
0201     struct ti_k3_rtc *priv = dev_get_drvdata(dev);
0202
0203     /*
0204      * HWBUG: The compare state machine is broken if the RTC module
0205      * is NOT unlocked in under one second of boot - which is pretty long
0206      * time from the perspective of Linux driver (module load, u-boot
0207      * shell all can take much longer than this.
0208      *
0209      * In such occurrence, it is assumed that the RTC module is unusable
0210      */
0211     if (priv->soc->unlock_irq_erratum) {
0212         ret = k3rtc_check_unlocked(priv);
0213         /* If there is an error OR if we are locked, return error */
0214         if (ret) {
0215             dev_err(dev,
0216                 HW_ERR "Erratum i2327 unlock QUIRK! Cannot operate!!\n");
0217             return -EFAULT;
0218         }
0219     } else {
0220         /* May need to explicitly unlock first time */
0221         ret = k3rtc_unlock_rtc(priv);
0222         if (ret) {
0223             dev_err(dev, "Failed to unlock(%d)!\n", ret);
0224             return ret;
0225         }
0226     }
0227
0228     /* Enable Shadow register sync on 32k clock boundary */
0229     k3rtc_field_write(priv, K3RTC_O32K_OSC_DEP_EN, 0x1);
0230
0231     /*
0232      * Wait at least clock sync time before proceeding further programming.
0233      * This ensures that the 32k based sync is active.
0234      */
0235     usleep_range(priv->sync_timeout_us, priv->sync_timeout_us + 5);
0236
0237     /* We need to ensure fence here to make sure sync here */
0238     ret = k3rtc_fence(priv);
0239     if (ret) {
0240         dev_err(dev,
0241             "Failed fence osc_dep enable(%d) - is 32k clk working?!\n", ret);
0242         return ret;
0243     }
0244
0245     /*
0246      * FMODE setting: Reading lower seconds will freeze value on higher
0247      * seconds. This also implies that we must *ALWAYS* read lower seconds
0248      * prior to reading higher seconds
0249      */
0250     k3rtc_field_write(priv, K3RTC_CNT_FMODE, K3RTC_CNT_FMODE_S_CNT_VALUE);
0251
0252     /* Clear any spurious IRQ sources if any */
0253     k3rtc_field_write(priv, K3RTC_IRQ_STATUS_ALT, 0x1);
0254     k3rtc_field_write(priv, K3RTC_IRQ_STATUS, 0x1);
0255     /* Disable all IRQs */
0256     k3rtc_field_write(priv, K3RTC_IRQ_ENABLE_CLR_ALT, 0x1);
0257     k3rtc_field_write(priv, K3RTC_IRQ_ENABLE_CLR, 0x1);
0258
0259     /* And.. Let us Sync the writes in */
0260     return k3rtc_fence(priv);
0261 }
0262
0263 static int ti_k3_rtc_read_time(struct device *dev, struct rtc_time *tm)
0264 {
0265     struct ti_k3_rtc *priv = dev_get_drvdata(dev);
0266     u32 seconds_lo, seconds_hi;
0267
0268     seconds_lo = k3rtc_field_read(priv, K3RTC_S_CNT_LSW);
0269     seconds_hi = k3rtc_field_read(priv, K3RTC_S_CNT_MSW);
0270
0271     rtc_time64_to_tm((((time64_t)seconds_hi) << 32) | (time64_t)seconds_lo, tm);
0272
0273     return 0;
0274 }
0275
0276 static int ti_k3_rtc_set_time(struct device *dev, struct rtc_time *tm)
0277 {
0278     struct ti_k3_rtc *priv = dev_get_drvdata(dev);
0279     time64_t seconds;
0280
0281     seconds = rtc_tm_to_time64(tm);
0282
0283     /*
0284      * Read operation on LSW will freeze the RTC, so to update
0285      * the time, we cannot use field operations. Just write since the
0286      * reserved bits are ignored.
0287      */
0288     regmap_write(priv->regmap, REG_K3RTC_S_CNT_LSW, seconds);
0289     regmap_write(priv->regmap, REG_K3RTC_S_CNT_MSW, seconds >> 32);
0290
0291     return k3rtc_fence(priv);
0292 }
0293
0294 static int ti_k3_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
0295 {
0296     struct ti_k3_rtc *priv = dev_get_drvdata(dev);
0297     u32 reg;
0298     u32 offset = enabled ? K3RTC_IRQ_ENABLE_SET : K3RTC_IRQ_ENABLE_CLR;
0299
0300     reg = k3rtc_field_read(priv, K3RTC_IRQ_ENABLE_SET);
0301     if ((enabled && reg) || (!enabled && !reg))
0302         return 0;
0303
0304     k3rtc_field_write(priv, offset, 0x1);
0305
0306     /*
0307      * Ensure the write sync is through - NOTE: it should be OK to have
0308      * ISR to fire as we are checking sync (which should be done in a 32k
0309      * cycle or so).
0310      */
0311     return k3rtc_fence(priv);
0312 }
0313
0314 static int ti_k3_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
0315 {
0316     struct ti_k3_rtc *priv = dev_get_drvdata(dev);
0317     u32 seconds_lo, seconds_hi;
0318
0319     seconds_lo = k3rtc_field_read(priv, K3RTC_ALM_S_CNT_LSW);
0320     seconds_hi = k3rtc_field_read(priv, K3RTC_ALM_S_CNT_MSW);
0321
0322     rtc_time64_to_tm((((time64_t)seconds_hi) << 32) | (time64_t)seconds_lo, &alarm->time);
0323
0324     alarm->enabled = k3rtc_field_read(priv, K3RTC_IRQ_ENABLE_SET);
0325
0326     return 0;
0327 }
0328
0329 static int ti_k3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
0330 {
0331     struct ti_k3_rtc *priv = dev_get_drvdata(dev);
0332     time64_t seconds;
0333     int ret;
0334
0335     seconds = rtc_tm_to_time64(&alarm->time);
0336
0337     k3rtc_field_write(priv, K3RTC_ALM_S_CNT_LSW, seconds);
0338     k3rtc_field_write(priv, K3RTC_ALM_S_CNT_MSW, (seconds >> 32));
0339
0340     /* Make sure the alarm time is synced in */
0341     ret = k3rtc_fence(priv);
0342     if (ret) {
0343         dev_err(dev, "Failed to fence(%d)! Potential config issue?\n", ret);
0344         return ret;
0345     }
0346
0347     /* Alarm IRQ enable will do a sync */
0348     return ti_k3_rtc_alarm_irq_enable(dev, alarm->enabled);
0349 }
0350
0351 static int ti_k3_rtc_read_offset(struct device *dev, long *offset)
0352 {
0353     struct ti_k3_rtc *priv = dev_get_drvdata(dev);
0354     u32 ticks_per_hr = priv->rate_32k * 3600;
0355     int comp;
0356     s64 tmp;
0357
0358     comp = k3rtc_field_read(priv, K3RTC_COMP);
0359
0360     /* Convert from RTC calibration register format to ppb format */
0361     tmp = comp * (s64)K3RTC_PPB_MULT;
0362     if (tmp < 0)
0363         tmp -= ticks_per_hr / 2LL;
0364     else
0365         tmp += ticks_per_hr / 2LL;
0366     tmp = div_s64(tmp, ticks_per_hr);
0367
0368     /* Offset value operates in negative way, so swap sign */
0369     *offset = (long)-tmp;
0370
0371     return 0;
0372 }
0373
0374 static int ti_k3_rtc_set_offset(struct device *dev, long offset)
0375 {
0376     struct ti_k3_rtc *priv = dev_get_drvdata(dev);
0377     u32 ticks_per_hr = priv->rate_32k * 3600;
0378     int comp;
0379     s64 tmp;
0380
0381     /* Make sure offset value is within supported range */
0382     if (offset < K3RTC_MIN_OFFSET || offset > K3RTC_MAX_OFFSET)
0383         return -ERANGE;
0384
0385     /* Convert from ppb format to RTC calibration register format */
0386     tmp = offset * (s64)ticks_per_hr;
0387     if (tmp < 0)
0388         tmp -= K3RTC_PPB_MULT / 2LL;
0389     else
0390         tmp += K3RTC_PPB_MULT / 2LL;
0391     tmp = div_s64(tmp, K3RTC_PPB_MULT);
0392
0393     /* Offset value operates in negative way, so swap sign */
0394     comp = (int)-tmp;
0395
0396     k3rtc_field_write(priv, K3RTC_COMP, comp);
0397
0398     return k3rtc_fence(priv);
0399 }
0400
0401 static irqreturn_t ti_k3_rtc_interrupt(s32 irq, void *dev_id)
0402 {
0403     struct device *dev = dev_id;
0404     struct ti_k3_rtc *priv = dev_get_drvdata(dev);
0405     u32 reg;
0406     int ret;
0407
0408     /*
0409      * IRQ assertion can be very fast, however, the IRQ Status clear
0410      * de-assert depends on 32k clock edge in the 32k domain
0411      * If we clear the status prior to the first 32k clock edge,
0412      * the status bit is cleared, but the IRQ stays re-asserted.
0413      *
0414      * To prevent this condition, we need to wait for clock sync time.
0415      * We can either do that by polling the 32k observability signal for
0416      * a toggle OR we could just sleep and let the processor do other
0417      * stuff.
0418      */
0419     usleep_range(priv->sync_timeout_us, priv->sync_timeout_us + 2);
0420
0421     /* Lets make sure that this is a valid interrupt */
0422     reg = k3rtc_field_read(priv, K3RTC_IRQ_STATUS);
0423
0424     if (!reg) {
0425         u32 raw = k3rtc_field_read(priv, K3RTC_IRQ_STATUS_RAW);
0426
0427         dev_err(dev,
0428             HW_ERR
0429             "Erratum i2327/IRQ trig: status: 0x%08x / 0x%08x\n", reg, raw);
0430         return IRQ_NONE;
0431     }
0432
0433     /*
0434      * Write 1 to clear status reg
0435      * We cannot use a field operation here due to a potential race between
0436      * 32k domain and vbus domain.
0437      */
0438     regmap_write(priv->regmap, REG_K3RTC_IRQSTATUS_SYS, 0x1);
0439
0440     /* Sync the write in */
0441     ret = k3rtc_fence(priv);
0442     if (ret) {
0443         dev_err(dev, "Failed to fence irq status clr(%d)!\n", ret);
0444         return IRQ_NONE;
0445     }
0446
0447     /*
0448      * Force the 32k status to be reloaded back in to ensure status is
0449      * reflected back correctly.
0450      */
0451     k3rtc_field_write(priv, K3RTC_RELOAD_FROM_BBD, 0x1);
0452
0453     /* Ensure the write sync is through */
0454     ret = k3rtc_fence(priv);
0455     if (ret) {
0456         dev_err(dev, "Failed to fence reload from bbd(%d)!\n", ret);
0457         return IRQ_NONE;
0458     }
0459
0460     /* Now we ensure that the status bit is cleared */
0461     ret = regmap_field_read_poll_timeout(priv->r_fields[K3RTC_IRQ_STATUS],
0462                          ret, !ret, 2, priv->sync_timeout_us);
0463     if (ret) {
0464         dev_err(dev, "Time out waiting for status clear\n");
0465         return IRQ_NONE;
0466     }
0467
0468     /* Notify RTC core on event */
0469     rtc_update_irq(priv->rtc_dev, 1, RTC_IRQF | RTC_AF);
0470
0471     return IRQ_HANDLED;
0472 }
0473
0474 static const struct rtc_class_ops ti_k3_rtc_ops = {
0475     .read_time = ti_k3_rtc_read_time,
0476     .set_time = ti_k3_rtc_set_time,
0477     .read_alarm = ti_k3_rtc_read_alarm,
0478     .set_alarm = ti_k3_rtc_set_alarm,
0479     .read_offset = ti_k3_rtc_read_offset,
0480     .set_offset = ti_k3_rtc_set_offset,
0481     .alarm_irq_enable = ti_k3_rtc_alarm_irq_enable,
0482 };
0483
0484 static int ti_k3_rtc_scratch_read(void *priv_data, unsigned int offset,
0485                   void *val, size_t bytes)
0486 {
0487     struct ti_k3_rtc *priv = (struct ti_k3_rtc *)priv_data;
0488
0489     return regmap_bulk_read(priv->regmap, REG_K3RTC_SCRATCH0 + offset, val, bytes / 4);
0490 }
0491
0492 static int ti_k3_rtc_scratch_write(void *priv_data, unsigned int offset,
0493                    void *val, size_t bytes)
0494 {
0495     struct ti_k3_rtc *priv = (struct ti_k3_rtc *)priv_data;
0496     int ret;
0497
0498     ret = regmap_bulk_write(priv->regmap, REG_K3RTC_SCRATCH0 + offset, val, bytes / 4);
0499     if (ret)
0500         return ret;
0501
0502     return k3rtc_fence(priv);
0503 }
0504
0505 static struct nvmem_config ti_k3_rtc_nvmem_config = {
0506     .name = "ti_k3_rtc_scratch",
0507     .word_size = 4,
0508     .stride = 4,
0509     .size = REG_K3RTC_SCRATCH7 - REG_K3RTC_SCRATCH0 + 4,
0510     .reg_read = ti_k3_rtc_scratch_read,
0511     .reg_write = ti_k3_rtc_scratch_write,
0512 };
0513
0514 static int k3rtc_get_32kclk(struct device *dev, struct ti_k3_rtc *priv)
0515 {
0516     int ret;
0517     struct clk *clk;
0518
0519     clk = devm_clk_get(dev, "osc32k");
0520     if (IS_ERR(clk))
0521         return PTR_ERR(clk);
0522
0523     ret = clk_prepare_enable(clk);
0524     if (ret)
0525         return ret;
0526
0527     ret = devm_add_action_or_reset(dev, (void (*)(void *))clk_disable_unprepare, clk);
0528     if (ret)
0529         return ret;
0530
0531     priv->rate_32k = clk_get_rate(clk);
0532
0533     /* Make sure we are exact 32k clock. Else, try to compensate delay */
0534     if (priv->rate_32k != 32768)
0535         dev_warn(dev, "Clock rate %ld is not 32768! Could misbehave!\n",
0536              priv->rate_32k);
0537
0538     /*
0539      * Sync timeout should be two 32k clk sync cycles = ~61uS. We double
0540      * it to comprehend intermediate bus segment and cpu frequency
0541      * deltas
0542      */
0543     priv->sync_timeout_us = (u32)(DIV_ROUND_UP_ULL(1000000, priv->rate_32k) * 4);
0544
0545     return ret;
0546 }
0547
0548 static int k3rtc_get_vbusclk(struct device *dev, struct ti_k3_rtc *priv)
0549 {
0550     int ret;
0551     struct clk *clk;
0552
0553     /* Note: VBUS isn't a context clock, it is needed for hardware operation */
0554     clk = devm_clk_get(dev, "vbus");
0555     if (IS_ERR(clk))
0556         return PTR_ERR(clk);
0557
0558     ret = clk_prepare_enable(clk);
0559     if (ret)
0560         return ret;
0561
0562     return devm_add_action_or_reset(dev, (void (*)(void *))clk_disable_unprepare, clk);
0563 }
0564
0565 static int ti_k3_rtc_probe(struct platform_device *pdev)
0566 {
0567     struct device *dev = &pdev->dev;
0568     struct ti_k3_rtc *priv;
0569     void __iomem *rtc_base;
0570     int ret;
0571
0572     priv = devm_kzalloc(dev, sizeof(struct ti_k3_rtc), GFP_KERNEL);
0573     if (!priv)
0574         return -ENOMEM;
0575
0576     rtc_base = devm_platform_ioremap_resource(pdev, 0);
0577     if (IS_ERR(rtc_base))
0578         return PTR_ERR(rtc_base);
0579
0580     priv->regmap = devm_regmap_init_mmio(dev, rtc_base, &ti_k3_rtc_regmap_config);
0581     if (IS_ERR(priv->regmap))
0582         return PTR_ERR(priv->regmap);
0583
0584     ret = devm_regmap_field_bulk_alloc(dev, priv->regmap, priv->r_fields,
0585                        ti_rtc_reg_fields, K3_RTC_MAX_FIELDS);
0586     if (ret)
0587         return ret;
0588
0589     ret = k3rtc_get_32kclk(dev, priv);
0590     if (ret)
0591         return ret;
0592     ret = k3rtc_get_vbusclk(dev, priv);
0593     if (ret)
0594         return ret;
0595
0596     ret = platform_get_irq(pdev, 0);
0597     if (ret < 0)
0598         return ret;
0599     priv->irq = (unsigned int)ret;
0600
0601     priv->rtc_dev = devm_rtc_allocate_device(dev);
0602     if (IS_ERR(priv->rtc_dev))
0603         return PTR_ERR(priv->rtc_dev);
0604
0605     priv->soc = of_device_get_match_data(dev);
0606
0607     priv->rtc_dev->ops = &ti_k3_rtc_ops;
0608     priv->rtc_dev->range_max = (1ULL << 48) - 1;    /* 48Bit seconds */
0609     ti_k3_rtc_nvmem_config.priv = priv;
0610
0611     ret = devm_request_threaded_irq(dev, priv->irq, NULL,
0612                     ti_k3_rtc_interrupt,
0613                     IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
0614                     dev_name(dev), dev);
0615     if (ret) {
0616         dev_err(dev, "Could not request IRQ: %d\n", ret);
0617         return ret;
0618     }
0619
0620     platform_set_drvdata(pdev, priv);
0621
0622     ret = k3rtc_configure(dev);
0623     if (ret)
0624         return ret;
0625
0626     if (device_property_present(dev, "wakeup-source"))
0627         device_init_wakeup(dev, true);
0628     else
0629         device_set_wakeup_capable(dev, true);
0630
0631     ret = devm_rtc_register_device(priv->rtc_dev);
0632     if (ret)
0633         return ret;
0634
0635     return devm_rtc_nvmem_register(priv->rtc_dev, &ti_k3_rtc_nvmem_config);
0636 }
0637
0638 static const struct ti_k3_rtc_soc_data ti_k3_am62_data = {
0639     .unlock_irq_erratum = true,
0640 };
0641
0642 static const struct of_device_id ti_k3_rtc_of_match_table[] = {
0643     {.compatible = "ti,am62-rtc", .data = &ti_k3_am62_data},
0644     {}
0645 };
0646 MODULE_DEVICE_TABLE(of, ti_k3_rtc_of_match_table);
0647
0648 static int __maybe_unused ti_k3_rtc_suspend(struct device *dev)
0649 {
0650     struct ti_k3_rtc *priv = dev_get_drvdata(dev);
0651
0652     if (device_may_wakeup(dev))
0653         enable_irq_wake(priv->irq);
0654     return 0;
0655 }
0656
0657 static int __maybe_unused ti_k3_rtc_resume(struct device *dev)
0658 {
0659     struct ti_k3_rtc *priv = dev_get_drvdata(dev);
0660
0661     if (device_may_wakeup(dev))
0662         disable_irq_wake(priv->irq);
0663     return 0;
0664 }
0665
0666 static SIMPLE_DEV_PM_OPS(ti_k3_rtc_pm_ops, ti_k3_rtc_suspend, ti_k3_rtc_resume);
0667
0668 static struct platform_driver ti_k3_rtc_driver = {
0669     .probe = ti_k3_rtc_probe,
0670     .driver = {
0671            .name = "rtc-ti-k3",
0672            .of_match_table = ti_k3_rtc_of_match_table,
0673            .pm = &ti_k3_rtc_pm_ops,
0674     },
0675 };
0676 module_platform_driver(ti_k3_rtc_driver);
0677
0678 MODULE_LICENSE("GPL");
0679 MODULE_DESCRIPTION("TI K3 RTC driver");
0680 MODULE_AUTHOR("Nishanth Menon");