drivers/rtc/rtc-tegra.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * An RTC driver for the NVIDIA Tegra 200 series internal RTC.
0004  *
0005  * Copyright (c) 2010-2019, NVIDIA Corporation.
0006  */
0007
0008 #include <linux/clk.h>
0009 #include <linux/delay.h>
0010 #include <linux/init.h>
0011 #include <linux/io.h>
0012 #include <linux/irq.h>
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/mod_devicetable.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/pm.h>
0018 #include <linux/rtc.h>
0019 #include <linux/slab.h>
0020
0021 /* Set to 1 = busy every eight 32 kHz clocks during copy of sec+msec to AHB. */
0022 #define TEGRA_RTC_REG_BUSY          0x004
0023 #define TEGRA_RTC_REG_SECONDS           0x008
0024 /* When msec is read, the seconds are buffered into shadow seconds. */
0025 #define TEGRA_RTC_REG_SHADOW_SECONDS        0x00c
0026 #define TEGRA_RTC_REG_MILLI_SECONDS     0x010
0027 #define TEGRA_RTC_REG_SECONDS_ALARM0        0x014
0028 #define TEGRA_RTC_REG_SECONDS_ALARM1        0x018
0029 #define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0  0x01c
0030 #define TEGRA_RTC_REG_INTR_MASK         0x028
0031 /* write 1 bits to clear status bits */
0032 #define TEGRA_RTC_REG_INTR_STATUS       0x02c
0033
0034 /* bits in INTR_MASK */
0035 #define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM  (1<<4)
0036 #define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM   (1<<3)
0037 #define TEGRA_RTC_INTR_MASK_MSEC_ALARM      (1<<2)
0038 #define TEGRA_RTC_INTR_MASK_SEC_ALARM1      (1<<1)
0039 #define TEGRA_RTC_INTR_MASK_SEC_ALARM0      (1<<0)
0040
0041 /* bits in INTR_STATUS */
0042 #define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM    (1<<4)
0043 #define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM (1<<3)
0044 #define TEGRA_RTC_INTR_STATUS_MSEC_ALARM    (1<<2)
0045 #define TEGRA_RTC_INTR_STATUS_SEC_ALARM1    (1<<1)
0046 #define TEGRA_RTC_INTR_STATUS_SEC_ALARM0    (1<<0)
0047
0048 struct tegra_rtc_info {
0049     struct platform_device *pdev;
0050     struct rtc_device *rtc;
0051     void __iomem *base; /* NULL if not initialized */
0052     struct clk *clk;
0053     int irq; /* alarm and periodic IRQ */
0054     spinlock_t lock;
0055 };
0056
0057 /*
0058  * RTC hardware is busy when it is updating its values over AHB once every
0059  * eight 32 kHz clocks (~250 us). Outside of these updates the CPU is free to
0060  * write. CPU is always free to read.
0061  */
0062 static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
0063 {
0064     return readl(info->base + TEGRA_RTC_REG_BUSY) & 1;
0065 }
0066
0067 /*
0068  * Wait for hardware to be ready for writing. This function tries to maximize
0069  * the amount of time before the next update. It does this by waiting for the
0070  * RTC to become busy with its periodic update, then returning once the RTC
0071  * first becomes not busy.
0072  *
0073  * This periodic update (where the seconds and milliseconds are copied to the
0074  * AHB side) occurs every eight 32 kHz clocks (~250 us). The behavior of this
0075  * function allows us to make some assumptions without introducing a race,
0076  * because 250 us is plenty of time to read/write a value.
0077  */
0078 static int tegra_rtc_wait_while_busy(struct device *dev)
0079 {
0080     struct tegra_rtc_info *info = dev_get_drvdata(dev);
0081     int retries = 500; /* ~490 us is the worst case, ~250 us is best */
0082
0083     /*
0084      * First wait for the RTC to become busy. This is when it posts its
0085      * updated seconds+msec registers to AHB side.
0086      */
0087     while (tegra_rtc_check_busy(info)) {
0088         if (!retries--)
0089             goto retry_failed;
0090
0091         udelay(1);
0092     }
0093
0094     /* now we have about 250 us to manipulate registers */
0095     return 0;
0096
0097 retry_failed:
0098     dev_err(dev, "write failed: retry count exceeded\n");
0099     return -ETIMEDOUT;
0100 }
0101
0102 static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm)
0103 {
0104     struct tegra_rtc_info *info = dev_get_drvdata(dev);
0105     unsigned long flags;
0106     u32 sec;
0107
0108     /*
0109      * RTC hardware copies seconds to shadow seconds when a read of
0110      * milliseconds occurs. use a lock to keep other threads out.
0111      */
0112     spin_lock_irqsave(&info->lock, flags);
0113
0114     readl(info->base + TEGRA_RTC_REG_MILLI_SECONDS);
0115     sec = readl(info->base + TEGRA_RTC_REG_SHADOW_SECONDS);
0116
0117     spin_unlock_irqrestore(&info->lock, flags);
0118
0119     rtc_time64_to_tm(sec, tm);
0120
0121     dev_vdbg(dev, "time read as %u, %ptR\n", sec, tm);
0122
0123     return 0;
0124 }
0125
0126 static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm)
0127 {
0128     struct tegra_rtc_info *info = dev_get_drvdata(dev);
0129     u32 sec;
0130     int ret;
0131
0132     /* convert tm to seconds */
0133     sec = rtc_tm_to_time64(tm);
0134
0135     dev_vdbg(dev, "time set to %u, %ptR\n", sec, tm);
0136
0137     /* seconds only written if wait succeeded */
0138     ret = tegra_rtc_wait_while_busy(dev);
0139     if (!ret)
0140         writel(sec, info->base + TEGRA_RTC_REG_SECONDS);
0141
0142     dev_vdbg(dev, "time read back as %d\n",
0143          readl(info->base + TEGRA_RTC_REG_SECONDS));
0144
0145     return ret;
0146 }
0147
0148 static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
0149 {
0150     struct tegra_rtc_info *info = dev_get_drvdata(dev);
0151     u32 sec, value;
0152
0153     sec = readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
0154
0155     if (sec == 0) {
0156         /* alarm is disabled */
0157         alarm->enabled = 0;
0158     } else {
0159         /* alarm is enabled */
0160         alarm->enabled = 1;
0161         rtc_time64_to_tm(sec, &alarm->time);
0162     }
0163
0164     value = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
0165     alarm->pending = (value & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;
0166
0167     return 0;
0168 }
0169
0170 static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
0171 {
0172     struct tegra_rtc_info *info = dev_get_drvdata(dev);
0173     unsigned long flags;
0174     u32 status;
0175
0176     tegra_rtc_wait_while_busy(dev);
0177     spin_lock_irqsave(&info->lock, flags);
0178
0179     /* read the original value, and OR in the flag */
0180     status = readl(info->base + TEGRA_RTC_REG_INTR_MASK);
0181     if (enabled)
0182         status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
0183     else
0184         status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */
0185
0186     writel(status, info->base + TEGRA_RTC_REG_INTR_MASK);
0187
0188     spin_unlock_irqrestore(&info->lock, flags);
0189
0190     return 0;
0191 }
0192
0193 static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
0194 {
0195     struct tegra_rtc_info *info = dev_get_drvdata(dev);
0196     u32 sec;
0197
0198     if (alarm->enabled)
0199         sec = rtc_tm_to_time64(&alarm->time);
0200     else
0201         sec = 0;
0202
0203     tegra_rtc_wait_while_busy(dev);
0204     writel(sec, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
0205     dev_vdbg(dev, "alarm read back as %d\n",
0206          readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0));
0207
0208     /* if successfully written and alarm is enabled ... */
0209     if (sec) {
0210         tegra_rtc_alarm_irq_enable(dev, 1);
0211         dev_vdbg(dev, "alarm set as %u, %ptR\n", sec, &alarm->time);
0212     } else {
0213         /* disable alarm if 0 or write error */
0214         dev_vdbg(dev, "alarm disabled\n");
0215         tegra_rtc_alarm_irq_enable(dev, 0);
0216     }
0217
0218     return 0;
0219 }
0220
0221 static int tegra_rtc_proc(struct device *dev, struct seq_file *seq)
0222 {
0223     if (!dev || !dev->driver)
0224         return 0;
0225
0226     seq_printf(seq, "name\t\t: %s\n", dev_name(dev));
0227
0228     return 0;
0229 }
0230
0231 static irqreturn_t tegra_rtc_irq_handler(int irq, void *data)
0232 {
0233     struct device *dev = data;
0234     struct tegra_rtc_info *info = dev_get_drvdata(dev);
0235     unsigned long events = 0;
0236     u32 status;
0237
0238     status = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
0239     if (status) {
0240         /* clear the interrupt masks and status on any IRQ */
0241         tegra_rtc_wait_while_busy(dev);
0242
0243         spin_lock(&info->lock);
0244         writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);
0245         writel(status, info->base + TEGRA_RTC_REG_INTR_STATUS);
0246         spin_unlock(&info->lock);
0247     }
0248
0249     /* check if alarm */
0250     if (status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0)
0251         events |= RTC_IRQF | RTC_AF;
0252
0253     /* check if periodic */
0254     if (status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM)
0255         events |= RTC_IRQF | RTC_PF;
0256
0257     rtc_update_irq(info->rtc, 1, events);
0258
0259     return IRQ_HANDLED;
0260 }
0261
0262 static const struct rtc_class_ops tegra_rtc_ops = {
0263     .read_time = tegra_rtc_read_time,
0264     .set_time = tegra_rtc_set_time,
0265     .read_alarm = tegra_rtc_read_alarm,
0266     .set_alarm = tegra_rtc_set_alarm,
0267     .proc = tegra_rtc_proc,
0268     .alarm_irq_enable = tegra_rtc_alarm_irq_enable,
0269 };
0270
0271 static const struct of_device_id tegra_rtc_dt_match[] = {
0272     { .compatible = "nvidia,tegra20-rtc", },
0273     {}
0274 };
0275 MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match);
0276
0277 static int tegra_rtc_probe(struct platform_device *pdev)
0278 {
0279     struct tegra_rtc_info *info;
0280     int ret;
0281
0282     info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
0283     if (!info)
0284         return -ENOMEM;
0285
0286     info->base = devm_platform_ioremap_resource(pdev, 0);
0287     if (IS_ERR(info->base))
0288         return PTR_ERR(info->base);
0289
0290     ret = platform_get_irq(pdev, 0);
0291     if (ret <= 0)
0292         return ret;
0293
0294     info->irq = ret;
0295
0296     info->rtc = devm_rtc_allocate_device(&pdev->dev);
0297     if (IS_ERR(info->rtc))
0298         return PTR_ERR(info->rtc);
0299
0300     info->rtc->ops = &tegra_rtc_ops;
0301     info->rtc->range_max = U32_MAX;
0302
0303     info->clk = devm_clk_get(&pdev->dev, NULL);
0304     if (IS_ERR(info->clk))
0305         return PTR_ERR(info->clk);
0306
0307     ret = clk_prepare_enable(info->clk);
0308     if (ret < 0)
0309         return ret;
0310
0311     /* set context info */
0312     info->pdev = pdev;
0313     spin_lock_init(&info->lock);
0314
0315     platform_set_drvdata(pdev, info);
0316
0317     /* clear out the hardware */
0318     writel(0, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
0319     writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
0320     writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);
0321
0322     device_init_wakeup(&pdev->dev, 1);
0323
0324     ret = devm_request_irq(&pdev->dev, info->irq, tegra_rtc_irq_handler,
0325                    IRQF_TRIGGER_HIGH, dev_name(&pdev->dev),
0326                    &pdev->dev);
0327     if (ret) {
0328         dev_err(&pdev->dev, "failed to request interrupt: %d\n", ret);
0329         goto disable_clk;
0330     }
0331
0332     ret = devm_rtc_register_device(info->rtc);
0333     if (ret)
0334         goto disable_clk;
0335
0336     dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");
0337
0338     return 0;
0339
0340 disable_clk:
0341     clk_disable_unprepare(info->clk);
0342     return ret;
0343 }
0344
0345 static int tegra_rtc_remove(struct platform_device *pdev)
0346 {
0347     struct tegra_rtc_info *info = platform_get_drvdata(pdev);
0348
0349     clk_disable_unprepare(info->clk);
0350
0351     return 0;
0352 }
0353
0354 #ifdef CONFIG_PM_SLEEP
0355 static int tegra_rtc_suspend(struct device *dev)
0356 {
0357     struct tegra_rtc_info *info = dev_get_drvdata(dev);
0358
0359     tegra_rtc_wait_while_busy(dev);
0360
0361     /* only use ALARM0 as a wake source */
0362     writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
0363     writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
0364            info->base + TEGRA_RTC_REG_INTR_MASK);
0365
0366     dev_vdbg(dev, "alarm sec = %d\n",
0367          readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0));
0368
0369     dev_vdbg(dev, "Suspend (device_may_wakeup=%d) IRQ:%d\n",
0370          device_may_wakeup(dev), info->irq);
0371
0372     /* leave the alarms on as a wake source */
0373     if (device_may_wakeup(dev))
0374         enable_irq_wake(info->irq);
0375
0376     return 0;
0377 }
0378
0379 static int tegra_rtc_resume(struct device *dev)
0380 {
0381     struct tegra_rtc_info *info = dev_get_drvdata(dev);
0382
0383     dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
0384          device_may_wakeup(dev));
0385
0386     /* alarms were left on as a wake source, turn them off */
0387     if (device_may_wakeup(dev))
0388         disable_irq_wake(info->irq);
0389
0390     return 0;
0391 }
0392 #endif
0393
0394 static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume);
0395
0396 static void tegra_rtc_shutdown(struct platform_device *pdev)
0397 {
0398     dev_vdbg(&pdev->dev, "disabling interrupts\n");
0399     tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
0400 }
0401
0402 static struct platform_driver tegra_rtc_driver = {
0403     .probe = tegra_rtc_probe,
0404     .remove = tegra_rtc_remove,
0405     .shutdown = tegra_rtc_shutdown,
0406     .driver = {
0407         .name = "tegra_rtc",
0408         .of_match_table = tegra_rtc_dt_match,
0409         .pm = &tegra_rtc_pm_ops,
0410     },
0411 };
0412 module_platform_driver(tegra_rtc_driver);
0413
0414 MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>");
0415 MODULE_DESCRIPTION("driver for Tegra internal RTC");
0416 MODULE_LICENSE("GPL");