drivers/rtc/rtc-sunplus.c

0001 // SPDX-License-Identifier: GPL-2.0
0002
0003 /*
0004  * The RTC driver for Sunplus   SP7021
0005  *
0006  * Copyright (C) 2019 Sunplus Technology Inc., All rights reseerved.
0007  */
0008
0009 #include <linux/bitfield.h>
0010 #include <linux/clk.h>
0011 #include <linux/err.h>
0012 #include <linux/io.h>
0013 #include <linux/ktime.h>
0014 #include <linux/module.h>
0015 #include <linux/of.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/reset.h>
0018 #include <linux/rtc.h>
0019
0020 #define RTC_REG_NAME            "rtc"
0021
0022 #define RTC_CTRL            0x40
0023 #define TIMER_FREEZE_MASK_BIT       BIT(5 + 16)
0024 #define TIMER_FREEZE            BIT(5)
0025 #define DIS_SYS_RST_RTC_MASK_BIT    BIT(4 + 16)
0026 #define DIS_SYS_RST_RTC         BIT(4)
0027 #define RTC32K_MODE_RESET_MASK_BIT  BIT(3 + 16)
0028 #define RTC32K_MODE_RESET       BIT(3)
0029 #define ALARM_EN_OVERDUE_MASK_BIT   BIT(2 + 16)
0030 #define ALARM_EN_OVERDUE        BIT(2)
0031 #define ALARM_EN_PMC_MASK_BIT       BIT(1 + 16)
0032 #define ALARM_EN_PMC            BIT(1)
0033 #define ALARM_EN_MASK_BIT       BIT(0 + 16)
0034 #define ALARM_EN            BIT(0)
0035 #define RTC_TIMER_OUT           0x44
0036 #define RTC_DIVIDER         0x48
0037 #define RTC_TIMER_SET           0x4c
0038 #define RTC_ALARM_SET           0x50
0039 #define RTC_USER_DATA           0x54
0040 #define RTC_RESET_RECORD        0x58
0041 #define RTC_BATT_CHARGE_CTRL        0x5c
0042 #define BAT_CHARGE_RSEL_MASK_BIT    GENMASK(3 + 16, 2 + 16)
0043 #define BAT_CHARGE_RSEL_MASK        GENMASK(3, 2)
0044 #define BAT_CHARGE_RSEL_2K_OHM      FIELD_PREP(BAT_CHARGE_RSEL_MASK, 0)
0045 #define BAT_CHARGE_RSEL_250_OHM     FIELD_PREP(BAT_CHARGE_RSEL_MASK, 1)
0046 #define BAT_CHARGE_RSEL_50_OHM      FIELD_PREP(BAT_CHARGE_RSEL_MASK, 2)
0047 #define BAT_CHARGE_RSEL_0_OHM       FIELD_PREP(BAT_CHARGE_RSEL_MASK, 3)
0048 #define BAT_CHARGE_DSEL_MASK_BIT    BIT(1 + 16)
0049 #define BAT_CHARGE_DSEL_MASK        GENMASK(1, 1)
0050 #define BAT_CHARGE_DSEL_ON      FIELD_PREP(BAT_CHARGE_DSEL_MASK, 0)
0051 #define BAT_CHARGE_DSEL_OFF     FIELD_PREP(BAT_CHARGE_DSEL_MASK, 1)
0052 #define BAT_CHARGE_EN_MASK_BIT      BIT(0 + 16)
0053 #define BAT_CHARGE_EN           BIT(0)
0054 #define RTC_TRIM_CTRL           0x60
0055
0056 struct sunplus_rtc {
0057     struct rtc_device *rtc;
0058     struct resource *res;
0059     struct clk *rtcclk;
0060     struct reset_control *rstc;
0061     void __iomem *reg_base;
0062     int irq;
0063 };
0064
0065 static void sp_get_seconds(struct device *dev, unsigned long *secs)
0066 {
0067     struct sunplus_rtc *sp_rtc = dev_get_drvdata(dev);
0068
0069     *secs = (unsigned long)readl(sp_rtc->reg_base + RTC_TIMER_OUT);
0070 }
0071
0072 static void sp_set_seconds(struct device *dev, unsigned long secs)
0073 {
0074     struct sunplus_rtc *sp_rtc = dev_get_drvdata(dev);
0075
0076     writel((u32)secs, sp_rtc->reg_base + RTC_TIMER_SET);
0077 }
0078
0079 static int sp_rtc_read_time(struct device *dev, struct rtc_time *tm)
0080 {
0081     unsigned long secs;
0082
0083     sp_get_seconds(dev, &secs);
0084     rtc_time64_to_tm(secs, tm);
0085
0086     return 0;
0087 }
0088
0089 static int sp_rtc_set_time(struct device *dev, struct rtc_time *tm)
0090 {
0091     unsigned long secs;
0092
0093     secs = rtc_tm_to_time64(tm);
0094     dev_dbg(dev, "%s, secs = %lu\n", __func__, secs);
0095     sp_set_seconds(dev, secs);
0096
0097     return 0;
0098 }
0099
0100 static int sp_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0101 {
0102     struct sunplus_rtc *sp_rtc = dev_get_drvdata(dev);
0103     unsigned long alarm_time;
0104
0105     alarm_time = rtc_tm_to_time64(&alrm->time);
0106     dev_dbg(dev, "%s, alarm_time: %u\n", __func__, (u32)(alarm_time));
0107     writel((u32)alarm_time, sp_rtc->reg_base + RTC_ALARM_SET);
0108
0109     return 0;
0110 }
0111
0112 static int sp_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0113 {
0114     struct sunplus_rtc *sp_rtc = dev_get_drvdata(dev);
0115     unsigned int alarm_time;
0116
0117     alarm_time = readl(sp_rtc->reg_base + RTC_ALARM_SET);
0118     dev_dbg(dev, "%s, alarm_time: %u\n", __func__, alarm_time);
0119
0120     if (alarm_time == 0)
0121         alrm->enabled = 0;
0122     else
0123         alrm->enabled = 1;
0124
0125     rtc_time64_to_tm((unsigned long)(alarm_time), &alrm->time);
0126
0127     return 0;
0128 }
0129
0130 static int sp_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
0131 {
0132     struct sunplus_rtc *sp_rtc = dev_get_drvdata(dev);
0133
0134     if (enabled)
0135         writel((TIMER_FREEZE_MASK_BIT | DIS_SYS_RST_RTC_MASK_BIT |
0136             RTC32K_MODE_RESET_MASK_BIT | ALARM_EN_OVERDUE_MASK_BIT |
0137             ALARM_EN_PMC_MASK_BIT | ALARM_EN_MASK_BIT) |
0138             (DIS_SYS_RST_RTC | ALARM_EN_OVERDUE | ALARM_EN_PMC | ALARM_EN),
0139             sp_rtc->reg_base + RTC_CTRL);
0140     else
0141         writel((ALARM_EN_OVERDUE_MASK_BIT | ALARM_EN_PMC_MASK_BIT | ALARM_EN_MASK_BIT) |
0142             0x0, sp_rtc->reg_base + RTC_CTRL);
0143
0144     return 0;
0145 }
0146
0147 static const struct rtc_class_ops sp_rtc_ops = {
0148     .read_time =        sp_rtc_read_time,
0149     .set_time =     sp_rtc_set_time,
0150     .set_alarm =        sp_rtc_set_alarm,
0151     .read_alarm =       sp_rtc_read_alarm,
0152     .alarm_irq_enable = sp_rtc_alarm_irq_enable,
0153 };
0154
0155 static irqreturn_t sp_rtc_irq_handler(int irq, void *dev_id)
0156 {
0157     struct platform_device *plat_dev = dev_id;
0158     struct sunplus_rtc *sp_rtc = dev_get_drvdata(&plat_dev->dev);
0159
0160     rtc_update_irq(sp_rtc->rtc, 1, RTC_IRQF | RTC_AF);
0161     dev_dbg(&plat_dev->dev, "[RTC] ALARM INT\n");
0162
0163     return IRQ_HANDLED;
0164 }
0165
0166 /*
0167  * -------------------------------------------------------------------------------------
0168  * bat_charge_rsel   bat_charge_dsel   bat_charge_en     Remarks
0169  *         x              x                 0            Disable
0170  *         0              0                 1            0.86mA (2K Ohm with diode)
0171  *         1              0                 1            1.81mA (250 Ohm with diode)
0172  *         2              0                 1            2.07mA (50 Ohm with diode)
0173  *         3              0                 1            16.0mA (0 Ohm with diode)
0174  *         0              1                 1            1.36mA (2K Ohm without diode)
0175  *         1              1                 1            3.99mA (250 Ohm without diode)
0176  *         2              1                 1            4.41mA (50 Ohm without diode)
0177  *         3              1                 1            16.0mA (0 Ohm without diode)
0178  * -------------------------------------------------------------------------------------
0179  */
0180 static void sp_rtc_set_trickle_charger(struct device dev)
0181 {
0182     struct sunplus_rtc *sp_rtc = dev_get_drvdata(&dev);
0183     u32 ohms, rsel;
0184     u32 chargeable;
0185
0186     if (of_property_read_u32(dev.of_node, "trickle-resistor-ohms", &ohms) ||
0187         of_property_read_u32(dev.of_node, "aux-voltage-chargeable", &chargeable)) {
0188         dev_warn(&dev, "battery charger disabled\n");
0189         return;
0190     }
0191
0192     switch (ohms) {
0193     case 2000:
0194         rsel = BAT_CHARGE_RSEL_2K_OHM;
0195         break;
0196     case 250:
0197         rsel = BAT_CHARGE_RSEL_250_OHM;
0198         break;
0199     case 50:
0200         rsel = BAT_CHARGE_RSEL_50_OHM;
0201         break;
0202     case 0:
0203         rsel = BAT_CHARGE_RSEL_0_OHM;
0204         break;
0205     default:
0206         dev_err(&dev, "invalid charger resistor value (%d)\n", ohms);
0207         return;
0208     }
0209
0210     writel(BAT_CHARGE_RSEL_MASK_BIT | rsel, sp_rtc->reg_base + RTC_BATT_CHARGE_CTRL);
0211
0212     switch (chargeable) {
0213     case 0:
0214         writel(BAT_CHARGE_DSEL_MASK_BIT | BAT_CHARGE_DSEL_OFF,
0215                sp_rtc->reg_base + RTC_BATT_CHARGE_CTRL);
0216         break;
0217     case 1:
0218         writel(BAT_CHARGE_DSEL_MASK_BIT | BAT_CHARGE_DSEL_ON,
0219                sp_rtc->reg_base + RTC_BATT_CHARGE_CTRL);
0220         break;
0221     default:
0222         dev_err(&dev, "invalid aux-voltage-chargeable value (%d)\n", chargeable);
0223         return;
0224     }
0225
0226     writel(BAT_CHARGE_EN_MASK_BIT | BAT_CHARGE_EN, sp_rtc->reg_base + RTC_BATT_CHARGE_CTRL);
0227 }
0228
0229 static int sp_rtc_probe(struct platform_device *plat_dev)
0230 {
0231     struct sunplus_rtc *sp_rtc;
0232     int ret;
0233
0234     sp_rtc = devm_kzalloc(&plat_dev->dev, sizeof(*sp_rtc), GFP_KERNEL);
0235     if (!sp_rtc)
0236         return -ENOMEM;
0237
0238     sp_rtc->res = platform_get_resource_byname(plat_dev, IORESOURCE_MEM, RTC_REG_NAME);
0239     sp_rtc->reg_base = devm_ioremap_resource(&plat_dev->dev, sp_rtc->res);
0240     if (IS_ERR(sp_rtc->reg_base))
0241         return dev_err_probe(&plat_dev->dev, PTR_ERR(sp_rtc->reg_base),
0242                         "%s devm_ioremap_resource fail\n", RTC_REG_NAME);
0243     dev_dbg(&plat_dev->dev, "res = 0x%x, reg_base = 0x%lx\n",
0244         sp_rtc->res->start, (unsigned long)sp_rtc->reg_base);
0245
0246     sp_rtc->irq = platform_get_irq(plat_dev, 0);
0247     if (sp_rtc->irq < 0)
0248         return dev_err_probe(&plat_dev->dev, sp_rtc->irq, "platform_get_irq failed\n");
0249
0250     ret = devm_request_irq(&plat_dev->dev, sp_rtc->irq, sp_rtc_irq_handler,
0251                    IRQF_TRIGGER_RISING, "rtc irq", plat_dev);
0252     if (ret)
0253         return dev_err_probe(&plat_dev->dev, ret, "devm_request_irq failed:\n");
0254
0255     sp_rtc->rtcclk = devm_clk_get(&plat_dev->dev, NULL);
0256     if (IS_ERR(sp_rtc->rtcclk))
0257         return dev_err_probe(&plat_dev->dev, PTR_ERR(sp_rtc->rtcclk),
0258                         "devm_clk_get fail\n");
0259
0260     sp_rtc->rstc = devm_reset_control_get_exclusive(&plat_dev->dev, NULL);
0261     if (IS_ERR(sp_rtc->rstc))
0262         return dev_err_probe(&plat_dev->dev, PTR_ERR(sp_rtc->rstc),
0263                         "failed to retrieve reset controller\n");
0264
0265     ret = clk_prepare_enable(sp_rtc->rtcclk);
0266     if (ret)
0267         goto free_clk;
0268
0269     ret = reset_control_deassert(sp_rtc->rstc);
0270     if (ret)
0271         goto free_reset_assert;
0272
0273     device_init_wakeup(&plat_dev->dev, 1);
0274     dev_set_drvdata(&plat_dev->dev, sp_rtc);
0275
0276     sp_rtc->rtc = devm_rtc_allocate_device(&plat_dev->dev);
0277     if (IS_ERR(sp_rtc->rtc)) {
0278         ret = PTR_ERR(sp_rtc->rtc);
0279         goto free_reset_assert;
0280     }
0281
0282     sp_rtc->rtc->range_max = U32_MAX;
0283     sp_rtc->rtc->range_min = 0;
0284     sp_rtc->rtc->ops = &sp_rtc_ops;
0285
0286     ret = devm_rtc_register_device(sp_rtc->rtc);
0287     if (ret)
0288         goto free_reset_assert;
0289
0290     /* Setup trickle charger */
0291     if (plat_dev->dev.of_node)
0292         sp_rtc_set_trickle_charger(plat_dev->dev);
0293
0294     /* Keep RTC from system reset */
0295     writel(DIS_SYS_RST_RTC_MASK_BIT | DIS_SYS_RST_RTC, sp_rtc->reg_base + RTC_CTRL);
0296
0297     return 0;
0298
0299 free_reset_assert:
0300     reset_control_assert(sp_rtc->rstc);
0301 free_clk:
0302     clk_disable_unprepare(sp_rtc->rtcclk);
0303
0304     return ret;
0305 }
0306
0307 static int sp_rtc_remove(struct platform_device *plat_dev)
0308 {
0309     struct sunplus_rtc *sp_rtc = dev_get_drvdata(&plat_dev->dev);
0310
0311     device_init_wakeup(&plat_dev->dev, 0);
0312     reset_control_assert(sp_rtc->rstc);
0313     clk_disable_unprepare(sp_rtc->rtcclk);
0314
0315     return 0;
0316 }
0317
0318 #ifdef CONFIG_PM_SLEEP
0319 static int sp_rtc_suspend(struct device *dev)
0320 {
0321     struct sunplus_rtc *sp_rtc = dev_get_drvdata(dev);
0322
0323     if (device_may_wakeup(dev))
0324         enable_irq_wake(sp_rtc->irq);
0325
0326     return 0;
0327 }
0328
0329 static int sp_rtc_resume(struct device *dev)
0330 {
0331     struct sunplus_rtc *sp_rtc = dev_get_drvdata(dev);
0332
0333     if (device_may_wakeup(dev))
0334         disable_irq_wake(sp_rtc->irq);
0335
0336     return 0;
0337 }
0338 #endif
0339
0340 static const struct of_device_id sp_rtc_of_match[] = {
0341     { .compatible = "sunplus,sp7021-rtc" },
0342     { /* sentinel */ }
0343 };
0344 MODULE_DEVICE_TABLE(of, sp_rtc_of_match);
0345
0346 static SIMPLE_DEV_PM_OPS(sp_rtc_pm_ops, sp_rtc_suspend, sp_rtc_resume);
0347
0348 static struct platform_driver sp_rtc_driver = {
0349     .probe   = sp_rtc_probe,
0350     .remove  = sp_rtc_remove,
0351     .driver  = {
0352         .name   = "sp7021-rtc",
0353         .of_match_table = sp_rtc_of_match,
0354         .pm = &sp_rtc_pm_ops,
0355     },
0356 };
0357 module_platform_driver(sp_rtc_driver);
0358
0359 MODULE_AUTHOR("Vincent Shih <vincent.sunplus@gmail.com>");
0360 MODULE_DESCRIPTION("Sunplus RTC driver");
0361 MODULE_LICENSE("GPL v2");
0362