drivers/rtc/rtc-stmp3xxx.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Freescale STMP37XX/STMP378X Real Time Clock driver
0004  *
0005  * Copyright (c) 2007 Sigmatel, Inc.
0006  * Peter Hartley, <peter.hartley@sigmatel.com>
0007  *
0008  * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
0009  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
0010  * Copyright 2011 Wolfram Sang, Pengutronix e.K.
0011  */
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014 #include <linux/io.h>
0015 #include <linux/init.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/delay.h>
0019 #include <linux/rtc.h>
0020 #include <linux/slab.h>
0021 #include <linux/of_device.h>
0022 #include <linux/of.h>
0023 #include <linux/stmp_device.h>
0024 #include <linux/stmp3xxx_rtc_wdt.h>
0025
0026 #define STMP3XXX_RTC_CTRL           0x0
0027 #define STMP3XXX_RTC_CTRL_ALARM_IRQ_EN      0x00000001
0028 #define STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN    0x00000002
0029 #define STMP3XXX_RTC_CTRL_ALARM_IRQ     0x00000004
0030 #define STMP3XXX_RTC_CTRL_WATCHDOGEN        0x00000010
0031
0032 #define STMP3XXX_RTC_STAT           0x10
0033 #define STMP3XXX_RTC_STAT_STALE_SHIFT       16
0034 #define STMP3XXX_RTC_STAT_RTC_PRESENT       0x80000000
0035 #define STMP3XXX_RTC_STAT_XTAL32000_PRESENT 0x10000000
0036 #define STMP3XXX_RTC_STAT_XTAL32768_PRESENT 0x08000000
0037
0038 #define STMP3XXX_RTC_SECONDS            0x30
0039
0040 #define STMP3XXX_RTC_ALARM          0x40
0041
0042 #define STMP3XXX_RTC_WATCHDOG           0x50
0043
0044 #define STMP3XXX_RTC_PERSISTENT0        0x60
0045 #define STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE        (1 << 0)
0046 #define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN      (1 << 1)
0047 #define STMP3XXX_RTC_PERSISTENT0_ALARM_EN       (1 << 2)
0048 #define STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP    (1 << 4)
0049 #define STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP    (1 << 5)
0050 #define STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ        (1 << 6)
0051 #define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE     (1 << 7)
0052
0053 #define STMP3XXX_RTC_PERSISTENT1        0x70
0054 /* missing bitmask in headers */
0055 #define STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER  0x80000000
0056
0057 struct stmp3xxx_rtc_data {
0058     struct rtc_device *rtc;
0059     void __iomem *io;
0060     int irq_alarm;
0061 };
0062
0063 #if IS_ENABLED(CONFIG_STMP3XXX_RTC_WATCHDOG)
0064 /**
0065  * stmp3xxx_wdt_set_timeout - configure the watchdog inside the STMP3xxx RTC
0066  * @dev: the parent device of the watchdog (= the RTC)
0067  * @timeout: the desired value for the timeout register of the watchdog.
0068  *           0 disables the watchdog
0069  *
0070  * The watchdog needs one register and two bits which are in the RTC domain.
0071  * To handle the resource conflict, the RTC driver will create another
0072  * platform_device for the watchdog driver as a child of the RTC device.
0073  * The watchdog driver is passed the below accessor function via platform_data
0074  * to configure the watchdog. Locking is not needed because accessing SET/CLR
0075  * registers is atomic.
0076  */
0077
0078 static void stmp3xxx_wdt_set_timeout(struct device *dev, u32 timeout)
0079 {
0080     struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
0081
0082     if (timeout) {
0083         writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG);
0084         writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
0085                rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
0086         writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
0087                rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET);
0088     } else {
0089         writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
0090                rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
0091         writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
0092                rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR);
0093     }
0094 }
0095
0096 static struct stmp3xxx_wdt_pdata wdt_pdata = {
0097     .wdt_set_timeout = stmp3xxx_wdt_set_timeout,
0098 };
0099
0100 static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
0101 {
0102     int rc = -1;
0103     struct platform_device *wdt_pdev =
0104         platform_device_alloc("stmp3xxx_rtc_wdt", rtc_pdev->id);
0105
0106     if (wdt_pdev) {
0107         wdt_pdev->dev.parent = &rtc_pdev->dev;
0108         wdt_pdev->dev.platform_data = &wdt_pdata;
0109         rc = platform_device_add(wdt_pdev);
0110     }
0111
0112     if (rc)
0113         dev_err(&rtc_pdev->dev,
0114             "failed to register stmp3xxx_rtc_wdt\n");
0115 }
0116 #else
0117 static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
0118 {
0119 }
0120 #endif /* CONFIG_STMP3XXX_RTC_WATCHDOG */
0121
0122 static int stmp3xxx_wait_time(struct stmp3xxx_rtc_data *rtc_data)
0123 {
0124     int timeout = 5000; /* 3ms according to i.MX28 Ref Manual */
0125     /*
0126      * The i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
0127      * states:
0128      * | The order in which registers are updated is
0129      * | Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds.
0130      * | (This list is in bitfield order, from LSB to MSB, as they would
0131      * | appear in the STALE_REGS and NEW_REGS bitfields of the HW_RTC_STAT
0132      * | register. For example, the Seconds register corresponds to
0133      * | STALE_REGS or NEW_REGS containing 0x80.)
0134      */
0135     do {
0136         if (!(readl(rtc_data->io + STMP3XXX_RTC_STAT) &
0137                 (0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)))
0138             return 0;
0139         udelay(1);
0140     } while (--timeout > 0);
0141     return (readl(rtc_data->io + STMP3XXX_RTC_STAT) &
0142         (0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)) ? -ETIME : 0;
0143 }
0144
0145 /* Time read/write */
0146 static int stmp3xxx_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
0147 {
0148     int ret;
0149     struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
0150
0151     ret = stmp3xxx_wait_time(rtc_data);
0152     if (ret)
0153         return ret;
0154
0155     rtc_time64_to_tm(readl(rtc_data->io + STMP3XXX_RTC_SECONDS), rtc_tm);
0156     return 0;
0157 }
0158
0159 static int stmp3xxx_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
0160 {
0161     struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
0162
0163     writel(rtc_tm_to_time64(rtc_tm), rtc_data->io + STMP3XXX_RTC_SECONDS);
0164     return stmp3xxx_wait_time(rtc_data);
0165 }
0166
0167 /* interrupt(s) handler */
0168 static irqreturn_t stmp3xxx_rtc_interrupt(int irq, void *dev_id)
0169 {
0170     struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev_id);
0171     u32 status = readl(rtc_data->io + STMP3XXX_RTC_CTRL);
0172
0173     if (status & STMP3XXX_RTC_CTRL_ALARM_IRQ) {
0174         writel(STMP3XXX_RTC_CTRL_ALARM_IRQ,
0175             rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
0176         rtc_update_irq(rtc_data->rtc, 1, RTC_AF | RTC_IRQF);
0177         return IRQ_HANDLED;
0178     }
0179
0180     return IRQ_NONE;
0181 }
0182
0183 static int stmp3xxx_alarm_irq_enable(struct device *dev, unsigned int enabled)
0184 {
0185     struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
0186
0187     if (enabled) {
0188         writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
0189                 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
0190             rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
0191                 STMP_OFFSET_REG_SET);
0192         writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
0193             rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
0194     } else {
0195         writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
0196                 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
0197             rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
0198                 STMP_OFFSET_REG_CLR);
0199         writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
0200             rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
0201     }
0202     return 0;
0203 }
0204
0205 static int stmp3xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
0206 {
0207     struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
0208
0209     rtc_time64_to_tm(readl(rtc_data->io + STMP3XXX_RTC_ALARM), &alm->time);
0210     return 0;
0211 }
0212
0213 static int stmp3xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
0214 {
0215     struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
0216
0217     writel(rtc_tm_to_time64(&alm->time), rtc_data->io + STMP3XXX_RTC_ALARM);
0218
0219     stmp3xxx_alarm_irq_enable(dev, alm->enabled);
0220
0221     return 0;
0222 }
0223
0224 static const struct rtc_class_ops stmp3xxx_rtc_ops = {
0225     .alarm_irq_enable =
0226               stmp3xxx_alarm_irq_enable,
0227     .read_time  = stmp3xxx_rtc_gettime,
0228     .set_time   = stmp3xxx_rtc_settime,
0229     .read_alarm = stmp3xxx_rtc_read_alarm,
0230     .set_alarm  = stmp3xxx_rtc_set_alarm,
0231 };
0232
0233 static int stmp3xxx_rtc_remove(struct platform_device *pdev)
0234 {
0235     struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(pdev);
0236
0237     if (!rtc_data)
0238         return 0;
0239
0240     writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
0241         rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
0242
0243     return 0;
0244 }
0245
0246 static int stmp3xxx_rtc_probe(struct platform_device *pdev)
0247 {
0248     struct stmp3xxx_rtc_data *rtc_data;
0249     struct resource *r;
0250     u32 rtc_stat;
0251     u32 pers0_set, pers0_clr;
0252     u32 crystalfreq = 0;
0253     int err;
0254
0255     rtc_data = devm_kzalloc(&pdev->dev, sizeof(*rtc_data), GFP_KERNEL);
0256     if (!rtc_data)
0257         return -ENOMEM;
0258
0259     r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0260     if (!r) {
0261         dev_err(&pdev->dev, "failed to get resource\n");
0262         return -ENXIO;
0263     }
0264
0265     rtc_data->io = devm_ioremap(&pdev->dev, r->start, resource_size(r));
0266     if (!rtc_data->io) {
0267         dev_err(&pdev->dev, "ioremap failed\n");
0268         return -EIO;
0269     }
0270
0271     rtc_data->irq_alarm = platform_get_irq(pdev, 0);
0272
0273     rtc_stat = readl(rtc_data->io + STMP3XXX_RTC_STAT);
0274     if (!(rtc_stat & STMP3XXX_RTC_STAT_RTC_PRESENT)) {
0275         dev_err(&pdev->dev, "no device onboard\n");
0276         return -ENODEV;
0277     }
0278
0279     platform_set_drvdata(pdev, rtc_data);
0280
0281     /*
0282      * Resetting the rtc stops the watchdog timer that is potentially
0283      * running. So (assuming it is running on purpose) don't reset if the
0284      * watchdog is enabled.
0285      */
0286     if (readl(rtc_data->io + STMP3XXX_RTC_CTRL) &
0287         STMP3XXX_RTC_CTRL_WATCHDOGEN) {
0288         dev_info(&pdev->dev,
0289              "Watchdog is running, skip resetting rtc\n");
0290     } else {
0291         err = stmp_reset_block(rtc_data->io);
0292         if (err) {
0293             dev_err(&pdev->dev, "stmp_reset_block failed: %d\n",
0294                 err);
0295             return err;
0296         }
0297     }
0298
0299     /*
0300      * Obviously the rtc needs a clock input to be able to run.
0301      * This clock can be provided by an external 32k crystal. If that one is
0302      * missing XTAL must not be disabled in suspend which consumes a
0303      * lot of power. Normally the presence and exact frequency (supported
0304      * are 32000 Hz and 32768 Hz) is detectable from fuses, but as reality
0305      * proves these fuses are not blown correctly on all machines, so the
0306      * frequency can be overridden in the device tree.
0307      */
0308     if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32000_PRESENT)
0309         crystalfreq = 32000;
0310     else if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32768_PRESENT)
0311         crystalfreq = 32768;
0312
0313     of_property_read_u32(pdev->dev.of_node, "stmp,crystal-freq",
0314                  &crystalfreq);
0315
0316     switch (crystalfreq) {
0317     case 32000:
0318         /* keep 32kHz crystal running in low-power mode */
0319         pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ |
0320             STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
0321             STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
0322         pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
0323         break;
0324     case 32768:
0325         /* keep 32.768kHz crystal running in low-power mode */
0326         pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
0327             STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
0328         pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP |
0329             STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ;
0330         break;
0331     default:
0332         dev_warn(&pdev->dev,
0333              "invalid crystal-freq specified in device-tree. Assuming no crystal\n");
0334         fallthrough;
0335     case 0:
0336         /* keep XTAL on in low-power mode */
0337         pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
0338         pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
0339             STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
0340     }
0341
0342     writel(pers0_set, rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
0343             STMP_OFFSET_REG_SET);
0344
0345     writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
0346             STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
0347             STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE | pers0_clr,
0348         rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
0349
0350     writel(STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN |
0351             STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
0352         rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
0353
0354     rtc_data->rtc = devm_rtc_allocate_device(&pdev->dev);
0355     if (IS_ERR(rtc_data->rtc))
0356         return PTR_ERR(rtc_data->rtc);
0357
0358     err = devm_request_irq(&pdev->dev, rtc_data->irq_alarm,
0359             stmp3xxx_rtc_interrupt, 0, "RTC alarm", &pdev->dev);
0360     if (err) {
0361         dev_err(&pdev->dev, "Cannot claim IRQ%d\n",
0362             rtc_data->irq_alarm);
0363         return err;
0364     }
0365
0366     rtc_data->rtc->ops = &stmp3xxx_rtc_ops;
0367     rtc_data->rtc->range_max = U32_MAX;
0368
0369     err = devm_rtc_register_device(rtc_data->rtc);
0370     if (err)
0371         return err;
0372
0373     stmp3xxx_wdt_register(pdev);
0374     return 0;
0375 }
0376
0377 #ifdef CONFIG_PM_SLEEP
0378 static int stmp3xxx_rtc_suspend(struct device *dev)
0379 {
0380     return 0;
0381 }
0382
0383 static int stmp3xxx_rtc_resume(struct device *dev)
0384 {
0385     struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
0386
0387     stmp_reset_block(rtc_data->io);
0388     writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
0389             STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
0390             STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
0391         rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
0392     return 0;
0393 }
0394 #endif
0395
0396 static SIMPLE_DEV_PM_OPS(stmp3xxx_rtc_pm_ops, stmp3xxx_rtc_suspend,
0397             stmp3xxx_rtc_resume);
0398
0399 static const struct of_device_id rtc_dt_ids[] = {
0400     { .compatible = "fsl,stmp3xxx-rtc", },
0401     { /* sentinel */ }
0402 };
0403 MODULE_DEVICE_TABLE(of, rtc_dt_ids);
0404
0405 static struct platform_driver stmp3xxx_rtcdrv = {
0406     .probe      = stmp3xxx_rtc_probe,
0407     .remove     = stmp3xxx_rtc_remove,
0408     .driver     = {
0409         .name   = "stmp3xxx-rtc",
0410         .pm = &stmp3xxx_rtc_pm_ops,
0411         .of_match_table = rtc_dt_ids,
0412     },
0413 };
0414
0415 module_platform_driver(stmp3xxx_rtcdrv);
0416
0417 MODULE_DESCRIPTION("STMP3xxx RTC Driver");
0418 MODULE_AUTHOR("dmitry pervushin <dpervushin@embeddedalley.com> and "
0419         "Wolfram Sang <kernel@pengutronix.de>");
0420 MODULE_LICENSE("GPL");