Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) STMicroelectronics 2017
0004  * Author:  Amelie Delaunay <amelie.delaunay@st.com>
0005  */
0006 
0007 #include <linux/bcd.h>
0008 #include <linux/clk.h>
0009 #include <linux/iopoll.h>
0010 #include <linux/ioport.h>
0011 #include <linux/mfd/syscon.h>
0012 #include <linux/module.h>
0013 #include <linux/of_device.h>
0014 #include <linux/pm_wakeirq.h>
0015 #include <linux/regmap.h>
0016 #include <linux/rtc.h>
0017 
0018 #define DRIVER_NAME "stm32_rtc"
0019 
0020 /* STM32_RTC_TR bit fields  */
0021 #define STM32_RTC_TR_SEC_SHIFT      0
0022 #define STM32_RTC_TR_SEC        GENMASK(6, 0)
0023 #define STM32_RTC_TR_MIN_SHIFT      8
0024 #define STM32_RTC_TR_MIN        GENMASK(14, 8)
0025 #define STM32_RTC_TR_HOUR_SHIFT     16
0026 #define STM32_RTC_TR_HOUR       GENMASK(21, 16)
0027 
0028 /* STM32_RTC_DR bit fields */
0029 #define STM32_RTC_DR_DATE_SHIFT     0
0030 #define STM32_RTC_DR_DATE       GENMASK(5, 0)
0031 #define STM32_RTC_DR_MONTH_SHIFT    8
0032 #define STM32_RTC_DR_MONTH      GENMASK(12, 8)
0033 #define STM32_RTC_DR_WDAY_SHIFT     13
0034 #define STM32_RTC_DR_WDAY       GENMASK(15, 13)
0035 #define STM32_RTC_DR_YEAR_SHIFT     16
0036 #define STM32_RTC_DR_YEAR       GENMASK(23, 16)
0037 
0038 /* STM32_RTC_CR bit fields */
0039 #define STM32_RTC_CR_FMT        BIT(6)
0040 #define STM32_RTC_CR_ALRAE      BIT(8)
0041 #define STM32_RTC_CR_ALRAIE     BIT(12)
0042 
0043 /* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */
0044 #define STM32_RTC_ISR_ALRAWF        BIT(0)
0045 #define STM32_RTC_ISR_INITS     BIT(4)
0046 #define STM32_RTC_ISR_RSF       BIT(5)
0047 #define STM32_RTC_ISR_INITF     BIT(6)
0048 #define STM32_RTC_ISR_INIT      BIT(7)
0049 #define STM32_RTC_ISR_ALRAF     BIT(8)
0050 
0051 /* STM32_RTC_PRER bit fields */
0052 #define STM32_RTC_PRER_PRED_S_SHIFT 0
0053 #define STM32_RTC_PRER_PRED_S       GENMASK(14, 0)
0054 #define STM32_RTC_PRER_PRED_A_SHIFT 16
0055 #define STM32_RTC_PRER_PRED_A       GENMASK(22, 16)
0056 
0057 /* STM32_RTC_ALRMAR and STM32_RTC_ALRMBR bit fields */
0058 #define STM32_RTC_ALRMXR_SEC_SHIFT  0
0059 #define STM32_RTC_ALRMXR_SEC        GENMASK(6, 0)
0060 #define STM32_RTC_ALRMXR_SEC_MASK   BIT(7)
0061 #define STM32_RTC_ALRMXR_MIN_SHIFT  8
0062 #define STM32_RTC_ALRMXR_MIN        GENMASK(14, 8)
0063 #define STM32_RTC_ALRMXR_MIN_MASK   BIT(15)
0064 #define STM32_RTC_ALRMXR_HOUR_SHIFT 16
0065 #define STM32_RTC_ALRMXR_HOUR       GENMASK(21, 16)
0066 #define STM32_RTC_ALRMXR_PM     BIT(22)
0067 #define STM32_RTC_ALRMXR_HOUR_MASK  BIT(23)
0068 #define STM32_RTC_ALRMXR_DATE_SHIFT 24
0069 #define STM32_RTC_ALRMXR_DATE       GENMASK(29, 24)
0070 #define STM32_RTC_ALRMXR_WDSEL      BIT(30)
0071 #define STM32_RTC_ALRMXR_WDAY_SHIFT 24
0072 #define STM32_RTC_ALRMXR_WDAY       GENMASK(27, 24)
0073 #define STM32_RTC_ALRMXR_DATE_MASK  BIT(31)
0074 
0075 /* STM32_RTC_SR/_SCR bit fields */
0076 #define STM32_RTC_SR_ALRA       BIT(0)
0077 
0078 /* STM32_RTC_VERR bit fields */
0079 #define STM32_RTC_VERR_MINREV_SHIFT 0
0080 #define STM32_RTC_VERR_MINREV       GENMASK(3, 0)
0081 #define STM32_RTC_VERR_MAJREV_SHIFT 4
0082 #define STM32_RTC_VERR_MAJREV       GENMASK(7, 4)
0083 
0084 /* STM32_RTC_WPR key constants */
0085 #define RTC_WPR_1ST_KEY         0xCA
0086 #define RTC_WPR_2ND_KEY         0x53
0087 #define RTC_WPR_WRONG_KEY       0xFF
0088 
0089 /* Max STM32 RTC register offset is 0x3FC */
0090 #define UNDEF_REG           0xFFFF
0091 
0092 struct stm32_rtc;
0093 
0094 struct stm32_rtc_registers {
0095     u16 tr;
0096     u16 dr;
0097     u16 cr;
0098     u16 isr;
0099     u16 prer;
0100     u16 alrmar;
0101     u16 wpr;
0102     u16 sr;
0103     u16 scr;
0104     u16 verr;
0105 };
0106 
0107 struct stm32_rtc_events {
0108     u32 alra;
0109 };
0110 
0111 struct stm32_rtc_data {
0112     const struct stm32_rtc_registers regs;
0113     const struct stm32_rtc_events events;
0114     void (*clear_events)(struct stm32_rtc *rtc, unsigned int flags);
0115     bool has_pclk;
0116     bool need_dbp;
0117     bool has_wakeirq;
0118 };
0119 
0120 struct stm32_rtc {
0121     struct rtc_device *rtc_dev;
0122     void __iomem *base;
0123     struct regmap *dbp;
0124     unsigned int dbp_reg;
0125     unsigned int dbp_mask;
0126     struct clk *pclk;
0127     struct clk *rtc_ck;
0128     const struct stm32_rtc_data *data;
0129     int irq_alarm;
0130     int wakeirq_alarm;
0131 };
0132 
0133 static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc)
0134 {
0135     const struct stm32_rtc_registers *regs = &rtc->data->regs;
0136 
0137     writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + regs->wpr);
0138     writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + regs->wpr);
0139 }
0140 
0141 static void stm32_rtc_wpr_lock(struct stm32_rtc *rtc)
0142 {
0143     const struct stm32_rtc_registers *regs = &rtc->data->regs;
0144 
0145     writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + regs->wpr);
0146 }
0147 
0148 static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc)
0149 {
0150     const struct stm32_rtc_registers *regs = &rtc->data->regs;
0151     unsigned int isr = readl_relaxed(rtc->base + regs->isr);
0152 
0153     if (!(isr & STM32_RTC_ISR_INITF)) {
0154         isr |= STM32_RTC_ISR_INIT;
0155         writel_relaxed(isr, rtc->base + regs->isr);
0156 
0157         /*
0158          * It takes around 2 rtc_ck clock cycles to enter in
0159          * initialization phase mode (and have INITF flag set). As
0160          * slowest rtc_ck frequency may be 32kHz and highest should be
0161          * 1MHz, we poll every 10 us with a timeout of 100ms.
0162          */
0163         return readl_relaxed_poll_timeout_atomic(
0164                     rtc->base + regs->isr,
0165                     isr, (isr & STM32_RTC_ISR_INITF),
0166                     10, 100000);
0167     }
0168 
0169     return 0;
0170 }
0171 
0172 static void stm32_rtc_exit_init_mode(struct stm32_rtc *rtc)
0173 {
0174     const struct stm32_rtc_registers *regs = &rtc->data->regs;
0175     unsigned int isr = readl_relaxed(rtc->base + regs->isr);
0176 
0177     isr &= ~STM32_RTC_ISR_INIT;
0178     writel_relaxed(isr, rtc->base + regs->isr);
0179 }
0180 
0181 static int stm32_rtc_wait_sync(struct stm32_rtc *rtc)
0182 {
0183     const struct stm32_rtc_registers *regs = &rtc->data->regs;
0184     unsigned int isr = readl_relaxed(rtc->base + regs->isr);
0185 
0186     isr &= ~STM32_RTC_ISR_RSF;
0187     writel_relaxed(isr, rtc->base + regs->isr);
0188 
0189     /*
0190      * Wait for RSF to be set to ensure the calendar registers are
0191      * synchronised, it takes around 2 rtc_ck clock cycles
0192      */
0193     return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr,
0194                          isr,
0195                          (isr & STM32_RTC_ISR_RSF),
0196                          10, 100000);
0197 }
0198 
0199 static void stm32_rtc_clear_event_flags(struct stm32_rtc *rtc,
0200                     unsigned int flags)
0201 {
0202     rtc->data->clear_events(rtc, flags);
0203 }
0204 
0205 static irqreturn_t stm32_rtc_alarm_irq(int irq, void *dev_id)
0206 {
0207     struct stm32_rtc *rtc = (struct stm32_rtc *)dev_id;
0208     const struct stm32_rtc_registers *regs = &rtc->data->regs;
0209     const struct stm32_rtc_events *evts = &rtc->data->events;
0210     unsigned int status, cr;
0211 
0212     rtc_lock(rtc->rtc_dev);
0213 
0214     status = readl_relaxed(rtc->base + regs->sr);
0215     cr = readl_relaxed(rtc->base + regs->cr);
0216 
0217     if ((status & evts->alra) &&
0218         (cr & STM32_RTC_CR_ALRAIE)) {
0219         /* Alarm A flag - Alarm interrupt */
0220         dev_dbg(&rtc->rtc_dev->dev, "Alarm occurred\n");
0221 
0222         /* Pass event to the kernel */
0223         rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
0224 
0225         /* Clear event flags, otherwise new events won't be received */
0226         stm32_rtc_clear_event_flags(rtc, evts->alra);
0227     }
0228 
0229     rtc_unlock(rtc->rtc_dev);
0230 
0231     return IRQ_HANDLED;
0232 }
0233 
0234 /* Convert rtc_time structure from bin to bcd format */
0235 static void tm2bcd(struct rtc_time *tm)
0236 {
0237     tm->tm_sec = bin2bcd(tm->tm_sec);
0238     tm->tm_min = bin2bcd(tm->tm_min);
0239     tm->tm_hour = bin2bcd(tm->tm_hour);
0240 
0241     tm->tm_mday = bin2bcd(tm->tm_mday);
0242     tm->tm_mon = bin2bcd(tm->tm_mon + 1);
0243     tm->tm_year = bin2bcd(tm->tm_year - 100);
0244     /*
0245      * Number of days since Sunday
0246      * - on kernel side, 0=Sunday...6=Saturday
0247      * - on rtc side, 0=invalid,1=Monday...7=Sunday
0248      */
0249     tm->tm_wday = (!tm->tm_wday) ? 7 : tm->tm_wday;
0250 }
0251 
0252 /* Convert rtc_time structure from bcd to bin format */
0253 static void bcd2tm(struct rtc_time *tm)
0254 {
0255     tm->tm_sec = bcd2bin(tm->tm_sec);
0256     tm->tm_min = bcd2bin(tm->tm_min);
0257     tm->tm_hour = bcd2bin(tm->tm_hour);
0258 
0259     tm->tm_mday = bcd2bin(tm->tm_mday);
0260     tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
0261     tm->tm_year = bcd2bin(tm->tm_year) + 100;
0262     /*
0263      * Number of days since Sunday
0264      * - on kernel side, 0=Sunday...6=Saturday
0265      * - on rtc side, 0=invalid,1=Monday...7=Sunday
0266      */
0267     tm->tm_wday %= 7;
0268 }
0269 
0270 static int stm32_rtc_read_time(struct device *dev, struct rtc_time *tm)
0271 {
0272     struct stm32_rtc *rtc = dev_get_drvdata(dev);
0273     const struct stm32_rtc_registers *regs = &rtc->data->regs;
0274     unsigned int tr, dr;
0275 
0276     /* Time and Date in BCD format */
0277     tr = readl_relaxed(rtc->base + regs->tr);
0278     dr = readl_relaxed(rtc->base + regs->dr);
0279 
0280     tm->tm_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT;
0281     tm->tm_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT;
0282     tm->tm_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT;
0283 
0284     tm->tm_mday = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT;
0285     tm->tm_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT;
0286     tm->tm_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT;
0287     tm->tm_wday = (dr & STM32_RTC_DR_WDAY) >> STM32_RTC_DR_WDAY_SHIFT;
0288 
0289     /* We don't report tm_yday and tm_isdst */
0290 
0291     bcd2tm(tm);
0292 
0293     return 0;
0294 }
0295 
0296 static int stm32_rtc_set_time(struct device *dev, struct rtc_time *tm)
0297 {
0298     struct stm32_rtc *rtc = dev_get_drvdata(dev);
0299     const struct stm32_rtc_registers *regs = &rtc->data->regs;
0300     unsigned int tr, dr;
0301     int ret = 0;
0302 
0303     tm2bcd(tm);
0304 
0305     /* Time in BCD format */
0306     tr = ((tm->tm_sec << STM32_RTC_TR_SEC_SHIFT) & STM32_RTC_TR_SEC) |
0307          ((tm->tm_min << STM32_RTC_TR_MIN_SHIFT) & STM32_RTC_TR_MIN) |
0308          ((tm->tm_hour << STM32_RTC_TR_HOUR_SHIFT) & STM32_RTC_TR_HOUR);
0309 
0310     /* Date in BCD format */
0311     dr = ((tm->tm_mday << STM32_RTC_DR_DATE_SHIFT) & STM32_RTC_DR_DATE) |
0312          ((tm->tm_mon << STM32_RTC_DR_MONTH_SHIFT) & STM32_RTC_DR_MONTH) |
0313          ((tm->tm_year << STM32_RTC_DR_YEAR_SHIFT) & STM32_RTC_DR_YEAR) |
0314          ((tm->tm_wday << STM32_RTC_DR_WDAY_SHIFT) & STM32_RTC_DR_WDAY);
0315 
0316     stm32_rtc_wpr_unlock(rtc);
0317 
0318     ret = stm32_rtc_enter_init_mode(rtc);
0319     if (ret) {
0320         dev_err(dev, "Can't enter in init mode. Set time aborted.\n");
0321         goto end;
0322     }
0323 
0324     writel_relaxed(tr, rtc->base + regs->tr);
0325     writel_relaxed(dr, rtc->base + regs->dr);
0326 
0327     stm32_rtc_exit_init_mode(rtc);
0328 
0329     ret = stm32_rtc_wait_sync(rtc);
0330 end:
0331     stm32_rtc_wpr_lock(rtc);
0332 
0333     return ret;
0334 }
0335 
0336 static int stm32_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0337 {
0338     struct stm32_rtc *rtc = dev_get_drvdata(dev);
0339     const struct stm32_rtc_registers *regs = &rtc->data->regs;
0340     const struct stm32_rtc_events *evts = &rtc->data->events;
0341     struct rtc_time *tm = &alrm->time;
0342     unsigned int alrmar, cr, status;
0343 
0344     alrmar = readl_relaxed(rtc->base + regs->alrmar);
0345     cr = readl_relaxed(rtc->base + regs->cr);
0346     status = readl_relaxed(rtc->base + regs->sr);
0347 
0348     if (alrmar & STM32_RTC_ALRMXR_DATE_MASK) {
0349         /*
0350          * Date/day doesn't matter in Alarm comparison so alarm
0351          * triggers every day
0352          */
0353         tm->tm_mday = -1;
0354         tm->tm_wday = -1;
0355     } else {
0356         if (alrmar & STM32_RTC_ALRMXR_WDSEL) {
0357             /* Alarm is set to a day of week */
0358             tm->tm_mday = -1;
0359             tm->tm_wday = (alrmar & STM32_RTC_ALRMXR_WDAY) >>
0360                       STM32_RTC_ALRMXR_WDAY_SHIFT;
0361             tm->tm_wday %= 7;
0362         } else {
0363             /* Alarm is set to a day of month */
0364             tm->tm_wday = -1;
0365             tm->tm_mday = (alrmar & STM32_RTC_ALRMXR_DATE) >>
0366                        STM32_RTC_ALRMXR_DATE_SHIFT;
0367         }
0368     }
0369 
0370     if (alrmar & STM32_RTC_ALRMXR_HOUR_MASK) {
0371         /* Hours don't matter in Alarm comparison */
0372         tm->tm_hour = -1;
0373     } else {
0374         tm->tm_hour = (alrmar & STM32_RTC_ALRMXR_HOUR) >>
0375                    STM32_RTC_ALRMXR_HOUR_SHIFT;
0376         if (alrmar & STM32_RTC_ALRMXR_PM)
0377             tm->tm_hour += 12;
0378     }
0379 
0380     if (alrmar & STM32_RTC_ALRMXR_MIN_MASK) {
0381         /* Minutes don't matter in Alarm comparison */
0382         tm->tm_min = -1;
0383     } else {
0384         tm->tm_min = (alrmar & STM32_RTC_ALRMXR_MIN) >>
0385                   STM32_RTC_ALRMXR_MIN_SHIFT;
0386     }
0387 
0388     if (alrmar & STM32_RTC_ALRMXR_SEC_MASK) {
0389         /* Seconds don't matter in Alarm comparison */
0390         tm->tm_sec = -1;
0391     } else {
0392         tm->tm_sec = (alrmar & STM32_RTC_ALRMXR_SEC) >>
0393                   STM32_RTC_ALRMXR_SEC_SHIFT;
0394     }
0395 
0396     bcd2tm(tm);
0397 
0398     alrm->enabled = (cr & STM32_RTC_CR_ALRAE) ? 1 : 0;
0399     alrm->pending = (status & evts->alra) ? 1 : 0;
0400 
0401     return 0;
0402 }
0403 
0404 static int stm32_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
0405 {
0406     struct stm32_rtc *rtc = dev_get_drvdata(dev);
0407     const struct stm32_rtc_registers *regs = &rtc->data->regs;
0408     const struct stm32_rtc_events *evts = &rtc->data->events;
0409     unsigned int cr;
0410 
0411     cr = readl_relaxed(rtc->base + regs->cr);
0412 
0413     stm32_rtc_wpr_unlock(rtc);
0414 
0415     /* We expose Alarm A to the kernel */
0416     if (enabled)
0417         cr |= (STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
0418     else
0419         cr &= ~(STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
0420     writel_relaxed(cr, rtc->base + regs->cr);
0421 
0422     /* Clear event flags, otherwise new events won't be received */
0423     stm32_rtc_clear_event_flags(rtc, evts->alra);
0424 
0425     stm32_rtc_wpr_lock(rtc);
0426 
0427     return 0;
0428 }
0429 
0430 static int stm32_rtc_valid_alrm(struct stm32_rtc *rtc, struct rtc_time *tm)
0431 {
0432     const struct stm32_rtc_registers *regs = &rtc->data->regs;
0433     int cur_day, cur_mon, cur_year, cur_hour, cur_min, cur_sec;
0434     unsigned int dr = readl_relaxed(rtc->base + regs->dr);
0435     unsigned int tr = readl_relaxed(rtc->base + regs->tr);
0436 
0437     cur_day = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT;
0438     cur_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT;
0439     cur_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT;
0440     cur_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT;
0441     cur_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT;
0442     cur_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT;
0443 
0444     /*
0445      * Assuming current date is M-D-Y H:M:S.
0446      * RTC alarm can't be set on a specific month and year.
0447      * So the valid alarm range is:
0448      *  M-D-Y H:M:S < alarm <= (M+1)-D-Y H:M:S
0449      * with a specific case for December...
0450      */
0451     if ((((tm->tm_year > cur_year) &&
0452           (tm->tm_mon == 0x1) && (cur_mon == 0x12)) ||
0453          ((tm->tm_year == cur_year) &&
0454           (tm->tm_mon <= cur_mon + 1))) &&
0455         ((tm->tm_mday > cur_day) ||
0456          ((tm->tm_mday == cur_day) &&
0457          ((tm->tm_hour > cur_hour) ||
0458           ((tm->tm_hour == cur_hour) && (tm->tm_min > cur_min)) ||
0459           ((tm->tm_hour == cur_hour) && (tm->tm_min == cur_min) &&
0460            (tm->tm_sec >= cur_sec))))))
0461         return 0;
0462 
0463     return -EINVAL;
0464 }
0465 
0466 static int stm32_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0467 {
0468     struct stm32_rtc *rtc = dev_get_drvdata(dev);
0469     const struct stm32_rtc_registers *regs = &rtc->data->regs;
0470     struct rtc_time *tm = &alrm->time;
0471     unsigned int cr, isr, alrmar;
0472     int ret = 0;
0473 
0474     tm2bcd(tm);
0475 
0476     /*
0477      * RTC alarm can't be set on a specific date, unless this date is
0478      * up to the same day of month next month.
0479      */
0480     if (stm32_rtc_valid_alrm(rtc, tm) < 0) {
0481         dev_err(dev, "Alarm can be set only on upcoming month.\n");
0482         return -EINVAL;
0483     }
0484 
0485     alrmar = 0;
0486     /* tm_year and tm_mon are not used because not supported by RTC */
0487     alrmar |= (tm->tm_mday << STM32_RTC_ALRMXR_DATE_SHIFT) &
0488           STM32_RTC_ALRMXR_DATE;
0489     /* 24-hour format */
0490     alrmar &= ~STM32_RTC_ALRMXR_PM;
0491     alrmar |= (tm->tm_hour << STM32_RTC_ALRMXR_HOUR_SHIFT) &
0492           STM32_RTC_ALRMXR_HOUR;
0493     alrmar |= (tm->tm_min << STM32_RTC_ALRMXR_MIN_SHIFT) &
0494           STM32_RTC_ALRMXR_MIN;
0495     alrmar |= (tm->tm_sec << STM32_RTC_ALRMXR_SEC_SHIFT) &
0496           STM32_RTC_ALRMXR_SEC;
0497 
0498     stm32_rtc_wpr_unlock(rtc);
0499 
0500     /* Disable Alarm */
0501     cr = readl_relaxed(rtc->base + regs->cr);
0502     cr &= ~STM32_RTC_CR_ALRAE;
0503     writel_relaxed(cr, rtc->base + regs->cr);
0504 
0505     /*
0506      * Poll Alarm write flag to be sure that Alarm update is allowed: it
0507      * takes around 2 rtc_ck clock cycles
0508      */
0509     ret = readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr,
0510                         isr,
0511                         (isr & STM32_RTC_ISR_ALRAWF),
0512                         10, 100000);
0513 
0514     if (ret) {
0515         dev_err(dev, "Alarm update not allowed\n");
0516         goto end;
0517     }
0518 
0519     /* Write to Alarm register */
0520     writel_relaxed(alrmar, rtc->base + regs->alrmar);
0521 
0522     stm32_rtc_alarm_irq_enable(dev, alrm->enabled);
0523 end:
0524     stm32_rtc_wpr_lock(rtc);
0525 
0526     return ret;
0527 }
0528 
0529 static const struct rtc_class_ops stm32_rtc_ops = {
0530     .read_time  = stm32_rtc_read_time,
0531     .set_time   = stm32_rtc_set_time,
0532     .read_alarm = stm32_rtc_read_alarm,
0533     .set_alarm  = stm32_rtc_set_alarm,
0534     .alarm_irq_enable = stm32_rtc_alarm_irq_enable,
0535 };
0536 
0537 static void stm32_rtc_clear_events(struct stm32_rtc *rtc,
0538                    unsigned int flags)
0539 {
0540     const struct stm32_rtc_registers *regs = &rtc->data->regs;
0541 
0542     /* Flags are cleared by writing 0 in RTC_ISR */
0543     writel_relaxed(readl_relaxed(rtc->base + regs->isr) & ~flags,
0544                rtc->base + regs->isr);
0545 }
0546 
0547 static const struct stm32_rtc_data stm32_rtc_data = {
0548     .has_pclk = false,
0549     .need_dbp = true,
0550     .has_wakeirq = false,
0551     .regs = {
0552         .tr = 0x00,
0553         .dr = 0x04,
0554         .cr = 0x08,
0555         .isr = 0x0C,
0556         .prer = 0x10,
0557         .alrmar = 0x1C,
0558         .wpr = 0x24,
0559         .sr = 0x0C, /* set to ISR offset to ease alarm management */
0560         .scr = UNDEF_REG,
0561         .verr = UNDEF_REG,
0562     },
0563     .events = {
0564         .alra = STM32_RTC_ISR_ALRAF,
0565     },
0566     .clear_events = stm32_rtc_clear_events,
0567 };
0568 
0569 static const struct stm32_rtc_data stm32h7_rtc_data = {
0570     .has_pclk = true,
0571     .need_dbp = true,
0572     .has_wakeirq = false,
0573     .regs = {
0574         .tr = 0x00,
0575         .dr = 0x04,
0576         .cr = 0x08,
0577         .isr = 0x0C,
0578         .prer = 0x10,
0579         .alrmar = 0x1C,
0580         .wpr = 0x24,
0581         .sr = 0x0C, /* set to ISR offset to ease alarm management */
0582         .scr = UNDEF_REG,
0583         .verr = UNDEF_REG,
0584     },
0585     .events = {
0586         .alra = STM32_RTC_ISR_ALRAF,
0587     },
0588     .clear_events = stm32_rtc_clear_events,
0589 };
0590 
0591 static void stm32mp1_rtc_clear_events(struct stm32_rtc *rtc,
0592                       unsigned int flags)
0593 {
0594     struct stm32_rtc_registers regs = rtc->data->regs;
0595 
0596     /* Flags are cleared by writing 1 in RTC_SCR */
0597     writel_relaxed(flags, rtc->base + regs.scr);
0598 }
0599 
0600 static const struct stm32_rtc_data stm32mp1_data = {
0601     .has_pclk = true,
0602     .need_dbp = false,
0603     .has_wakeirq = true,
0604     .regs = {
0605         .tr = 0x00,
0606         .dr = 0x04,
0607         .cr = 0x18,
0608         .isr = 0x0C, /* named RTC_ICSR on stm32mp1 */
0609         .prer = 0x10,
0610         .alrmar = 0x40,
0611         .wpr = 0x24,
0612         .sr = 0x50,
0613         .scr = 0x5C,
0614         .verr = 0x3F4,
0615     },
0616     .events = {
0617         .alra = STM32_RTC_SR_ALRA,
0618     },
0619     .clear_events = stm32mp1_rtc_clear_events,
0620 };
0621 
0622 static const struct of_device_id stm32_rtc_of_match[] = {
0623     { .compatible = "st,stm32-rtc", .data = &stm32_rtc_data },
0624     { .compatible = "st,stm32h7-rtc", .data = &stm32h7_rtc_data },
0625     { .compatible = "st,stm32mp1-rtc", .data = &stm32mp1_data },
0626     {}
0627 };
0628 MODULE_DEVICE_TABLE(of, stm32_rtc_of_match);
0629 
0630 static int stm32_rtc_init(struct platform_device *pdev,
0631               struct stm32_rtc *rtc)
0632 {
0633     const struct stm32_rtc_registers *regs = &rtc->data->regs;
0634     unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr;
0635     unsigned int rate;
0636     int ret = 0;
0637 
0638     rate = clk_get_rate(rtc->rtc_ck);
0639 
0640     /* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */
0641     pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT;
0642     pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT;
0643 
0644     for (pred_a = pred_a_max; pred_a + 1 > 0; pred_a--) {
0645         pred_s = (rate / (pred_a + 1)) - 1;
0646 
0647         if (((pred_s + 1) * (pred_a + 1)) == rate)
0648             break;
0649     }
0650 
0651     /*
0652      * Can't find a 1Hz, so give priority to RTC power consumption
0653      * by choosing the higher possible value for prediv_a
0654      */
0655     if ((pred_s > pred_s_max) || (pred_a > pred_a_max)) {
0656         pred_a = pred_a_max;
0657         pred_s = (rate / (pred_a + 1)) - 1;
0658 
0659         dev_warn(&pdev->dev, "rtc_ck is %s\n",
0660              (rate < ((pred_a + 1) * (pred_s + 1))) ?
0661              "fast" : "slow");
0662     }
0663 
0664     stm32_rtc_wpr_unlock(rtc);
0665 
0666     ret = stm32_rtc_enter_init_mode(rtc);
0667     if (ret) {
0668         dev_err(&pdev->dev,
0669             "Can't enter in init mode. Prescaler config failed.\n");
0670         goto end;
0671     }
0672 
0673     prer = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) & STM32_RTC_PRER_PRED_S;
0674     writel_relaxed(prer, rtc->base + regs->prer);
0675     prer |= (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) & STM32_RTC_PRER_PRED_A;
0676     writel_relaxed(prer, rtc->base + regs->prer);
0677 
0678     /* Force 24h time format */
0679     cr = readl_relaxed(rtc->base + regs->cr);
0680     cr &= ~STM32_RTC_CR_FMT;
0681     writel_relaxed(cr, rtc->base + regs->cr);
0682 
0683     stm32_rtc_exit_init_mode(rtc);
0684 
0685     ret = stm32_rtc_wait_sync(rtc);
0686 end:
0687     stm32_rtc_wpr_lock(rtc);
0688 
0689     return ret;
0690 }
0691 
0692 static int stm32_rtc_probe(struct platform_device *pdev)
0693 {
0694     struct stm32_rtc *rtc;
0695     const struct stm32_rtc_registers *regs;
0696     int ret;
0697 
0698     rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
0699     if (!rtc)
0700         return -ENOMEM;
0701 
0702     rtc->base = devm_platform_ioremap_resource(pdev, 0);
0703     if (IS_ERR(rtc->base))
0704         return PTR_ERR(rtc->base);
0705 
0706     rtc->data = (struct stm32_rtc_data *)
0707             of_device_get_match_data(&pdev->dev);
0708     regs = &rtc->data->regs;
0709 
0710     if (rtc->data->need_dbp) {
0711         rtc->dbp = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
0712                                "st,syscfg");
0713         if (IS_ERR(rtc->dbp)) {
0714             dev_err(&pdev->dev, "no st,syscfg\n");
0715             return PTR_ERR(rtc->dbp);
0716         }
0717 
0718         ret = of_property_read_u32_index(pdev->dev.of_node, "st,syscfg",
0719                          1, &rtc->dbp_reg);
0720         if (ret) {
0721             dev_err(&pdev->dev, "can't read DBP register offset\n");
0722             return ret;
0723         }
0724 
0725         ret = of_property_read_u32_index(pdev->dev.of_node, "st,syscfg",
0726                          2, &rtc->dbp_mask);
0727         if (ret) {
0728             dev_err(&pdev->dev, "can't read DBP register mask\n");
0729             return ret;
0730         }
0731     }
0732 
0733     if (!rtc->data->has_pclk) {
0734         rtc->pclk = NULL;
0735         rtc->rtc_ck = devm_clk_get(&pdev->dev, NULL);
0736     } else {
0737         rtc->pclk = devm_clk_get(&pdev->dev, "pclk");
0738         if (IS_ERR(rtc->pclk)) {
0739             dev_err(&pdev->dev, "no pclk clock");
0740             return PTR_ERR(rtc->pclk);
0741         }
0742         rtc->rtc_ck = devm_clk_get(&pdev->dev, "rtc_ck");
0743     }
0744     if (IS_ERR(rtc->rtc_ck)) {
0745         dev_err(&pdev->dev, "no rtc_ck clock");
0746         return PTR_ERR(rtc->rtc_ck);
0747     }
0748 
0749     if (rtc->data->has_pclk) {
0750         ret = clk_prepare_enable(rtc->pclk);
0751         if (ret)
0752             return ret;
0753     }
0754 
0755     ret = clk_prepare_enable(rtc->rtc_ck);
0756     if (ret)
0757         goto err_no_rtc_ck;
0758 
0759     if (rtc->data->need_dbp)
0760         regmap_update_bits(rtc->dbp, rtc->dbp_reg,
0761                    rtc->dbp_mask, rtc->dbp_mask);
0762 
0763     /*
0764      * After a system reset, RTC_ISR.INITS flag can be read to check if
0765      * the calendar has been initialized or not. INITS flag is reset by a
0766      * power-on reset (no vbat, no power-supply). It is not reset if
0767      * rtc_ck parent clock has changed (so RTC prescalers need to be
0768      * changed). That's why we cannot rely on this flag to know if RTC
0769      * init has to be done.
0770      */
0771     ret = stm32_rtc_init(pdev, rtc);
0772     if (ret)
0773         goto err;
0774 
0775     rtc->irq_alarm = platform_get_irq(pdev, 0);
0776     if (rtc->irq_alarm <= 0) {
0777         ret = rtc->irq_alarm;
0778         goto err;
0779     }
0780 
0781     ret = device_init_wakeup(&pdev->dev, true);
0782     if (rtc->data->has_wakeirq) {
0783         rtc->wakeirq_alarm = platform_get_irq(pdev, 1);
0784         if (rtc->wakeirq_alarm > 0) {
0785             ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
0786                                 rtc->wakeirq_alarm);
0787         } else {
0788             ret = rtc->wakeirq_alarm;
0789             if (rtc->wakeirq_alarm == -EPROBE_DEFER)
0790                 goto err;
0791         }
0792     }
0793     if (ret)
0794         dev_warn(&pdev->dev, "alarm can't wake up the system: %d", ret);
0795 
0796     platform_set_drvdata(pdev, rtc);
0797 
0798     rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name,
0799                         &stm32_rtc_ops, THIS_MODULE);
0800     if (IS_ERR(rtc->rtc_dev)) {
0801         ret = PTR_ERR(rtc->rtc_dev);
0802         dev_err(&pdev->dev, "rtc device registration failed, err=%d\n",
0803             ret);
0804         goto err;
0805     }
0806 
0807     /* Handle RTC alarm interrupts */
0808     ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_alarm, NULL,
0809                     stm32_rtc_alarm_irq, IRQF_ONESHOT,
0810                     pdev->name, rtc);
0811     if (ret) {
0812         dev_err(&pdev->dev, "IRQ%d (alarm interrupt) already claimed\n",
0813             rtc->irq_alarm);
0814         goto err;
0815     }
0816 
0817     /*
0818      * If INITS flag is reset (calendar year field set to 0x00), calendar
0819      * must be initialized
0820      */
0821     if (!(readl_relaxed(rtc->base + regs->isr) & STM32_RTC_ISR_INITS))
0822         dev_warn(&pdev->dev, "Date/Time must be initialized\n");
0823 
0824     if (regs->verr != UNDEF_REG) {
0825         u32 ver = readl_relaxed(rtc->base + regs->verr);
0826 
0827         dev_info(&pdev->dev, "registered rev:%d.%d\n",
0828              (ver >> STM32_RTC_VERR_MAJREV_SHIFT) & 0xF,
0829              (ver >> STM32_RTC_VERR_MINREV_SHIFT) & 0xF);
0830     }
0831 
0832     return 0;
0833 
0834 err:
0835     clk_disable_unprepare(rtc->rtc_ck);
0836 err_no_rtc_ck:
0837     if (rtc->data->has_pclk)
0838         clk_disable_unprepare(rtc->pclk);
0839 
0840     if (rtc->data->need_dbp)
0841         regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0);
0842 
0843     dev_pm_clear_wake_irq(&pdev->dev);
0844     device_init_wakeup(&pdev->dev, false);
0845 
0846     return ret;
0847 }
0848 
0849 static int stm32_rtc_remove(struct platform_device *pdev)
0850 {
0851     struct stm32_rtc *rtc = platform_get_drvdata(pdev);
0852     const struct stm32_rtc_registers *regs = &rtc->data->regs;
0853     unsigned int cr;
0854 
0855     /* Disable interrupts */
0856     stm32_rtc_wpr_unlock(rtc);
0857     cr = readl_relaxed(rtc->base + regs->cr);
0858     cr &= ~STM32_RTC_CR_ALRAIE;
0859     writel_relaxed(cr, rtc->base + regs->cr);
0860     stm32_rtc_wpr_lock(rtc);
0861 
0862     clk_disable_unprepare(rtc->rtc_ck);
0863     if (rtc->data->has_pclk)
0864         clk_disable_unprepare(rtc->pclk);
0865 
0866     /* Enable backup domain write protection if needed */
0867     if (rtc->data->need_dbp)
0868         regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0);
0869 
0870     dev_pm_clear_wake_irq(&pdev->dev);
0871     device_init_wakeup(&pdev->dev, false);
0872 
0873     return 0;
0874 }
0875 
0876 #ifdef CONFIG_PM_SLEEP
0877 static int stm32_rtc_suspend(struct device *dev)
0878 {
0879     struct stm32_rtc *rtc = dev_get_drvdata(dev);
0880 
0881     if (rtc->data->has_pclk)
0882         clk_disable_unprepare(rtc->pclk);
0883 
0884     if (device_may_wakeup(dev))
0885         return enable_irq_wake(rtc->irq_alarm);
0886 
0887     return 0;
0888 }
0889 
0890 static int stm32_rtc_resume(struct device *dev)
0891 {
0892     struct stm32_rtc *rtc = dev_get_drvdata(dev);
0893     int ret = 0;
0894 
0895     if (rtc->data->has_pclk) {
0896         ret = clk_prepare_enable(rtc->pclk);
0897         if (ret)
0898             return ret;
0899     }
0900 
0901     ret = stm32_rtc_wait_sync(rtc);
0902     if (ret < 0) {
0903         if (rtc->data->has_pclk)
0904             clk_disable_unprepare(rtc->pclk);
0905         return ret;
0906     }
0907 
0908     if (device_may_wakeup(dev))
0909         return disable_irq_wake(rtc->irq_alarm);
0910 
0911     return ret;
0912 }
0913 #endif
0914 
0915 static SIMPLE_DEV_PM_OPS(stm32_rtc_pm_ops,
0916              stm32_rtc_suspend, stm32_rtc_resume);
0917 
0918 static struct platform_driver stm32_rtc_driver = {
0919     .probe      = stm32_rtc_probe,
0920     .remove     = stm32_rtc_remove,
0921     .driver     = {
0922         .name   = DRIVER_NAME,
0923         .pm = &stm32_rtc_pm_ops,
0924         .of_match_table = stm32_rtc_of_match,
0925     },
0926 };
0927 
0928 module_platform_driver(stm32_rtc_driver);
0929 
0930 MODULE_ALIAS("platform:" DRIVER_NAME);
0931 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
0932 MODULE_DESCRIPTION("STMicroelectronics STM32 Real Time Clock driver");
0933 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!