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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * SuperH On-Chip RTC Support
0004  *
0005  * Copyright (C) 2006 - 2009  Paul Mundt
0006  * Copyright (C) 2006  Jamie Lenehan
0007  * Copyright (C) 2008  Angelo Castello
0008  *
0009  * Based on the old arch/sh/kernel/cpu/rtc.c by:
0010  *
0011  *  Copyright (C) 2000  Philipp Rumpf <prumpf@tux.org>
0012  *  Copyright (C) 1999  Tetsuya Okada & Niibe Yutaka
0013  */
0014 #include <linux/module.h>
0015 #include <linux/mod_devicetable.h>
0016 #include <linux/kernel.h>
0017 #include <linux/bcd.h>
0018 #include <linux/rtc.h>
0019 #include <linux/init.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/seq_file.h>
0022 #include <linux/interrupt.h>
0023 #include <linux/spinlock.h>
0024 #include <linux/io.h>
0025 #include <linux/log2.h>
0026 #include <linux/clk.h>
0027 #include <linux/slab.h>
0028 #ifdef CONFIG_SUPERH
0029 #include <asm/rtc.h>
0030 #else
0031 /* Default values for RZ/A RTC */
0032 #define rtc_reg_size        sizeof(u16)
0033 #define RTC_BIT_INVERTED        0   /* no chip bugs */
0034 #define RTC_CAP_4_DIGIT_YEAR    (1 << 0)
0035 #define RTC_DEF_CAPABILITIES    RTC_CAP_4_DIGIT_YEAR
0036 #endif
0037 
0038 #define DRV_NAME    "sh-rtc"
0039 
0040 #define RTC_REG(r)  ((r) * rtc_reg_size)
0041 
0042 #define R64CNT      RTC_REG(0)
0043 
0044 #define RSECCNT     RTC_REG(1)  /* RTC sec */
0045 #define RMINCNT     RTC_REG(2)  /* RTC min */
0046 #define RHRCNT      RTC_REG(3)  /* RTC hour */
0047 #define RWKCNT      RTC_REG(4)  /* RTC week */
0048 #define RDAYCNT     RTC_REG(5)  /* RTC day */
0049 #define RMONCNT     RTC_REG(6)  /* RTC month */
0050 #define RYRCNT      RTC_REG(7)  /* RTC year */
0051 #define RSECAR      RTC_REG(8)  /* ALARM sec */
0052 #define RMINAR      RTC_REG(9)  /* ALARM min */
0053 #define RHRAR       RTC_REG(10) /* ALARM hour */
0054 #define RWKAR       RTC_REG(11) /* ALARM week */
0055 #define RDAYAR      RTC_REG(12) /* ALARM day */
0056 #define RMONAR      RTC_REG(13) /* ALARM month */
0057 #define RCR1        RTC_REG(14) /* Control */
0058 #define RCR2        RTC_REG(15) /* Control */
0059 
0060 /*
0061  * Note on RYRAR and RCR3: Up until this point most of the register
0062  * definitions are consistent across all of the available parts. However,
0063  * the placement of the optional RYRAR and RCR3 (the RYRAR control
0064  * register used to control RYRCNT/RYRAR compare) varies considerably
0065  * across various parts, occasionally being mapped in to a completely
0066  * unrelated address space. For proper RYRAR support a separate resource
0067  * would have to be handed off, but as this is purely optional in
0068  * practice, we simply opt not to support it, thereby keeping the code
0069  * quite a bit more simplified.
0070  */
0071 
0072 /* ALARM Bits - or with BCD encoded value */
0073 #define AR_ENB      0x80    /* Enable for alarm cmp   */
0074 
0075 /* Period Bits */
0076 #define PF_HP       0x100   /* Enable Half Period to support 8,32,128Hz */
0077 #define PF_COUNT    0x200   /* Half periodic counter */
0078 #define PF_OXS      0x400   /* Periodic One x Second */
0079 #define PF_KOU      0x800   /* Kernel or User periodic request 1=kernel */
0080 #define PF_MASK     0xf00
0081 
0082 /* RCR1 Bits */
0083 #define RCR1_CF     0x80    /* Carry Flag             */
0084 #define RCR1_CIE    0x10    /* Carry Interrupt Enable */
0085 #define RCR1_AIE    0x08    /* Alarm Interrupt Enable */
0086 #define RCR1_AF     0x01    /* Alarm Flag             */
0087 
0088 /* RCR2 Bits */
0089 #define RCR2_PEF    0x80    /* PEriodic interrupt Flag */
0090 #define RCR2_PESMASK    0x70    /* Periodic interrupt Set  */
0091 #define RCR2_RTCEN  0x08    /* ENable RTC              */
0092 #define RCR2_ADJ    0x04    /* ADJustment (30-second)  */
0093 #define RCR2_RESET  0x02    /* Reset bit               */
0094 #define RCR2_START  0x01    /* Start bit               */
0095 
0096 struct sh_rtc {
0097     void __iomem        *regbase;
0098     unsigned long       regsize;
0099     struct resource     *res;
0100     int         alarm_irq;
0101     int         periodic_irq;
0102     int         carry_irq;
0103     struct clk      *clk;
0104     struct rtc_device   *rtc_dev;
0105     spinlock_t      lock;
0106     unsigned long       capabilities;   /* See asm/rtc.h for cap bits */
0107     unsigned short      periodic_freq;
0108 };
0109 
0110 static int __sh_rtc_interrupt(struct sh_rtc *rtc)
0111 {
0112     unsigned int tmp, pending;
0113 
0114     tmp = readb(rtc->regbase + RCR1);
0115     pending = tmp & RCR1_CF;
0116     tmp &= ~RCR1_CF;
0117     writeb(tmp, rtc->regbase + RCR1);
0118 
0119     /* Users have requested One x Second IRQ */
0120     if (pending && rtc->periodic_freq & PF_OXS)
0121         rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF);
0122 
0123     return pending;
0124 }
0125 
0126 static int __sh_rtc_alarm(struct sh_rtc *rtc)
0127 {
0128     unsigned int tmp, pending;
0129 
0130     tmp = readb(rtc->regbase + RCR1);
0131     pending = tmp & RCR1_AF;
0132     tmp &= ~(RCR1_AF | RCR1_AIE);
0133     writeb(tmp, rtc->regbase + RCR1);
0134 
0135     if (pending)
0136         rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF);
0137 
0138     return pending;
0139 }
0140 
0141 static int __sh_rtc_periodic(struct sh_rtc *rtc)
0142 {
0143     unsigned int tmp, pending;
0144 
0145     tmp = readb(rtc->regbase + RCR2);
0146     pending = tmp & RCR2_PEF;
0147     tmp &= ~RCR2_PEF;
0148     writeb(tmp, rtc->regbase + RCR2);
0149 
0150     if (!pending)
0151         return 0;
0152 
0153     /* Half period enabled than one skipped and the next notified */
0154     if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT))
0155         rtc->periodic_freq &= ~PF_COUNT;
0156     else {
0157         if (rtc->periodic_freq & PF_HP)
0158             rtc->periodic_freq |= PF_COUNT;
0159         rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF);
0160     }
0161 
0162     return pending;
0163 }
0164 
0165 static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id)
0166 {
0167     struct sh_rtc *rtc = dev_id;
0168     int ret;
0169 
0170     spin_lock(&rtc->lock);
0171     ret = __sh_rtc_interrupt(rtc);
0172     spin_unlock(&rtc->lock);
0173 
0174     return IRQ_RETVAL(ret);
0175 }
0176 
0177 static irqreturn_t sh_rtc_alarm(int irq, void *dev_id)
0178 {
0179     struct sh_rtc *rtc = dev_id;
0180     int ret;
0181 
0182     spin_lock(&rtc->lock);
0183     ret = __sh_rtc_alarm(rtc);
0184     spin_unlock(&rtc->lock);
0185 
0186     return IRQ_RETVAL(ret);
0187 }
0188 
0189 static irqreturn_t sh_rtc_periodic(int irq, void *dev_id)
0190 {
0191     struct sh_rtc *rtc = dev_id;
0192     int ret;
0193 
0194     spin_lock(&rtc->lock);
0195     ret = __sh_rtc_periodic(rtc);
0196     spin_unlock(&rtc->lock);
0197 
0198     return IRQ_RETVAL(ret);
0199 }
0200 
0201 static irqreturn_t sh_rtc_shared(int irq, void *dev_id)
0202 {
0203     struct sh_rtc *rtc = dev_id;
0204     int ret;
0205 
0206     spin_lock(&rtc->lock);
0207     ret = __sh_rtc_interrupt(rtc);
0208     ret |= __sh_rtc_alarm(rtc);
0209     ret |= __sh_rtc_periodic(rtc);
0210     spin_unlock(&rtc->lock);
0211 
0212     return IRQ_RETVAL(ret);
0213 }
0214 
0215 static inline void sh_rtc_setaie(struct device *dev, unsigned int enable)
0216 {
0217     struct sh_rtc *rtc = dev_get_drvdata(dev);
0218     unsigned int tmp;
0219 
0220     spin_lock_irq(&rtc->lock);
0221 
0222     tmp = readb(rtc->regbase + RCR1);
0223 
0224     if (enable)
0225         tmp |= RCR1_AIE;
0226     else
0227         tmp &= ~RCR1_AIE;
0228 
0229     writeb(tmp, rtc->regbase + RCR1);
0230 
0231     spin_unlock_irq(&rtc->lock);
0232 }
0233 
0234 static int sh_rtc_proc(struct device *dev, struct seq_file *seq)
0235 {
0236     struct sh_rtc *rtc = dev_get_drvdata(dev);
0237     unsigned int tmp;
0238 
0239     tmp = readb(rtc->regbase + RCR1);
0240     seq_printf(seq, "carry_IRQ\t: %s\n", (tmp & RCR1_CIE) ? "yes" : "no");
0241 
0242     tmp = readb(rtc->regbase + RCR2);
0243     seq_printf(seq, "periodic_IRQ\t: %s\n",
0244            (tmp & RCR2_PESMASK) ? "yes" : "no");
0245 
0246     return 0;
0247 }
0248 
0249 static inline void sh_rtc_setcie(struct device *dev, unsigned int enable)
0250 {
0251     struct sh_rtc *rtc = dev_get_drvdata(dev);
0252     unsigned int tmp;
0253 
0254     spin_lock_irq(&rtc->lock);
0255 
0256     tmp = readb(rtc->regbase + RCR1);
0257 
0258     if (!enable)
0259         tmp &= ~RCR1_CIE;
0260     else
0261         tmp |= RCR1_CIE;
0262 
0263     writeb(tmp, rtc->regbase + RCR1);
0264 
0265     spin_unlock_irq(&rtc->lock);
0266 }
0267 
0268 static int sh_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
0269 {
0270     sh_rtc_setaie(dev, enabled);
0271     return 0;
0272 }
0273 
0274 static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm)
0275 {
0276     struct sh_rtc *rtc = dev_get_drvdata(dev);
0277     unsigned int sec128, sec2, yr, yr100, cf_bit;
0278 
0279     if (!(readb(rtc->regbase + RCR2) & RCR2_RTCEN))
0280         return -EINVAL;
0281 
0282     do {
0283         unsigned int tmp;
0284 
0285         spin_lock_irq(&rtc->lock);
0286 
0287         tmp = readb(rtc->regbase + RCR1);
0288         tmp &= ~RCR1_CF; /* Clear CF-bit */
0289         tmp |= RCR1_CIE;
0290         writeb(tmp, rtc->regbase + RCR1);
0291 
0292         sec128 = readb(rtc->regbase + R64CNT);
0293 
0294         tm->tm_sec  = bcd2bin(readb(rtc->regbase + RSECCNT));
0295         tm->tm_min  = bcd2bin(readb(rtc->regbase + RMINCNT));
0296         tm->tm_hour = bcd2bin(readb(rtc->regbase + RHRCNT));
0297         tm->tm_wday = bcd2bin(readb(rtc->regbase + RWKCNT));
0298         tm->tm_mday = bcd2bin(readb(rtc->regbase + RDAYCNT));
0299         tm->tm_mon  = bcd2bin(readb(rtc->regbase + RMONCNT)) - 1;
0300 
0301         if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
0302             yr  = readw(rtc->regbase + RYRCNT);
0303             yr100 = bcd2bin(yr >> 8);
0304             yr &= 0xff;
0305         } else {
0306             yr  = readb(rtc->regbase + RYRCNT);
0307             yr100 = bcd2bin((yr == 0x99) ? 0x19 : 0x20);
0308         }
0309 
0310         tm->tm_year = (yr100 * 100 + bcd2bin(yr)) - 1900;
0311 
0312         sec2 = readb(rtc->regbase + R64CNT);
0313         cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF;
0314 
0315         spin_unlock_irq(&rtc->lock);
0316     } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0);
0317 
0318 #if RTC_BIT_INVERTED != 0
0319     if ((sec128 & RTC_BIT_INVERTED))
0320         tm->tm_sec--;
0321 #endif
0322 
0323     /* only keep the carry interrupt enabled if UIE is on */
0324     if (!(rtc->periodic_freq & PF_OXS))
0325         sh_rtc_setcie(dev, 0);
0326 
0327     dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
0328         "mday=%d, mon=%d, year=%d, wday=%d\n",
0329         __func__,
0330         tm->tm_sec, tm->tm_min, tm->tm_hour,
0331         tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday);
0332 
0333     return 0;
0334 }
0335 
0336 static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm)
0337 {
0338     struct sh_rtc *rtc = dev_get_drvdata(dev);
0339     unsigned int tmp;
0340     int year;
0341 
0342     spin_lock_irq(&rtc->lock);
0343 
0344     /* Reset pre-scaler & stop RTC */
0345     tmp = readb(rtc->regbase + RCR2);
0346     tmp |= RCR2_RESET;
0347     tmp &= ~RCR2_START;
0348     writeb(tmp, rtc->regbase + RCR2);
0349 
0350     writeb(bin2bcd(tm->tm_sec),  rtc->regbase + RSECCNT);
0351     writeb(bin2bcd(tm->tm_min),  rtc->regbase + RMINCNT);
0352     writeb(bin2bcd(tm->tm_hour), rtc->regbase + RHRCNT);
0353     writeb(bin2bcd(tm->tm_wday), rtc->regbase + RWKCNT);
0354     writeb(bin2bcd(tm->tm_mday), rtc->regbase + RDAYCNT);
0355     writeb(bin2bcd(tm->tm_mon + 1), rtc->regbase + RMONCNT);
0356 
0357     if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
0358         year = (bin2bcd((tm->tm_year + 1900) / 100) << 8) |
0359             bin2bcd(tm->tm_year % 100);
0360         writew(year, rtc->regbase + RYRCNT);
0361     } else {
0362         year = tm->tm_year % 100;
0363         writeb(bin2bcd(year), rtc->regbase + RYRCNT);
0364     }
0365 
0366     /* Start RTC */
0367     tmp = readb(rtc->regbase + RCR2);
0368     tmp &= ~RCR2_RESET;
0369     tmp |= RCR2_RTCEN | RCR2_START;
0370     writeb(tmp, rtc->regbase + RCR2);
0371 
0372     spin_unlock_irq(&rtc->lock);
0373 
0374     return 0;
0375 }
0376 
0377 static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off)
0378 {
0379     unsigned int byte;
0380     int value = -1;         /* return -1 for ignored values */
0381 
0382     byte = readb(rtc->regbase + reg_off);
0383     if (byte & AR_ENB) {
0384         byte &= ~AR_ENB;    /* strip the enable bit */
0385         value = bcd2bin(byte);
0386     }
0387 
0388     return value;
0389 }
0390 
0391 static int sh_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
0392 {
0393     struct sh_rtc *rtc = dev_get_drvdata(dev);
0394     struct rtc_time *tm = &wkalrm->time;
0395 
0396     spin_lock_irq(&rtc->lock);
0397 
0398     tm->tm_sec  = sh_rtc_read_alarm_value(rtc, RSECAR);
0399     tm->tm_min  = sh_rtc_read_alarm_value(rtc, RMINAR);
0400     tm->tm_hour = sh_rtc_read_alarm_value(rtc, RHRAR);
0401     tm->tm_wday = sh_rtc_read_alarm_value(rtc, RWKAR);
0402     tm->tm_mday = sh_rtc_read_alarm_value(rtc, RDAYAR);
0403     tm->tm_mon  = sh_rtc_read_alarm_value(rtc, RMONAR);
0404     if (tm->tm_mon > 0)
0405         tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */
0406 
0407     wkalrm->enabled = (readb(rtc->regbase + RCR1) & RCR1_AIE) ? 1 : 0;
0408 
0409     spin_unlock_irq(&rtc->lock);
0410 
0411     return 0;
0412 }
0413 
0414 static inline void sh_rtc_write_alarm_value(struct sh_rtc *rtc,
0415                         int value, int reg_off)
0416 {
0417     /* < 0 for a value that is ignored */
0418     if (value < 0)
0419         writeb(0, rtc->regbase + reg_off);
0420     else
0421         writeb(bin2bcd(value) | AR_ENB,  rtc->regbase + reg_off);
0422 }
0423 
0424 static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
0425 {
0426     struct sh_rtc *rtc = dev_get_drvdata(dev);
0427     unsigned int rcr1;
0428     struct rtc_time *tm = &wkalrm->time;
0429     int mon;
0430 
0431     spin_lock_irq(&rtc->lock);
0432 
0433     /* disable alarm interrupt and clear the alarm flag */
0434     rcr1 = readb(rtc->regbase + RCR1);
0435     rcr1 &= ~(RCR1_AF | RCR1_AIE);
0436     writeb(rcr1, rtc->regbase + RCR1);
0437 
0438     /* set alarm time */
0439     sh_rtc_write_alarm_value(rtc, tm->tm_sec,  RSECAR);
0440     sh_rtc_write_alarm_value(rtc, tm->tm_min,  RMINAR);
0441     sh_rtc_write_alarm_value(rtc, tm->tm_hour, RHRAR);
0442     sh_rtc_write_alarm_value(rtc, tm->tm_wday, RWKAR);
0443     sh_rtc_write_alarm_value(rtc, tm->tm_mday, RDAYAR);
0444     mon = tm->tm_mon;
0445     if (mon >= 0)
0446         mon += 1;
0447     sh_rtc_write_alarm_value(rtc, mon, RMONAR);
0448 
0449     if (wkalrm->enabled) {
0450         rcr1 |= RCR1_AIE;
0451         writeb(rcr1, rtc->regbase + RCR1);
0452     }
0453 
0454     spin_unlock_irq(&rtc->lock);
0455 
0456     return 0;
0457 }
0458 
0459 static const struct rtc_class_ops sh_rtc_ops = {
0460     .read_time  = sh_rtc_read_time,
0461     .set_time   = sh_rtc_set_time,
0462     .read_alarm = sh_rtc_read_alarm,
0463     .set_alarm  = sh_rtc_set_alarm,
0464     .proc       = sh_rtc_proc,
0465     .alarm_irq_enable = sh_rtc_alarm_irq_enable,
0466 };
0467 
0468 static int __init sh_rtc_probe(struct platform_device *pdev)
0469 {
0470     struct sh_rtc *rtc;
0471     struct resource *res;
0472     char clk_name[6];
0473     int clk_id, ret;
0474 
0475     rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
0476     if (unlikely(!rtc))
0477         return -ENOMEM;
0478 
0479     spin_lock_init(&rtc->lock);
0480 
0481     /* get periodic/carry/alarm irqs */
0482     ret = platform_get_irq(pdev, 0);
0483     if (unlikely(ret <= 0)) {
0484         dev_err(&pdev->dev, "No IRQ resource\n");
0485         return -ENOENT;
0486     }
0487 
0488     rtc->periodic_irq = ret;
0489     rtc->carry_irq = platform_get_irq(pdev, 1);
0490     rtc->alarm_irq = platform_get_irq(pdev, 2);
0491 
0492     res = platform_get_resource(pdev, IORESOURCE_IO, 0);
0493     if (!res)
0494         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0495     if (unlikely(res == NULL)) {
0496         dev_err(&pdev->dev, "No IO resource\n");
0497         return -ENOENT;
0498     }
0499 
0500     rtc->regsize = resource_size(res);
0501 
0502     rtc->res = devm_request_mem_region(&pdev->dev, res->start,
0503                     rtc->regsize, pdev->name);
0504     if (unlikely(!rtc->res))
0505         return -EBUSY;
0506 
0507     rtc->regbase = devm_ioremap(&pdev->dev, rtc->res->start, rtc->regsize);
0508     if (unlikely(!rtc->regbase))
0509         return -EINVAL;
0510 
0511     if (!pdev->dev.of_node) {
0512         clk_id = pdev->id;
0513         /* With a single device, the clock id is still "rtc0" */
0514         if (clk_id < 0)
0515             clk_id = 0;
0516 
0517         snprintf(clk_name, sizeof(clk_name), "rtc%d", clk_id);
0518     } else
0519         snprintf(clk_name, sizeof(clk_name), "fck");
0520 
0521     rtc->clk = devm_clk_get(&pdev->dev, clk_name);
0522     if (IS_ERR(rtc->clk)) {
0523         /*
0524          * No error handling for rtc->clk intentionally, not all
0525          * platforms will have a unique clock for the RTC, and
0526          * the clk API can handle the struct clk pointer being
0527          * NULL.
0528          */
0529         rtc->clk = NULL;
0530     }
0531 
0532     rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
0533     if (IS_ERR(rtc->rtc_dev))
0534         return PTR_ERR(rtc->rtc_dev);
0535 
0536     clk_enable(rtc->clk);
0537 
0538     rtc->capabilities = RTC_DEF_CAPABILITIES;
0539 
0540 #ifdef CONFIG_SUPERH
0541     if (dev_get_platdata(&pdev->dev)) {
0542         struct sh_rtc_platform_info *pinfo =
0543             dev_get_platdata(&pdev->dev);
0544 
0545         /*
0546          * Some CPUs have special capabilities in addition to the
0547          * default set. Add those in here.
0548          */
0549         rtc->capabilities |= pinfo->capabilities;
0550     }
0551 #endif
0552 
0553     if (rtc->carry_irq <= 0) {
0554         /* register shared periodic/carry/alarm irq */
0555         ret = devm_request_irq(&pdev->dev, rtc->periodic_irq,
0556                 sh_rtc_shared, 0, "sh-rtc", rtc);
0557         if (unlikely(ret)) {
0558             dev_err(&pdev->dev,
0559                 "request IRQ failed with %d, IRQ %d\n", ret,
0560                 rtc->periodic_irq);
0561             goto err_unmap;
0562         }
0563     } else {
0564         /* register periodic/carry/alarm irqs */
0565         ret = devm_request_irq(&pdev->dev, rtc->periodic_irq,
0566                 sh_rtc_periodic, 0, "sh-rtc period", rtc);
0567         if (unlikely(ret)) {
0568             dev_err(&pdev->dev,
0569                 "request period IRQ failed with %d, IRQ %d\n",
0570                 ret, rtc->periodic_irq);
0571             goto err_unmap;
0572         }
0573 
0574         ret = devm_request_irq(&pdev->dev, rtc->carry_irq,
0575                 sh_rtc_interrupt, 0, "sh-rtc carry", rtc);
0576         if (unlikely(ret)) {
0577             dev_err(&pdev->dev,
0578                 "request carry IRQ failed with %d, IRQ %d\n",
0579                 ret, rtc->carry_irq);
0580             goto err_unmap;
0581         }
0582 
0583         ret = devm_request_irq(&pdev->dev, rtc->alarm_irq,
0584                 sh_rtc_alarm, 0, "sh-rtc alarm", rtc);
0585         if (unlikely(ret)) {
0586             dev_err(&pdev->dev,
0587                 "request alarm IRQ failed with %d, IRQ %d\n",
0588                 ret, rtc->alarm_irq);
0589             goto err_unmap;
0590         }
0591     }
0592 
0593     platform_set_drvdata(pdev, rtc);
0594 
0595     /* everything disabled by default */
0596     sh_rtc_setaie(&pdev->dev, 0);
0597     sh_rtc_setcie(&pdev->dev, 0);
0598 
0599     rtc->rtc_dev->ops = &sh_rtc_ops;
0600     rtc->rtc_dev->max_user_freq = 256;
0601 
0602     if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
0603         rtc->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_1900;
0604         rtc->rtc_dev->range_max = RTC_TIMESTAMP_END_9999;
0605     } else {
0606         rtc->rtc_dev->range_min = mktime64(1999, 1, 1, 0, 0, 0);
0607         rtc->rtc_dev->range_max = mktime64(2098, 12, 31, 23, 59, 59);
0608     }
0609 
0610     ret = devm_rtc_register_device(rtc->rtc_dev);
0611     if (ret)
0612         goto err_unmap;
0613 
0614     device_init_wakeup(&pdev->dev, 1);
0615     return 0;
0616 
0617 err_unmap:
0618     clk_disable(rtc->clk);
0619 
0620     return ret;
0621 }
0622 
0623 static int __exit sh_rtc_remove(struct platform_device *pdev)
0624 {
0625     struct sh_rtc *rtc = platform_get_drvdata(pdev);
0626 
0627     sh_rtc_setaie(&pdev->dev, 0);
0628     sh_rtc_setcie(&pdev->dev, 0);
0629 
0630     clk_disable(rtc->clk);
0631 
0632     return 0;
0633 }
0634 
0635 static void sh_rtc_set_irq_wake(struct device *dev, int enabled)
0636 {
0637     struct sh_rtc *rtc = dev_get_drvdata(dev);
0638 
0639     irq_set_irq_wake(rtc->periodic_irq, enabled);
0640 
0641     if (rtc->carry_irq > 0) {
0642         irq_set_irq_wake(rtc->carry_irq, enabled);
0643         irq_set_irq_wake(rtc->alarm_irq, enabled);
0644     }
0645 }
0646 
0647 static int __maybe_unused sh_rtc_suspend(struct device *dev)
0648 {
0649     if (device_may_wakeup(dev))
0650         sh_rtc_set_irq_wake(dev, 1);
0651 
0652     return 0;
0653 }
0654 
0655 static int __maybe_unused sh_rtc_resume(struct device *dev)
0656 {
0657     if (device_may_wakeup(dev))
0658         sh_rtc_set_irq_wake(dev, 0);
0659 
0660     return 0;
0661 }
0662 
0663 static SIMPLE_DEV_PM_OPS(sh_rtc_pm_ops, sh_rtc_suspend, sh_rtc_resume);
0664 
0665 static const struct of_device_id sh_rtc_of_match[] = {
0666     { .compatible = "renesas,sh-rtc", },
0667     { /* sentinel */ }
0668 };
0669 MODULE_DEVICE_TABLE(of, sh_rtc_of_match);
0670 
0671 static struct platform_driver sh_rtc_platform_driver = {
0672     .driver     = {
0673         .name   = DRV_NAME,
0674         .pm = &sh_rtc_pm_ops,
0675         .of_match_table = sh_rtc_of_match,
0676     },
0677     .remove     = __exit_p(sh_rtc_remove),
0678 };
0679 
0680 module_platform_driver_probe(sh_rtc_platform_driver, sh_rtc_probe);
0681 
0682 MODULE_DESCRIPTION("SuperH on-chip RTC driver");
0683 MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, "
0684           "Jamie Lenehan <lenehan@twibble.org>, "
0685           "Angelo Castello <angelo.castello@st.com>");
0686 MODULE_LICENSE("GPL v2");
0687 MODULE_ALIAS("platform:" DRV_NAME);
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